Gate induced voltage suppression circuit and driving system

Abstract

The invention discloses a grid induced voltage suppression circuit and a driving system, and relates to the technical field of power electronics. The gate induced voltage suppression circuit comprises a gate driving module, the input end of which is electrically connected with a driving signal end, and the output end of which is electrically connected with the gate of a target power device; the first end of the positive voltage stabilization clamping module is electrically connected with a first target node in the gate driving module, and the second end of the positive voltage stabilization clamping module is electrically connected with a first power supply voltage end; the first end of the positive voltage absorption module is electrically connected with a second target node in the gate driving module, and the second end of the positive voltage absorption module is electrically connected with the reference grounding end; the first end of the negative pressure clamping absorption module is electrically connected with the grid electrode of the target power device, and the second end of the negative pressure clamping absorption module is electrically connected with the source electrode of the target power device and the reference grounding end. According to the embodiment of the invention, the grid induced voltage of the power device can be effectively suppressed.

Description

Technical Field

[0001] This application belongs to the field of power electronics technology, and in particular relates to a gate induced voltage suppression circuit and driving system. Background Technology

[0002] In the field of power electronics, power devices are the core electronic components in servo motor controllers or power inverter circuits. Examples of power devices include SiC-MOS (Silicon Carbide Metal-Oxide-Semiconductor Field-Effect Transistor), IGBT (Insulated Gate Bipolar Transistor), and MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). During circuit operation, power devices typically need to reliably switch on and off to achieve reliable motor control or efficient conversion and transmission of electrical energy.

[0003] However, during circuit operation, especially during rapid switching, power devices often experience gate voltage fluctuations due to their own parasitic capacitance and the parasitic inductance in the circuit, resulting in gate induced voltage. This gate induced voltage can lead to mis-conduction of the power device or even a short circuit, easily damaging the power transistor and reducing the overall stability and reliability of the circuit, potentially causing economic losses.

[0004] Therefore, how to effectively suppress the gate induced voltage of power devices in order to fully improve the reliability and performance of circuit operation and thus avoid the safety hazards caused by the gate induced voltage is a problem that the industry urgently needs to solve. Summary of the Invention

[0005] This application provides a gate induced voltage suppression circuit and driving system that can effectively suppress the gate induced voltage of power devices.

[0006] In a first aspect, embodiments of this application provide a gate-induced voltage suppression circuit, the gate-induced voltage suppression circuit comprising:

[0007] The gate drive module has its input terminal electrically connected to the drive signal terminal and its output terminal electrically connected to the gate of the target power device.

[0008] A positive voltage regulator clamping module, the first end of which is electrically connected to the first target node in the gate drive module, and the second end of which is electrically connected to the first power supply voltage terminal, is used to stabilize the gate voltage of the target power device at the first power supply voltage during the non-conducting phase of the target power device.

[0009] The positive voltage absorption module has its first end electrically connected to the second target node in the gate drive module and its second end electrically connected to the reference ground terminal, and is used to absorb the induced positive voltage spike of the gate of the target power device.

[0010] The negative voltage clamping absorption module has its first end electrically connected to the gate of the target power device, and its second end electrically connected to the source and reference ground of the target power device, respectively, to clamp the induced negative voltage of the gate of the target power device within a preset safety range.

[0011] In some possible implementations, the gate drive module includes:

[0012] The forward conduction submodule is located between the drive signal terminal and the gate of the target power device to enable current flow from the drive signal terminal to the gate of the target power device.

[0013] The reverse conduction submodule is connected in parallel with the forward conduction submodule to enable current flow from the gate of the target power device to the drive signal terminal.

[0014] The first target node is a node on the forward-guided submodule, and the second target node is a node on the reverse-guided submodule.

[0015] In some possible implementations, the positive voltage stabilizing clamping module includes:

[0016] An operational amplifier, wherein the first input terminal of the operational amplifier is electrically connected to the first power supply voltage terminal, and the second input terminal of the operational amplifier is electrically connected to the first target node;

[0017] The first transistor has its control terminal electrically connected to the output terminal of the operational amplifier, its first terminal electrically connected to the second power supply voltage terminal, and its second terminal electrically connected to the first target node.

[0018] In some possible implementations, the positive voltage stabilizing clamping module further includes:

[0019] The first resistor has its first end electrically connected to the output terminal of the operational amplifier, and its second end electrically connected to the control terminal of the first transistor.

[0020] In some possible implementations, the forward conduction submodule includes:

[0021] The first diode has its anode electrically connected to the drive signal terminal and its cathode electrically connected to the first target node.

[0022] The second resistor has its first end electrically connected to the first target node and its second end electrically connected to the gate of the target power device.

[0023] In some possible implementations, the forward conduction submodule further includes:

[0024] The third resistor is set between the drive signal terminal and the anode of the first diode, or the third resistor is set between the cathode of the first diode and the first target node.

[0025] The second diode has its anode electrically connected to the second terminal of the second resistor and its cathode electrically connected to the gate of the target power device; or, the anode of the second diode is electrically connected to the first target node and its cathode is electrically connected to the first terminal of the second resistor.

[0026] In some possible implementations, the reverse conduction submodule includes:

[0027] The cathode of the third diode is electrically connected to the drive signal terminal, and the anode of the third diode is electrically connected to the gate of the target power device.

[0028] In some possible implementations, the positive pressure absorption module includes:

[0029] The fourth resistor has its first end electrically connected to the drive signal terminal, and its second end and the cathode of the third diode electrically connected to the second target node; or, the first end of the fourth resistor and the anode of the third diode are electrically connected to the second target node, and the second end of the fourth resistor is electrically connected to the gate of the target power device.

[0030] The control terminal of the second transistor is electrically connected to the first terminal of the fourth resistor, the first terminal of the second transistor is electrically connected to the second target node, and the second terminal of the second transistor is electrically connected to the third power supply voltage terminal.

[0031] The first capacitor has its first terminal electrically connected to the second terminal of the second transistor, and its second terminal electrically connected to the reference ground terminal.

[0032] In some possible implementations, the negative voltage clamping absorption module includes a fourth diode and a first Zener diode connected in series;

[0033] The cathode of the fourth diode is electrically connected to the gate of the target power device, the anode of the fourth diode is electrically connected to the anode of the first Zener diode, and the cathode of the first Zener diode is electrically connected to the source of the target power device and the reference ground terminal, respectively.

[0034] Alternatively, the anode of the first Zener diode is electrically connected to the gate of the target power device, the cathode of the first Zener diode is electrically connected to the cathode of the fourth diode, and the anode of the fourth diode is electrically connected to the source of the target power device and the reference ground terminal, respectively.

[0035] Based on the same inventive concept, in a second aspect, embodiments of this application provide a driving system, which includes: a driving chip and a gate-induced voltage suppression circuit as described in any of the foregoing embodiments of this application, wherein the driving chip includes a driving signal terminal and a reference ground terminal;

[0036] The drive system is used to drive the target power device and suppress the gate induced voltage of the target power device, which is the upper or lower bridge arm power device in the power bridge arm group.

[0037] As described above, the gate induced voltage suppression circuit and driving system of this application, in order to reduce the risk of the gate induced positive voltage and induced negative voltage exceeding the device threshold in the high-current switching state of the target power device, comprises a gate driving module, a positive voltage regulation clamping module, a positive voltage absorption module, and a negative voltage clamping absorption module. The positive voltage absorption module can quickly absorb voltage spikes when a positive voltage is induced at the gate, thereby preventing damage to the target power device from the induced positive voltage spikes. The positive voltage regulation clamping module, based on the absorption of the induced positive voltage spikes, further achieves a voltage regulation clamping effect on the gate voltage, thereby ensuring that the target power device will not experience false turn-on during the non-conduction phase. The negative voltage clamping absorption module can stably clamp the device gate voltage within a preset safe range when a negative voltage is induced at the gate of the target power device.

[0038] Compared to existing technologies, the gate-induced voltage suppression circuit and driving system provided in this application, starting from the principle and path of gate-induced voltage, absorbs and clamps both positive and negative gate-induced voltages, thus effectively suppressing the gate-induced voltage of power devices and achieving the purpose of protecting the gate of power devices. Therefore, this application not only effectively ensures the service life of the target power device and the reliability and performance of related products, but also fully avoids safety hazards caused by gate-induced voltage. Attached Figure Description

[0039] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a schematic diagram of the gate-induced voltage suppression circuit provided in one embodiment of this application;

[0041] Figure 2 This is a schematic diagram of the structure and flow of a gate-induced voltage suppression circuit provided in another embodiment of this application;

[0042] Figure 3 This is a schematic diagram of the gate-induced voltage suppression circuit provided in another embodiment of this application;

[0043] Figure 4 This is a schematic diagram of the gate-induced voltage suppression circuit provided in another embodiment of this application;

[0044] Figure 5 This is a schematic diagram of the gate-induced voltage suppression circuit provided in another embodiment of this application;

[0045] Figure 6 This is a schematic diagram of the structure of a drive system provided in an embodiment of this application;

[0046] Figure 7 This is a schematic diagram of the drive system provided in another embodiment of this application.

[0047] In the attached image:

[0048] 100. Gate-induced voltage suppression circuit; 10. Gate drive module; 20. Positive voltage regulation clamping module; 30. Positive voltage absorption module; 40. Negative voltage clamping absorption module; 11. Forward conduction sub-module; 12. Reverse conduction sub-module; Q1. Target power device / upper arm power device; Q2. First transistor; Q3. Second transistor; OP. Operational amplifier; R1. First resistor; R2. Second resistor; R3. Third resistor; R4. Fourth resistor; C1. First capacitor; D1. First diode; D2. Second diode; D3. Third diode; D4. Fourth diode; DZ1. First Zener diode; VCC1. First power supply voltage terminal; VCC2. Second power supply voltage terminal; VCC3. Third power supply voltage terminal; 200. Driver chip; 1000. Driver system; HV. High voltage side; GND. Low voltage side; Q4. Lower arm power device. Detailed Implementation

[0049] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0050] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0051] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0052] It should be noted that the transistors in the embodiments of this application can be either N-type or P-type transistors. For N-type transistors, the on-level is high and the off-level is low. That is, when the gate of an N-type transistor is high, its first and second terminals are connected; when the gate of an N-type transistor is low, its first and second terminals are off. For P-type transistors, the on-level is low and the off-level is high. That is, when the control terminal of a P-type transistor is low, its first and second terminals are connected; when the control terminal of a P-type transistor is high, its first and second terminals are off. In specific implementations, the gate of each transistor is used as its control terminal. Furthermore, depending on the signal and type of the gate of each transistor, its first terminal can be used as the source and its second terminal as the drain, or vice versa. No distinction is made here. Additionally, the on-level and off-level in the embodiments of this invention are general terms. The on-level refers to any level that enables the transistor to conduct, and the off-level refers to any level that enables the transistor to turn off / become off.

[0053] In the embodiments of this application, the term "electrical connection" can refer to a direct electrical connection between two components, or it can refer to an electrical connection between two components via one or more other components.

[0054] In the embodiments of this application, the first node, the second node, and the third node are defined only for the convenience of describing the circuit structure, and the first node, the second node, and the third node are not actual circuit units.

[0055] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this application can be combined with each other without contradiction.

[0056] Before describing the technical solutions provided in the embodiments of this application, in order to facilitate understanding of the embodiments of this application, this application first specifically explains the problems existing in the related technologies:

[0057] As mentioned earlier, gate-induced voltage can cause mis-enabling of power devices and even short-circuit risks, easily damaging power transistors and reducing the overall stability and reliability of the circuit, potentially leading to economic losses. To address these issues, existing technologies propose the following three methods to suppress gate-induced voltage: Method 1: Changing the gate resistance to reduce the gate-induced voltage by slowing down the turn-on and turn-off speeds; Method 2: Increasing the gate capacitance to absorb transient voltages and suppress gate-induced voltage; Method 3: Using a negative voltage to drive the turn-off gate voltage to a negative value, preventing it from exceeding the threshold voltage Vth.

[0058] However, the inventors of this application have discovered that all three methods for suppressing gate induced voltage have certain drawbacks. Regarding method 1: While changing the gate resistance can slow down the switching rate, this method not only requires consideration of the power consumption of the resistor during switching but also affects the switching losses of the power device. In products with limited heat dissipation or small size, the heat dissipation of the device and even the entire product needs to be reconsidered. Regarding method 2: This method absorbs the gate induced voltage by increasing the gate capacitance. However, since the Cgs (Gate-to-Source Capacitance) of the power device is connected in parallel with the external gate-source capacitance, the gate charge increases, leading to a larger drive power that may even exceed the power consumption of the driver chip. Regarding method 3: This method requires adding a power supply circuit or power module to provide a negative power supply, which significantly increases cost and product power consumption. Furthermore, even with a negative voltage power supply, a large induced voltage still exists when the power device's IDS (Drain-to-Source Current) is applied with a high current, making it impossible to effectively suppress the gate induced voltage of the power device.

[0059] In view of the above, in order to solve the above technical problems, the embodiments of this application provide a gate induced voltage suppression circuit and driving system, which can more reasonably and effectively suppress the gate induced voltage of power devices, so as to fully improve the reliability and performance of circuit operation, thereby avoiding safety hazards caused by gate induced voltage.

[0060] The gate-induced voltage suppression circuit provided in the embodiments of this application will be described below.

[0061] Figure 1 This is a schematic diagram of the gate-induced voltage suppression circuit 100 provided in one embodiment of this application. Figure 1 As shown, this application embodiment provides a gate-induced voltage suppression circuit 100, such as... Figure 1 As shown, the gate-induced voltage suppression circuit 100 of this application embodiment includes:

[0062] Gate drive module 10, the input terminal of gate drive module 10 is electrically connected to drive signal terminal, and the output terminal of gate drive module 10 is electrically connected to the gate of target power device Q1.

[0063] Positive voltage regulation clamping module 20, the first end of the positive voltage regulation clamping module 20 is electrically connected to the first target node in the gate drive module 10, and the second end of the positive voltage regulation clamping module 20 is electrically connected to the first power supply voltage terminal VCC1, used to stabilize the gate voltage of the target power device Q1 at the first power supply voltage during the non-conducting stage of the target power device Q1.

[0064] Positive voltage absorption module 30, the first end of which is electrically connected to the second target node in the gate drive module 10, and the second end of which is electrically connected to the reference ground terminal, is used to absorb the induced positive voltage spike of the gate of the target power device Q1.

[0065] The negative pressure clamping absorption module 40 has its first end electrically connected to the gate of the target power device Q1, and its second end electrically connected to the source and reference ground of the target power device Q1, respectively, for clamping the induced negative pressure of the gate of the target power device Q1 within a preset safety range.

[0066] In this application, both the aforementioned drive signal terminal and the aforementioned reference ground terminal can be provided by corresponding driver chips. The driver chip can be used to provide a drive voltage to the gate of the target power device Q1, thereby driving the target power device Q1 to conduct. The driver chip can be, for example, a microcontroller unit (MCU), and is not strictly limited thereto.

[0067] In this application, the target power device Q1 is, for example, a SiC-MOS transistor, an IGBT, or other types of MOS transistors. Considering the characteristics of actual power devices, the target power device Q1 can specifically be a SiC-MOS transistor, but this is not strictly limited.

[0068] The target power device Q1 mentioned above can be located in the power circuit, specifically it can be an upper or lower bridge arm power device in the power bridge arm group, without strict limitation. Taking the target power device Q1 as an upper bridge arm power device as an example, when current flows through the lower bridge arm power device, the frequent switching of the power device causes a rapid change in the rate of change of current in the line, which will induce a voltage on the gate of the target power device Q1.

[0069] In this application, in order to reduce the risk that the gate induced positive voltage and induced negative voltage of the target power device Q1 in the high current switching state exceed the device threshold, the above-mentioned gate drive module 10, positive voltage regulation clamping module 20, positive voltage absorption module 30 and negative voltage clamping absorption module 40 are set.

[0070] The aforementioned positive voltage absorption module 30 can quickly absorb voltage spikes when an induced positive voltage appears on the gate, thereby preventing damage to the target power device Q1 from the induced positive voltage spike. For example, in the positive voltage absorption module 30, the absorption characteristics of a capacitor for voltage can be used to absorb the aforementioned induced positive voltage spike, and its specific implementation structure is not strictly limited here.

[0071] The positive voltage regulation clamping module 20 can further achieve a voltage regulation clamping effect on the gate voltage after the induced positive voltage spike is absorbed, thereby ensuring that the target power device Q1 will not be falsely turned on during the non-conducting stage. For example, the positive voltage regulation clamping module can suppress the induced positive voltage by using an operational amplifier and a comparator, or it can use a Zener diode to achieve its voltage regulation clamping function; there is no strict limitation here.

[0072] The negative voltage clamping absorption module 40 can stably clamp the gate voltage of the target power device Q1 within a preset safe range when an induced negative voltage appears on the gate. For example, the negative voltage clamping absorption module 40 can use devices such as Zener diodes to achieve voltage stabilization clamping.

[0073] Compared to existing technologies, the gate-induced voltage suppression circuit 100 provided in this application, based on the principle and path of gate-induced voltage, absorbs and clamps both positive and negative gate-induced voltages, thus effectively suppressing the gate-induced voltage of the power device and achieving the purpose of protecting the gate of the power device. Therefore, this application not only effectively ensures the service life of the target power device Q1 and the reliability and performance of its related products, but also fully avoids safety hazards caused by the gate-induced voltage of the device.

[0074] Please see below. Figure 2 , Figure 2 This is a schematic diagram of the gate-induced voltage suppression circuit 100 provided in another embodiment of this application. Optionally, according to some feasible embodiments of this application, such as... Figure 2 As shown, the gate driving module 10 includes:

[0075] Forward conduction submodule 11 is disposed between the drive signal terminal and the gate of the target power device Q1, and is used to realize the current flow from the drive signal terminal to the gate of the target power device Q1.

[0076] The reverse conduction submodule 12 is connected in parallel with the forward conduction submodule 11 to enable current flow from the gate of the target power device Q1 to the drive signal terminal.

[0077] The first target node is a node on the forward-guided submodule 11, and the second target node is a node on the reverse-guided submodule 12.

[0078] In this embodiment, a forward conduction submodule 11 and a reverse conduction submodule 12 are connected in parallel between the drive signal terminal and the gate of the target power device Q1, thereby forming a forward conduction path from the gate of the target power device Q1 to the drive signal terminal and a reverse conduction path from the gate of the target power device Q1 to the drive signal terminal.

[0079] Both the forward conduction submodule 11 and the reverse conduction submodule 12 described above have unidirectional conduction. This unidirectional conduction can be achieved by setting unidirectional conduction devices (such as diodes), and there are no strict limitations here.

[0080] Taking the target power device Q1 as the upper bridge arm power device as an example, when current flows through the lower bridge arm power device, the frequent switching of the power device causes the current change rate on the line to change rapidly, which will cause an induced voltage to appear on the gate of the target power device Q1.

[0081] Specifically, when the other bridge arm power device is turned on, the rate of change of the source-drain voltage of the target power device Q1 increases rapidly. Due to the presence of internal parasitic capacitance in the target power device Q1, a displacement current is generated.

[0082] Since both the forward conduction submodule 11 and the reverse conduction submodule 12 have unidirectional conduction, the displacement current will first flow through the reverse conduction submodule 12 and then through the forward conduction submodule 11. Under the action of the impedance in the circuit through which the displacement current flows, a positive voltage is induced at the gate of the target power device Q1.

[0083] Based on this, when the displacement current flows through the second target node in the reverse conduction submodule 12, the positive voltage absorption module 30 works, which can quickly absorb voltage spikes and thus avoid damage to the target power device Q1 caused by the induced positive voltage spikes.

[0084] When the displacement current flows through the first target node, the positive voltage regulation clamping module 20 can further achieve the voltage regulation clamping effect on the gate voltage based on the absorption of the induced positive voltage spike, thereby ensuring that the target power device Q1 will not be falsely turned on during the non-conducting stage.

[0085] Please continue reading Figure 2 Optionally, according to some feasible embodiments of this application, the positive voltage stabilizing clamping module 20 includes:

[0086] The operational amplifier OP has its first input terminal electrically connected to the first power supply voltage terminal VCC1, and its second input terminal electrically connected to the first target node.

[0087] The first transistor Q2 has its control terminal electrically connected to the output terminal of the operational amplifier OP, its first terminal electrically connected to the second power supply voltage terminal VCC2, and its second terminal electrically connected to the first target node.

[0088] In this embodiment, during the non-conducting phase of the target power device Q1, the positive voltage clamping module provides feedback regulation of the first target node potential by setting up an operational amplifier OP and a first transistor Q2, thereby achieving gate voltage regulation and clamping of the target power device Q1. In this embodiment, the first transistor Q2 is, for example, an NPN transistor, with its control terminal being the base, its first terminal being the collector, and its second terminal being the emitter.

[0089] Specifically, the positive voltage regulator clamping module 20 uses the gate voltage at the first target node as the feedback voltage, thus forming a negative feedback circuit. In actual operation, the feedback voltage of the first target node is fed back to the first input terminal of the operational amplifier OP, and the first power supply voltage provided by the first power supply voltage terminal VCC1 is provided to the second input terminal of the operational amplifier OP.

[0090] The operational amplifier (OP) compares the voltage difference between the feedback voltage of the first target node and the first power supply voltage. When the feedback voltage is detected to be greater than or less than the reference first power supply voltage, the OP controls and adjusts the current at its output terminal based on its device characteristics. By adjusting the current, the potential of the emitter (second terminal) of the first transistor Q2 can be adjusted, thereby keeping the output voltage of the first transistor Q2 constant at the first power supply voltage, and thus keeping the potentials at the first and second input terminals of the operational amplifier OP consistent.

[0091] Thus, through the current control mechanism of the operational amplifier OP at its output terminal, and combined with the driving characteristics of the first transistor Q2 controlled by the base current, the voltage of the first target node can be stabilized at the first power supply voltage, thereby stabilizing the gate voltage of the power device around the first power supply voltage and ensuring the stable clamping of the gate induced positive voltage.

[0092] It should be noted that when the target power device Q1 needs to be turned on, the driving voltage provided by the aforementioned driving signal terminal is supplied to the gate of the target power device Q1 via the forward conduction submodule 11. The voltage value of this driving voltage is higher than the voltage provided by the first power supply voltage terminal VCC1 and the second power supply voltage terminal VCC2. For example, the driving voltage is 18V, the first power supply voltage provided by the first power supply voltage terminal VCC1 is 1V, and the voltage provided by the second power supply voltage terminal VCC2 is, for example, 5V, 10V, etc.

[0093] Under the influence of the driving voltage, the voltage of the first target node is raised, and the emitter of the first transistor Q2 is raised to a potential higher than that of the collector of the first transistor Q2. In this case, the first transistor Q2 cannot meet the conduction conditions of forward bias of the emitter junction (the emitter is at a low potential relative to the base) and reverse bias of the collector junction (the collector is at a high potential relative to the base). Therefore, the first transistor Q2 will not conduct, the feedback clamping effect of the positive voltage regulator clamping module 20 fails, and the target power device Q1 can be driven to conduct normally.

[0094] Please see below. Figure 3 , Figure 3 This is a schematic diagram of the gate-induced voltage suppression circuit 100 provided in another embodiment of this application. Optionally, according to some feasible embodiments of this application, such as... Figure 3 As shown, the positive voltage stabilizing clamping module 20 also includes:

[0095] The first resistor R1 has its first end electrically connected to the output terminal of the operational amplifier OP, and its second end electrically connected to the control terminal of the first transistor Q2.

[0096] In this embodiment, a first resistor R1 is provided between the output terminal of the operational amplifier OP and the control terminal of the first transistor Q2. This first resistor R1 is a base current resistor. The specific value of the first resistor R1 can be determined according to the actual base current limiting requirements, and will not be strictly specified here.

[0097] The first resistor R1 effectively limits the base current, thereby protecting the first transistor Q2. Furthermore, the first resistor R1 effectively reduces base circuit fluctuations, thus minimizing the impact of noise and interference on the first transistor Q2 and improving circuit stability. By appropriately selecting the first resistor R1, the stability and reliability of the first transistor Q2's operation can be ensured.

[0098] Please continue reading below. Figure 3 Optionally, according to some feasible embodiments of this application, the forward conduction submodule 11 includes:

[0099] The first diode D1 has its anode electrically connected to the drive signal terminal and its cathode electrically connected to the first target node.

[0100] The second resistor R2 has its first end electrically connected to the first target node and its second end electrically connected to the gate of the target power device Q1.

[0101] In this embodiment, as Figure 3 As shown, by setting a first diode D1 on the left side of the gate voltage feedback node of the positive voltage stabilizing clamp module 20, i.e. the first target node, the first diode D1 can ensure the unidirectional conduction characteristic of the forward conduction submodule 11 and block the current flowing from the gate to the drive signal terminal.

[0102] Furthermore, it should be noted that the placement of the first diode D1 can also effectively block the current flow from the forward voltage regulation clamp module to the drive signal terminal, thereby avoiding signal interference and other adverse effects on the drive signal terminal.

[0103] In this embodiment, the second resistor R2 is also provided on the right side of the gate voltage feedback node of the positive voltage stabilization clamping module 20, i.e., the first target node, for current limiting protection.

[0104] The setting of the second resistor R2 can effectively prevent the first transistor Q2 from being broken down by the induced current, and can also effectively protect the gate of the target power device Q1.

[0105] Please see below. Figure 4 , Figure 4 This is a schematic diagram of the gate-induced voltage suppression circuit 100 provided in another embodiment of this application. Optionally, according to some feasible embodiments of this application, such as... Figure 4 As shown, the forward guidance submodule 11 also includes:

[0106] The third resistor R3 is set between the drive signal terminal and the anode of the first diode D1, or the third resistor R3 is set between the cathode of the first diode D1 and the first target node.

[0107] The anode of the second diode D2 is electrically connected to the second terminal of the second resistor R2, and the cathode of the second diode D2 is electrically connected to the gate of the target power device Q1. Alternatively, the anode of the second diode D2 is electrically connected to the first target node, and the cathode of the second diode D2 is electrically connected to the first terminal of the second resistor R2.

[0108] In this embodiment, by adding the aforementioned third resistor R3 and second diode D2 to the forward conduction submodule 11, the overall reliability of the circuit operation and the safety of the device can be significantly improved, which helps to more stably and continuously suppress the gate induced voltage of the target power device Q1.

[0109] by Figure 4 As shown in the example, by adding a third resistor R3 between the drive signal terminal and the anode of the first diode D1, current limiting protection in the forward conduction path can be achieved more effectively.

[0110] By placing the second diode D2 between the second end of the second resistor R2 and the gate of the target power device Q1, the displacement current can be effectively blocked from flowing from the gate of the target power device Q1 to the first transistor Q2, thereby better protecting the first transistor Q2.

[0111] Please continue reading Figure 4 Optionally, according to some feasible embodiments of this application, the reverse conduction submodule 12 includes:

[0112] The cathode of the third diode D3 is electrically connected to the drive signal terminal, and the anode of the third diode D3 is electrically connected to the gate of the target power device Q1.

[0113] In this embodiment, the reverse conduction submodule 12 is configured with the third diode D3 to fully realize the reverse conduction function from the gate of the target power device Q1 to the drive signal terminal. This ensures that when the target power device Q1 is turned off, the displacement current on its gate will flow unidirectionally through the reverse conduction submodule 12.

[0114] Please continue reading below. Figure 4 Optionally, according to some feasible embodiments of this application, the positive pressure absorption module 30 includes:

[0115] The fourth resistor R4 has its first end electrically connected to the drive signal terminal, and its second end and the cathode of the third diode D3 electrically connected to the second target node. Alternatively, the first end of the fourth resistor R4 and the anode of the third diode D3 are electrically connected to the second target node, and the second end of the fourth resistor R4 is electrically connected to the gate of the target power device Q1.

[0116] The control terminal of the second transistor Q3 is electrically connected to the first terminal of the fourth resistor R4, the first terminal of the second transistor Q3 is electrically connected to the second target node, and the second terminal of the second transistor Q3 is electrically connected to the third power supply voltage terminal VCC3.

[0117] The first capacitor C1 is electrically connected to the second terminal of the second transistor Q3, and the second terminal of the first capacitor C1 is electrically connected to the reference ground terminal.

[0118] In this embodiment, by setting a fourth resistor R4, a second transistor Q3, and a first capacitor C1, the positive voltage absorption module 30 can effectively absorb voltage spikes when an induced positive voltage appears on the gate. The second transistor Q3 is a PNP transistor, with its first terminal being the emitter, the control terminal being the base, and the second terminal being the collector.

[0119] Specifically, combined Figure 4 As shown, the fourth resistor R4 is set between the drive signal terminal and the cathode of the third diode D3. The second target node can be understood as the node at the second end of the fourth resistor R4.

[0120] When a displacement current occurs at the gate, due to the unidirectional conduction characteristics of the forward conduction submodule 11 and the reverse conduction submodule 12, the displacement current flows from the second end of the fourth resistor R4 to the first end of the fourth resistor R4, and a voltage drop occurs across the fourth resistor R4.

[0121] Due to the voltage drop across the fourth resistor R4, the emitter potential of the second transistor Q3 is higher than its base potential. The collector of the second transistor Q3 is electrically connected to the third power supply terminal VCC3, which can provide a negative voltage, such as -3V. In this situation, the second transistor Q3 meets the conduction condition and therefore conducts. The conduction of the second transistor Q3 connects the second target node to the first capacitor C1. By utilizing the characteristic that the voltage across the first capacitor C1 does not change abruptly, the induced positive voltage is fully absorbed.

[0122] In this embodiment, since the second transistor Q3 is only turned on when a positive induced voltage is present, it is equivalent to the first capacitor C1 being connected only when a positive induced voltage is present. Therefore, unlike the method 2 of the prior art, the increase in gate capacitance will not lead to an increase in gate charge, thereby increasing the driving power or even exceeding the power consumption of the driving chip.

[0123] It should be noted that in actual operation, the positive voltage absorption module 30 has a limited voltage absorption rate and cannot completely eliminate the positive induced voltage. Therefore, the main function of the positive voltage absorption module 30 in this embodiment is to absorb voltage spikes and prevent the target power device Q1 from being mis-conducted, thus causing the power transistor to break down. The aforementioned positive voltage regulation clamping module 20 can then be used to clamp and protect the gate-induced positive voltage.

[0124] It should also be noted that the fourth resistor R4 can effectively protect the current flowing through the circuit during reverse conduction, thus contributing to more stable circuit operation.

[0125] Please continue reading Figure 4 Optionally, according to some feasible embodiments of this application, the negative pressure clamping absorption module 40 includes a fourth diode D4 and a first Zener diode DZ1 connected in series;

[0126] The cathode of the fourth diode D4 is electrically connected to the gate of the target power device Q1, the anode of the fourth diode D4 is electrically connected to the anode of the first Zener diode DZ1, and the cathode of the first Zener diode DZ1 is electrically connected to the source of the target power device Q1 and the reference ground terminal, respectively.

[0127] Alternatively, the anode of the first Zener diode DZ1 is electrically connected to the gate of the target power device Q1, the cathode of the first Zener diode DZ1 is electrically connected to the cathode of the fourth diode D4, and the anode of the fourth diode D4 is electrically connected to the source of the target power device Q1 and the reference ground terminal, respectively.

[0128] In this embodiment, by setting the fourth diode D4 and the first Zener diode DZ1, the negative voltage clamping absorption module 40 can reasonably achieve the safety clamping effect of the gate-induced negative voltage of the target power device Q1. The first Zener diode DZ1 can be implemented using a Zener diode, whose main function is to achieve voltage regulation by utilizing reverse breakdown characteristics.

[0129] Specifically, combined Figure 4 As shown, the example is a connection method in which the cathode of the fourth diode D4 is electrically connected to the gate of the target power device Q1, the anode of the fourth diode D4 is electrically connected to the anode of the first Zener diode DZ1, and the cathode of the first Zener diode DZ1 is electrically connected to the source of the target power device Q1 and the reference ground terminal.

[0130] A negative voltage is generated at the gate of the target power device Q1 due to the parasitic inductance of the source and the rapidly changing rate of current. In this case, the voltage regulation effect of the first Zener diode DZ1 can keep the gate-induced negative voltage of the target power device Q1 stable within a preset safe range. At the same time, the fourth diode D4 can effectively block the displacement current when the gate-induced positive voltage occurs, ensuring that the positive voltage absorption module 30 and the positive voltage regulation clamping module 20 can stably and effectively suppress the gate-induced positive voltage.

[0131] It should be noted that in practical applications, the model parameters of the first Zener diode DZ1 can be flexibly selected according to the requirements for suppressing the gate induced negative voltage of the target power device Q1. This application does not impose strict restrictions on this.

[0132] It is understood that the above are all examples and do not serve as a substantial limitation on the protection circuits protected by this application.

[0133] To facilitate a more intuitive understanding of the protection circuit for the power switch provided in the above embodiments, a specific complete embodiment will be used as an example to illustrate its overall functionality. Figure 5 This is a schematic diagram of the protection circuit for a power switch provided in another embodiment of this application. Figure 5 In the context of actual operating circuit scenarios for power devices in servo motor controllers or power supply fields, the target power device Q1 can be a power device in the bridge arm group, such as the upper bridge arm power device. Specifically, the target power device Q1 can be a SiC-MOS transistor. It should be noted that in some other embodiments, the target power device Q1 can also be a lower bridge arm power device, which is not strictly limited here.

[0134] In this scenario embodiment, a gate-induced voltage suppression circuit 100 for a power device in a high-current switching state of a SiC-MOS transistor is involved. This circuit effectively suppresses induced conduction through gate positive and negative voltage absorption and clamping protection functions.

[0135] Specifically, for example, the upper bridge power device Q1 and the lower bridge power device Q4 are two SiC-MOS transistors, connected in series to form the main power circuit. HV represents the high-voltage side, specifically the power supply for the high-voltage side. GND represents the low-voltage side, specifically, for example, the ground terminal of the low-voltage side. The HV potential is much greater than VCC2 and VCC1.

[0136] The gate-induced voltage suppression circuit 100 includes a gate drive module 10, a positive voltage regulation clamping module 20, a positive voltage absorption module 30, and a negative voltage clamping absorption module 40. The drive chip may include a drive signal terminal and a reference ground terminal. The drive voltage output by the drive chip is provided to the gate and source terminals of the upper bridge arm power device Q1 through the gate drive circuit. The positive voltage regulation clamping module 20 can consistently stabilize the gate-induced positive voltage of the upper bridge arm power device Q1 at the first power supply voltage during the non-conducting phase. The positive voltage absorption module 30 is used to quickly absorb voltage spikes when a positive voltage is induced at the gate of the upper bridge arm power device Q1. The negative voltage clamping absorption module 40 is used to clamp the gate-induced negative voltage of the upper bridge arm power device Q1 within a preset safe range.

[0137] In the gate drive module 10, R2 and R3 are gate turn-on resistors, and D1, D2, and D3 are diodes that act as blocking circuits. R2, R3, D1, and D2 form the turn-on path for the SiC-MOS transistor, corresponding to the aforementioned forward conduction submodule 11. D3 forms the turn-off path for the SiC-MOS transistor, corresponding to the aforementioned reverse conduction submodule 12. In this scenario embodiment, R4 in the positive voltage absorption module 30 can also be used as the gate turn-off resistor, and R4 and D3 together form the turn-off path for the SiC-MOS transistor.

[0138] In the positive voltage regulation clamping module 20, OP is an operational amplifier, R1 is a current-limiting resistor, and Q2 is an NPN transistor. By feeding back the feedback voltage of the first target node to the input of OP, the gate voltage of the upper bridge arm power device Q1 can be effectively stabilized at the first power supply voltage.

[0139] In the positive voltage absorption module 30, Q3 is a PNP transistor, R2 provides the on-state voltage drop of Q3, and C1 is a capacitor. The absorption of the gate-induced positive voltage spike is achieved through Q3, R2, and C1. Since C1 is effective only when the gate is induced and the path is turned off, it is equivalent to C1 only being connected when an induced positive voltage occurs. Therefore, unlike the aforementioned prior art method 2, it does not lead to an increase in drive power, or even exceed the power consumption of the drive chip.

[0140] In the negative voltage clamping absorption module 40, D4 is a diode that blocks the circuit, and DZ1 is a Zener diode that regulates the voltage. D4 and DZ1 together form the negative voltage clamping absorption module 40, which is used to absorb the induced negative voltage appearing on the gate of the upper bridge arm power device Q1, ensuring that the induced negative voltage on the gate is clamped within a preset safety range.

[0141] The following is a description of the overall implementation process and suppression principle of a gate-induced voltage suppression circuit 100 in this scenario embodiment:

[0142] When current flows through the lower bridge arm power device Q4 in the main power circuit, the frequent switching of the power device causes a rapid change in the rate of change of current di / dt in the line, which induces a voltage at the gate of the target power device Q1, i.e., the upper bridge arm power device Q1. The magnitude of the induced voltage at the gate of the upper bridge arm power device Q1 is positively correlated with the magnitude of the current flowing through the lower bridge arm power device Q4.

[0143] When testing the gate-induced positive voltage of the upper bridge power device Q1, Q1 is turned off and the lower bridge power device Q4 is turned on. The DS-terminal voltage of the upper bridge power device Q1 rises rapidly at a rate of dv / dt. dv / dt generates a displacement current through the internal parasitic capacitance Cgd of the upper bridge power device Q1, and through the impedance, forms the gate-induced positive voltage of the upper bridge power device Q1.

[0144] When displacement current flows, such as Figure 5 As shown, the displacement current first flows through D3 and R4. The displacement current flowing through resistor R4 creates a voltage drop, causing Q3 to conduct. This absorbs the induced positive voltage by utilizing the principle that the voltage across capacitor C1 cannot change abruptly. However, the positive voltage absorption module 30 has a limited absorption rate and cannot completely eliminate the positive induced voltage. The main function of this positive voltage absorption module is to absorb voltage spikes and prevent damage to devices such as Q1 in the upper bridge arm.

[0145] Meanwhile, during the turn-off phase of the upper bridge arm power device Q1, the positive voltage regulator clamping module 20 can always regulate the gate voltage of the upper bridge arm power device Q1 at VCC1, preventing damage to the power device caused by excessive forward induction. After the displacement current weakens and disappears, the voltage drop across resistor R4 disappears, and Q3 turns off.

[0146] Specifically, the positive voltage regulation clamping module 20 forms a negative feedback circuit by using the gate voltage as the feedback voltage. The feedback voltage is compared with the reference voltage VCC1. As long as the feedback voltage is detected to be greater than or less than the reference voltage VCC1, the output current of the operational amplifier OPOP is adjusted, thereby adjusting the potential of the emitter of Q2 through the current. In this way, the output voltage is kept constant at VCC1, thereby achieving the voltage regulation clamping effect.

[0147] It should be added that when the upper bridge power device Q1 is turned on, the driver chip outputs, for example, an 18V voltage (higher than VCC2 and VCC1) to the gate of the upper bridge power device Q1. In this case, the emitter voltage of Q2 is raised, and Q2 cannot meet the turn-on condition, so it remains turned off. The feedback clamping function of the positive voltage regulator clamping module 20 fails, and the upper bridge power device Q1 can be driven normally.

[0148] When the gate of the upper-arm power device Q1 is induced with a positive voltage, the lower-arm power device Q4 is turned off. In this case, the gate of the upper-arm power device Q1 will generate a lower negative voltage due to the parasitic inductance of the source and the rapidly changing current rate di / dt. The voltage regulation effect of the DZ41 Zener diode is used to keep the gate voltage stable and clamped within the preset safe range.

[0149] In a circuit test example, when the above-mentioned solution provided in this application is not applied, the gate-induced positive voltage of the target power device Q1 (such as a SiC-MOS transistor) is 4.5V and the gate-induced negative voltage reaches -16.35V when a current of 150A flows through it. Using the gate-induced voltage suppression circuit 100 provided in this application, the gate-induced positive voltage of the target power device Q1 can be suppressed to within 1V, and the gate-induced negative voltage can be suppressed to within -7.78V. The positive voltage is absorbed by at least 3.5V, and the negative voltage is absorbed by at least 8.57V.

[0150] Overall, this embodiment proposes a novel circuit structure for suppressing gate induced voltage in power devices (such as SiC-MOS transistors). Addressing the risk that positive and negative voltages may exceed the absolute values ​​of the device even under high-current switching conditions when power devices are turned off by negative voltage, this embodiment, based on the principle and path of induced voltage, absorbs and clamps the gate induced positive and negative voltages respectively, achieving the purpose of protecting the gate, ensuring the service life of the power device, and thus contributing to improving the performance and lifespan of related products.

[0151] The gate-induced voltage suppression circuit 100 proposed in this embodiment achieves power device protection using very few conventional components, offering significant advantages in component selection, layout, and miniaturization. The application of this gate-induced voltage suppression circuit 100 ensures circuit stability and reliability, greatly improving product reliability. Therefore, it possesses a significant competitive advantage in applications such as parallel connection of SiC-MOS transistors in servo or power supply applications.

[0152] Based on the gate-induced voltage suppression circuit 100 provided in the foregoing embodiments, this application provides a driving system 1000 accordingly. Please refer to the following... Figure 6 , Figure 6 This is a schematic diagram of the structure of a drive system 1000 provided in one embodiment of this application. Figure 6 As shown, the driving system 1000 includes: a driving chip 200 and a gate sensing voltage suppression circuit 100 as described in any of the preceding embodiments of this application. The driving chip 200 includes a driving signal terminal and a reference ground terminal.

[0153] The drive system 1000 is used to drive the target power device and suppress the gate induced voltage of the target power device, which is the upper or lower bridge arm power device in the power bridge arm group.

[0154] It should be understood that the driving system 1000 provided in this application embodiment has the beneficial effects of the gate induced voltage suppression circuit 100 provided in this application embodiment. For details, please refer to the specific description of the gate induced voltage suppression circuit 100 in the above embodiments. This embodiment will not repeat the description here.

[0155] In practical applications, there may be multiple drive systems 1000 as described in this application. Figure 7 This is a schematic diagram of the drive system 1000 provided in another embodiment of this application. In a bridge arm group, corresponding drive chips 200 and gate induced voltage suppression circuits 100 as provided in the foregoing embodiments can be respectively provided for the upper bridge arm power device Q1 and the lower bridge arm power device Q4.

[0156] The functional blocks shown in the above-described structural diagram can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application-specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of this application are programs or code segments used to perform the required tasks. Programs or code segments can be stored on a machine-readable medium or transmitted over a transmission medium or communication link via data signals carried on a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio frequency (RF) links, etc. Code segments can be downloaded via computer networks such as the Internet, intranets, etc.

[0157] It should be noted that, in this document, the terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0158] It should be clarified that the various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. According to the embodiments described above, these embodiments do not exhaustively describe all details, nor do they limit this application to only the specific embodiments described. Obviously, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to make good use of this application and modifications based on it. This application is limited only by the claims and their full scope and equivalents.

[0159] Those skilled in the art will understand that the above embodiments are exemplary and not restrictive. Different technical features appearing in different embodiments can be combined to achieve beneficial effects. Based on a study of the drawings, specification, and claims, those skilled in the art should be able to understand and implement other variations of the disclosed embodiments. In the claims, the term "comprising" does not exclude other structures; the quantity refers to "one" but does not exclude multiple; the terms "first" and "second" are used to identify names and not to indicate any particular order. Any reference numerals in the claims should not be construed as limiting the scope of protection. The appearance of certain technical features in different dependent claims does not mean that these technical features cannot be combined to achieve beneficial effects.

[0160] This document uses specific examples to illustrate the principles and implementation methods of this application. The examples are merely for the purpose of helping to understand the method and core ideas of this application. The above are only preferred embodiments of this application. It should be noted that due to the limitations of written expression, and the existence of an infinite number of specific structures, those skilled in the art can make several improvements, modifications, or changes without departing from the principles of this application, and can also combine the above technical features in an appropriate manner. These improvements, modifications, changes, or combinations, or the direct application of the concept and technical solution of this application to other situations without modification, should all be considered within the scope of protection of this application.

Claims

1. A gate-induced voltage suppression circuit, characterized in that, The circuit includes: A gate driving module, wherein the input terminal of the gate driving module is electrically connected to the driving signal terminal, and the output terminal of the gate driving module is electrically connected to the gate of the target power device; A positive voltage regulator clamping module, wherein a first end of the positive voltage regulator clamping module is electrically connected to a first target node in the gate drive module, and a second end of the positive voltage regulator clamping module is electrically connected to a first power supply voltage terminal, for stabilizing the gate voltage of the target power device at the first power supply voltage during the non-conducting phase of the target power device; A positive voltage absorption module, wherein the first end of the positive voltage absorption module is electrically connected to the second target node in the gate driving module, and the second end of the positive voltage absorption module is electrically connected to the reference ground terminal, for absorbing the induced positive voltage spike of the gate of the target power device; A negative voltage clamping absorption module is provided, wherein a first end of the negative voltage clamping absorption module is electrically connected to the gate of the target power device, and a second end of the negative voltage clamping absorption module is electrically connected to the source of the target power device and the reference ground terminal, respectively, for clamping the induced negative voltage of the gate of the target power device within a preset safety range.

2. The circuit according to claim 1, characterized in that, The gate driving module includes: A forward conduction submodule is disposed between the drive signal terminal and the gate of the target power device to enable current flow from the drive signal terminal to the gate of the target power device. A reverse conduction submodule, which is connected in parallel with the forward conduction submodule, is used to enable current flow from the gate of the target power device to the drive signal terminal; The first target node is a node on the forward conduction submodule, and the second target node is a node on the reverse conduction submodule.

3. The circuit according to claim 2, characterized in that, The positive voltage stabilizing clamping module includes: An operational amplifier, wherein the first input terminal of the operational amplifier is electrically connected to the first power supply voltage terminal, and the second input terminal of the operational amplifier is electrically connected to the first target node; The first transistor has its control terminal electrically connected to the output terminal of the operational amplifier, its first terminal electrically connected to the second power supply voltage terminal, and its second terminal electrically connected to the first target node.

4. The circuit according to claim 3, characterized in that, The positive voltage stabilizing clamping module also includes: The first resistor has its first end electrically connected to the output terminal of the operational amplifier, and its second end electrically connected to the control terminal of the first transistor.

5. The circuit according to claim 2, characterized in that, The forward guidance submodule includes: The first diode has its anode electrically connected to the drive signal terminal and its cathode electrically connected to the first target node. The second resistor has a first end electrically connected to the first target node and a second end electrically connected to the gate of the target power device.

6. The circuit according to claim 5, characterized in that, The forward guidance submodule also includes: The third resistor is disposed between the driving signal terminal and the anode of the first diode, or the third resistor is disposed between the cathode of the first diode and the first target node; The second diode has its anode electrically connected to the second terminal of the second resistor and its cathode electrically connected to the gate of the target power device; or, the anode of the second diode is electrically connected to the first target node and its cathode is electrically connected to the first terminal of the second resistor.

7. The circuit according to claim 2, characterized in that, The reverse conduction submodule includes: The third diode has its cathode electrically connected to the drive signal terminal and its anode electrically connected to the gate of the target power device.

8. The circuit according to claim 7, characterized in that, The positive pressure absorption module includes: A fourth resistor, wherein the first end of the fourth resistor is electrically connected to the drive signal terminal, and the second end of the fourth resistor and the cathode of the third diode are electrically connected to the second target node; or, the first end of the fourth resistor and the anode of the third diode are electrically connected to the second target node, and the second end of the fourth resistor is electrically connected to the gate of the target power device. The second transistor has its control terminal electrically connected to the first terminal of the fourth resistor, its first terminal electrically connected to the second target node, and its second terminal electrically connected to the third power supply voltage terminal. A first capacitor, the first terminal of which is electrically connected to the second terminal of the second transistor, and the second terminal of which is electrically connected to the reference ground terminal.

9. The circuit according to claim 1, characterized in that, The negative pressure clamping absorption module includes a fourth diode and a first Zener diode connected in series; The cathode of the fourth diode is electrically connected to the gate of the target power device, the anode of the fourth diode is electrically connected to the anode of the first Zener diode, and the cathode of the first Zener diode is electrically connected to the source of the target power device and the reference ground terminal, respectively. Alternatively, the anode of the first Zener diode is electrically connected to the gate of the target power device, the cathode of the first Zener diode is electrically connected to the cathode of the fourth diode, and the anode of the fourth diode is electrically connected to the source of the target power device and the reference ground terminal, respectively.

10. A drive system, characterized in that, The driving system includes a driving chip and a gate-induced voltage suppression circuit as described in any one of claims 1-9, wherein the driving chip includes a driving signal terminal and a reference ground terminal; The driving system is used to drive the target power device and suppress the gate induced voltage of the target power device, wherein the target power device is the upper arm power device or the lower arm power device in the power bridge arm group.

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