Automatic repair type frequency source and implementation method thereof

Abstract

The invention discloses an automatic repair type frequency source and an implementation method thereof, and belongs to the technical field of radar communication and frequency synthesis. In order to solve the problems that after a traditional frequency source breaks down, the maintenance efficiency is low, and the shutdown loss of a system is large, a double-backup hardware architecture of two sets of phase-locked loops and two sets of radio frequency signal conditioning circuits is adopted, intelligent management of power supply and signal paths is achieved through a radio frequency switch network, and the working state of each assembly is collected in real time through a monitoring module; and the FPGA control unit executes an automatic repair action based on a locking detection signal and a level signal fed back by the monitoring module, so as to realize instant diagnosis and seamless switching of a fault. According to the invention, the fault repair time is shortened from several days in the prior art to milliseconds, the zero-shutdown operation of the system is realized, the economic loss of hundreds of thousands of yuan is effectively avoided by increasing the hardware cost of thousands of yuan, and the usability and maintainability of the high-reliability electronic system are remarkably improved.

Description

Technical Field

[0001] This invention relates to the fields of radar communication and frequency synthesis technology, specifically to an automatically repairing frequency source and its implementation method. Background Technology

[0002] Frequency sources, as the "heart" of modern electronic systems, provide stable and accurate reference clocks or carrier signals for the entire system. Their performance directly determines key indicators such as communication quality, radar ranging accuracy, and instrument measurement accuracy. In applications such as aerospace, defense, industrial control, and high-end communications, the reliability and stability of frequency sources are subject to extremely stringent requirements. A failure in a frequency source can lead to the paralysis or performance degradation of the entire complex electronic system, causing significant economic losses or even safety incidents.

[0003] Currently, most widely used traditional frequency sources employ a single modular design, consisting of a phase-locked loop (PLL) circuit paired with an RF signal conditioning circuit (typically including amplification and filtering functions). While this architecture is simple and low-cost, its inherent reliability bottleneck lies in the lack of effective redundancy backup and fault handling mechanisms. When the PLL inside the frequency source fails due to unlocking, component aging, or other reasons, or when the RF conditioning circuit experiences abnormal output due to malfunctions in components such as power amplifiers or filters, the entire frequency source fails.

[0004] The main challenges facing existing technologies lie in the post-fault handling process. First, fault detection relies on system-level functional anomalies or routine maintenance checks, making real-time detection impossible. Second, fault localization is difficult. When complex systems experience functional anomalies, maintenance personnel need to use specialized instruments (such as spectrum analyzers and frequency counters) to troubleshoot step-by-step to ultimately determine if the fault lies with the frequency source module itself. This process is cumbersome, highly dependent on personnel experience, and time-consuming, typically taking hours or even days. Third, fault repair efficiency is low. After confirming a frequency source fault, the entire module often needs to be removed from the system for repair or replacement. This series of processes—disassembly, rework, reinstallation, and debugging—further leads to prolonged system downtime.

[0005] For large industrial production lines, uninterrupted communication networks, or critical facilities, every second of system downtime translates into enormous economic losses or strategic risks. Statistics show that a single unplanned downtime can cause direct and indirect economic losses of hundreds of thousands or even millions of RMB to large enterprises. Therefore, a long-standing and pressing technical challenge within the industry is how to significantly improve the availability of frequency sources and achieve rapid, even instantaneous, fault repair without significantly increasing costs and system complexity, thereby ensuring the continuous and stable operation of critical systems.

[0006] Existing high-reliability designs typically focus on passive protection measures at the component level, such as derating, redundant power supplies, and environmental hardening, or on system-level cold backup solutions. The former cannot fundamentally prevent random failures, while the latter is costly, bulky, and involves complex switching logic. Currently, there is a lack of proactive repair solutions that target the frequency source module itself, can be integrated within the module, and achieve automatic fault detection, intelligent decision-making, and seamless switching. This is precisely the core technical problem that this invention aims to solve. Summary of the Invention

[0007] To address the technical problems of poor reliability, lengthy fault repair time, and severe system downtime losses associated with traditional frequency sources in existing technologies, this invention provides an automatically repairable frequency source and its implementation method. Through a built-in dual-backup hardware architecture and FPGA-based intelligent control logic, it achieves real-time monitoring of its own operating status. When a fault is detected, it can automatically, quickly, and accurately switch the signal path from the faulty component to the backup component, thereby completing fault repair without the user's awareness. This significantly improves system availability and reliability and effectively avoids huge economic losses caused by frequency source failures.

[0008] To achieve the above objectives, the technical solution adopted by the present invention is as follows: An automatically repairable frequency source includes: a reference clock source, a 1-to-2 power divider, a first phase-locked loop, a second phase-locked loop, a first radio frequency signal conditioning circuit, a second radio frequency signal conditioning circuit, a radio frequency switch network, a monitoring module, and an FPGA control unit. The output of the reference clock source is connected to the input of the 1-to-2 power divider, and the two outputs of the 1-to-2 power divider are respectively connected to the reference inputs of the first phase-locked loop and the second phase-locked loop. The radio frequency switch network is controlled by the FPGA control unit and is used to selectively conduct the power supply and output signal paths of the first phase-locked loop or the second phase-locked loop, and to selectively conduct the power supply and output signal paths of the first radio frequency signal conditioning circuit or the second radio frequency signal conditioning circuit. The monitoring module is used to monitor the working lock status of the first phase-locked loop and the second phase-locked loop in real time, as well as the output signal status of the first radio frequency signal conditioning circuit and the second radio frequency signal conditioning circuit, and to feed the monitoring signals back to the FPGA control unit. The FPGA control unit is used to receive the monitoring signal fed back by the monitoring module and output a control signal to the radio frequency switch network accordingly, so as to automatically switch to the backup phase-locked loop or radio frequency signal conditioning circuit when a fault is detected in the currently operating phase-locked loop or radio frequency signal conditioning circuit.

[0009] Specifically, the radio frequency switch network includes: The first analog switch is connected in series in the power supply circuit of the first phase-locked loop; The second analog switch is connected in series in the power supply circuit of the second phase-locked loop; The third analog switch is connected in series in the power supply circuit of the first radio frequency signal conditioning circuit; The fourth analog switch is connected in series in the power supply circuit of the second radio frequency signal conditioning circuit; The first single-pole double-throw switch has its first input terminal connected to the output terminal of the first phase-locked loop, its second input terminal connected to the output terminal of the second phase-locked loop, and its common output terminal connected to a signal node. The second single-pole double-throw switch has its common input terminal connected to the signal node, its first output terminal connected to the input terminal of the first radio frequency signal conditioning circuit, and its second output terminal connected to the input terminal of the second radio frequency signal conditioning circuit. The third single-pole double-throw switch has its first input terminal connected to the output terminal of the first radio frequency signal conditioning circuit, its second input terminal connected to the output terminal of the second radio frequency signal conditioning circuit, and its common output terminal serving as the radio frequency signal output terminal of the frequency source.

[0010] Specifically, the monitoring module includes: The first monitoring branch is used to acquire the first locking detection signal LD1 of the first phase-locked loop; The second monitoring branch is used to acquire the second locking detection signal LD2 of the second phase-locked loop; The third monitoring branch is used to monitor the output signal power of the first radio frequency signal conditioning circuit and output the first level signal LVTTL1. The fourth monitoring branch is used to monitor the output signal power of the second radio frequency signal conditioning circuit and output the second level signal LVTTL2.

[0011] Specifically, the third monitoring branch includes a first coupler, a first detector, and a first comparator connected in sequence. The input terminal of the first coupler is coupled to the output terminal of the first radio frequency signal conditioning circuit, and the first comparator outputs the first level signal LVTTL1 to the FPGA control unit. The fourth monitoring branch includes a second coupler, a second detector, and a second comparator connected in sequence. The input terminal of the second coupler is coupled to the output terminal of the second radio frequency signal conditioning circuit, and the second comparator outputs the second level signal LVTTL2 to the FPGA control unit.

[0012] Specifically, the reference voltage thresholds of the first comparator and the second comparator are set to be 1dB to 3dB lower than the normal output power of the corresponding radio frequency signal.

[0013] Specifically, the first phase-locked loop and the second phase-locked loop have the same model and configuration parameters; the first radio frequency signal conditioning circuit and the second radio frequency signal conditioning circuit have the same circuit topology and component parameters.

[0014] Specifically, the response time of the FPGA control unit from fault diagnosis to path switching is less than 200 milliseconds.

[0015] Based on the above structure, the present invention also provides a method for implementing the above-mentioned automatic repair frequency source, which is executed by the FPGA control unit and includes the following steps: S1. System power-on initialization, control the RF switch network to select the main path composed of the first phase-locked loop and the first RF signal conditioning circuit; S2. Real-time monitoring of the status monitoring signal of the main channel; S3. If the status monitoring signal indicates that it is normal, maintain the current status and return to S2; S4. If the status monitoring signal indicates a fault, determine the fault type; S5. Based on the fault type, control the RF switch network to start and switch to the corresponding backup circuit; S6. After confirming that the backup circuit is working properly, control the RF switch network to isolate the faulty circuit.

[0016] Specifically, in S4, the fault types include phase-locked loop faults and radio frequency signal conditioning circuit faults; In step S5, if a phase-locked loop (PLL) fault is detected, the RF switch network is controlled to power on the second PLL and switch its output signal path to the first RF signal conditioning circuit; if a RF signal conditioning circuit fault is detected, the RF switch network is controlled to power on the second RF signal conditioning circuit and switch the input and output signal paths to the second RF signal conditioning circuit.

[0017] Specifically, the status monitoring signal includes a first lock detection signal LD1 of the first phase-locked loop and a first level signal LVTTL1 representing the output power of the first radio frequency signal conditioning circuit. The FPGA control unit determines the fault type by judging the level combination of the first lock detection signal LD1 and the first level signal LVTTL1.

[0018] Compared with the prior art, the present invention has the following beneficial effects: (1) This invention adopts a dual-backup hardware architecture consisting of a first phase-locked loop, a second phase-locked loop, a first radio frequency signal conditioning circuit and a second radio frequency signal conditioning circuit, and uses a radio frequency switch network to realize the rapid switching of power supply and signal path, thereby shortening the repair time after frequency source failure from several days (≥2 days) required by traditional technology to milliseconds (<200ms), realizing zero downtime operation of the system and completely avoiding major economic losses caused by critical signal interruption.

[0019] (2) By setting up a monitoring module containing four independent monitoring branches, the present invention collects the phase-locked loop locking status signal (LD1, LD2) and the radio frequency output power level signal (LVTTL1, LVTTL2) in real time, and the FPGA control unit performs comprehensive judgment on the multiple signals, thereby realizing the instant and accurate location and classification of faults. This overcomes the disadvantages of traditional technology where fault diagnosis relies on manual labor and is inefficient, and significantly improves maintenance efficiency and automation level.

[0020] (3) The present invention uses an FPGA control unit to execute an optimized control algorithm, manage the RF switch network and monitoring module, and constructs a fully automatic closed-loop control link of "monitoring-judgment-execution". This makes the entire fault repair process free of any human intervention, which not only reduces the dependence on professional maintenance personnel, but also fundamentally eliminates the secondary risks caused by human subjective misjudgment or operation delay, and ensures the high reliability of the system.

[0021] (4) Although the present invention introduces dual backup components, the additional hardware cost is precisely controlled to the level of several thousand yuan through optimized system design and component selection. This limited increase in cost is extremely cost-effective compared to the system downtime loss of up to hundreds of thousands of yuan that can be avoided by a single failure, providing an excellent solution to the traditional contradiction between high reliability and economy. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the circuit structure of an embodiment of the present invention.

[0023] Figure 2 This is a schematic diagram of the control flow of an embodiment of the present invention.

[0024] In the above figures, the component names corresponding to the reference numerals are as follows: 1-Reference clock source; 2-1-to-2 power divider; 3-First phase-locked loop; 4-Second phase-locked loop; 5-First analog switch; 6-Second analog switch; 7-First single-pole double-throw switch; 8-First RF signal conditioning circuit; 9-Second RF signal conditioning circuit; 10-Third analog switch; 11-Fourth analog switch; 12-First coupler; 13-First detector; 14-First comparator; 15-Second single-pole double-throw switch; 16-Third single-pole double-throw switch; 17-FPGA control unit; 18-Second coupler; 19-Second detector; 20-Second comparator. Detailed Implementation

[0025] The present invention will be further described below with reference to the accompanying drawings and embodiments. The embodiments of the present invention include, but are not limited to, the following embodiments.

[0026] like Figures 1 to 2 As shown, the automatic repair frequency source includes a reference clock source 1, a 1-to-2 power divider 2, a first phase-locked loop (PLL) 3, a second PLL 4, a first radio frequency (RF) signal conditioning circuit 8, a second RF signal conditioning circuit 9, an RF switch network, a monitoring module, and an FPGA control unit 17 as the system control core. The first PLL 3, second PLL 4, first RF signal conditioning circuit 8, and second RF signal conditioning circuit 9 form a dual-backup architecture. The first PLL 3 and second PLL 4 have identical models and configuration parameters, used to generate RF signals with the same frequency and phase. The first RF signal conditioning circuit 8 and second RF signal conditioning circuit 9 have identical circuit topologies and component parameters, used to amplify, filter, and condition the signals output by the PLLs. The RF switch network includes a first analog switch 5, a second analog switch 6, a third analog switch 10, a fourth analog switch 11, a first single-pole double-throw (SPD) switch 7, a second SPD switch 15, and a third SPD switch 16.

[0027] The output of reference clock source 1 is connected to the input of a 1-to-2 power divider 2. The two outputs of the 1-to-2 power divider 2 are connected to the reference inputs of the first phase-locked loop 3 and the second phase-locked loop 4, respectively. A first analog switch 5 is connected in series in the power supply circuit of the first phase-locked loop 3 to control its power supply. A second analog switch 6 is connected in series in the power supply circuit of the second phase-locked loop 4 to control its power supply. The output of the first phase-locked loop 3 is connected to the first input of the first single-pole double-throw switch 7, and the output of the second phase-locked loop 4 is connected to the second input of the first single-pole double-throw switch 7. The common output of the first single-pole double-throw switch 7 is connected to a signal node, and through this signal node, it is connected to the common input of the second single-pole double-throw switch 15. The first output of the second single-pole double-throw switch 15 is connected to the input of the first radio frequency signal conditioning circuit 8, and the second output is connected to the input of the second radio frequency signal conditioning circuit 9. The third analog switch 10 is connected in series in the power supply circuit of the first RF signal conditioning circuit 8 to control its power supply. The fourth analog switch 11 is connected in series in the power supply circuit of the second RF signal conditioning circuit 9 to control its power supply. The output terminal of the first RF signal conditioning circuit 8 is connected to the first input terminal of the third single-pole double-throw switch 16, and the output terminal of the second RF signal conditioning circuit 9 is connected to the second input terminal of the third single-pole double-throw switch 16. The common output terminal of the third single-pole double-throw switch 16 serves as the RF signal output terminal of the entire frequency source. The RF switch network is controlled by the FPGA control unit 17 to selectively conduct the power supply and output signal paths of the first phase-locked loop 3 or the second phase-locked loop 4, and to selectively conduct the power supply and output signal paths of the first RF signal conditioning circuit 8 or the second RF signal conditioning circuit 9. Normally, the first phase-locked loop (PLL) and the first radio frequency (RF) signal conditioning circuit are selected as the primary path by default to output the RF signal normally. In this case, the second PLL and the second RF signal conditioning circuit serve as backup circuits. When a fault is detected in the first PLL, the second PLL is selected to be turned on and the first PLL is turned off to switch the circuit and ensure normal output of the RF signal. When a fault is detected in the first RF signal conditioning circuit, the second RF signal conditioning circuit is selected to be turned on and the first RF signal conditioning circuit is turned off to switch the circuit and ensure normal output of the RF signal.

[0028] The monitoring module is used to monitor the working lock status of the first phase-locked loop (PLL) and the second PLL in real time, as well as the output signal status of the first and second radio frequency (RF) signal conditioning circuits. Specifically, the monitoring module includes four monitoring branches: the first monitoring branch directly acquires the first lock detection signal LD1 of the first PLL 3 and outputs it to the FPGA control unit; the second monitoring branch directly acquires the second lock detection signal LD2 of the second PLL 4 and outputs it to the FPGA control unit; the third monitoring branch monitors the output signal power of the first RF signal conditioning circuit 8 and outputs a first-level signal LVTTL1 to the FPGA control unit; and the fourth monitoring branch monitors the output signal power of the second RF signal conditioning circuit 9 and outputs a second-level signal LVTTL2 to the FPGA control unit. The third monitoring branch is composed of a first coupler 12, a first detector 13, and a first comparator 14 connected in sequence. The input terminal of the first coupler 12 is coupled to the output terminal of the first RF signal conditioning circuit 8 to sample its output signal, which is then used by the first detector 13 and the first comparator 14 to generate the first-level signal LVTTL1 to the FPGA control unit. The fourth monitoring branch consists of a second coupler 18, a second detector 19, and a second comparator 20 connected in sequence. The input terminal of the second coupler 18 is coupled to the output terminal of the second RF signal conditioning circuit 9 to sample its output signal, which is then transmitted to the FPGA control unit via the second detector 19 and the second comparator 20 to generate a second level signal LVTTL2. The reference voltage thresholds of the first comparator 14 and the second comparator 20 are set to be 1dB to 3dB lower than the normal output power of the corresponding RF signal.

[0029] The FPGA control unit 17 receives monitoring signals from the aforementioned monitoring module and outputs control signals to the control terminals of all analog switches and single-pole double-throw switches in the RF switch network, thus forming a complete "monitoring-judgment-execution" closed-loop control system. Specifically, after receiving the first lock detection signal LD1, the second lock detection signal LD2, the first level signal LVTTL1, and the second level signal LVTTL2, the FPGA control unit determines whether a fault has occurred and the type of fault if it has occurred based on its built-in intelligent algorithm. Then, it outputs control signals to the control terminals of the corresponding analog switches and single-pole double-throw switches in the RF switch network to automatically switch to the corresponding backup circuit to ensure normal output of the RF signal. The response time of the FPGA control unit 17 from fault judgment to path switching is less than 200 milliseconds.

[0030] Based on the above-described structure of the self-healing frequency source, its implementation is executed by the FPGA control unit. The FPGA control unit can internally use a state machine written in Verilog HDL to achieve this. Figure 2 The control flow is shown below. Specifically, it includes the following steps: S1. System Power-On Initialization: After power-on, the FPGA control unit first initializes itself. Then, the FPGA control unit controls the first analog switch 5 and the third analog switch 10 to turn on, supplying power to the first phase-locked loop 3 and the first radio frequency signal conditioning circuit 8; simultaneously, it keeps the second analog switch 6 and the fourth analog switch 11 in the off state. The FPGA control unit controls the first single-pole double-throw switch 7, the second single-pole double-throw switch 15, and the third single-pole double-throw switch 16 to select the main path formed by the first phase-locked loop and the first radio frequency signal conditioning circuit. The internal counter of the FPGA control unit starts timing, delaying for a set time, such as 500ms, to ensure the stability of the main path.

[0031] S2. Real-time monitoring of the status monitoring signal of the main path. The FPGA control unit continuously monitors the first lock detection signal LD1 of the first phase-locked loop and the first level signal LVTTL1 that characterizes the output power of the first radio frequency signal conditioning circuit.

[0032] Judgment condition: IF (LD1 == 1'b1) AND (LVTTL1 == 1'b1) / / that is, both are high level. If the condition is true, it means that the main path is working normally, and jump to S3; if the condition is false, that is, either signal is low level, it means that the main path is faulty, and immediately jump to S4.

[0033] S3 indicates normal operation when the status monitoring signal is normal. In this state, the FPGA control unit maintains all current switch states and control signals unchanged. Simultaneously, it continuously executes S2 to monitor the main path status, achieving real-time monitoring.

[0034] S4. When the status monitoring signal indicates a fault, the FPGA control unit first determines the fault type, which includes phase-locked loop (PLL) faults and RF signal conditioning circuit faults. Specifically, the fault type is determined by judging the level combination of the first lock-in detection signal LD1 and the first level signal LVTTL1. The determination process is as follows: If (LD1 == 1'b0) AND (LVTTL1 == 1'b1), it is determined to be a phase-locked loop (PLL lost lock). If (LD1 == 1'b1) AND (LVTTL1 == 1'b0), the problem is identified as a fault in the RF signal conditioning circuit (insufficient power). If (LD1 == 1'b0) AND (LVTTL1 == 1'b0), it is determined to be a serious fault (both may be faulty or there may be a serious problem at the front end). The processing logic can be the same as a phase-locked loop fault or triggering the highest level alarm.

[0035] S5. Based on the fault type, control the RF switch network to start and switch to the corresponding backup circuit. Specifically, if the fault is determined to be a phase-locked loop (PLL) fault in S4, the FPGA control unit controls the second analog switch 6 to conduct, powering on the second PLL 4, and simultaneously controls the first single-pole double-throw switch 7 to switch to its second input terminal, connecting the second PLL and ensuring that the output signal path of the second PLL is to the first RF signal conditioning circuit. If the fault is determined to be a fault in the RF signal conditioning circuit in S4: the FPGA control unit controls the fourth analog switch 11 to conduct, powering on the second RF signal conditioning circuit 9, and simultaneously controls the second single-pole double-throw switch 15 to switch to its second output terminal and controls the third single-pole double-throw switch 16 to switch to its second input terminal, connecting the second RF signal conditioning circuit and ensuring that the input and output signal paths are to the second RF signal conditioning circuit.

[0036] S6. Confirmation and Isolation: The FPGA control unit monitors the status signal of the backup circuit (LD2 or LVTTL2). After confirming that it is normal, it disconnects the power supply to the faulty primary component (disables the first analog switch 5 or the third analog switch 10) to complete the isolation.

[0037] The following description uses a frequency source with an output frequency of 2.2 GHz as an example to illustrate the configuration of each component. However, the technical solution described in this invention is not limited to this specific frequency. By selecting components of the corresponding frequency band, this invention can also be applied to other frequency points, such as 100 MHz (as a high-precision clock reference), 1.5 GHz (GPS L1), 2.4 GHz (ISM), 3.5 GHz (5G), or higher frequency bands.

[0038] The FPGA control unit 17 uses a Xilinx Spartan-6 series XC6SLX9 chip to execute the control algorithm. Reference clock source 1 uses a 100MHz oven-controlled crystal oscillator (OCXO) with a phase noise of -160dBc / Hz@1kHz. The 1-to-2 power divider 2 uses a Mini-Circuits SBTC-2-10L+. The first phase-locked loop 3 and the second phase-locked loop 4 both use LMX2594RHAT chips, configured with the same register values, and output a 2.2GHz frequency. The first analog switch 5, the second analog switch 6, the third analog switch 10, and the fourth analog switch 11 all use ADG849YKSZ-REEL7 to control the switching of the +5V power supply line. The first single-pole double-throw switch 7, the second single-pole double-throw switch 15, and the third single-pole double-throw switch 16 all use HMC536MS8GE for high-frequency signal path switching, with a switching time of less than 30ns. The first RF signal conditioning circuit 8 and the second RF signal conditioning circuit 9 both include a single-stage PHA-1+ driver amplifier (Output Power @1dB compression 22dBm) and an LFCN-2500 low-pass filter (cutoff frequency 2.5GHz). The first coupler 12 and the second coupler 18 both use BDCA-10-25+ with a coupling of 10dB. The first detector 13 and the second detector 19 both use AD8318ACPZ-REEL7 logarithmic detectors. The first comparator 14 and the second comparator 20 both use MAX9010EXT high-speed comparators, whose reference voltage threshold is set so that when the RF output power is 2dB lower than the normal value (+17dBm) (i.e., +15dBm), the detection voltage is lower than the reference voltage, and the comparator outputs a low level.

[0039] Testing has shown that the above configuration fully achieves the intended effect of this invention. The test results are as follows: 1. Performance Specifications: Output frequency 2.2GHz, phase noise -110dBc / Hz@1kHz, output power 17dBm±0.5dB, frequency stability ≤±0.5ppm.

[0040] 2. Fault Response Performance: Simulating a phase-locked loop (PLL) fault, manually cutting off the power supply to the first PLL causes the LD1 signal to immediately go low. The FPGA detects LD1 going low within the next monitoring cycle (microseconds) and triggers the fault handling process. The system completes the switching (including PLL lockout time) within 50ms and resumes output, with an output interruption time of less than 1μs. It should be noted that the FPGA's response time from fault detection to path switching specifically refers to the electrical response time within the FPGA from detecting the fault signal transition, through logical judgment, to finally issuing all switching commands to the RF switching network. This time does not include the inherent lockout time and warm-up stabilization time of the backup components after power-on. Spectrum analysis shows that the output signal only experiences brief spikes at the moment of switching, and the frequency stability and power (≤±0.5ppm, ≤±0.5dB) are no different from before the switching. In the case of a fault in the simulated conditioning circuit, a strong interference signal is injected into the amplifier input of the first RF signal conditioning circuit, causing its output power to drop to 14dBm. The LVTTL1 signal immediately goes low. The FPGA detects that LVTTL1 is low and triggers the switching process. The system completes the switching within 50ms (including power-on stabilization time) and resumes output. The output interruption time is less than 100ns.

[0041] 3. Reliability verification: Continuous operation for 96 hours without failure, with a 100% switchover success rate.

[0042] 4. Economic benefits: The hardware cost (second PLL, conditioning circuit, switches, etc.) increases by less than 2,000 yuan. For a large production line that relies on this frequency source, avoiding a downtime of only two days can prevent an economic loss of about 400,000 yuan, making the return on investment extremely high.

[0043] Therefore, it can be seen that the present invention, through the hardware architecture and control method described above, successfully achieves automatic and rapid repair of frequency source faults, significantly improving the reliability and availability of the system.

[0044] The above embodiments are merely preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any changes made based on the design principles of the present invention, or any non-creative modifications made thereon, shall fall within the scope of protection of the present invention.

Claims

1. An automatically repairable frequency source, characterized in that, include: Reference clock source (1), one-to-two power divider (2), first phase-locked loop (3), second phase-locked loop (4), first radio frequency signal conditioning circuit (8), second radio frequency signal conditioning circuit (9), radio frequency switch network, monitoring module and FPGA control unit (17). The output of the reference clock source (1) is connected to the input of the 1-to-2 power divider (2), and the two outputs of the 1-to-2 power divider (2) are respectively connected to the reference inputs of the first phase-locked loop (3) and the second phase-locked loop (4); The radio frequency switch network is controlled by the FPGA control unit (17) for selectively turning on the power supply and output signal paths of the first phase-locked loop (3) or the second phase-locked loop (4), and selectively turning on the power supply and output signal paths of the first radio frequency signal conditioning circuit (8) or the second radio frequency signal conditioning circuit (9). The monitoring module is used to monitor the working lock status of the first phase-locked loop (3) and the second phase-locked loop (4) in real time, as well as the output signal status of the first radio frequency signal conditioning circuit (8) and the second radio frequency signal conditioning circuit (9), and feed the monitoring signal back to the FPGA control unit (17). The FPGA control unit (17) is used to receive the monitoring signal fed back by the monitoring module and output a control signal to the radio frequency switch network accordingly, so as to automatically switch to the backup phase-locked loop or radio frequency signal conditioning circuit when a fault is detected in the currently operating phase-locked loop or radio frequency signal conditioning circuit.

2. The self-healing frequency source according to claim 1, characterized in that, The radio frequency switch network includes: The first analog switch (5) is connected in series in the power supply circuit of the first phase-locked loop (3); The second analog switch (6) is connected in series in the power supply circuit of the second phase-locked loop (4); The third analog switch (10) is connected in series in the power supply circuit of the first radio frequency signal conditioning circuit (8); The fourth analog switch (11) is connected in series in the power supply circuit of the second radio frequency signal conditioning circuit (9); The first single-pole double-throw switch (7) has its first input terminal connected to the output terminal of the first phase-locked loop (3), its second input terminal connected to the output terminal of the second phase-locked loop (4), and its common output terminal connected to a signal node. The second single-pole double-throw switch (15) has its common input terminal connected to the signal node, its first output terminal connected to the input terminal of the first radio frequency signal conditioning circuit (8), and its second output terminal connected to the input terminal of the second radio frequency signal conditioning circuit (9). The third single-pole double-throw switch (16) has its first input terminal connected to the output terminal of the first radio frequency signal conditioning circuit (8), its second input terminal connected to the output terminal of the second radio frequency signal conditioning circuit (9), and its common output terminal serving as the radio frequency signal output terminal of the frequency source.

3. The self-healing frequency source according to claim 1, characterized in that, The monitoring module includes: The first monitoring branch is used to acquire the first locking detection signal LD1 of the first phase-locked loop (3); The second monitoring branch is used to acquire the second locking detection signal LD2 of the second phase-locked loop (4); The third monitoring branch is used to monitor the output signal power of the first radio frequency signal conditioning circuit (8) and output the first level signal LVTTL1; The fourth monitoring branch is used to monitor the output signal power of the second radio frequency signal conditioning circuit (9) and output the second level signal LVTTL2.

4. The self-healing frequency source according to claim 3, characterized in that, The third monitoring branch includes a first coupler (12), a first detector (13) and a first comparator (14) connected in sequence. The input terminal of the first coupler (12) is coupled to the output terminal of the first radio frequency signal conditioning circuit (8), and the first comparator (14) outputs the first level signal LVTTL1 to the FPGA control unit (17). The fourth monitoring branch includes a second coupler (18), a second detector (19), and a second comparator (20) connected in sequence. The input of the second coupler (18) is coupled to the output of the second radio frequency signal conditioning circuit (9), and the second comparator (20) outputs the second level signal LVTTL2 to the FPGA control unit (17).

5. The self-healing frequency source according to claim 4, characterized in that, The reference voltage thresholds of the first comparator (14) and the second comparator (20) are set to be 1dB to 3dB lower than the normal output power of the corresponding radio frequency signal.

6. The self-healing frequency source according to claim 1, characterized in that, The first phase-locked loop (3) and the second phase-locked loop (4) have the same model and configuration parameters; the first radio frequency signal conditioning circuit (8) and the second radio frequency signal conditioning circuit (9) have the same circuit topology and component parameters.

7. The self-correcting frequency source according to any one of claims 1-6, characterized in that, The FPGA control unit (17) completes the response time from fault diagnosis to path switching in less than 200 milliseconds.

8. The method for implementing the automatic repair frequency source as described in any one of claims 1-7, characterized in that, Executed by the FPGA control unit, the following steps are included: S1. System power-on initialization, control the RF switch network to select the main path composed of the first phase-locked loop and the first RF signal conditioning circuit; S2. Real-time monitoring of the status monitoring signal of the main channel; S3. If the status monitoring signal indicates that it is normal, maintain the current status and return to S2; S4. If the status monitoring signal indicates a fault, determine the fault type; S5. Based on the fault type, control the RF switch network to start and switch to the corresponding backup circuit; S6. After confirming that the backup circuit is working properly, control the RF switch network to isolate the faulty circuit.

9. The method for implementing the automatic repair frequency source according to claim 8, characterized in that, In S4, the fault types include phase-locked loop faults and radio frequency signal conditioning circuit faults; In step S5, if a phase-locked loop (PLL) fault is detected, the RF switch network is controlled to power on the second PLL and switch its output signal path to the first RF signal conditioning circuit; if a RF signal conditioning circuit fault is detected, the RF switch network is controlled to power on the second RF signal conditioning circuit and switch the input and output signal paths to the second RF signal conditioning circuit.

10. The method for implementing the automatic repair frequency source according to claim 8, characterized in that, The status monitoring signal includes a first lock detection signal LD1 of the first phase-locked loop and a first level signal LVTTL1 that characterizes the output power of the first radio frequency signal conditioning circuit. The FPGA control unit determines the fault type by judging the level combination of the first lock detection signal LD1 and the first level signal LVTTL1.

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