Digital integral pixel circuit and reading circuit of infrared focal plane

Abstract

The invention discloses a digital integral pixel circuit and a reading circuit of an infrared focal plane, and the pixel circuit is a digital integral pixel circuit based on an analog counter, and is composed of a photocurrent source, an injection transistor, an integrating capacitor, a comparator, the analog counter, a charge packet deduction circuit and a row selection switch. And the pixel outputs the output voltage of the analog counter and the residual voltage of the integration node. The reading circuit is a single-channel ADC time-division quantization method based on the time division multiplexing technology and a dual-channel parallel ADC synchronous quantization scheme based on the time division multiplexing technology. The analog counter has the advantages of being small in area and low in power consumption, counting of the analog counter is integrated in the pixel circuit based on the digital integration technology, possibility is provided for implementation of a small-size digital integration pixel circuit, and the analog counter has the advantage in the aspect of low power consumption. And a new thought is provided for miniaturization and high-performance development of the infrared detector. The residual voltage of the integral node is precisely quantized, quantization noise can be reduced, and the charge resolution is improved.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, specifically relating to a digital integration pixel circuit and readout circuit for an infrared focal plane, and more particularly to a digital integration readout circuit for an infrared focal plane suitable for small-pitch pixels. Background Technology

[0002] The readout circuit is one of the core components of an infrared imaging system. Its main functions are twofold: first, to provide stable bias voltages to each pixel of the detector and process the photoelectric signals; and second, to read out the photoelectric signals from the detector in a specific order and transmit them to the imaging processing circuit. The readout circuit is directly connected to the detector, and the detector's performance is reflected through the readout circuit. The charge capacity of the readout circuit refers to the maximum amount of charge it can effectively receive, store, and convert within a single integration cycle. It determines the circuit's ability to handle photoelectric signals and affects the dynamic range, sensitivity, and other performance characteristics of the infrared detector. The charge capacity of the readout circuit is directly related to the pixel design; the integration technique used by the pixel determines the upper limit of the charge capacity. Pixel circuits using analog integration integrate the current signal output by the detector, buffer and output the resulting voltage signal, and then amplify and perform analog-to-digital processing in the column stage or output stage circuit. The charge capacity of an analog integration pixel circuit can be written as: , It is an in-pixel integrating capacitor. Let be the voltage swing of the integration node. As shown in the equation above, the capacitance size within a pixel and the power supply voltage limit the charge capacity, resulting in a lower dynamic range and limited sensitivity of the detector.

[0003] Figure 1 This is a circuit architecture diagram for a digital pixel using digital integration. In the digital pixel readout circuit, row and column multiplexing and transmission of photoelectric signals are performed in the digital domain, which improves signal transmission quality and avoids interference between signals. Figure 2 This is a traditional digital integration pixel circuit diagram. A digital pixel circuit using digital integration is a pixel-level ADC circuit that realizes photoelectric flux conversion in an image sensor. It completes the extraction, quantization, and integration of photoelectric signals within the pixel, and the pixel directly outputs a digital signal. Figure 3The timing diagram is shown below. When the integration period begins, the readout unit circuit injects the photocurrent output from the detector into the integrating capacitor for integration. When the integrating voltage equals the comparator's reference voltage Vref, the comparator flips to output a high level. The charge deduction circuit deducts a certain amount of charge from the integrating capacitor, resetting the voltage at the integration node to Vrst. The comparator outputs a low level, and simultaneously, the comparator's output pulse sends a count to the digital counter. This process is repeated until the integration period ends, and the final count value of the counter is the pixel's output signal. The core of the digital integrating pixel circuit lies in converting the traditional analog domain integration process into a multiple digital domain integration process. Its charge capacity can be written as: , N represents the number of bits in the digital counter. Compared to analog integrating pixel circuits, the charge processing capacity is increased through multiple integration and accumulation, thereby improving the detector's dynamic range and temperature sensitivity. Traditional digital integrating pixel circuits use digital counters, which employ multiple cascaded D flip-flops to form the counter, resulting in a large layout area. Furthermore, the digital counter needs to drive multiple stages of flip-flops to switch at full swing voltage during the counting process, leading to high dynamic power consumption.

[0004] The literature "A Large Dynamic Range, High Sensitivity Infrared Focal Plane Digital Pixel Readout Circuit Technology" (Chen Nan et al., Infrared and Laser Engineering, 2022, Issue 03) points out that digital integrating pixel circuits have advantages in terms of maximum charge storage capacity. However, the digital counter and memory in the pixel occupy about 4 / 5 of the entire pixel area, resulting in a large pixel layout area. This indicates that, under conventional processes, digital integrating technology is difficult to apply to small-pitch infrared focal planes. Furthermore, if a conventional 0.18μm standard CMOS process is used, the integrating capacitor is in the fF range, resulting in a charge capacity in the tens of thousands of electrons range and low charge resolution. While advanced processes can reduce the area and improve charge resolution, they cannot reduce the ADC counting frequency, cannot solve the problem of high dynamic power consumption, and significantly increase costs. Therefore, the widespread application of digital integrating pixel circuits in large-area, small-pixel infrared detectors has become an urgent problem to be solved.

[0005] Analog counters count by incrementing analog voltages, requiring only a small number of transistors and capacitors, resulting in a small layout area. During operation, the output voltage increments by only one voltage step, leading to low power consumption. Therefore, compared to digital counters, analog counters are more suitable for circuits with high requirements for area and power consumption. However, analog counters are susceptible to noise, have low accuracy, weak noise immunity, and limited counting bit width, which may lead to insufficient charge resolution in single-step pixel circuits. Therefore, the digital integration technology based on analog counters proposed in this invention needs to be combined with a two-step column-level ADC architecture to improve spatial resolution, dynamic range, charge resolution, and reduce power consumption, driving the development of readout circuits towards higher integration, lower power consumption, and stronger environmental adaptability. Summary of the Invention

[0006] The purpose of this invention is to provide an infrared focal plane digital integration pixel circuit and readout circuit, which can solve the problems of low integration density, high power consumption and insufficient charge resolution of existing digital integration readout circuits, and at the same time solve the problem of limited dynamic range of small-size analog integration readout circuits.

[0007] To achieve the above objectives, the present invention provides the following technical solution: An infrared focal plane digital integration readout circuit employs a time-division quantization method using a single-channel ADC with time-division multiplexing technology and a synchronous quantization method using a dual-channel parallel ADC architecture.

[0008] The pixel circuit is a digital integrating pixel circuit based on an analog counter. The injection stage uses direct injection (DI), which offers advantages such as simple structure, small footprint, and low power consumption. The integrating capacitor uses a MOS capacitor, which, compared to MIM capacitors, can achieve a larger capacitance value within a limited area. The comparator uses a 5-transistor OTA amplifier, which can balance the effects of area, bandwidth, power consumption, and noise, providing better matching. The analog counter can be implemented using a switched current source and charge transfer method, mainly composed of switches and capacitors. Compared to digital counters, it has a smaller area and lower power consumption, which is beneficial for applications in large-area arrays and small-pitch infrared focal plane arrays.

[0009] The time-division multiplexing ADC quantization scheme structure connects the pixel output signals Vcnt and Vrsd to the two input channels of a 2-to-1 multiplexer, achieving dynamic switching of the signal path through time-division multiplexing control. The output of this multiplexer is cascaded with the analog input of the first-stage analog-to-digital converter (ADC1) unit, sharing the same ADC resources using a time-division multiplexing mechanism, thereby enabling digital sampling and quantization of two analog signals.

[0010] The synchronous quantization scheme of the parallel ADC architecture is a fully parallel quantization architecture composed of pixel output signals and dual-channel ADC circuits. The pixel output signal is divided into two independent analog signal channels, which are respectively connected to the analog input terminals of the second-stage analog-to-digital converter (ADC2) unit and the third-stage analog-to-digital converter (ADC3) unit to achieve parallel quantization processing of the two signals. The lower N bits of the ADC3 output data for quantizing the residual voltage are used, and the higher M bits of the ADC2 output data for quantizing the analog counter output voltage are used.

[0011] The beneficial effects of this invention include: (1) The two-step digital integration pixel circuit based on an analog counter proposed in this invention significantly improves the charge processing capacity compared with an analog integration pixel circuit of the same pixel size by employing digital integration technology. Due to the small area and low power consumption of the analog counter, this structure can reduce the pixel layout area and power consumption compared with traditional digital pixel circuits. The reduction in pixel layout area is beneficial to improving the spatial resolution of the infrared detector, while the reduction in pixel power consumption makes it more suitable for widespread application in large-area infrared detectors. Furthermore, the secondary quantization processing of the residual voltage at the integration node helps reduce quantization noise, improve charge resolution, and thus improve the detector's sensitivity and signal-to-noise ratio. (2) The single-channel ADC time-division quantization method based on time-division multiplexing technology of the present invention optimizes hardware resource configuration through timing control, improves system integration, and helps reduce power consumption. The first column-level analog-to-digital converter ADC1 unit with N-bit quantization precision is used to achieve an output with 2N-bit effective resolution. Compared with the traditional direct conversion scheme with 2N-bit quantization precision, this architecture reduces the system clock frequency from an exponential growth mode with resolution to a linear growth mode, thereby improving the dynamic power consumption characteristics of the conversion system by orders of magnitude while maintaining high conversion accuracy; (3) The synchronous quantization method of the dual-channel parallel ADC architecture of the present invention adopts a space-for-time strategy, and eliminates the time deviation of the time-division multiplexing architecture by establishing dual quantization channels, thereby improving the quantization speed and efficiency of the ADC. Attached Figure Description

[0012] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments of the present invention will be briefly described below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0013] Figure 1 This is a traditional digital pixel readout circuit architecture diagram. In the diagram: 1-Digital pixel circuit, 2-Row multiplexer circuit, 3-Column multiplexer circuit.

[0014] Figure 2 This is a traditional digital integrating pixel circuit diagram. In the diagram: 101-Diode, 102-Transistor, 103-Switch, 104-Integrating capacitor, 105-Comparator, 106-Charge packet deduction circuit, 107-Digital counter, 108-Switch.

[0015] Figure 3 This is a timing diagram for a traditional digital pixel circuit.

[0016] Figure 4 The diagram shows the two-step digital integration pixel circuit based on an analog counter. In the diagram: 401-first photodiode, 402-first injection transistor, 403-first switch controlling the integration process, 404-first integration capacitor, 405-first comparator, 406-first charge packet deduction circuit, 407-analog counter, 408-second row selection switch, 409-third row selection switch.

[0017] Figure 5 This is a schematic diagram of an infrared focal plane digital integration readout circuit according to the present invention. It adopts a time-division multiplexing ADC time-division quantization architecture. In the figure: 4-digital integration pixel unit based on analog counter, 5-first row multiplexer circuit, 6-two-to-one selector circuit, 7-first column-level analog-to-digital converter ADC1 unit, 8-first column multiplexer circuit.

[0018] Figure 6 This is a schematic diagram of an infrared focal plane digital integration readout circuit according to the present invention. It adopts a parallel ADC synchronous quantization architecture. In the figure: 4-digital integration pixel unit based on analog counter, 10-second column-level analog-to-digital converter ADC2 unit, 11-third column-level analog-to-digital converter ADC3 unit, 12-second column multiplexer circuit.

[0019] Figure 7 The timing diagram is shown for the two-step digital integration pixel circuit based on the analog counter. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to specific embodiments and the accompanying drawings. Obviously, the drawings described below are only a part of the embodiments of this invention, and not all of them. Based on the embodiments of this invention, those skilled in the art can obtain other embodiments without creative effort, and all of these fall within the protection scope of this invention.

[0021] like Figure 4As shown, a two-step digital integration pixel circuit based on an analog counter mainly consists of a first photodiode 401, a first injection transistor 402, a first switch 403 for controlling the integration process, a first integration capacitor 404, a first comparator 405, a first charge packet deduction circuit 406, an analog counter 407, a second row selection switch 408, and a third row selection switch 409.

[0022] One end of the first photodiode 401 is connected to the source of the first injection transistor 402, and the other end is connected to the power supply voltage. The drain of the first injection transistor 402 is connected to the source of the first switch 403 that controls the integration process. The drain of the first switch 403 is connected to the lower plate of the first integrating capacitor 404. The positive input of the first comparator 405 is connected to the lower plate of the first integrating capacitor, the negative input is connected to the reference voltage Vref, and the output is connected to the input of the analog counter. One end of the charge deduction circuit 406 is connected to the output of the first comparator 405, and the other end is connected to the integration node. The input of the analog counter 407 is connected to the output of the first comparator 405, and the output is connected to the second row selection switch 408. The second row selection switch 408 is connected to the output of the analog counter 407, and the third row selection switch 409 is connected to the integration node.

[0023] The first switch 403 controls the start and end of the integration process. When the INT signal is low, the switch is on; otherwise, it is off. The first integrating capacitor 404 integrates the input optical signal. When the optical signal shines on the first photodiode 401, a photocurrent proportional to the light intensity is generated. The photocurrent is integrated through the first integrating capacitor 404, accumulating the current signal into a voltage signal. The first comparator 405 compares the voltage on the first integrating capacitor 404 with the reference voltage Vref. When the integrated voltage reaches the reference voltage Vref, the first comparator 405 outputs a high-level narrow pulse. The analog counter 407 counts the signal pulses output by the first comparator 405. For each narrow pulse output by the first comparator 405, the voltage on the analog counter 407 increases by one step. The row selection second switch 408, after the integration process is completed, is controlled to turn on via the RD signal, thereby transmitting the output voltage Vcnt of the analog counter 407 to the column bus. The function of the row selection third switch 409 is to control the row selection third switch 409 to be turned on after integration is completed, thereby outputting the residual voltage Vrsd of the integration node to the column bus.

[0024] Its working principle is as follows: When incident light shines on the first photodiode 401, photons are absorbed and converted into electron-hole pairs. Under the influence of the built-in electric field, these electron-hole pairs form a photocurrent I. pdThe photocurrent accumulates charge on the first integrating capacitor 404, resulting in a voltage signal Vint, which is proportional to the light intensity. When Vint increases to a level higher than the reference voltage Vref of the first comparator 405, the first comparator 405 flips and outputs a high-level narrow pulse. The charge deduction circuit deducts a certain amount of charge from the first integrating capacitor, Vint decreases, and the first comparator 405 outputs a low level. The high-level narrow pulse signal output by the first comparator 405 serves as the input pulse for the analog counter 407, enabling counting in the analog domain. After integration in each frame, the second row selection switch 408 and the third row selection switch 409 are opened. The output voltage of the analog counter 407 and the residual voltage of the integration node are output to the column-level analog-to-digital converter circuit to obtain a digital signal value. By repeating the above process, the integration, quantization, and output of the photocurrent can be completed within each frame period.

[0025] like Figure 5 As shown, an infrared focal plane digital integration readout circuit based on a time-division multiplexed quantization ADC mainly includes a pixel unit array 4, a first row multiplexer circuit 5, a 2-to-1 selector circuit 6, a first column-level analog-to-digital converter ADC1 unit 7, and a first column multiplexer circuit 8.

[0026] The first row multiplexer circuit 5 is connected to the pixel unit array 4, and its function is to provide relevant timing signals to the pixel unit array 4. The output of the pixel unit array 4 is connected to the 2-to-1 selector circuit 6, and its function is to time-division select the output voltages Vout_rsd and Vout_cnt of the pixels. The output of the 2-to-1 selector circuit 6 is connected to the first column-level analog-to-digital converter (ADC1) unit 7, and its function is to time-division convert the output voltages Vout_rsd and Vout_cnt of the pixels to digital values. The output of the first column-level ADC1 unit 7 is connected to the first column multiplexer circuit 8, and its function is to convert the parallel data output by the ADC to serial and multiplex it to obtain a digital output value.

[0027] A time-division multiplexing ADC time-division quantization architecture is adopted. The output voltage Vout_cnt and residual voltage Vout_rsd of the in-pixel analog counter are respectively connected to the two input channels of a 2-to-1 multiplexer. When the control signal of the MUX is high, the output voltage of the analog counter is used as the input of the ADC, and the digital value N1 of voltage Vout_cnt is obtained by quantization. When the control signal of the MUX is low, the residual voltage of the integrator node in the pixel is used as the input of the ADC, and the digital value N2 of voltage Vout_rsd is obtained by quantization. In the output data, N2 is in the low N bits and N1 is in the high N bits. This quantization method uses a time-division multiplexing mechanism to share the same ADC resource, thereby realizing the digital sampling and quantization of two analog signals. This architecture optimizes hardware resource configuration through timing control, improves system integration, and helps reduce power consumption. In addition, this solution uses an ADC with N-bit quantization precision to achieve an output with 2N-bit effective resolution. Compared to traditional direct conversion schemes with 2N-bit quantization precision, this architecture reduces the system clock frequency requirement from an exponential growth rate with resolution to a linear growth rate, thereby improving the dynamic power consumption characteristics of the conversion system by orders of magnitude while maintaining high conversion precision.

[0028] like Figure 6 As shown, an infrared focal plane digital integration readout circuit based on a parallel quantization ADC mainly includes a pixel unit array 4, a second row multiplexer circuit 9, a second column-level analog-to-digital converter (ADC2) unit 10, a third column-level ADC3 unit 11, and a second column multiplexer circuit 12.

[0029] The second row multiplexer circuit 9 is connected to the pixel unit array 4, providing relevant timing signals for the pixel unit array 4. The output voltage Vout_cnt of the pixel unit array 4 is connected to the second column-level analog-to-digital converter (ADC2) unit 10, performing analog-to-digital conversion on Vout_cnt to output a digital value. The output voltage Vout_rsd of the pixel unit array 4 is connected to the third column-level ADC3 unit 11, performing analog-to-digital conversion on Vout_rsd to output a digital value. The outputs of the second column-level ADC2 unit 10 and the third column-level ADC3 unit 11 are connected to the second column multiplexer circuit 12, combining, converting from parallel to serial, and multiplexing the parallel data output from the third column-level ADC3 unit 11 and the second column multiplexer circuit 12 to obtain a digital output value. The lower N bits of the ADC3 output data (quantizing the residual voltage) and the higher M bits of the ADC2 output data (quantizing the analog counter output voltage) are used to quantize the ADC3 output data. This method trades space for time, eliminating the time bias of the time-division multiplexing architecture by establishing dual quantization channels, thereby improving the quantization speed and efficiency of the ADC.

[0030] like Figure 7The following is a timing diagram of the two-step digital integrating pixel circuit based on an analog counter. At the start of integration, the INT signal controls the first switch 403 to turn on, and the current begins to integrate across the first integrating capacitor. When the integrating voltage Vint increases to the reference voltage Vref of the first comparator, the first comparator flips, outputting a high-level narrow pulse. The charge deduction circuit deducts a certain amount of charge, resetting the voltage Vint at the integrating node to Vrst, and the first comparator outputs a low level. Each high-level narrow pulse output by the first comparator causes the analog counter to count once, incrementing the voltage value. To ensure counting accuracy, the voltage increment of the analog counter must remain consistent each time it counts. In other words, the digital integrating pixel circuit based on the analog counter requires the analog counter to have high linearity performance. After integration, the RD signal controls the second row selection switch 408 and the third row selection switch 409 to turn on. Using a time-division multiplexed ADC architecture, the pixel output signal is selected by the MUX and quantized by the ADC. The quantized result of the output voltage of the analog counter within the pixel is N1, and the quantized result of the residual voltage at the integrating node is N2. The circuit employs a parallel ADC architecture, where the two signals output by a pixel are quantized by ADC2 and ADC3 respectively, and analog-to-digital conversion is performed simultaneously to obtain the corresponding counting result value.

[0031] It should be noted that the above embodiments only illustrate preferred embodiments of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be pointed out that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this patent should be determined by the appended claims.

Claims

1. A digital integrating pixel circuit for an infrared focal plane, characterized in that, The system includes a first photodiode (401), a first injection transistor (402), a first switch (403) controlling the integration process, a first integrating capacitor (404), a first comparator (405), a first charge packet deduction circuit (406), an analog counter (407), a second row selection switch (408), and a third row selection switch (409). The first photodiode (401) is connected to the source of the first injection transistor (402). The drain of the first injection transistor (402) is connected to the source of the first switch (403) controlling the integration process. The drain of the first switch (403) is connected to the lower plate of the first integrating capacitor (404). The positive input terminal of the first comparator (405) is connected to the lower plate of the first integrating capacitor, and the negative input terminal is connected to the reference voltage Vref. The output... The input terminal of the analog counter is connected to the input terminal of the analog counter; one end of the charge deduction circuit (406) is connected to the output of the first comparator (405), and the other end is connected to the integration node; the input terminal of the analog counter (407) is connected to the output terminal of the first comparator (405), and the output terminal is connected to the row selection second switch (408); the row selection second switch (408) is connected to the output of the analog counter (407). After the integration process is completed, the second switch (408) is turned on by the RD signal, thereby transmitting the output voltage Vcnt of the analog counter (407) to the column bus; the row selection third switch (409) is connected to the integration node. After the integration is completed, the row selection third switch (409) is turned on by the RD signal, thereby outputting the residual voltage Vrsd of the integration node to the column bus.

2. The digital integrating pixel circuit for the infrared focal plane according to claim 1, characterized in that, The analog counter (407) is based on the charging and discharging principle of a capacitor and realizes the counting function by simulating voltage increment.

3. The digital integrating pixel circuit for the infrared focal plane according to claim 1, characterized in that, The first switch (403) is used to control the start and end of the integration process. When the INT signal is low, the switch is turned on, and vice versa.

4. The digital integrating pixel circuit for the infrared focal plane according to claim 1, characterized in that, The first integrating capacitor (404) is used to integrate the input optical signal. When the optical signal shines on the first photodiode (401), a photocurrent proportional to the light intensity is generated. The photocurrent is integrated through the first integrating capacitor (404) to accumulate the current signal into a voltage signal.

5. The digital integrating pixel circuit for the infrared focal plane according to claim 1, characterized in that, The first comparator (405) is used to compare the voltage on the first integrating capacitor (404) with the reference voltage Vref. When the integrated voltage reaches the reference voltage Vref, the first comparator (405) outputs a high-level narrow pulse.

6. The digital integrating pixel circuit for the infrared focal plane according to claim 1, characterized in that, The analog counter (407) is used to count the signal pulses output by the first comparator (405); for each narrow pulse output by the first comparator (405), the voltage on the analog counter (407) increases by one step value.

7. The digital integrating pixel circuit for the infrared focal plane according to claim 1, characterized in that, The row selection second switch (408) is used to control the second switch (408) to turn on through the RD signal after the integration process is completed, so as to transmit the output voltage Vcnt of the analog counter (407) to the column bus; the row selection third switch (409) is used to control the row selection third switch (409) to turn on through the RD signal after the integration is completed, so as to output the residual voltage Vrsd of the integration node to the column bus.

8. A readout circuit for a digital integrating pixel circuit of an infrared focal plane according to any one of claims 1-7, characterized in that, It includes several pixel unit arrays (4), a first row multiplexer circuit (5), a 2-to-1 selector circuit (6), a first column-level analog-to-digital converter (ADC1) unit (7), and a first column multiplexer circuit (8). The analog output of each pixel unit array (4) is selected row by row to the corresponding first column-level analog-to-digital converter (ADC1) unit (7) under the control of the row selection signal RD. The pixel output signals Vcnt and Vrsd are respectively connected to the two input channels of the 2-to-1 selector circuit (6), and the dynamic switching of the signal path is realized by the time-division multiplexing control method. The output terminal of the 2-to-1 selector circuit (6) and the analog input terminal of the first column-level analog-to-digital converter (ADC1) unit (7) form a cascade structure, and share the same ADC resource by using the time-division multiplexing mechanism to realize the digital sampling and quantization of two analog signals. The first column-level analog-to-digital converter (ADC1) unit (7) realizes the output of 2N-bit effective resolution.

9. A readout circuit for a digital integrating pixel circuit of an infrared focal plane according to any one of claims 1-7, characterized in that, The system includes a pixel unit array (4), a second row multiplexing circuit (9), a second column-level analog-to-digital converter (ADC2) unit (10), a third column-level analog-to-digital converter (ADC3) unit (11), and a second column multiplexing circuit (12). It is a fully parallel quantization architecture composed of pixel output signals Vout_cnt, Vout_rsd, and dual-channel ADC circuits. The pixel output signal is divided into two independent analog signal channels, which are connected to the analog input terminals of the second column-level analog-to-digital converter (ADC2) unit (10) and the third column-level analog-to-digital converter (ADC3) unit (11) respectively, to realize parallel quantization processing of the two signals. The third column-level analog-to-digital converter (ADC3) unit (11) outputs the low N bits of the residual voltage and the second column-level analog-to-digital converter (ADC2) unit (10) outputs the high M bits of the voltage output by the analog counter.

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