Error correction method, device and equipment based on low-density parity check code

Abstract

The invention discloses an error correction method, device and equipment based on a low-density parity check code, and relates to the technical field of data error correction. In the error correction method, when data error correction is carried out based on the low-density parity check code, if a conflict variable node exists in variable nodes specified by a first target row and a second target row of a check matrix, the data error correction is carried out; when the number of the variable nodes specified by the first target row is larger than that of the variable nodes specified by the second target row, reading a first group of variable nodes specified by the first target row, calculating the first group of variable nodes based on a verification equation specified by the first target row, and updating the first group of variable nodes in the updating process of the first group of variable nodes; and reading a second group of variable nodes specified by a second target row. Due to the fact that the number of the second set of variable nodes is smaller than that of the first set of variable nodes, in the updating process of the first set of variable nodes, the second set of variable nodes can be read in parallel only by waiting for the conflict variable nodes to be updated, and therefore the error correction efficiency can be improved.

Description

Technical Field

[0001] This application relates to the field of data error correction technology, and in particular to error correction methods, apparatus and devices based on low-density parity-check codes. Background Technology

[0002] Low-Density Parity-Check (LDPC) codes are widely used due to their strong error correction capabilities. When performing data error correction based on LDPC codes, different rows of the parity-check matrix are typically used to specify variable nodes and parity equations. Then, according to the parity equation specified in each row, the variable nodes can be updated. This completes the data error correction process.

[0003] Since different rows of the parity-check matrix may specify the same variable nodes, to avoid update conflicts, some techniques currently update the variable nodes specified in the previous row according to the parity-check equation, and then update the variable nodes specified in the next row according to the parity-check equation. This method of updating variable nodes increases error correction latency and reduces error correction efficiency. Summary of the Invention

[0004] This application provides an error correction method, apparatus, electronic device, and computer-readable storage medium based on low-density parity-check codes, to at least solve the problem of reduced error correction efficiency in related technologies.

[0005] This application provides an error correction method based on low-density parity-check codes, including: Obtain the verification matrix. Each row of the verification matrix is ​​used to specify the variable node to be read and the verification equation to be calculated on the read variable node. At least some rows specify different variable nodes. For the first target row and the second target row in the verification matrix, if there are conflicting variable nodes among the variable nodes specified in the first target row and the second target row, and the number of variable nodes specified in the first target row is greater than the number of variable nodes specified in the second target row, then the first group of variable nodes specified in the first target row is read, and the first group of variable nodes is calculated based on the verification equation specified in the first target row. Conflicting variable nodes refer to variable nodes specified in both the first target row and the second target row. Based on the calculation results of the first group of variable nodes, update the first group of variable nodes; During the update of the first set of variable nodes, the second set of variable nodes specified by the second target line is read. If a conflicting variable node is not updated during the reading of the second set of variable nodes, the reading of the conflicting variable node is paused.

[0006] This application also provides an error correction device based on a low-density parity-check code, comprising: The verification matrix acquisition module is used to acquire the verification matrix. Each row of the verification matrix is ​​used to specify the variable node to be read and the verification equation to be calculated on the read variable node. At least some rows specify different variable nodes. The variable node processing module is used to handle the first target row and the second target row in the verification matrix. If there are conflicting variable nodes among the variable nodes specified in the first target row and the second target row, and the number of variable nodes specified in the first target row is greater than the number of variable nodes specified in the second target row, then the first group of variable nodes specified in the first target row is read, and the first group of variable nodes is calculated based on the verification equation specified in the first target row. Conflicting variable nodes refer to variable nodes specified in both the first target row and the second target row. The variable node update module is used to update the first group of variable nodes based on the calculation results of the first group of variable nodes; The conflict variable node reading control module is used to read the second set of variable nodes specified by the second target line during the update process of the first set of variable nodes. If the conflict variable node is not updated during the reading of the second set of variable nodes, the reading of the conflict variable node is paused.

[0007] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for implementing the steps of any of the above-described error correction methods based on low-density parity-check codes when executing the computer program.

[0008] This application also provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, it implements the steps of any of the above-described error correction methods based on low-density parity-check codes.

[0009] In some embodiments of this application, when performing data error correction based on low-density parity-check codes, if there are conflicting variable nodes in the variable nodes specified in the first and second target rows of the parity-check matrix, and the number of variable nodes specified in the first target row is greater than the number of variable nodes specified in the second target row, then the first set of variable nodes specified in the first target row is read, and calculations are performed on the first set of variable nodes based on the parity-check equation specified in the first target row. During the update process of the first set of variable nodes, the second set of variable nodes specified in the second target row is read. Since the second set of variable nodes is less than the first set of variable nodes, during the update process of the first set of variable nodes, it is only necessary to wait for the conflicting variable nodes to be updated before the second set of variable nodes can be read in parallel. That is, the partial update stage of the first set of variable nodes can be parallel to the reading stage of the second set of variable nodes. This improves error correction efficiency and solves the problem of reduced error correction efficiency in related technologies. Attached Figure Description

[0010] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 A flowchart illustrating an error correction method based on low-density parity-check codes provided for some embodiments of this application; Figure 2 A schematic diagram of a module for an error correction device based on low-density parity-check codes provided for some embodiments of this application; Figure 3 A schematic diagram of the modules of an electronic device provided for some embodiments of this application. Detailed Implementation

[0012] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0013] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0014] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0015] In the error correction logic of LDPC codes, from the construction of the parity check matrix to the application of variable nodes, there is an error correction mechanism based on the interaction between the parity check equation and the nodes. Its core logic and related concepts are as follows.

[0016] 1) Check matrix: also known as H matrix, is the core carrier of LDPC code error correction. Each row of the matrix corresponds to a check equation, which is used to apply linear constraints to a set of variable nodes; the non-zero elements in the matrix are used to specify the variable nodes required by the check equation.

[0017] 2) Variable Nodes (VNs): These represent each bit in the encoded bitstream. The encoded bitstream is composed of the original bitstream and parity bits. For example, if the original bitstream is 1011100, adding three parity bits (101) results in the encoded bitstream as 1011100101. Each bit in the encoded bitstream is a variable node, and each variable node also stores the confidence level of the corresponding bit.

[0018] 3) Parity check equation: Defined by the rows of the parity check matrix, this equation checks whether the bits of the connected variable nodes satisfy the even parity condition. For example, if columns 1, 3, and 5 of the first row of the parity check matrix are 1, it means that the 1st, 3rd, and 5th variable nodes need to be read. These three variable nodes are then substituted into the parity check equation corresponding to the first row for calculation. If the calculation result matches the expectation, it means that the bits corresponding to these three variable nodes are correct; if it does not match the expectation, it means that there is an error in the bits corresponding to these three variable nodes.

[0019] 4) LDPC code error correction process: Error correction based on the parity check matrix involves substituting the bits in the corresponding variable nodes into the corresponding parity check equation for each row, checking whether the calculation result meets the expectations, and deciding whether to update the value of each bit based on the result, thereby achieving error correction.

[0020] Since different rows of the parity-check matrix may specify the same variable nodes, to avoid update conflicts, some techniques currently update the variable nodes specified in the previous row according to the parity-check equation, and then update the variable nodes specified in the next row according to the parity-check equation. This method of updating variable nodes increases error correction latency and reduces error correction efficiency.

[0021] Therefore, this application provides an error correction method based on low-density parity-check codes, which can solve the above problems. The error correction method based on low-density parity-check codes can be applied to electronic devices. Electronic devices may include, but are not limited to, tablet computers, laptops, desktop computers, servers, etc. (See also...) Figure 1 The above is a flowchart illustrating an error correction method based on low-density parity-check codes provided in some embodiments of this application. Figure 1 In this context, the error correction method based on low-density parity-check codes includes the following steps: Step S101: Obtain the verification matrix. Each row of the verification matrix is ​​used to specify the variable node to be read and the verification equation to be calculated for the read variable node. At least some rows specify different variable nodes.

[0022] Specifically, the error correction process of LDPC codes relies on a check matrix. In the application scenarios of LDPC codes, such as high-speed data communication and data verification in storage systems, a check matrix is ​​needed to ensure the accuracy of data transmission or storage.

[0023] Table 1 shows a schematic diagram of the parity check matrix. Non-zero cells represent non-zero blocks in the parity check matrix, and cells with a value of 0 represent all-zero blocks. Non-zero cells in each row are used to specify variable nodes. For example, cells labeled 1, 2, 3, and 4 in the first row specify the 1st, 3rd, 5th, and 7th variable nodes, respectively. Similarly, cells labeled 5, 6, 7, 8, and 9 in the second row specify the 1st, 2nd, 4th, 5th, and 8th variable nodes, respectively.

[0024] Table 1. Schematic diagram of the verification matrix

[0025] In practical LDPC code applications, to achieve comprehensive and effective error correction, the parity check matrix needs multiple rows of different check equations. This requires that at least some rows specify different variable nodes. If all rows specify the same variable nodes, then multiple check equations are essentially performing repeated checks on the same set of variable nodes, failing to cover more combinations of variable nodes, thus not fully utilizing the error correction capability of LDPC codes, and struggling to handle complex data error situations. Therefore, only when at least some rows specify different variable nodes can different check equations be used to check different combinations of variable nodes, thereby more comprehensively detecting and correcting errors in the data and ensuring data accuracy.

[0026] Step S102: For the first target row and the second target row in the verification matrix, if there are conflicting variable nodes among the variable nodes specified in the first target row and the second target row, and the number of variable nodes specified in the first target row is greater than the number of variable nodes specified in the second target row, then read the first group of variable nodes specified in the first target row, and calculate the first group of variable nodes based on the verification equation specified in the first target row. Conflicting variable nodes refer to variable nodes specified in both the first target row and the second target row.

[0027] Specifically, the first and second target rows are any two rows in the parity check matrix that participate in the variable node reading and parity equation calculation operations. According to the row-level decoding algorithm, the variable nodes specified in the first target row must be updated before the variable nodes specified in the second target row are updated. If the variable nodes specified in the first target row are written while the variable nodes specified in the second target row are read simultaneously, a read-write conflict may occur. For clarity, refer to Table 1. The variable node corresponding to cell 1 needs to be written first, and then the variable node corresponding to cell 5 needs to be read. Since cells 1 and 5 correspond to the same variable nodes, and row update operations also take time, the write operation for the variable node corresponding to cell 1 will be later than the read operation for the variable node corresponding to cell 5, thus failing to meet the requirements of the row-level decoding algorithm. Here, the read-write conflict between cells 1 and 5 is a column conflict. Similar column conflicts exist for groups of cells 3, 8, and 12, and groups of cells 6 and 10, etc.

[0028] A conflicting variable node is a variable node specified by both the first and second target lines. When such a conflicting variable node exists, it is necessary to determine which line's variable node should be read and the verification equation calculated first. The first group of variable nodes consists of all the variable nodes specified by the first target line. These variable nodes represent the bits in the encoded bitstream that need to participate in the verification equation calculation for the first target line.

[0029] In this embodiment, when the number of variable nodes specified in the first target row is greater than the number of variable nodes specified in the second target row, the first group of variable nodes specified in the first target row is read first, and then the first group of variable nodes is calculated based on the verification equation specified in the first target row. The function of this verification equation is to apply linear constraints to the first group of variable nodes. By calculation, it can be determined whether the bits corresponding to the first group of variable nodes meet the verification requirements. If they do not meet the requirements, it indicates that there may be errors in these bits, providing a basis for subsequent error correction operations.

[0030] Step S103: Update the first set of variable nodes based on the calculation results of the first set of variable nodes.

[0031] Specifically, the calculation result of the first group of variable nodes refers to the result obtained based on the first target row check equation. This result directly reflects whether the bits corresponding to the first group of variable nodes meet the check requirements.

[0032] Updating the first set of variable nodes refers to adjusting the bit state and confidence level stored in the variable nodes based on the calculation results of the first set of variable nodes. This update operation based on the calculation results provides a more accurate basis for subsequent message passing between the verification nodes and variable nodes.

[0033] Step S104: During the update process of the first group of variable nodes, read the second group of variable nodes specified by the second target line. If the conflicting variable nodes are not updated during the reading of the second group of variable nodes, the reading of the conflicting variable nodes is paused.

[0034] Specifically, the second set of variable nodes consists of all the variable nodes specified in the second target row. These variable nodes also correspond to specific bits in the encoded bitstream, storing the corresponding bit states and confidence levels, and are the calculation objects of the second target row check equation. Parallel processing of the reading of the second set of variable nodes during the update of the first set of variable nodes can improve the overall efficiency of the LDPC code error correction process and reduce the delay caused by waiting for a single operation to complete.

[0035] When the first set of variable nodes is being updated, if a conflicting variable node has not yet been updated, reading that conflicting variable node should be paused. This avoids using outdated error information in the verification calculation of the second target row. For example, if a conflicting variable node should actually be "0" but is still stored as an old value of "1", reading it too early will distort the calculation result of the second target row verification equation, thus affecting subsequent error correction judgments. This reading strategy ensures the accuracy of the second set of variable node information, providing reliable input for subsequent calculations based on the second target row verification equation.

[0036] In summary, in some embodiments of this application, when performing data error correction based on low-density parity-check codes, if there are conflicting variable nodes in the variable nodes specified in the first and second target rows of the parity-check matrix, and the number of variable nodes specified in the first target row is greater than the number of variable nodes specified in the second target row, then the first set of variable nodes specified in the first target row is read, and calculations are performed on the first set of variable nodes based on the parity-check equation specified in the first target row. Furthermore, during the update process of the first set of variable nodes, the second set of variable nodes specified in the second target row is read. Since the second set of variable nodes is less than the first set of variable nodes, during the update process of the first set of variable nodes, it is only necessary to wait for the conflicting variable nodes to be updated before the second set of variable nodes can be read in parallel. That is, the partial update phase of the first set of variable nodes can be parallel to the reading phase of the second set of variable nodes. This improves error correction efficiency and solves the problem of reduced error correction efficiency in related technologies.

[0037] In some implementations, during the update process of the first set of variable nodes, reading the second set of variable nodes specified in the second target line includes: In the first group of variable nodes, the update order between variable nodes is adjusted, and in the second group of variable nodes, the read order between variable nodes is adjusted so that when a conflicting variable node is read, the conflicting variable node has already been updated.

[0038] Specifically, in the error correction process of LDPC codes, when the updating of the first set of variable nodes and the reading of the second set of variable nodes occur simultaneously, the order of updating and reading directly affects the processing efficiency of conflicting variable nodes. If a conflict exists, a conflicting variable node may be read before it is updated, leading to erroneous data being introduced into the verification calculation of the second set of variable nodes. Therefore, the operation order of the two sets of variable nodes needs to be adjusted to achieve a timing order in which conflicting variable nodes are updated first and then read. For example, assuming the first set of variable nodes includes nodes 1, 2, and 3, and the second set of variable nodes includes nodes 1, 4, and 5, the following operations can be performed.

[0039] 1) Adjust the update order of the first group of variable nodes: When the default update order is 2, 3, 1, the update of conflict node 1 is delayed, which may cause node 1 to still have the old value when the second group is read. Adjusting the update order to 1, 2, 3 prioritizes the update of conflict node 1, ensuring that node 1 is in an accurate state before being read. This avoids the problem of unupdated conflict nodes being read from the source, providing a reliable data foundation for reading the second group of variable nodes.

[0040] 2) Adjust the reading order of the second group of variable nodes: If the update order of the first group cannot be adjusted first, then adjust the reading order of the second group. The default reading order is 1, 4, 5, which prioritizes reading the unupdated node 1. In this case, the reading order is adjusted to 4, 5, 1, first reading the conflict-free nodes 4 and 5. After the first group completes the update of node 1, the latest state of node 1 is then read. This order adjustment avoids the reading timing of conflicting nodes, achieving timing matching without changing the update process of the first group.

[0041] 3) Adjust the operation order of the two sets of variable nodes: If the update order of the first set is 2, 3, 1, and the default read order of the second set is 1, 4, 5, then the update order of the first set can be slightly adjusted to 1, 2, 3, and the read order of the second set can be adjusted to 4, 5, 1. In this way, the overall processing efficiency of the two sets of variable nodes is not affected, and the update and read order of conflicting nodes can be accurately matched.

[0042] In the above implementation, by adjusting the update and read order of variable nodes in one or two directions, it can be ensured that conflicting variable nodes always participate in the verification calculation of the second group in the accurate updated state when processing the first group of updates and the second group of reads, thus avoiding error correction deviations caused by outdated data and improving the accuracy of the LDPC code error correction process.

[0043] In some implementations, the first set of variable nodes includes a first non-conflicting variable node, which is a variable node specified in the first target line but not specified in the second target line; In the first group of variable nodes, adjust the update order among the variable nodes, including: If the update time of the conflicting variable node is later than the update time of the first non-conflicting variable node, then the update times of the conflicting variable node and the first non-conflicting variable node are adjusted so that the update time of the conflicting variable node is earlier than the update time of the first non-conflicting variable node.

[0044] Specifically, the first non-conflicting variable node refers to a node that only participates in the verification calculation of the first target row, and whose update status will not affect the processing of the second target row, so it does not need to be updated first.

[0045] When a conflicting variable node is updated later than the first non-conflicting variable node, the risk of the second group reading old data increases significantly. Therefore, it is necessary to adjust the update time of the two to ensure that the conflicting variable node completes its update first. As a shared node for both the first and second target rows, the update status of the conflicting variable node directly determines the accuracy of the data read from the second target row. If the update is delayed, the second group will use uncorrected old values ​​when reading, causing verification errors.

[0046] In the first group of variable nodes, conflicting variable nodes and the first non-conflicting variable nodes are identified first. Their default update times are then compared. If a conflicting variable node updates later, their update order is swapped or reordered to ensure the conflicting variable node updates earlier. For example, if the first group contains conflicting node 3 and the first non-conflicting nodes 1 and 2, with a default update order of 1, 2, 3, the order is adjusted to 3, 1, 2. This ensures node 3 updates first, while nodes 1 and 2 update second and third, respectively. Even if the second group reads node 3 first or second, it can still obtain accurate updated data. This process is repeated for all conflicting and non-conflicting nodes within the first group, ensuring all conflicting nodes are updated first.

[0047] In the above implementation, by prioritizing the updating of conflict variable nodes, sufficient time is reserved for the second group to read conflict nodes, reducing the situation where data is read before it is updated. This does not affect the subsequent updating of the first conflict variable node and the verification calculation of the first target row, laying the foundation for the efficient advancement of LDPC code error correction.

[0048] In some implementations, the second set of variable nodes includes a second non-conflicting variable node, which is a variable node specified in the second target line but not specified in the first target line; In the second group of variable nodes, adjust the reading order between the variable nodes, including: If the reading time of the conflicting variable node is earlier than the reading time of the second non-conflicting variable node, then the reading times of the conflicting variable node and the second non-conflicting variable node are adjusted so that the reading time of the conflicting variable node is later than the reading time of the second non-conflicting variable node.

[0049] Specifically, the second non-conflicting variable node refers to a node that only participates in the verification calculation of the second target row. Its reading does not depend on the update status of the first group of variable nodes and can be retrieved and used at any time. Conflicting variable nodes, because they are associated with both the first and second target rows, require data that depends on the update results of the first group. If they are read before the first group completes its update, the verification calculation of the second target row will use old data, resulting in incorrect verification results. When the reading time of a conflicting variable node is earlier than that of the second non-conflicting variable node, the problem of introducing old data is likely to occur. Therefore, it is necessary to adjust the reading times of both, delaying the reading of the conflicting variable node to allow time for the first group's update.

[0050] In practice, within the second group of variable nodes, conflicting variable nodes are first distinguished from non-conflicting variable nodes. Then, their default read times are compared. If a conflicting variable node is read earlier, the read order is reordered, prioritizing the read of non-conflicting variable nodes. For example, if the second group contains conflicting node 3 and non-conflicting nodes 1 and 2, with a default read order of 3, 1, 2, the order is adjusted to 1, 2, 3. This ensures that nodes 1 and 2 are read in the first and second time slots respectively, and node 3 is read in the third time slot. Utilizing the read times of nodes 1 and 2, the first group can update node 3 between the first, second, and third time slots, ensuring the accuracy of the data read in the third time slot. This process is repeated for all conflicting and non-conflicting nodes within the second group, ensuring that all conflicting nodes are read later.

[0051] In the above implementation, by delaying the reading time of conflicting variable nodes, we can both wait for the first group to complete the update of conflicting nodes and avoid verification errors caused by unsynchronized data, and prioritize reading the second non-conflicting variable nodes to avoid wasting the time resources of parallel processing. This achieves a balance between accuracy and efficiency in the LDPC code error correction process and provides reliable data support for the subsequent calculation of the second target row check equation.

[0052] In some implementations, adjusting the update order of variable nodes in the first group of variable nodes and adjusting the read order of variable nodes in the second group of variable nodes includes: Based on the update order of the first group of variable nodes, determine the first target time when the conflicting variable node is updated; Based on the first target time, the reading order of variable nodes in the second group of variable nodes is adjusted so that the reading time of conflicting variable nodes is later than the first target time.

[0053] Specifically, the first target time refers to the exact moment when the conflicting variable node completes its bit state and confidence correction in the first update process. Based on the first target time, it can be determined whether the conflicting variable node is in an available state. The read time of the conflicting variable node refers to the moment when the conflicting variable node in the second set of variable nodes is retrieved to participate in the verification calculation. If this time is earlier than the first target time, it will directly cause the second target row check equation to use outdated data, leading to error correction bias. The timing relationship between the two must satisfy the logic of first determining the update completion time and then determining the read time in reverse, based on which the following operations are performed.

[0054] In practice, the update order of the first group of variable nodes is followed first. The first target time for each conflicting variable node to complete its update is calculated. Then, at the first target time, the reading order of the second group of variable nodes is rearranged to ensure that the reading of conflicting variable nodes occurs after the first target time. For example, if the update order of conflicting variable node 3 in the first group is 2nd, its first target time is determined to be the second moment. In the second group, the original reading order is 3, 1, 2, where node 3 was originally read at the first moment, which is earlier than the second moment. The reading order is then adjusted to 1, 2, 3, so that nodes 1 and 2 are read between the first and second moments, and the reading time of node 3 is delayed to the third moment, which is later than the second moment, ensuring that node 3 has been updated when it is read. This process is repeated for all conflicting variable nodes, determining the first target time and adjusting the reading order to be later than the first target time.

[0055] In the above implementation, by adjusting the reading order of conflicting variable nodes in the second group based on the update completion time of the conflicting variable nodes, it is ensured that the conflicting variable nodes always participate in the verification calculation in the updated accurate state, avoiding the time waste caused by waiting, and achieving a balance between accuracy and efficiency in the LDPC code error correction process.

[0056] In some implementations, the method further includes: Based on the adjusted reading order, if the conflicting variable node is the last variable node read in the second group of variable nodes, and the reading time of the conflicting variable node is earlier than the update time of the conflicting variable node, then the reading time of the second group of variable nodes will be delayed.

[0057] Specifically, the adjusted reading order refers to the order in which conflicting variable nodes are placed at the end of the second group of variable node reading sequence, meaning that all non-conflicting variable nodes in the second group are read before the conflicting variable nodes. Delaying the reading time of the second group of variable nodes involves adding an interpolation before the reading operation of the second group of variable nodes, i.e., a preset waiting time interval, to postpone the reading time of conflicting variable nodes until the timing requirement that the reading time of conflicting variable nodes is later than the update time is met. This operation is aimed at ensuring that even if conflicting nodes are placed last for reading, their reading time is still earlier than the update time, and is the last resort to guarantee the timing requirement.

[0058] In practice, first confirm that the reading order of the second group of variable nodes has been adjusted, meaning the conflicting variable node has been set as the last read object. Then compare the reading time and update time of the conflicting variable node. If the reading time is still earlier than the update time, add an interpolation before the overall reading operation of the second group of variable nodes. For example, if the update time of the conflicting variable node is the second moment, and its reading time in the second group is the first moment after adjustment (the first moment is earlier than the second moment), calculate the time difference between the first and second moments and record it as the waiting time. The length of the waiting time for all variable nodes in the second group to be shifted back is exactly synchronized with the update time of the conflicting variable node, ensuring that the conflicting variable node has been updated before it is read. Similarly, if multiple conflicting variable nodes still have timing conflicts after being shifted back, the interpolation time can be calculated based on the maximum time difference to complete the delay adjustment of the second group's reading time in one go.

[0059] In the above implementation, timing issues are first resolved by adjusting the order of conflicting nodes to avoid unnecessary waiting delays. When the order adjustment cannot meet the requirements, the delay is supplemented by insertion. This operation maximizes the efficiency of parallel processing, avoids performance loss caused by waiting, and limits the use of insertion to necessary scenarios while ensuring the accuracy of LDPC code error correction, thus minimizing the computational delay that insertion may cause.

[0060] In some implementations, delaying the reading time of the second set of variable nodes includes: Determine the second target time when the second group of variable nodes is triggered to be read; After the second target time, add one or more idle clock cycles to obtain the third target time, and at the third target time, trigger the reading of the second set of variable nodes.

[0061] Specifically, the second target time refers to the initial moment when the second group of variable nodes would have been triggered to begin reading operations without any delay adjustment. An idle clock cycle refers to a blank time unit where no variable node reading or calculation operations are performed; its duration is strictly matched to the clock frequency of the hardware circuit and is the smallest unit for quantifying delay duration. The third target time refers to the moment when the second group of variable nodes actually begins reading operations after adding idle clock cycles; it is also the final execution time that ensures conflicting variable nodes are updated before being read. The relationship between the three can be expressed as the third target time equals the second target time plus the clock cycle duration of N idle clock cycles.

[0062] In practice, the second target time for the second group of variable nodes is first obtained. Then, based on the difference between the update time of the conflicting variable nodes and the second target time, the number of idle clock cycles is calculated. These idle clock cycles are then inserted after the second target time to obtain the third target time. Finally, the read operation for the second group of variable nodes is triggered at the third target time. By this time, the conflicting variable nodes have already been updated, ensuring the accuracy of the read data. For example, the second group should originally be read at the first moment (i.e., the second target time is the first moment, and the update time of the conflicting variable nodes is the second moment). The idle clock cycles are then calculated based on the first and second moments, and inserted after the first moment to obtain the third target time. Finally, the read operation for the second group of variable nodes is triggered at the third target time. If multiple conflicting variable nodes exist, the number of idle cycles is calculated based on the latest update time, ensuring that the third target time covers the update needs of all conflicting variable nodes.

[0063] In the above implementation, by adjusting the reading time in units of idle clock cycles and inserting idle cycles to achieve delay, the hierarchical strategy of first adjusting the order and then supplementing the gaps is continued. When the order adjustment cannot resolve the timing conflict, the insertion of quantized idle cycles can provide a reliable solution, further improving the flexibility and reliability of the LDPC code error correction process in complex environments.

[0064] In some implementations, the method further includes the following steps before adding idle clock cycles: Obtain the fourth target time when the conflict variable node is updated, and the fifth target time when the conflict variable node is read; The number of idle clock cycles is determined based on the time difference between the fourth target time and the fifth target time.

[0065] Specifically, the fourth target time refers to the actual moment when the conflicting variable node completes its bit state and confidence correction in the first update process. Based on the fourth target time, the availability of the conflicting variable node can be determined. Since the read operation occurs after the fourth target time, the value of the conflicting variable node is the accurate value after verification and optimization. The fifth target time refers to the initial moment when the conflicting variable node is triggered for reading in the second read process without adding idle clock cycles. This time is determined by the original read order of the second group. The time difference refers to the difference between the fourth and fifth target times. Its sign and magnitude determine whether and how many idle clock cycles need to be added. If the fourth target time is later than the fifth target time (i.e., the time difference is positive), it indicates that the read is earlier than the update, and this time difference needs to be compensated by adding idle clock cycles. If the fourth target time is earlier than the fifth target time (i.e., the time difference is negative), no idle cycles need to be added, and the read can proceed directly in the original order.

[0066] In practice, the fourth and fifth target times of the conflicting variable nodes are recorded separately. For example, if the update completion time of a conflicting variable node is the first moment (i.e., the fourth target time is the first moment), and the initial read time of the same conflicting variable node in the second group is the second moment (i.e., the fifth target time is the second moment), and the first moment is later than the second moment, the time difference between the first and second moments is calculated. Assuming this time difference is 3 clock cycles, the number of idle clock cycles to be added is directly determined to be 3, ensuring that the fifth target time is postponed to the first moment, so that the read action is executed after the update is completed. If there are multiple conflicting variable nodes, the time difference of each node is calculated separately, and the largest time difference is used as the final number of idle clock cycles to be added, ensuring that all conflicting variable nodes meet the timing requirement of update first, then read.

[0067] In the above implementation, the number of idle cycles is determined based on the actual time difference, avoiding resource waste caused by adding more cycles than required, or verification errors caused by adding fewer cycles than required. By using the strategy of taking the maximum time difference, there is no need to adjust each conflict node individually, simplifying the operation process while ensuring the consistency of the global timing. This scheme based on quantified idle waiting time, while resolving column conflicts, also takes into account the overall efficiency of the LDPC code error correction process, providing support for decoding stability.

[0068] In some implementations, there are multiple conflicting variable nodes in the variable nodes specified in the first target row and the second target row; In the first group of variable nodes, adjust the update order between variable nodes, and in the second group of variable nodes, adjust the read order between variable nodes, including: In the first group of variable nodes, the update order between variable nodes is adjusted to the first update order, and in the second group of variable nodes, the read order between variable nodes is adjusted to the first read order, so that when the first conflicting variable node is read, the first conflicting variable node has already been updated; In the first group of variable nodes, the first update order is adjusted to the second update order, and in the second group of variable nodes, the first read order is adjusted to the second read order, so that when reading other conflicting variable nodes after the first conflicting variable node, the other conflicting variable nodes have already been updated.

[0069] Specifically, multiple conflicting variable nodes refer to two or more variable nodes jointly specified by the first target row and the second target row. The update and read sequences of multiple conflicting variable nodes must be matched one by one to avoid affecting the overall verification accuracy due to timing conflicts of a single conflicting variable node. The first update order refers to the optimized update order for the first conflicting variable node, ensuring that this node is updated before other non-conflicting nodes in the first group, allowing sufficient time for subsequent reads. The first read order refers to the read order that matches the first conflicting variable node, ensuring that its read time is later than its update time. The second update order and the second read order refer to the iterative optimization order for the remaining conflicting variable nodes.

[0070] In practice, for example, the first target row corresponds to the first group of variable nodes, which includes conflicting variable nodes 1, 2, and 3, as well as non-conflicting nodes 4 and 5. The second target row corresponds to the second group of variable nodes, which includes conflicting variable nodes 1, 2, and 3, as well as non-conflicting nodes 6 and 7. The specific operation is as follows.

[0071] 1) Handling the first conflict variable node 1: The default update order of the first group of variable nodes is 4, 5, 1, 2, 3. It is adjusted to the first update order 1, 4, 5, 2, 3 to ensure that node 1 is updated first. The default reading order of the second group of variable nodes is 1, 2, 3, 6, 7. It is adjusted to the first reading order 6, 1, 7, 2, 3 to postpone the rated reading time of variable node 1 to the second moment. The second moment is later than the first moment, which satisfies the condition of updating before reading.

[0072] 2) Handling the remaining conflicting variable nodes 2 and 3: The update time of variable node 2 is the third moment, which is later than the original read time of node 2 in the first read order. Therefore, the first update order of the first group is adjusted to the second update order 1, 2, 4, 5, 3, advancing the update time of variable node 2 to the original read time of node 2 in the first read order. Simultaneously, the first read order of the second group is adjusted to the second read order 6, 1, 7, 2, 3, delaying the read time of variable node 2 to the third moment. Similarly, for variable node 3, its second update order and second read order are iteratively adjusted until the timing of all conflicting variable nodes is adjusted.

[0073] In the above embodiments, by locating conflicting variable nodes one by one, adjusting the update and read order accordingly, and iteratively optimizing the process of the remaining nodes, the update and read order can be optimized according to the actual situation of each conflicting node, adapting to the characteristics of scenarios with multiple conflicting variable nodes. This method can ensure that all conflicting nodes meet the timing requirement of updating before reading in scenarios with multiple conflicting variable nodes, providing a guarantee for the accuracy and stability of the LDPC code error correction process.

[0074] In some implementations, the method further includes: After adjusting the update and read order among variable nodes, if the read time of at least one conflicting variable node is earlier than its update time, the read time of the second group of variable nodes is delayed.

[0075] Specifically, adjusting the update and read order among variable nodes refers to completing the initial timing adjustment of all conflicting variable nodes. Having at least one conflicting variable node read earlier than its update time means that even after order adjustment, some conflicting nodes still have a read time in the second group earlier than their update time in the first group; that is, the order adjustment scheme cannot resolve the timing conflict problem. Delaying the read time of the second group of variable nodes means shifting the trigger time of the second group's read operations backward by adding idle clock cycles, etc., to ensure that all conflicting nodes meet the timing requirement of update first, then read.

[0076] In practice, for example, the first group contains conflicting variable nodes 1, 2, and 3, and the second group contains conflicting variable nodes 1, 2, and 3. The specific operation is as follows.

[0077] 1) Conflict detection: The update time and read time of the adjusted conflict variable nodes are compared one by one. It is found that conflict variable nodes 1 and 3 both satisfy the rule that the update time is earlier than the read time. However, the read time of conflict variable node 2 is earlier than its update time. Therefore, it is determined that there is still 1 conflict variable node.

[0078] 2) Delay duration calculation: Based on the time difference of the remaining conflicting variable nodes, the delay duration is determined to be 1 clock cycle to ensure that the reading time of the conflicting variable node 2 after the delay can cover its update time.

[0079] 3) Delayed Execution: Insert one idle clock cycle at the beginning of the reading process for the second group of variable nodes, shifting the reading time of all nodes in the second group back by one cycle to resolve all remaining conflicting variable nodes at once. If multiple remaining conflicting nodes exist, calculate the delay duration based on the maximum time difference to avoid repeated adjustments.

[0080] In the above implementation, by delaying the second group of reading times as a whole, the order of individual nodes does not need to be repeatedly adjusted, thus resolving timing conflicts that cannot be resolved by the order adjustment scheme. This scheme of adjusting first and then delaying ensures the timing reliability in multi-conflict scenarios and provides a complete solution for the stable advancement of the LDPC code error correction process.

[0081] In some implementations, during the update process of the first set of variable nodes, reading the second set of variable nodes specified in the second target line includes: In the first group of variable nodes, the updated values ​​of each variable node are written into the register in sequence; During the process of writing the updated values ​​of each variable node into the register in sequence, the updated values ​​of conflicting variable nodes are read from the register. After writing the updated values ​​of all variable nodes in the first group of variable nodes into the register, the updated values ​​in the register are written into the storage medium.

[0082] Specifically, a register refers to a high-speed storage unit used to temporarily store updated values ​​of variable nodes. Its read and write speed is much faster than that of the back-end storage medium, enabling write-and-read operations. The updated value of a variable node refers to the bit state and confidence data of the first set of variable nodes after calculation and correction by the check equation. The storage medium refers to the storage module used to permanently store variable node data and is the data carrier in the LDPC code error correction process.

[0083] In practice, for example, the first group of variable nodes includes conflicting nodes 1 and 2 and non-conflicting nodes 3 and 4, and the second group of variable nodes includes conflicting nodes 1 and 2 and non-conflicting nodes 5 and 6. Two registers 1 and 2 are configured. The specific implementation steps are as follows.

[0084] 1) Update values ​​are written to registers in sequence: After the first group of variable nodes are updated in the order of 1, 3, 2, 4, the update value of node 1 is written to register 1, then the update value of node 3 is written to register 2, then the update value of node 2 is written to register 1, and finally the update value of node 4 is written to register 2.

[0085] 2) Reading the updated value of conflicting variable nodes: When the second group reads the variable nodes of the second group, after the first group writes the updated value of variable node 1 into register 1, it does not need to wait for the updated values ​​of variable nodes 3, 2, and 4 to be written. It can immediately read the updated value of variable node 1 from register 1 for the calculation of the second target row check equation. Similarly, after the updated value of variable node 2 is written into the register, the second group can immediately read the updated value of variable node 2, realizing the synchronous operation of the first group updating and writing into the register and the second group reading.

[0086] 3) Write register values ​​to storage medium: After all the updated values ​​of the first group of variable nodes 1, 3, 2 and 4 have been written to the registers, write all the updated values ​​temporarily stored in the registers to the back-end storage medium at once.

[0087] In the above implementation, the operation method of reading conflict nodes based on registers without waiting for storage medium to write can significantly improve the efficiency of the overall LDPC code error correction process, and provide an efficient hardware adaptation solution for the application of LDPC codes in high-speed data communication, low-latency storage and other scenarios.

[0088] In some implementations, the method further includes: During the update of the first set of variable nodes, if the reading of the second set of variable nodes is completed, the reading of the third set of variable nodes specified in the third target line continues. The number of variable nodes specified in the third target line is less than the number of variable nodes specified in the first target line.

[0089] Specifically, the third target row refers to the row in the verification matrix that, excluding the first and second target rows, needs to participate in variable node reading and verification calculation. The number of specified variable nodes in this row is less than that in the first target row, meaning the verification equation in this row involves fewer variable nodes and has lower computational complexity. The third set of variable nodes refers to the set of variable nodes to be read specified in the third target row. This may include conflicting nodes overlapping with the first and second target rows, or it may consist of independent, non-conflicting nodes. The logic of this implementation is to utilize the time gap between the first set of updates and immediately start the third set of reads after the second set is completed, avoiding idle hardware processing units.

[0090] The reading order of the target rows (first, second, and third) is adjusted by sorting them in descending order of complexity. The new reading order is determined, and the first group of variable nodes is updated in the predetermined order. Simultaneously, the reading of the second group of variable nodes begins. After the second group of variable nodes is read, the reading of the third group of variable nodes begins immediately, without waiting for the first group to be fully updated or for subsequent write operations corresponding to the second group's reading results.

[0091] In the above implementation, the next group is started as soon as the previous group is read, and multiple groups of read operations are completed during the time interval of the first group's update, avoiding the time wasted due to waiting for a single process; moreover, the number of variable nodes in the third target row is small, and the probability of row conflict with the first and second target rows is low. This scheme provides an efficient scheduling scheme for parallel error correction of multiple target rows in LDPC codes, and is suitable for verification scenarios with large parity check matrices and multiple target rows that need to be processed quickly.

[0092] Corresponding to the error correction method based on low-density parity-check codes, this application also provides an error correction device based on low-density parity-check codes. (See also...) Figure 2 The diagram below shows a module schematic of an error correction device based on low-density parity-check codes provided in some embodiments of this application. Figure 2 In this context, error correction devices based on low-density parity-check codes include: The verification matrix acquisition module 201 is used to acquire the verification matrix. Each row of the verification matrix is ​​used to specify the variable node to be read and the verification equation to be calculated on the read variable node. At least some rows specify different variable nodes.

[0093] The variable node processing module 202 is used to, for the first target row and the second target row in the verification matrix, if there are conflicting variable nodes among the variable nodes specified in the first target row and the second target row, and the number of variable nodes specified in the first target row is greater than the number of variable nodes specified in the second target row, then read the first group of variable nodes specified in the first target row, and calculate the first group of variable nodes based on the verification equation specified in the first target row. Conflicting variable nodes refer to variable nodes specified in both the first target row and the second target row.

[0094] The variable node update module 203 is used to update the first group of variable nodes based on the calculation results of the first group of variable nodes.

[0095] The conflict variable node reading control module 204 is used to read the second set of variable nodes specified by the second target line during the update process of the first set of variable nodes. If the conflict variable node is not updated during the reading of the second set of variable nodes, the reading of the conflict variable node is paused.

[0096] In some optional implementations, the conflict variable node read control module 204 includes: The conflict variable node timing adjustment unit is used to adjust the update order between variable nodes in the first group of variable nodes and the read order between variable nodes in the second group of variable nodes, so that when a conflict variable node is read, the conflict variable node has already been updated.

[0097] In some optional implementations, the first group of variable nodes includes a first non-conflicting variable node, which refers to a variable node specified in the first target line but not specified in the second target line. The conflicting variable node timing adjustment unit includes: The conflict variable node update priority scheduling subunit is used to adjust the update times of the conflict variable node and the first non-conflicting variable node if the update time of the conflict variable node is later than the update time of the first non-conflicting variable node, so that the update time of the conflict variable node is earlier than the update time of the first non-conflicting variable node.

[0098] In some optional implementations, the second set of variable nodes includes a second set of non-conflicting variable nodes, which are variable nodes specified in the second target line but not specified in the first target line. The conflicting variable node timing adjustment unit further includes: The conflict variable node read lag scheduling subunit is used to adjust the read times of the conflict variable node and the second non-conflicting variable node so that the read time of the conflict variable node is later than the read time of the second non-conflicting variable node if the read time of the conflict variable node is earlier than the read time of the second non-conflicting variable node.

[0099] In some optional implementations, the conflict variable node timing adjustment unit further includes: The conflict variable node update time determination subunit is used to determine the first target time when a conflict variable node is updated based on the update order of the first group of variable nodes. The conflict variable node reading order adjustment subunit is used to adjust the reading order of variable nodes in the second group of variable nodes based on the first target time, so that the reading time of the conflict variable node is later than the first target time.

[0100] In some optional implementations, the conflict variable node timing adjustment unit further includes: The delayed reading of conflict variable nodes is used to insert a gap sub-unit based on the adjusted reading order. If the conflict variable node is the last variable node read in the second group of variable nodes, and the reading time of the conflict variable node is earlier than the update time of the conflict variable node, then the reading time of the second group of variable nodes is delayed.

[0101] In some optional implementations, the conflict variable node hysteresis read insertion subunit includes: The second set of read time determination subunits is used to determine the second target time when the second set of variable nodes is triggered to read; The idle cycle insertion sub-unit is used to add one or more idle clock cycles after the second target time to obtain the third target time, and trigger the reading of the second set of variable nodes at the third target time.

[0102] In some alternative implementations, the idle cycle insertion subunit includes: The conflict variable node timing difference acquisition sub-unit is used to acquire the fourth target time when the conflict variable node is updated, and the fifth target time when the conflict variable node is read. The idle cycle quantization calculation subunit is used to determine the number of idle clock cycles based on the time difference between the fourth target time and the fifth target time.

[0103] In some optional implementations, multiple conflicting variable nodes exist among the variable nodes specified in the first target row and the second target row, and the conflicting variable node timing adjustment unit further includes: The first conflicting variable node update read adjustment subunit is used to adjust the update order between variable nodes in the first group of variable nodes to the first update order, and to adjust the read order between variable nodes in the second group of variable nodes to the first read order, so that the first conflicting variable node has been updated when it is read; The subsequent conflict variable node update read adjustment subunit is used to adjust the first update order to the second update order in the first group of variable nodes, and to adjust the first read order to the second read order in the second group of variable nodes, so that when reading other conflict variable nodes after the first conflict variable node, the other conflict variable nodes have been updated.

[0104] In some optional implementations, the conflict variable node timing adjustment unit further includes: The residual conflict variable node read delay subunit is used to delay the read time of the second group of variable nodes if the read time of at least one conflict variable node is earlier than the update time after adjusting the update order and read order among variable nodes.

[0105] In some optional implementations, the conflict variable node read control module 204 further includes: The variable node update value register write unit is used to write the update value of each variable node into the register sequentially in the first group of variable nodes; The conflict variable node update value register read unit is used to read the update value of the conflict variable node from the register during the process of writing the update values ​​of each variable node into the register in sequence; The register data storage medium synchronization unit is used to write the updated values ​​in the registers into the storage medium after all the updated values ​​of the variable nodes in the first group of variable nodes have been written into the registers.

[0106] In some optional implementations, the conflict variable node read control module 204 further includes: The target line reading continuation unit is used to continue reading the third set of variable nodes specified in the third target line if the reading of the second set of variable nodes is completed during the updating process of the first set of variable nodes. The number of variable nodes specified in the third target line is less than the number of variable nodes specified in the first target line.

[0107] For a description of the features in the embodiment of the error correction device based on low-density parity-check code, please refer to the relevant description of the embodiment of the sample data processing method, which will not be repeated here.

[0108] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0109] See also Figure 3 The embodiments of this application also provide an electronic device, including a memory 10 and a processor 20, wherein the memory 10 stores a computer program and the processor 20 is configured to run the computer program to perform the steps in any of the above embodiments of the error correction method based on low-density parity-check codes.

[0110] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above embodiments of the error correction method based on low-density parity-check codes when running.

[0111] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0112] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above embodiments of the error correction method based on low-density parity-check codes.

[0113] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above embodiments of the error correction method based on low-density parity-check codes.

[0114] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0115] The foregoing has provided a detailed description of an error correction method, apparatus, device, and storage medium based on low-density parity-check codes provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only intended to aid in understanding the method and its core ideas. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. An error correction method based on low-density parity-check codes, characterized in that, The method includes: Obtain a verification matrix, wherein each row of the verification matrix is ​​used to specify the variable node to be read and the verification equation to be calculated on the read variable node, and at least some rows specify different variable nodes; For the first target row and the second target row in the verification matrix, if there are conflicting variable nodes among the variable nodes specified in the first target row and the second target row, and the number of variable nodes specified in the first target row is greater than the number of variable nodes specified in the second target row, then the first group of variable nodes specified in the first target row is read, and the first group of variable nodes is calculated based on the verification equation specified in the first target row. The conflicting variable nodes refer to the variable nodes specified in both the first target row and the second target row. Based on the calculation results of the first group of variable nodes, the first group of variable nodes are updated; During the update process of the first group of variable nodes, the second group of variable nodes specified by the second target line is read. If the conflicting variable node is not updated during the reading of the second group of variable nodes, the reading of the conflicting variable node is paused.

2. The method according to claim 1, characterized in that, The step of reading the second set of variable nodes specified in the second target row during the update process of the first set of variable nodes includes: In the first group of variable nodes, the update order between variable nodes is adjusted, and in the second group of variable nodes, the read order between variable nodes is adjusted, so that when the conflicting variable node is read, the conflicting variable node has already been updated.

3. The method according to claim 2, characterized in that, The first group of variable nodes includes a first non-conflicting variable node, which refers to a variable node specified in the first target line but not specified in the second target line; The step of adjusting the update order among the variable nodes in the first group of variable nodes includes: If the update time of the conflicting variable node is later than the update time of the first non-conflicting variable node, then the update times of the conflicting variable node and the first non-conflicting variable node are adjusted so that the update time of the conflicting variable node is earlier than the update time of the first non-conflicting variable node.

4. The method according to claim 2, characterized in that, The second group of variable nodes includes a second non-conflicting variable node, which refers to a variable node specified in the second target line but not specified in the first target line; The step of adjusting the reading order between variable nodes in the second group of variable nodes includes: If the reading time of the conflicting variable node is earlier than the reading time of the second non-conflicting variable node, then the reading times of the conflicting variable node and the second non-conflicting variable node are adjusted so that the reading time of the conflicting variable node is later than the reading time of the second non-conflicting variable node.

5. The method according to any one of claims 2 to 4, characterized in that, The steps of adjusting the update order of variable nodes in the first group of variable nodes and adjusting the read order of variable nodes in the second group of variable nodes include: Based on the update order of the first group of variable nodes, determine the first target time when the conflicting variable node is updated; Based on the first target time, the reading order of variable nodes in the second group of variable nodes is adjusted so that the reading time of the conflicting variable node is later than the first target time.

6. The method according to any one of claims 2 to 4, characterized in that, The method further includes: Based on the adjusted reading order, if the conflicting variable node is the last variable node read in the second group of variable nodes, and the reading time of the conflicting variable node is earlier than the update time of the conflicting variable node, then the reading time of the second group of variable nodes is delayed.

7. The method according to claim 6, characterized in that, The delay in reading the second set of variable nodes includes: Determine the second target time when the second group of variable nodes is triggered to be read; After the second target time, add one or more idle clock cycles to obtain the third target time, and at the third target time, trigger the reading of the second set of variable nodes.

8. The method according to claim 7, characterized in that, Before adding the idle clock cycle, the method further includes: Obtain the fourth target time when the conflict variable node is updated, and the fifth target time when the conflict variable node is read; The number of idle clock cycles is determined based on the time difference between the fourth target time and the fifth target time.

9. The method according to claim 2, characterized in that, There are multiple conflicting variable nodes in the variable nodes specified in the first target row and the second target row; The steps of adjusting the update order of variable nodes in the first group of variable nodes and adjusting the read order of variable nodes in the second group of variable nodes include: In the first group of variable nodes, the update order between variable nodes is adjusted to the first update order, and in the second group of variable nodes, the read order between variable nodes is adjusted to the first read order, so that when the first conflicting variable node is read, the first conflicting variable node has already been updated; In the first group of variable nodes, the first update order is adjusted to the second update order, and in the second group of variable nodes, the first read order is adjusted to the second read order, so that when reading other conflicting variable nodes after the first conflicting variable node, the other conflicting variable nodes have been updated.

10. The method according to claim 9, characterized in that, The method further includes: After adjusting the update and read order among variable nodes, if the read time of at least one conflicting variable node is earlier than its update time, the read time of the second group of variable nodes is delayed.

11. The method according to claim 1, characterized in that, The step of reading the second set of variable nodes specified in the second target row during the update process of the first set of variable nodes includes: In the first group of variable nodes, the updated values ​​of each variable node are written into the register in sequence; During the process of writing the updated values ​​of each variable node into the register in sequence, the updated values ​​of the conflicting variable nodes are read from the register. After writing the updated values ​​of all variable nodes in the first group of variable nodes into the register, the updated values ​​in the register are written into the storage medium.

12. The method according to claim 1, characterized in that, The method further includes: During the update process of the first group of variable nodes, if the reading of the second group of variable nodes is completed, the reading of the third group of variable nodes specified in the third target line continues. The number of variable nodes specified in the third target line is less than the number of variable nodes specified in the first target line.

13. An error correction device based on low-density parity-check codes, characterized in that, The device includes: A verification matrix acquisition module is used to acquire a verification matrix. Each row of the verification matrix is ​​used to specify the variable node to be read and the verification equation to be calculated on the read variable node. At least some rows specify different variable nodes. The variable node processing module is used to, for the first target row and the second target row in the verification matrix, if there are conflicting variable nodes among the variable nodes specified in the first target row and the second target row, and the number of variable nodes specified in the first target row is greater than the number of variable nodes specified in the second target row, then read the first group of variable nodes specified in the first target row, and calculate the first group of variable nodes based on the verification equation specified in the first target row. The conflicting variable nodes refer to the variable nodes specified in both the first target row and the second target row. The variable node update module is used to update the first group of variable nodes based on the calculation results of the first group of variable nodes; The conflict variable node reading control module is used to read the second set of variable nodes specified by the second target row during the update process of the first set of variable nodes. If the conflict variable node is not updated during the reading of the second set of variable nodes, the reading of the conflict variable node is paused.

14. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the error correction method based on low-density parity-check codes as described in any one of claims 1 to 12 when executing the computer program.

15. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, it implements the steps of the error correction method based on low-density parity-check codes as described in any one of claims 1 to 12.

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