Signal receiving device and method with channel identification mechanism

Abstract

The invention provides a signal receiving method with a channel identification mechanism. The signal receiving method comprises the following steps of: receiving signals by signal channels which are included by a signal receiving interface and are respectively provided with a pair of differential signal lines; enabling the signal processing circuit to detect the semaphores of the signal channels in a link training program, so as to judge that the signal channels of which the semaphores meet a preset condition are actual communication signal channels; enabling the signal processing circuit to detect a test data sequence transmitted by the actual communication signal channels in a link training program so as to identify a polarity sequence of differential signal lines of the actual communication signal channels and a channel number sequence among the actual communication signal channels according to a data pattern; and enabling the signal processing circuit to receive actual data from the signal transmission line according to the polarity sequence and the channel number sequence after the link training program is finished.

Description

Technical Field

[0001] This invention relates to signal receiving technology, and more particularly to a signal receiving device and method with a channel identification mechanism. Background Technology

[0002] The transmission of electronic signals requires a specific interface. For example, the transmission of image signals can be carried out through, but is not limited to, a DisplayPort (DP) or a Universal Serial Bus Type-C (USB Type-C) interface.

[0003] The aforementioned signal transmission interface uses multiple pairs of differential signal lines for data transmission. However, the order of these differential signal lines is not the same for the receiving and transmitting ends. If this is not properly configured during design and there is no corresponding handling mechanism, the receiving and transmitting ends will be unable to communicate correctly. Summary of the Invention

[0004] In view of the problems of the prior art, one object of the present invention is to provide a signal receiving device and method with a channel identification mechanism to improve the prior art.

[0005] This invention includes a signal receiving device with a channel identification mechanism, comprising: a signal receiving interface and a signal processing circuit. The signal receiving interface includes multiple signal channels electrically coupled to a signal transmission line for signal reception, each signal channel including a pair of differential signal lines. The signal processing circuit is configured to: during a link training program, detect the signal quantity of each signal channel to determine if the signal quantity meets preset conditions as multiple actual communication signal channels; during the link training program, detect multiple test data sequences transmitted by the actual communication signal channels to identify the polarity order of the differential signal lines and the channel numbering order among the actual communication signal channels based on the data pattern of each test data sequence; and after the link training program ends, receive actual data from the signal transmission line through the actual communication signal channels according to the polarity order and the channel numbering order.

[0006] The present invention also includes a signal receiving method with a channel identification mechanism, applied in a signal receiving device, comprising: electrically coupling a signal receiving interface to a signal transmission line for signal receiving by a plurality of signal channels included in the signal receiving interface, wherein each signal channel includes a pair of differential signal lines; having a signal processing circuit detect the signal quantity of each signal channel in a link training program to determine that the signal channel whose signal quantity meets preset conditions is a plurality of actual communication signal channels; having the signal processing circuit detect a plurality of test data sequences transmitted by the actual communication signal channels in a link training program to identify the polarity order of the differential signal lines of each actual communication signal channel and the channel numbering order among the actual communication signal channels according to the data pattern of each test data sequence; and having the signal processing circuit receive actual data from the signal transmission line through the actual communication signal channels according to the polarity order and the channel numbering order after the link training program ends.

[0007] Regarding the features, implementation, and effects of this case, the preferred embodiments are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0008] Figure 1A A block diagram of a communication system according to one embodiment of the present invention is shown;

[0009] Figure 1B A block diagram of a signal transmission device according to one embodiment of the present invention is shown;

[0010] Figure 1C A block diagram of a signal transmission line according to one embodiment of the present invention is shown;

[0011] Figure 1D A block diagram of a signal receiving device according to one embodiment of the present invention is shown;

[0012] Figure 1E A block diagram of a signal receiving device with a misconfigured signal receiving interface is shown in one embodiment of the present invention.

[0013] Figure 2A as well as Figure 2B The diagrams show the signals received by the signal processing circuit through the differential signal line of the signal channel under different conditions in one embodiment of the present invention.

[0014] Figure 3 A schematic diagram of a test data sequence on a signal channel is shown in one embodiment of the present invention;

[0015] Figure 4A A block diagram of a signal transmission device is shown in another embodiment of the present invention;

[0016] Figure 4B A block diagram of a signal transmission line is shown in another embodiment of the present invention;

[0017] Figure 4C A block diagram of a signal receiving device according to another embodiment of the present invention is shown; and

[0018] Figure 5 A flowchart of a signal receiving method with a channel identification mechanism is shown in one embodiment of the present invention.

[0019] Explanation of reference numerals in the attached figures:

[0020] 100: Communication system; 110: Signal transmission device; 120: Signal receiving device

[0021] 130: Signal transmission line; 140: Signal transmission interface; 145: Signal processing circuit.

[0022] 150: First end; 155: Second end; 160: Wiring.

[0023] 170: Signal receiving interface; 175: Signal processing circuit; TM0~TM14: Timing.

[0024] 440: Signal transmission interface; 445: Signal processing circuit; 450: First terminal

[0025] 455: Second terminal; 460: Wiring; 470: Signal receiving interface

[0026] 475: Signal processing circuit; 500: Signal receiving method; S510~S540: Steps

[0027] AM: Instantaneous quantity; DS0~DS3: Test data sequence; DT0~DT9: Data

[0028] NE1~NE3: Negative edge; PE1~PE4: Positive edge; SA, SN: Signal

[0029] T1, T2: Time intervals LT0~LT3, LR0~LR3: Signal channels

[0030] ST: Preset semaphore threshold value; LR0+~LR3+, LR0-~LR3-: Differential signal lines

[0031] LT0+~LT3+, LT0-~LT3-: Differential signal lines Detailed Implementation

[0032] One object of the present invention is to provide a signal receiving device and method with a channel identification mechanism, which automatically identifies the number of channels, signal polarity and sequence by detecting the signal quantity and test data sequence, and can correctly receive signals under any channel configuration.

[0033] Please refer to Figure 1A . Figure 1A A block diagram of a communication system 100 according to an embodiment of the present invention is shown. The communication system 100 includes a signal transmitting device 110, a signal receiving device 120, and a signal transmission line 130.

[0034] The signal transmitting device 110 is configured to transmit signals via the signal transmission line 130. The signal receiving device 120 receives signals via the signal transmission line 130. In this embodiment, the signal transmitting device 110, the signal receiving device 120, and the signal transmission line 130 transmit and receive signals through a DisplayPort (DP) interface format.

[0035] Please refer to Figure 1B . Figure 1B A block diagram of a signal transmission device 110 according to an embodiment of the present invention is shown. The signal transmission device 110 includes a signal transmission interface 140 and a signal processing circuit 145.

[0036] The signal transmission interface 140 includes multiple signal channels LT0 to LT3 electrically coupled to the signal transmission line 130 for signal transmission. Each signal channel LT0 to LT3 includes a pair of differential signal lines. Since the differential signal lines have opposite polarities, the pair of differential signal lines corresponding to signal channel LT0 is labeled as LT0+ and LT0-, the pair of differential signal lines corresponding to signal channel LT1 is labeled as LT1+ and LT1-, the pair of differential signal lines corresponding to signal channel LT2 is labeled as LT2+ and LT2-, and the pair of differential signal lines corresponding to signal channel LT3 is labeled as LT3+ and LT3-.

[0037] In one embodiment, signal channels LT0-LT3 may be, for example, but not limited to, channels used to transmit high-speed image signals and referred to as the main link. Furthermore, the signal transmission interface 140 may actually include other channels not specified in the main link. Figure 1B The channel is shown. This invention is not limited thereto.

[0038] In one embodiment, the signal lines of the channels included in the signal transmission interface 140 may each have corresponding pin numbers, so as to be electrically coupled to the signal transmission line 130 through pins having these pin numbers. Figure 1BFor example, differential signal lines LT0+ and LT0- can have pin numbers 1 and 3 respectively, differential signal lines LT1+ and LT1- can have pin numbers 4 and 6 respectively, differential signal lines LT2+ and LT2- can have pin numbers 7 and 9 respectively, and differential signal lines LT3+ and LT3- can have pin numbers 10 and 12 respectively.

[0039] The signal processing circuit 145 is configured to generate signals to be transmitted for each signal channel LT0 to LT3, so as to transmit the signals to the signal transmission line 130 through the signal transmission interface 140.

[0040] Please refer to Figure 1C . Figure 1C A block diagram of a signal transmission line 130 according to an embodiment of the present invention is shown. The signal transmission line 130 includes a first end 150, a second end 155, and a trace 160.

[0041] Both the first end 150 and the second end 155 have pins with corresponding pin numbers. The trace 160 is configured to electrically couple the pins of the first end 150 and the second end 155. For example... Figure 1C As shown, the pin of the first terminal 150 is electrically coupled in reverse to the pin of the second terminal 155. More specifically, the pin of the first terminal 150 with pin number 1 is electrically coupled to the pin of the second terminal 155 with pin number 12. The pin of the first terminal 150 with pin number 2 is electrically coupled to the pin of the second terminal 155 with pin number 10. And so on, the pin of the first terminal 150 with pin number 12 is electrically coupled to the pin of the second terminal 155 with pin number 1.

[0042] Please refer to Figure 1D . Figure 1D A block diagram of a signal receiving device 120 according to an embodiment of the present invention is shown. The signal receiving device 120 includes a signal receiving interface 170 and a signal processing circuit 175.

[0043] The signal receiving interface 170 includes multiple signal channels LR0 to LR3 electrically coupled to the signal transmission line 130 for signal reception. Each signal channel LR0 to LR3 includes a pair of differential signal lines. Since the differential signal lines have opposite polarities, the pair of differential signal lines corresponding to signal channel LR0 are labeled as LR0+ and LR0-, the pair of differential signal lines corresponding to signal channel LR1 are labeled as LR1+ and LR1-, the pair of differential signal lines corresponding to signal channel LR2 are labeled as LR2+ and LR2-, and the pair of differential signal lines corresponding to signal channel LR3 are labeled as LR3+ and LR3-.

[0044] In one embodiment, signal channels LR0 to LR3 may be, for example, but not limited to, channels used to transmit high-speed image signals and referred to as the main link. Furthermore, the signal receiving interface 170 may actually include other channels not specified in the main link. Figure 1D The channel is shown. This invention is not limited thereto.

[0045] In one embodiment, the signal lines of the channels included in the signal receiving interface 170 may each have corresponding pin numbers, so as to be electrically coupled to the signal transmission line 130 through the pins having these pin numbers. However, it should be noted that, due to the configuration of the signal transmission line 130, the polarity order and channel order of the differential signal lines of the signal receiving interface 170 of the signal receiving device 120 are different from the polarity order and channel order of the differential signal lines of the signal transmission interface 140 of the signal transmission device 110.

[0046] by Figure 1D For example, differential signal lines LR3- and LR3+ can have pin numbers 1 and 3 respectively, differential signal lines LR2- and LR2+ can have pin numbers 4 and 6 respectively, differential signal lines LR1- and LR1+ can have pin numbers 7 and 9 respectively, and differential signal lines LR0- and LR0+ can have pin numbers 10 and 12 respectively. As can be seen from the above, the polarity order and channel order of the differential signal lines in the signal receiving interface 170 are completely opposite to those in the signal transmitting interface 140.

[0047] Signal processing circuit 175 is configured to receive signals from signal receiving interface 170 for processing. In one embodiment, based on the channel order of signal channels LT0 to LT3 of signal transmission device 110 and the polarity order of each pair of differential signal lines, signal processing circuit 175 anticipates receiving signals transmitted by signal transmission device 110 via each pair of differential signal lines of signal channels LT0 to LT3 from each pair of differential signal lines of signal channels LR0 to LR3.

[0048] Taking signal channel LR0 as an example, signal processing circuit 175 is expected to receive the signal from the differential signal line LR0+ of signal channel LR0 to the signal receiving and transmitting device 110 via the differential signal line LT0+ of signal channel LT0, and is expected to receive the signal from the differential signal line LR0- of signal channel LR0 to the signal receiving and transmitting device 110 via the differential signal line LT0- of signal channel LT0.

[0049] However, in some cases, the signal receiving device 120 may not have configured the channels of the signal receiving interface 170 according to the proper channel order during manufacturing.

[0050] Please refer to Figure 1E . Figure 1EA block diagram of a signal receiving device 120 with a misconfigured signal receiving interface 170 is shown in one embodiment of the present invention. Figure 1E In the signal receiving interface 170 and the signal transmitting interface 140, the polarity order and channel order configuration of the differential signal lines are the same, such that the differential signal lines LR0+ and LR0- have pin numbers of 1 and 3 respectively, the differential signal lines LR1+ and LR1- have pin numbers of 4 and 6 respectively, the differential signal lines LR2+ and LR2- have pin numbers of 7 and 9 respectively, and the differential signal lines LR3+ and LR3- have pin numbers of 10 and 12 respectively.

[0051] In this situation, taking signal channel LR0 as an example, the signal processing circuit 175 originally expected to receive the signal from the receiving signal transmission device 110 via the differential signal line LT0+ of signal channel LT0 from the differential signal line LR0+ of signal channel LR0. However, in reality, the signal processing circuit 175 will receive the signal from the receiving signal transmission device 110 via the differential signal line LT3- of signal channel LT3. Without a corresponding processing mechanism, the signal processing circuit 175 will be unable to correctly receive the signal due to the misconfiguration of the signal receiving interface 170.

[0052] The signal receiving device 120 of the present invention has a channel identification mechanism, even if such as Figure 1E Even when the channel configuration of the signal receiving interface 170 shown is incorrect, it can still receive signals correctly. The channel identification mechanism includes: (1) determining the actual communication signal channel; and (2) identifying the polarity order and the channel number order. The channel identification mechanism of the signal receiving device 120 will be described in sequence below.

[0053] (1) Determine the actual communication signal channel: The signal processing circuit 175 of the signal receiving device 120 is configured to detect the signal quantity of each signal channel in the link training program, so as to determine that the signal channel whose signal quantity meets the preset conditions is one of the multiple actual communication signal channels.

[0054] In the display interface protocol, the link training program is used to perform the establishment of the main link, and includes a clock signal transmission program for transmitting clock signals and a test data signal transmission program for transmitting test data sequences.

[0055] The signal transmission device 110 transmits a clock signal in the clock signal transmission procedure so that the signal receiving device 120 can confirm the frequency of the received signal. The signal transmission device 110 transmits a test data sequence in the test data signal transmission procedure so that the signal receiving device 120 can confirm whether the test data sequence can be received correctly. After the link training procedure is completed, the signal transmission device 110 performs actual data transmission to transmit image data, and the signal receiving device 120 performs actual data reception to receive the image data.

[0056] The signal processing circuit 175 can selectively detect the signal quantity of the clock signal in the clock signal transmission procedure, or selectively detect the signal quantity of the test data sequence in the test data signal transmission procedure, and detect the test data sequence in the test data signal transmission procedure. In practice, the signal processing circuit 175 may include multiple detection circuits (not shown) corresponding to each pair of differential signal lines of signal channels LR0 to LR3 to detect the signal quantity on signal channels LR0 to LR3.

[0057] Please refer to Figure 2A as well as Figure 2B . Figure 2A as well as Figure 2B The diagrams show the signals received by the signal processing circuit 175 under different conditions during the clock signal transmission process through the differential signal line LR3+ of the signal channel LR3 in one embodiment of the present invention.

[0058] In one embodiment, the signal processing circuit 175 is configured to determine whether the instantaneous quantity or average quantity of the signal is greater than a preset signal threshold value, so that if the instantaneous quantity or average quantity is greater than the preset signal threshold value, the signal is determined to meet a preset condition. The determination of the instantaneous quantity of the signal will be described below.

[0059] When the signal processing circuit 175 receives a signal through the differential signal line LR3+ of signal channel LR0, such as... Figure 2A When the signal SA is shown, the instantaneous quantity AM of time T1 is greater than the preset signal quantity threshold value ST, and it is determined that the signal quantity of signal channel LR3 meets the preset condition. At this time, the signal processing circuit 175 will determine that the signal on signal channel LR3 is actually transmitted from signal transmission device 110 through signal transmission line 130, and thus determine that signal channel LR3 is the actual communication signal channel.

[0060] When the signal processing circuit 175 receives a signal through the differential signal line LR3+ of signal channel LR3, such as... Figure 2BWhen the signal SN is shown, it will be determined that the instantaneous quantity at each time point is never greater than the preset signal quantity threshold value ST, and the signal quantity of signal channel LR3 will be determined that it does not meet the preset condition. At this time, the signal processing circuit 175 will determine that the signal on signal channel LR3 is generated by, for example but not limited to, noise, and thus determine that signal channel LR3 is not an actual communication signal channel.

[0061] Similarly, the signal processing circuit 175 can detect the average value of the signal over a period of time, and determine that the signal meets the preset condition when the average value is greater than a preset signal threshold value. Further details will not be provided here.

[0062] In another embodiment, the signal processing circuit 175 is configured to determine the number of times the change in the signal quantity is greater than a preset change threshold value, so that when the number of changes is greater than the threshold value, the signal quantity satisfies a preset condition.

[0063] More specifically, when the change in the signal quantity exceeds a preset change threshold, the signal processing circuit 175 determines whether the signal has undergone a state transition and exhibited a positive or negative edge. Therefore, the signal processing circuit 175 essentially determines that the signal quantity meets the preset condition when the number of occurrences of positive and negative edges exceeds a threshold.

[0064] For example, if the threshold value is 6, when the signal processing circuit 175 receives a signal through the differential signal line LR3+ of signal channel LR3, such as... Figure 2A When signal SA is shown, between time T1 and time T2, since signal SA has four positive edges PE1 to PE4 and three negative edges NE1 to NE3, the number of times the change in signal quantity exceeds a preset change threshold (7 times) exceeds a number threshold (6 times), and thus it is determined that the signal quantity of signal channel LR3 meets the preset condition. At this time, signal processing circuit 175 will determine that the signal on signal channel LR3 is actually transmitted from signal transmission device 110 through signal transmission line 130, and thus determine that signal channel LR3 is the actual communication signal channel.

[0065] When the signal processing circuit 175 receives a signal through the differential signal line LR3+ of signal channel LR3, such as... Figure 2B When the signal SN is shown, the circuit will determine that the number of times the change in the signal quantity exceeds a preset change threshold is 0 and does not exceed the number threshold, and thus determine that the signal quantity of signal channel LR3 does not meet the preset condition. At this time, the signal processing circuit 175 will determine that the signal on signal channel LR3 is generated by, for example but not limited to, noise, and thus determine that signal channel LR3 is not an actual communication signal channel.

[0066] In another embodiment, the signal processing circuit 175 determines that the signal quantity meets the preset condition only when the signal quantity is greater than a preset signal quantity threshold and the number of times the signal quantity changes greater than a preset change threshold is greater than a number threshold. In other embodiments, the signal processing circuit 175 may also make the determination based on parameters obtained by other calculations of the signal quantity. The present invention is not limited thereto.

[0067] It should be noted that, generally speaking, the differential signal lines of each signal channel LR0 to LR3 will receive signals with opposite polarities. Therefore, for each signal channel LR0 to LR3, the signal processing circuit 175 can determine the signal quantity only for one of the differential signal lines in the pair (for example, only for the differential signal line that is positive), instead of determining the signal quantity for both differential signal lines in the pair.

[0068] In one embodiment, in addition to the link training procedure, the signal transmitting device 110 and the signal receiving device 120 can also perform a handshake procedure through the signal transmitting interface 140, the signal transmission line 130, and the auxiliary (AUX) channel (not shown) included in the signal receiving interface 170. This allows the signal transmitting device 110 to inform the signal receiving device 120 of the frequency of the signal transmission to be performed and the signal channel used. However, even after obtaining the above information through the handshake procedure, the signal receiving device 120 can still reconfirm the actual communication signal channel among signal channels LR0 to LR3 through the aforementioned signal quantity detection and judgment.

[0069] On the other hand, when the signal transmitting device 110 and the signal receiving device 120 do not perform a handshake procedure, the signal receiving device 120 can also determine the actual communication signal channel in the signal channels LR0 to LR3 by detecting and judging the above-mentioned signal quantity.

[0070] In the display interface protocol, the signal receiving device 120 can operate in single-signal-channel (1-lane) mode, dual-signal-channel (2-lane) mode, or quad-signal-channel (4-lane) mode. Therefore, after the signal processing circuit 175 completes the detection and judgment of the above-mentioned signal quantity, the signal receiving device 120 can determine whether the actual number of communication signal channels in signal channels LR0 to LR3 is 1, 2, or 4.

[0071] (2) Identifying polarity order and channel number order: The signal processing circuit 175 of the signal receiving device 120 is configured to detect multiple test data sequences transmitted by the actual communication signal channel in the link training program, so as to identify the polarity order of the differential signal lines of each actual communication signal channel and the channel number order of the actual communication signal channel according to the data pattern of each test data sequence.

[0072] Since the test data sequence is transmitted by the signal transmission device 110 in the test data signal transmission program of the link training program, the detection of the test data sequence by the signal processing circuit 175 is performed in the test data signal transmission program.

[0073] The detection and identification of test data sequences can be categorized into different application scenarios depending on whether a handshake procedure is executed and the version of the display interface. The following will describe examples for four different application scenarios.

[0074] In the first application scenario, a handshake procedure is performed between the signal transmitting device 110 and the signal receiving device 120, and the display interface is version 1.4. More specifically, in this application scenario, the signal processing circuit 175 detects the test data sequence transmitted through the actual communication signal channel after the handshake procedure has been executed.

[0075] At this time, the signal processing circuit 175 is configured to identify the polarity order by comparing the data pattern with the expected data pattern. More specifically, the data pattern of the test data sequence transmitted by the signal transmission device 110 is periodic. The signal processing circuit 175 of the signal receiving device 120 stores the expected data pattern, and therefore knows what the content of the test data sequence data pattern is in the positive polarity order.

[0076] The signal processing circuit 175 can determine that the polarity order of the pair of differential signal lines is positive when the received data pattern matches the expected data pattern, and determine that the polarity order of the pair of differential signal lines is negative when the received data pattern does not match the expected data pattern. In one embodiment, when the received data pattern does not match the expected data pattern, the signal processing circuit 175 can also reverse the polarity of the data pattern of the test data sequence and compare it with the expected data pattern, or simultaneously store the expected data pattern with reversed polarity for comparison with the data pattern of the test data sequence, to further confirm that the polarity order of the pair of differential signal lines is negative.

[0077] In one embodiment, the signal processing circuit 175 may pre-store a expected data pattern, or obtain and store the expected data pattern from the signal transmission device 110 through the execution of the handshake procedure. In one embodiment, since the signal processing circuit 175 can know the code pattern of the test data sequence in advance through the execution of the handshake procedure, the expected value of the cyclic redundancy check (CRC) can be used as the basis for judging the expected data pattern. The signal processing circuit 175 can calculate the actual value of the CRC of the received test data sequence as the data pattern to determine whether it matches the expected value of the CRC, and then determine the polarity order of the differential signal lines.

[0078] On the other hand, the signal processing circuit 175 is configured to determine that the data patterns of each test data sequence in the test data sequence are the same and that they have different and fixed transmission timings, so as to determine the order of the channel numbers of the actual communication signal channels according to the order of the transmission timings.

[0079] The following explanation assumes that all signal channels LR0 to LR3 are determined to be actual communication signal channels (four-signal channel mode).

[0080] Please refer to Figure 3 . Figure 3 The diagram shows a schematic of the test data sequence DS0-DS3 on signal channels LR0-LR3 in one embodiment of the present invention.

[0081] like Figure 3 As shown, the test data sequences DS0 to DS3 all include periodically occurring data patterns, and these data patterns include data DT0 to DT9, which are, for example, but not limited to, K28.5-, D11.6, K28.5+, D11.6, D10.2, D10.2, D10.2, D10.2, D10.2, and D10.2. When transmitting the test data sequences DS0 to DS3, the signal transmission device 110 transmits the test data sequences DS0 to DS3 at different and fixed intervals according to the order of the signal channels LT0 to LT3 of the signal transmission interface 140. Therefore, after receiving the test data sequences DS0 to DS3, the signal processing circuit 175 can first calculate the actual value of the cyclic redundancy check (CRC) based on the test data sequences DS0 to DS3 and compare it with the expected value of the CRC to determine the polarity order of the differential signal lines, and then determine the order of the channel numbers of the actual communication signal channels based on the order of the transmission times.

[0082] In practice, the signal processing circuit 175 can select one of the data DT0 to DT9 as the basis for timing counting. For example, the signal processing circuit 175 can reset the count value to zero when it receives data DT0, and sequentially increment the count value by 1 when it receives data DT1 to DT9.

[0083] by Figure 3 In one embodiment, the signal processing circuit 175 counts the test data sequence DS3 from 0 to 9 in timings TM0 to TM9, and resets the count of test data sequence DS3 to zero in timing TM10. The signal processing circuit 175 counts the test data sequence DS2 from 0 to 8 in timings TM2 to TM10, counts the test data sequence DS1 from 0 to 6 in timings TM4 to TM10, and counts the test data sequence DS0 from 0 to 4 in timings TM6 to TM10.

[0084] During timing TM6, the signal processing circuit 175 can sequentially obtain count values ​​of 0, 2, 4, and 6 for the test data sequences DS0 to DS3. Since the count values ​​form an arithmetic sequence, the signal processing circuit 175 can determine that the transmission timings are different and the intervals are fixed. Furthermore, it can determine that the transmission order is: test data sequence DS3 first, test data sequence DS2 second, test data sequence DS1 third, and test data sequence DS0 last. The signal processing circuit 175 further determines that the channel order corresponding to the signal channel LR3 receiving test data sequence DS3 is first, the channel order corresponding to the signal channel LR2 receiving test data sequence DS2 is second, the channel order corresponding to the signal channel LR1 receiving test data sequence DS1 is third, and the channel order corresponding to the signal channel LR0 receiving test data sequence DS0 is last.

[0085] Therefore, the signal processing circuit 175 can determine, based on the aforementioned channel order, that signal channel LR3 actually corresponds to the first signal channel LT0 in the signal transmission interface 140 of the signal transmission device 110. Signal channel LR2 actually corresponds to the next signal channel LT1 in the signal transmission interface 140 of the signal transmission device 110. Signal channel LR1 actually corresponds to the next signal channel LT2 in the signal transmission interface 140 of the signal transmission device 110. Signal channel LR0 actually corresponds to the last signal channel LT3 in the signal transmission interface 140 of the signal transmission device 110.

[0086] In the second application scenario, a handshake procedure is performed between the signal transmitting device 110 and the signal receiving device 120, and the display interface is version 2.1. More specifically, in this application scenario, the signal processing circuit 175 detects the test data sequence transmitted through the actual communication signal channel after the handshake procedure has been executed.

[0087] At this time, the signal processing circuit 175 is configured to identify the polarity order by comparing specific data content in the data sample with the expected data content.

[0088] In one embodiment, when the display interface is version 2.1, the data pattern of the test data sequence transmitted by the signal transmission device 110 will be a 128b132B_DP_TPS2 sequence, and this sequence includes a physical layer synchronization symbol (PHY sync symbol). The signal processing circuit 175 will pre-store the positive content 33CCCCCCh of the physical layer synchronization symbol when the polarity is positive, and store the negative content CC333333h of the physical layer synchronization symbol when the polarity is negative.

[0089] Therefore, after receiving the test data sequence data sample, the signal processing circuit 175 determines whether the physical layer synchronization code (specific data content) it includes conforms to the positive content. If the physical layer synchronization code conforms to the positive content, the polarity order of the pair of differential signal lines is determined to be positive. Furthermore, if the physical layer synchronization code does not conform to the positive content, or if the physical layer synchronization code conforms to the negative content, the signal processing circuit 175 determines the polarity order of the pair of differential signal lines to be negative.

[0090] On the other hand, the signal processing circuit 175 is configured to descramble multiple permutations of the test data sequence DS0 to DS3 according to multiple preset initial values ​​for the corresponding channel numbers. When the data symbol of the data sample generated after descrambling a specific combination matches the preset value, the channel number order of the actual communication signal channel is determined based on that specific combination. For example, when the transmitted data sequence is a 128b132B_DP_TPS2 sequence, the data symbol is fixed at 0. However, the present invention is not limited to this.

[0091] For example, the signal processing circuit 175 can sequentially assume that the order of one of the 24 permutations of the test data sequence DS0 to DS3 matches the channel numbering order, and descramble each of the 24 permutations one by one using known channel preset initial values. When the data symbols of the data sample generated after descrambling for a specific combination of the 24 permutations are all 0, it indicates that the descrambling result is correct. The signal processing circuit 175 can therefore determine that the order of this specific combination corresponds to the channel numbering order of the actual communication signal channel.

[0092] For example, when the descrambling result of the test data sequence DS3, DS2, DS1, DS0 is correct, the signal processing circuit 175 determines that the order of this specific combination corresponds to the channel numbering order of the actual communication signal channels. The signal processing circuit 175 further determines that the signal channel LR3 receiving the test data sequence DS3 actually corresponds to signal channel LT0 in the signal transmission interface 140 of the signal transmission device 110; the signal channel LR2 receiving the test data sequence DS2 actually corresponds to the next-order signal channel LT1 in the signal transmission interface 140 of the signal transmission device 110; the signal channel LR1 receiving the test data sequence DS1 actually corresponds to the next-order signal channel LT2 in the signal transmission interface 140 of the signal transmission device 110; and the signal channel LR0 receiving the test data sequence DS0 actually corresponds to the last-order signal channel LT3 in the signal transmission interface 140 of the signal transmission device 110.

[0093] In the third application scenario, no handshake procedure was performed between the signal transmitting device 110 and the signal receiving device 120, and the display interface was version 1.4.

[0094] When the signal transmission device 110 and the signal receiving device 120 have not executed the handshake procedure, the signal processing circuit 175 can first perform a clock data recovery procedure to reconstruct the test data sequence, and then test the test data sequence.

[0095] More specifically, even if the handshake procedure is not executed, the signal processing circuit 175 can still determine the frequency of the clock signal by detecting the signal quantity in the first stage and perform the clock data recovery procedure. When the regular clock signal ends and irregular positive and negative edges are detected, it determines that the test data signal transmission procedure has started and detects the test data sequence accordingly.

[0096] At this time, the signal processing circuit 175 is configured to identify the polarity order by comparing specific data content in the data sample with the expected data content.

[0097] In one embodiment, when the display interface is version 1.4, the test data sequence transmitted by the signal transmission device 110 includes Main Stream Attribute Data (MSA). The signal processing circuit 175 determines the polarity order to be forward when the MSA in the data samples corresponding to different frames after descrambling is identical and the data size meets a preset condition. Furthermore, the signal processing circuit 175 determines the polarity order to be reverse when the MSA in the data samples corresponding to different frames after descrambling is different from each other or the data size does not meet the preset condition. In one embodiment, for MSA, the preset condition is that the total image length is always greater than the length of the actual image display area, and the total image width is always greater than the width of the actual image display area. However, the present invention is not limited to the use of MSA and may have different preset conditions depending on the data sample used.

[0098] On the other hand, the signal transmission device 110 can determine, using the same method as in the first application scenario, that the data patterns of each test data sequence in the test data sequence are the same and that they have different and fixed transmission timing sequences, so as to determine the order of the channel numbers of the actual communication signal channels according to the order of the transmission timing sequences. Further details will not be elaborated here.

[0099] In the fourth application scenario, no handshake procedure was performed between the signal transmitting device 110 and the signal receiving device 120, and the display interface was version 2.1.

[0100] Similar to the third application scenario, when the signal transmission device 110 and the signal receiving device 120 have not executed the handshake procedure, the signal processing circuit 175 can first perform a clock data recovery procedure to reconstruct the test data sequence, and then detect the test data sequence.

[0101] At this point, the signal processing circuit 175 can identify the polarity order of the differential signal lines by comparing specific data content in the data sample with the expected data content, using the same method as in the second application scenario. It should be noted that the physical layer synchronization code, when transmitting image data, differs from the transmission of the 128b132B_DP_TPS2 sequence; it may contain XY111111h or XY4444444h, etc. However, if the polarity is reversed, it will periodically receive X'Y'EEEEEEh or X'Y'BBBBBBh content. The signal processing circuit 175 can therefore determine the polarity status accordingly.

[0102] On the other hand, the signal processing circuit 175 can descramble multiple permutations of the test data sequence DS0 to DS3 using the same method as in the second application scenario, with preset initial values ​​for the channels, and determine the channel numbering order of the actual communication signal channels based on the descrambling results. For example, only when the channel numbering order is correct will the descrambled data have the same control link symbol, and the data following the specific control link symbol will be identical. The signal processing circuit 175 can therefore determine the channel numbering order of the actual communication signal channels accordingly.

[0103] It should be noted that, generally speaking, the differential signal lines of each signal channel LR0 to LR3 transmit signals with opposite polarities. Therefore, for each signal channel LR0 to LR3, the signal processing circuit 175 can perform the test data sequence DS0 to DS3 judgment only on one of the differential signal lines in the pair (for example, only on the positive differential signal line), instead of performing the test data sequence DS0 to DS3 judgment on all differential signal lines in the pair.

[0104] In the above embodiment, the example is given with four actual communication signal channels (four-channel mode). However, when the number of actual communication signal channels is two (two-channel mode), the signal processing circuit 175 can also identify the polarity order of the differential signal lines and the channel numbering order among the actual communication signal channels using the method described above for detecting the test data sequence. When the number of actual communication signal channels is one (single-channel mode), the signal processing circuit 175 only needs to identify the polarity order and does not need to additionally determine the channel numbering order.

[0105] After the link training program is completed, the signal processing circuit 175 receives actual data from the signal transmission line through the actual communication signal channel according to the polarity order and channel number order.

[0106] More specifically, when the polarity order is forward, the signal processing circuit 175 directly receives the data received by the corresponding pair of differential signal lines in each actual communication signal channel. When the polarity order is reverse, the signal processing circuit 175 reverses the data received by the corresponding pair of differential signal lines in each actual communication signal channel before receiving it. On the other hand, the signal processing circuit 175 receives actual data from the signal transmission line through the actual communication signal channel according to the determined channel number order.

[0107] by Figure 1EIn an embodiment, when the signal processing circuit 175 determines that signal channels LR0 to LR3 are all actual communication signal channels (four-signal channel mode), it will further determine that the polarity order of each pair of differential signal lines is reversed, and that signal channels LR3 to LR0 actually correspond to signal channels LT0 to LT3.

[0108] Therefore, after processing by the channel identification mechanism, the signal processing circuit 175 receives actual data according to the channel order of signal channels LR3 to LR0, and reverses the data of each pair of differential signal lines in signal channels LR3 to LR0.

[0109] The signal processing circuit 175 can determine whether the differential signal lines LR3- and LR3+ of signal channel LR3 receive signals from the differential signal lines LT0+ and LT0- of signal channel LT0; whether the differential signal lines LR2- and LR2+ of signal channel LR2 receive signals from the differential signal lines LT1+ and LT1- of signal channel LT1; whether the differential signal lines LR1- and LR1+ of signal channel LR1 receive signals from the differential signal lines LT2+ and LT2- of signal channel LT2; and whether the differential signal lines LR0- and LR0+ of signal channel LR0 receive signals from the differential signal lines LT3+ and LT3- of signal channel LT3, thus obtaining the correct signal reception result.

[0110] Please refer to the following at the same time Figure 4A , Figure 4B as well as Figure 4C . Figure 4A A block diagram of a signal transmission device 110 according to another embodiment of the present invention is shown. Figure 4B A block diagram of the signal transmission line 130 is shown in another embodiment of the present invention.

[0111] Figure 4C A block diagram of a signal receiving device 120 is shown in another embodiment of the present invention. In this embodiment, the signal transmitting device 110, the signal receiving device 120, and the signal transmission line 130 can transmit and receive signals via an interface format of Universal Serial Bus Type-C (USB Type-C).

[0112] In this embodiment, the signal transmission device 110 includes a signal transmission interface 440 and a signal processing circuit 445. The signal receiving device 120 includes a signal receiving interface 470 and a signal processing circuit 475. The signal transmission interface 440 and the signal receiving interface 445 each include multiple signal channels LT0 to LT3 and multiple signal channels LR0 to LR3, and each signal channel includes a pair of differential signal lines. The pairs of differential signal lines are sequentially labeled A2 and A3, A10 and A11, B2 and B3, and B10 and B11.

[0113] The signal transmission line 130 includes a first end 450, a second end 455, and a trace 460. The first end 450 and the second end 455 each have pins corresponding to the aforementioned differential signal lines. The trace 460 electrically couples the pins of the first end 450 and the second end 455 in reverse order. Since the Type-C universal serial bus interface supports both normal and reverse insertion, the pins of the signal transmission line 430 at the first end 450 and the second end 455 are labeled A2 / B2 and A3 / B3, A10 / B10 and A11 / B11, B2 / A2 and B3 / A3, and B10 / A10 and B11 / A11, respectively. The normal insertion state is indicated before the symbol " / ", and the reverse insertion state is indicated after the symbol " / ".

[0114] Because the signal transmission line 130 can be inserted in both directions, the signal processing circuit 470 of the signal receiving device 120 also needs to determine the number, polarity, and channel order of the actual communication signal channels to ensure correct signal reception. The signal receiving device 420 can make this determination according to the methods described in the embodiments using the display interface as an example, in order to implement a channel identification mechanism and achieve the goal of correctly receiving actual data.

[0115] Please refer to Figure 5 . Figure 5 A flowchart of a signal receiving method 500 with a channel identification mechanism is shown in one embodiment of the present invention.

[0116] In addition to the aforementioned apparatus, this invention also discloses a signal receiving method 500 with a channel identification mechanism, applicable to, for example, but not limited to, the signal receiving apparatus 100 of FIG. 1. One embodiment of the signal receiving method 500 is as follows: Figure 5 As shown, it includes the following steps.

[0117] In step S510, the signal receiving interface 170 is electrically coupled to the signal transmission line 130 to receive signals from the plurality of signal channels LR0 to LR3 included in the signal receiving interface 170, wherein each of the signal channels LR0 to LR3 includes a pair of differential signal lines.

[0118] In step S520, the signal processing circuit 175 detects the signal quantity of each signal channel in the link training program LR0 to LR3 to determine that the signal channel whose signal quantity meets the preset conditions is one of the multiple actual communication signal channels.

[0119] In step S530, the signal processing circuit 175 detects multiple test data sequences transmitted by the actual communication signal channel in the link training program, so as to identify the polarity order of the differential signal lines of each actual communication signal channel and the channel numbering order between the actual communication signal channels according to the data pattern of each test data sequence.

[0120] In step S540, after the link training program is completed, the signal processing circuit 175 receives actual data from the signal transmission line through the actual communication signal channel according to the polarity order and channel number order.

[0121] It should be noted that the above-described implementation is only one embodiment. In other embodiments, those skilled in the art can make modifications and variations without departing from the spirit of the invention.

[0122] For example, the present invention can be applied to other signal transmission interfaces with multiple signal channels, and is not limited to the aforementioned display interface and Type-C universal serial bus interface. Furthermore, the number of signal channels described above is only one embodiment; the present invention can be applied to scenarios with a greater number of signal channels. Moreover, the above embodiments are all described with the channel order of the signal receiving interface being completely reversed compared to the channel order of the signal transmitting interface. However, the present invention can identify signal receiving interfaces with any channel order arrangement, and is not limited to the channel order of the above embodiments.

[0123] In summary, the signal receiving device and method with channel identification mechanism of the present invention can automatically identify the number of channels, signal polarity and sequence by detecting the signal quantity and test data sequence, and can correctly receive signals under any channel configuration.

[0124] While the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention. Those skilled in the art can make changes to the technical features of the present invention based on the explicit or implicit content of the present invention, and all such changes fall within the scope of protection claimed by the present invention. In other words, the scope of protection of the present invention should be determined by the claims of the present invention.

Claims

1. A signal receiving device with a channel identification mechanism, comprising: A signal receiving interface includes multiple signal channels electrically coupled to a signal transmission line for signal reception, each of the multiple signal channels including a pair of differential signal lines; and A signal processing circuit, configured with: In a link training program, a semaphore of each of the multiple signal channels is detected to determine that the multiple signal channels whose semaphores satisfy a preset condition are multiple actual communication signal channels. In the link training program, multiple test data sequences transmitted by the multiple actual communication signal channels are detected, so as to identify a polarity order of the differential signal lines of each actual communication signal channel and a channel numbering order among the multiple actual communication signal channels based on a data pattern of each test data sequence. as well as After the link training program is completed, actual data is received from the signal transmission line through the multiple actual communication signal channels according to the polarity order and the channel number order.

2. The signal receiving device according to claim 1, characterized in that, The signal processing circuit is configured to determine whether an instantaneous quantity or an average quantity of the signal is greater than a preset signal threshold value, so that when the instantaneous quantity or the average quantity is greater than the preset signal threshold value, the signal satisfies the preset condition.

3. The signal receiving device according to claim 1, characterized in that, The signal processing circuit is configured to determine the number of times a change in the signal quantity exceeds a preset change threshold, and to determine that the signal quantity meets the preset condition when the number of changes exceeds the threshold.

4. The signal receiving device according to claim 1, characterized in that, The signal processing circuit is configured to identify the polarity order by comparing the data pattern with a expected data pattern or by comparing a specific data content in the data pattern with an expected data content, and is further configured to: When the data pattern matches the expected data pattern or the specific data content matches the expected data content, the polarity order is determined to be a positive order. When the data pattern does not match the expected data pattern or the specific data content does not match the expected data content, the polarity order is determined to be a reverse order. When the polarity order is the positive order, the data received by the differential signal line of each of the plurality of actual communication signal channels is received; as well as When the polarity order is the reverse order, the data received by the differential signal lines of each of the plurality of actual communication signal channels is reversed before being received.

5. The signal receiving device according to claim 4, characterized in that, The specific data content is a physical layer synchronization code or a main stream attribute data. When the physical layer synchronization code conforms to a positive content or the main stream attribute data in the data patterns corresponding to multiple different screens are all the same and a data size meets a preset condition, the polarity order is determined to be the positive order.

6. The signal receiving device according to claim 1, characterized in that, The signal processing circuit is configured to determine that the data patterns of each of the plurality of test data sequences are the same and that there is a transmission timing sequence that is different from each other and is spaced at a fixed interval, so as to determine the order of the channel numbers of the plurality of actual communication signal channels according to the order of the transmission timing sequence.

7. The signal receiving device according to claim 1, characterized in that, The signal processing circuit is configured to descramble multiple permutations and combinations of the multiple test data sequences according to multiple preset initial values ​​corresponding to the channel numbering order, so that when a data symbol of the data pattern generated after descrambling a specific combination of the multiple permutations and combinations matches a preset value, the channel numbering order of the multiple actual communication signal channels is determined according to the specific combination.

8. The signal receiving device according to claim 1, characterized in that, The signal processing circuit is configured to detect the plurality of test data sequences transmitted by the plurality of actual communication signal channels after a handshake procedure has been executed, or to perform a clock data recovery procedure to reconstruct the plurality of test data sequences for detection when the handshake procedure has not been executed.

9. The signal receiving device according to claim 1, characterized in that, The link training program includes a clock signal transmission program for transmitting a clock signal and a test data signal transmission program for transmitting the test data sequence. The signal processing circuit is configured to selectively detect the signal quantity in the clock signal transmission procedure or selectively detect the signal quantity in the test data signal transmission procedure, and to detect the test data sequence in the test data signal transmission procedure.

10. A signal receiving method with a channel identification mechanism, applied in a signal receiving device, comprising: A signal receiving interface is electrically coupled to a signal transmission line to receive signals through a plurality of signal channels included in the signal receiving interface, wherein each of the plurality of signal channels includes a pair of differential signal lines. A signal processing circuit in a link training program detects a signal quantity of each of the multiple signal channels to determine that the multiple signal channels whose signal quantities satisfy a preset condition are multiple actual communication signal channels. The signal processing circuit detects multiple test data sequences transmitted by the multiple actual communication signal channels in the link training program, so as to identify a polarity order of the differential signal lines of each actual communication signal channel and a channel numbering order among the multiple actual communication signal channels based on a data pattern of each test data sequence. as well as After the link training program is completed, the signal processing circuit receives actual data from the signal transmission line through the multiple actual communication signal channels according to the polarity order and the channel number order.

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