Coherent optical module dither signal generation method and circuit

Abstract

The application discloses a coherent light module Dither signal generation method and circuit, belongs to the technical field of coherent light module Dither signal generation, and comprises the following steps: generating a first square wave signal, a second square wave signal, a first DAC signal, a second DAC signal and a third DAC signal, and determining the voltage amplitude of the first DAC signal, the voltage amplitude of the second DAC signal and the voltage amplitude of the third DAC signal based on the optical power detection voltage reflecting the change of I-path output optical power, the optical power detection voltage reflecting the change of Q-path output optical power and the detection voltage reflecting the difference between the phase of I-path output optical power and the phase of Q-path output optical power. The application can simplify the IQ modulator bias point control circuit in the coherent light module, optimize the software design, and save the external DAC with high sampling rate requirement.

Description

TECHNICAL FIELD

[0001] The application relates to a Dither signal generation technology of a coherent optical module, in particular to a Dither signal generation method and circuit of a coherent optical module. BACKGROUND

[0002] The coherent optical communication has been an optimal scheme for long-distance data transmission because of the use of coherent modulation and coherent receiving technology and the combination of powerful algorithm functions. In recent years, with the continuous increase of the data volume of communication links, the coherent optical communication is gradually valued in the fields of data centers and satellite Internet and is constantly popularized and applied due to the rich modulation formats, strong data bearing capacity and high sensitivity. The bias point locking technology of an IQ modulator is one of key technologies of a coherent optical module and is a basic guarantee for normal transmission of a coherent optical modulation signal. At present, the method commonly used for bias point control is to add Dither signals (perturbation signals) to the I path and Q path bias of an IQ modulator, and the bias point is judged and locked through the power size of the corresponding Dither signals in the output optical power of the IQ modulator. SUMMARY

[0003] The application aims to provide a Dither signal generation method and circuit of a coherent optical module, which can simplify the bias point control circuit of an IQ modulator in the coherent optical module, optimize the software design, save the DAC with a high external sampling rate requirement, reduce the design cost and achieve the expected bias point control function.

[0004] A Dither signal generation method of a coherent optical module comprises the following steps:

[0005] First, second, third, fourth and fifth DAC signals are generated, and the voltage amplitudes of the first, second and third DAC signals are determined based on the optical power detection voltage reflecting the change of the I path output optical power, the optical power detection voltage reflecting the change of the Q path output optical power and the detection voltage reflecting the difference between the phase of the I path output optical power and the phase of the Q path output optical power.

[0006] The first Dither signal is obtained by performing addition operation on the first DAC signal after the first square wave signal is filtered, and the second Dither signal is obtained by performing addition operation on the second DAC signal after the second square wave signal is filtered.

[0007] The first Dither signal is loaded to the I path bias voltage control pin of the IQ modulator, the second Dither signal is loaded to the Q path bias voltage control pin of the IQ modulator, and the third DAC signal is loaded to the phase bias point voltage control pin of the IQ modulator.

[0008] The IQ modulator generates an optical power detection current reflecting the change of the I output optical power, an optical power detection current reflecting the change of the Q output optical power, and a detection current reflecting the difference between the phase of the I output optical power and the phase of the Q output optical power;

[0009] The optical power detection current reflecting the change of the I output optical power, the optical power detection current reflecting the change of the Q output optical power, and the detection current reflecting the difference between the phase of the I output optical power and the phase of the Q output optical power are correspondingly converted into an optical power detection voltage reflecting the change of the I output optical power, an optical power detection voltage reflecting the change of the Q output optical power, and a detection voltage reflecting the difference between the phase of the I output optical power and the phase of the Q output optical power.

[0010] The direct current bias voltage loaded on the I bias voltage control pin and the direct current bias voltage loaded on the Q bias voltage control pin are both set at the NULL point, and the phase bias point loaded on the phase bias voltage control pin is 1 / 2π.

[0011] Before the band-pass filtering, further comprising: a step of performing signal attenuation processing on the first square wave signal and the second square wave signal, respectively.

[0012] Before the corresponding determination of the voltage amplitude of the first DAC signal, the voltage amplitude of the second DAC signal, and the voltage amplitude of the third DAC signal based on the optical power detection voltage reflecting the change of the I output optical power, the optical power detection voltage reflecting the change of the Q output optical power, and the detection voltage reflecting the difference between the phase of the I output optical power and the phase of the Q output optical power, further comprising: a step of sequentially performing amplification and low-pass filtering processing on the optical power detection voltage reflecting the change of the I output optical power, the optical power detection voltage reflecting the change of the Q output optical power, and the detection voltage reflecting the difference between the phase of the I output optical power and the phase of the Q output optical power.

[0013] The first square wave signal and the second square wave signal are both periodic square wave signals with a duty cycle of 50%.

[0014] A coherent optical module Dither signal generation circuit, comprising:

[0015] A processing unit for generating a first square wave signal, a second square wave signal, a first DAC signal, a second DAC signal, and a third DAC signal, and for correspondingly determining the voltage amplitude of the first DAC signal, the voltage amplitude of the second DAC signal, and the voltage amplitude of the third DAC signal based on an optical power detection voltage reflecting the change of the I output optical power, an optical power detection voltage reflecting the change of the Q output optical power, and a detection voltage reflecting the difference between the phase of the I output optical power and the phase of the Q output optical power.

[0016] a first band-pass filter for band-pass filtering the first square wave signal;

[0017] a first adder circuit for adding the band-pass filtered first square wave signal and a first DAC signal and outputting a first Dither signal;

[0018] a second band-pass filter for band-pass filtering the second square wave signal;

[0019] a second adder circuit for adding the band-pass filtered second square wave signal and a second DAC signal and outputting a second Dither signal;

[0020] an IQ modulator, an I-path bias voltage control pin of which is loaded with the first Dither signal, a Q-path bias voltage control pin of which is loaded with the second Dither signal, a phase bias point voltage control pin of which is loaded with the third DAC signal, and an optical power detection output pin of which outputs an optical power detection current reflecting changes in I-path output optical power, an optical power detection current reflecting changes in Q-path output optical power, and a detection current reflecting the difference between the phase of the I-path output optical power and the phase of the Q-path output optical power;

[0021] an amplification circuit for converting the optical power detection current reflecting changes in I-path output optical power, the optical power detection current reflecting changes in Q-path output optical power, and the detection current reflecting the difference between the phase of the I-path output optical power and the phase of the Q-path output optical power into optical power detection voltages reflecting changes in I-path output optical power, optical power detection voltages reflecting changes in Q-path output optical power, and detection voltages reflecting the difference between the phase of the I-path output optical power and the phase of the Q-path output optical power, and amplifying the same.

[0022] the DC bias voltage loaded in the I-path bias voltage control pin and the DC bias voltage loaded in the Q-path bias voltage control pin are set at NULL points, and the phase bias point loaded in the phase bias point voltage control pin is 1 / 2π.

[0023] further comprising:

[0024] a first attenuator, an input end of which inputs the first square wave signal, and an output end of which is electrically connected to an input end of the first band-pass filter;

[0025] a second attenuator, an input end of which inputs the second square wave signal, and an output end of which is electrically connected to an input end of the second band-pass filter.

[0026] further comprising:

[0027] a low-pass filter, an input end of which is electrically connected to an output end of the amplification circuit, and an output end of which is electrically connected to an ADC0 input end of the processing unit.

[0028] The first square wave signal and the second square wave signal are periodic square wave signals with a duty cycle of 50%.

[0029] Compared with the prior art, the application has the following advantages and beneficial effects:

[0030] 1. The application eliminates the DAC chip with a higher sampling rate requirement in the prior art, and instead uses an attenuator and a band-pass filter, thus having obvious cost advantage.

[0031] 2. The processing unit of the application only needs to output periodic square wave signals, thus simplifying the algorithm design of related waveform generation.

[0032] 3. The application uses a band-pass filter to generate a sine signal, so that the spectrum of the Dither signal is cleaner and does not need to be filtered again.

[0033] 4. The application uses an attenuator and a band-pass filter, thus occupying smaller PCB size and being more conducive to the application of circuit high integration. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 The figure is a principle block diagram of the coherent light module Dither signal generation circuit of the application.

[0035] Figure 2 The figure is a structure schematic diagram of the specific circuit of the first band-pass filter, the second band-pass filter, the first attenuator and the second attenuator of the application.

[0036] Figure 3 The figure is a structure schematic diagram of the specific circuit of the first addition operation circuit and the second addition operation circuit of the application.

[0037] Figure 4 The figure is a structure schematic diagram of the specific circuit of the low-pass filter and the amplification circuit of the application. DETAILED DESCRIPTION

[0038] Referring to Figure 1 The coherent light module Dither signal generation circuit of the application comprises a processing unit 101, an IQ modulator 102, a first band-pass filter 104, a first addition operation circuit 105, an amplification circuit 107, a second band-pass filter 108 and a second addition operation circuit 109. Figure 1 In the formula, XI_DATA is an I path input data signal of the IQ modulator 102, XQ_DATA is a Q path input data signal of the IQ modulator 102, XI is an I path data input pin of the IQ modulator 102, and XQ is a Q path data input pin of the IQ modulator 102.

[0039] The processing unit 101 is configured to generate a first square wave signal, a second square wave signal, a first DAC signal, a second DAC signal and a third DAC signal. The first square wave signal and the second square wave signal are periodic square wave signals with a duty cycle of 50%. The processing unit 101 is also configured to determine the voltage amplitude of the first DAC signal, the voltage amplitude of the second DAC signal and the voltage amplitude of the third DAC signal according to the light power detection voltage reflecting the change of the I-path output light power, the light power detection voltage reflecting the change of the Q-path output light power and the detection voltage reflecting the difference between the phase of the I-path output light power and the phase of the Q-path output light power.

[0040] For example, the processing unit 101 can be a single-chip microcomputer, which generates the first square wave signal and the second square wave signal through an internal timer. The first square wave signal and the second square wave signal are periodic low-frequency square wave signals. The frequency of the first square wave signal and the frequency of the second square wave signal are not correlated, for example, they can be 1.2 kHz and 3 kHz. Through timer initialization configuration, the first square wave signal and the second square wave signal can be easily generated, and then output from the PWM1 pin and the PWM2 pin of the single-chip microcomputer, respectively. The first DAC signal, the second DAC signal and the third DAC signal are output from the DAC1 pin, the DAC2 pin and the DAC3 pin of the single-chip microcomputer, respectively. The first DAC signal, the second DAC signal and the third DAC signal are periodic voltage scanning signals, and the voltage can be 0V-2.5V.

[0041] The ADC0 input end of the single-chip microcomputer is configured to collect the voltage value of the light power detection current reflecting the output of the IQ modulator 102. Through algorithm analysis, the appropriate bias voltage setting value of the first DAC signal, the second DAC signal and the third DAC signal is determined, so as to realize the setting and locking of the three voltage bias points of the IQ modulator 102. The method for determining the appropriate bias voltage setting value of the first DAC signal, the second DAC signal and the third DAC signal through algorithm analysis comprises the following steps:

[0042] 1) After power-on, the DAC1 pin, the DAC2 pin and the DAC3 pin are pre-set with an initial voltage, for example, the initial voltage can be 1V, that is, the voltage amplitude of the first DAC signal, the second DAC signal and the third DAC signal is the initial voltage;

[0043] 2) The DAC1 pin generates a scanning signal, which continuously and cyclically scans in the range of 0V-2*Vπ (Vπ is the half-wave voltage of the IQ modulator), and the light power detection voltage reflecting the change of the I-path output light power is collected through the ADC0 input end, so as to obtain the voltage value VImax corresponding to the maximum power point of the I-path and the voltage value VImin corresponding to the minimum power point of the I-path. The output voltage value of the DAC1 pin is set to VImax, that is, the voltage amplitude of the first DAC signal is VImax;

[0044] 3) DAC2 pin generates a scanning signal, continuously scans in the range of 0V-2*Vπ, collects the light power detection voltage reflecting the Q output light power change through the ADC0 input end, obtains the voltage value VQmax corresponding to the Q output light power maximum point and the voltage value VQmin corresponding to the Q output light power minimum point; the output voltage value of the DAC2 pin is set to VQmax, that is, the voltage value of the second DAC signal is VQmax;

[0045] 4) DAC3 pin generates a scanning signal, continuously scans in the range of 0V-2*Vπ, collects the detection voltage reflecting the phase difference between the I output light power and the Q output light power through the ADC0 input end, obtains the third maximum power point VPmax and the third minimum power point VPmin;

[0046] 5) the voltage value of the first DAC signal is set to VImin, the voltage value of the second DAC signal is set to VQmin, and the voltage value of the third DAC signal is set to (VPmax-VPmin) / 2;

[0047] 6) real-time collection of the light power detection voltage reflecting the I output light power change, the light power detection voltage reflecting the Q output light power change and the detection voltage reflecting the phase difference between the I output light power and the Q output light power through the ADC0 input end, the processing unit 101 performs FFT conversion on the light power detection voltage reflecting the I output light power change, the light power detection voltage reflecting the Q output light power change and the detection voltage reflecting the phase difference between the I output light power and the Q output light power, and performs frequency spectrum analysis on the corresponding results. The first DAC signal output voltage value is fine-tuned on the basis of VImin and adjusted to the voltage value at which the power of the first Dither signal frequency base component fi is the smallest; the second DAC output voltage value is fine-tuned on the basis of VQmin and adjusted to the voltage value at which the power of the second Dither signal frequency base component fq is the smallest; and the third DAC signal output voltage is adjusted to the voltage value at which the power of the fi-fq (fi>fq) frequency component is the smallest on the basis of (VPmax-VPmin) / 2.

[0048] Step (6) needs real-time detection and real-time adjustment to maintain the dynamic control of the three bias points of the first Dither signal, the second Dither signal and the third DAC signal.

[0049] The bias point locking is divided into two steps, step 1) to step 5) are coarse adjustment, and the bias point position is roughly found out, and step 6) is fine adjustment, and the polarization point is dynamically locked at the correct position on the basis of the coarse adjustment.

[0050] The first band-pass filter 104 is configured to perform band-pass filtering on the first square wave signal. The first adder circuit 105 is configured to perform addition operation on the band-pass filtered first square wave signal and the first DAC signal and output the first Dither signal.

[0051] The second band-pass filter 108 is configured to perform band-pass filtering on the second square wave signal. The second adder circuit 109 is configured to perform addition operation on the band-pass filtered second square wave signal and the second DAC signal and output the second Dither signal.

[0052] The I-path bias voltage control pin XI_Bias of the IQ modulator 102 is loaded with the first Dither signal, the Q-path bias voltage control pin XQ_Bias of the IQ modulator 102 is loaded with the second Dither signal, the phase bias point voltage control pin XPhase_Bias of the IQ modulator 102 is loaded with the third DAC signal, and the optical power detection output pin MPD_X of the IQ modulator 102 outputs the optical power detection current reflecting the change of the I-path output optical power, the optical power detection current reflecting the change of the Q-path output optical power, and the detection current reflecting the difference between the phase of the I-path output optical power and the phase of the Q-path output optical power.

[0053] The DC bias voltage loaded on the I-path bias voltage control pin XI_Bias and the DC bias voltage loaded on the Q-path bias voltage control pin XQ_Bias are both set at the NULL point, and the phase bias point loaded on the phase bias point voltage control pin XPhase_Bias is 1 / 2π.

[0054] The amplification circuit 107 is configured to convert the optical power detection current reflecting the change of the I-path output optical power, the optical power detection current reflecting the change of the Q-path output optical power, and the detection current reflecting the difference between the phase of the I-path output optical power and the phase of the Q-path output optical power into the optical power detection voltage reflecting the change of the I-path output optical power, the optical power detection voltage reflecting the change of the Q-path output optical power, and the detection voltage reflecting the difference between the phase of the I-path output optical power and the phase of the Q-path output optical power, and amplify the same. Specifically, the input end of the amplification circuit 107 is electrically connected with the optical power detection output pin of the IQ modulator 102, and the output end of the amplification circuit 107 outputs the optical power detection voltage reflecting the change of the I-path output optical power, the optical power detection voltage reflecting the change of the Q-path output optical power, and the detection voltage reflecting the difference between the phase of the I-path output optical power and the phase of the Q-path output optical power.

[0055] In some embodiments, the Dither signal generation circuit of the coherent optical module further comprises a first attenuator 103 and a second attenuator 110.

[0056] The input end of the first attenuator 103 inputs a first square wave signal, and the output end of the first attenuator 103 is electrically connected with the input end of the first band-pass filter 104.

[0057] The input end of the second attenuator 110 inputs a second square wave signal, and the output end of the second attenuator 110 is electrically connected with the input end of the second band-pass filter 108.

[0058] In some embodiments, the coherent light module Dither signal generation circuit further comprises a low-pass filter 106.

[0059] The input end of the low-pass filter 106 is electrically connected with the output end of the amplification circuit 107, and the output end of the low-pass filter 106 is electrically connected with the ADC0 input end of the processing unit 101. The low-pass filter 106 is used to filter the light power detection voltage reflecting the change of the I-path output light power, the light power detection voltage reflecting the change of the Q-path output light power, and the detection voltage reflecting the difference between the phase of the I-path output light power and the phase of the Q-path output light power.

[0060] The specific circuit of the first attenuator 103 and the second attenuator 110 is the same, and the specific circuit of the first band-pass filter 104 and the second band-pass filter 108 is the same, as shown in Figure 2 The attenuation of the first square wave signal and the second square wave signal is realized in the form of resistance voltage division, and the proportional relationship between the amplitude of the output signal and the amplitude of the input signal is R2 / (R1+R2). Because a too large Dither signal will affect the actual signal transmission effect and make the link noise larger, the amplitude of the Dither signal needs to be controlled within a proper range, which is generally less than or equal to 10% of the actual modulation signal. The first band-pass filter 104 and the second band-pass filter 108 adopt a multiple feedback type band-pass filter, the first operational amplifier U1 is a general low-noise integrated operational amplifier circuit, and the center frequency of the first band-pass filter 104 can be determined by formula (1).

[0061] (1)

[0062] For example, R3=3.1kohm, R4=154ohm, C2=C3=180nF, R5=3.7kohm, and the center frequency of the band-pass filter can be calculated by the above formula to be 1.201kHz. Similarly, the circuit parameters corresponding to 3kHz or other frequency points can be determined by the above formula (1). Figure 2 In the formula, C1 is a coupling capacitor, V1 is an input signal, and V2 is an output signal.

[0063] The specific circuit of the first adder circuit 105 and the second adder circuit 109 is the same, as shown in Figure 3As shown in the figure, the specific circuit of the first addition operation circuit 105 and the second addition operation circuit 109 is a same-phase summation operation circuit, the second operational amplifier U2 is a general integrated operational amplifier circuit, and the relationship between the input voltage and the output resistance is shown in the following formula (2).

[0064] (2)

[0065] Va is the first input voltage, Vb is the second input voltage, and Vc is the output voltage. When R9=R7=R6, Vc=Va+Vb, and the value of R8 can be the same as R9, R7 and R6.

[0066] The specific circuit of the low-pass filter 106 and the amplification circuit 107 is as shown in the figure. Figure 4 As shown in the figure, the amplification circuit 107 adopts a three-stage amplification form, the third operational amplifier U3, the fourth operational amplifier U4 and the fifth operational amplifier U5 are all general low-noise integrated operational amplifiers, the third operational amplifier U3 and the resistors R10 and R11 constitute a transimpedance amplification circuit, which converts and amplifies the light power detection current reflecting the change of the I-path output light power, the light power detection current reflecting the change of the Q-path output light power and the detection current reflecting the difference between the phase of the I-path output light power and the phase of the Q-path output light power into the light power detection voltage reflecting the change of the I-path output light power, the light power detection voltage reflecting the change of the Q-path output light power and the detection voltage reflecting the difference between the phase of the I-path output light power and the phase of the Q-path output light power. The fourth operational amplifier U4 and the resistors R12, R13 and R16 constitute a first-stage inverting proportional amplification circuit, and the fifth operational amplifier U5 and the resistors R14, R15 and R17 constitute a second-stage inverting proportional amplification circuit. The low-pass filter 106 is an RC low-pass filter circuit, i.e., an RC low-pass filter circuit composed of the resistor R16 and the capacitor C4.

[0067] The application also discloses a coherent light module Dither signal generation method, which comprises the following steps S1 to S4.

[0068] S1, generating a first square wave signal, a second square wave signal, a first DAC signal, a second DAC signal and a third DAC signal, and determining the voltage amplitude of the first DAC signal, the voltage amplitude of the second DAC signal and the voltage amplitude of the third DAC signal based on the light power detection voltage reflecting the change of the I-path output light power, the light power detection voltage reflecting the change of the Q-path output light power and the detection voltage reflecting the difference between the phase of the I-path output light power and the phase of the Q-path output light power.

[0069] S2, the first square wave signal is subjected to band-pass filtering and then subjected to addition operation with the first DAC signal to obtain a first Dither signal, and the second square wave signal is subjected to band-pass filtering and then subjected to addition operation with the second DAC signal to obtain a second Dither signal.

[0070] S3, a first Dither signal is loaded to an I path bias voltage control pin of the IQ modulator, a second Dither signal is loaded to a Q path bias voltage control pin of the IQ modulator, and a third DAC signal is loaded to a phase bias point voltage control pin of the IQ modulator;

[0071] S4, the IQ modulator generates optical power detection currents, and converts the optical power detection currents reflecting changes in I path output optical power, the optical power detection currents reflecting changes in Q path output optical power, and the detection currents reflecting differences between the phase of the I path output optical power and the phase of the Q path output optical power into optical power detection voltages reflecting changes in I path output optical power, optical power detection voltages reflecting changes in Q path output optical power, and detection voltages reflecting differences between the phase of the I path output optical power and the phase of the Q path output optical power.

[0072] In some embodiments, the DC bias voltage loaded to the I path bias voltage control pin and the DC bias voltage loaded to the Q path bias voltage control pin are both set at NULL points, and the phase bias point loaded to the phase bias point voltage control pin is 1 / 2π.

[0073] In some embodiments, before the band-pass filtering, the method further comprises the step of: performing signal attenuation processing on the first square wave signal and the second square wave signal, respectively.

[0074] In some embodiments, before determining the voltage amplitudes of the first DAC signal, the second DAC signal, and the third DAC signal based on the optical power detection voltages reflecting changes in I path output optical power, the optical power detection voltages reflecting changes in Q path output optical power, and the detection voltages reflecting differences between the phase of the I path output optical power and the phase of the Q path output optical power, the method further comprises the step of: performing amplification and low-pass filtering processing on the optical power detection voltages reflecting changes in I path output optical power, the optical power detection voltages reflecting changes in Q path output optical power, and the detection voltages reflecting differences between the phase of the I path output optical power and the phase of the Q path output optical power, in sequence.

[0075] In some embodiments, the first square wave signal and the second square wave signal are both periodic square wave signals with a duty cycle of 50%.

[0076] Finally, it should be noted that the above only describes the preferred embodiments of the present application and is not intended to limit the present application. Although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent replacements to some technical features, as long as they fall within the spirit and principles of the present application. Any modification, equivalent replacement, improvement, etc. made within the scope of the present application shall be included in the protection scope of the present application.

Claims

1. A method for generating Dither signals in a coherent optical module, characterized in that, Includes the following steps: A first square wave signal, a second square wave signal, a first DAC signal, a second DAC signal, and a third DAC signal are generated. The voltage amplitudes of the first DAC signal, the second DAC signal, and the third DAC signal are determined based on the optical power detection voltage reflecting the change in I-channel output optical power, the optical power detection voltage reflecting the change in Q-channel output optical power, and the detection voltage reflecting the phase difference between the I-channel output optical power and the Q-channel output optical power. The first square wave signal is bandpass filtered and then added to the first DAC signal to obtain the first Dither signal; the second square wave signal is bandpass filtered and then added to the second DAC signal to obtain the second Dither signal. The first Dither signal is applied to the I-channel bias voltage control pin of the IQ modulator, the second Dither signal is applied to the Q-channel bias voltage control pin of the IQ modulator, and the third DAC signal is applied to the phase bias point voltage control pin of the IQ modulator. The IQ modulator generates an optical power detection current that reflects changes in the output optical power of the I-channel, an optical power detection current that reflects changes in the output optical power of the Q-channel, and a detection current that reflects the phase difference between the output optical power of the I-channel and the output optical power of the Q-channel. The optical power detection current reflecting the change in I-channel output optical power, the optical power detection current reflecting the change in Q-channel output optical power, and the detection current reflecting the phase difference between the I-channel output optical power and the Q-channel output optical power are respectively converted into the optical power detection voltage reflecting the change in I-channel output optical power, the optical power detection voltage reflecting the change in Q-channel output optical power, and the detection voltage reflecting the phase difference between the I-channel output optical power and the Q-channel output optical power.

2. The method for generating Dither signals in a coherent optical module according to claim 1, characterized in that, The DC bias voltage applied to the I-channel bias voltage control pin and the Q-channel bias voltage control pin are both set to the NULL point, and the phase bias point applied to the phase bias point voltage control pin is 1 / 2π.

3. The method for generating Dither signals in a coherent optical module according to claim 1, characterized in that, Before bandpass filtering, the process also includes the step of attenuating the first square wave signal and the second square wave signal respectively.

4. The method for generating Dither signals in a coherent optical module according to claim 1, characterized in that, Before determining the voltage amplitudes of the first DAC signal, the second DAC signal, and the third DAC signal based on the optical power detection voltage reflecting the change in I-channel output optical power, the optical power detection voltage reflecting the change in Q-channel output optical power, and the detection voltage reflecting the phase difference between the I-channel output optical power and the Q-channel output optical power, the method further includes: sequentially amplifying and low-pass filtering the optical power detection voltage reflecting the change in I-channel output optical power, the optical power detection voltage reflecting the change in Q-channel output optical power, and the detection voltage reflecting the phase difference between the I-channel output optical power and the Q-channel output optical power.

5. The method for generating Dither signals in a coherent optical module according to claim 1, characterized in that, Both the first square wave signal and the second square wave signal are periodic square wave signals with a duty cycle of 50%.

6. A coherent optical module Dither signal generation circuit, characterized in that, include: The processing unit is used to generate a first square wave signal, a second square wave signal, a first DAC signal, a second DAC signal, and a third DAC signal. It is used to determine the voltage amplitude of the first DAC signal, the voltage amplitude of the second DAC signal, and the voltage amplitude of the third DAC signal by correspondingly using the optical power detection voltage reflecting the change of the I-channel output optical power, the optical power detection voltage reflecting the change of the Q-channel output optical power, and the detection voltage reflecting the phase difference between the I-channel output optical power and the Q-channel output optical power. A first bandpass filter is used to bandpass filter the first square wave signal; The first addition circuit is used to add the first square wave signal after bandpass filtering to the first DAC signal and output the first Dither signal. The second bandpass filter is used to bandpass filter the second square wave signal; The second adder circuit is used to add the second square wave signal after bandpass filtering to the second DAC signal and output the second Dither signal. The IQ modulator has a first Dither signal loaded on its I-channel bias voltage control pin, a second Dither signal loaded on its Q-channel bias voltage control pin, a third DAC signal loaded on its phase bias point voltage control pin, and an optical power detection output pin that outputs the optical power detection current reflecting the change in the I-channel output optical power, the optical power detection current reflecting the change in the Q-channel output optical power, and the detection current reflecting the phase difference between the I-channel output optical power and the Q-channel output optical power. An amplifier circuit is used to convert the optical power detection current reflecting the change in optical power of the I-channel output, the optical power detection current reflecting the change in optical power of the Q-channel output, and the detection current reflecting the phase difference between the phase of the I-channel output and the phase of the Q-channel output, into optical power detection voltage reflecting the change in optical power of the I-channel output, the optical power detection voltage reflecting the change in optical power of the Q-channel output, and the detection voltage reflecting the phase difference between the phase of the I-channel output and the phase of the Q-channel output, and then amplify them.

7. The coherent optical module Dither signal generation circuit according to claim 6, characterized in that, The DC bias voltage applied to the I-channel bias voltage control pin and the Q-channel bias voltage control pin are both set to the NULL point, and the phase bias point applied to the phase bias point voltage control pin is 1 / 2π.

8. The coherent optical module Dither signal generation circuit according to claim 6, characterized in that, Also includes: The first attenuator receives a first square wave signal at its input terminal and its output terminal is electrically connected to the input terminal of the first bandpass filter. The second attenuator receives a second square wave signal at its input and its output is electrically connected to the input of the second bandpass filter.

9. The coherent optical module Dither signal generation circuit according to claim 6, characterized in that, Also includes: The low-pass filter has its input terminal electrically connected to the output terminal of the amplifier circuit, and its output terminal electrically connected to the input terminal of the ADC0 of the processing unit.

10. The coherent optical module Dither signal generation circuit according to claim 6, characterized in that, Both the first square wave signal and the second square wave signal are periodic square wave signals with a duty cycle of 50%.

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