Semiconductor device including vertical active pattern

Abstract

A semiconductor device includes a memory region and a peripheral region. The memory region includes a cell vertical active pattern, an on-cell source / drain pattern and a cell contact plug sequentially stacked on the cell vertical active pattern, and a cell isolation pattern on a side surface of the on-cell source / drain pattern and a side surface of the cell contact plug. The peripheral region includes a peripheral vertical active pattern, a peripheral upper source / drain pattern and a peripheral contact plug sequentially stacked on the peripheral vertical active pattern, a peripheral isolation pattern on a side surface of the peripheral upper source / drain pattern and a side surface of the peripheral contact plug, and an upper wiring on the peripheral contact plug and the peripheral isolation pattern. The on-cell source / drain pattern includes a first on-cell source / drain pattern and a second on-cell source / drain pattern sequentially stacked.

Description

Technical Field

[0001] Some exemplary embodiments of this disclosure relate to semiconductor devices and / or methods of manufacturing semiconductor devices. Background Technology

[0002] Research has been ongoing to reduce the size of components included in semiconductor devices and improve their performance. For example, in DRAM, research has been conducted to reliably and stably form smaller components, but as component size continues to decrease, the dispersion property of semiconductor devices may deteriorate. Summary of the Invention

[0003] Some example embodiments of this disclosure are intended to provide semiconductor devices that can increase integration density and improve performance.

[0004] Some example embodiments disclosed herein are intended to provide a method for manufacturing the semiconductor device.

[0005] According to some example embodiments, a semiconductor device includes a storage region and a peripheral region. The storage region includes: a cell vertical active pattern; a cell gate electrode having a side surface facing a side surface of the cell vertical active pattern; a cell on-cell source / drain pattern and a cell contact plug, the cell on-cell source / drain pattern and the cell contact plug being sequentially stacked on the cell vertical active pattern; a cell isolation pattern located on the side surface of the cell on-cell source / drain pattern and the side surface of the cell contact plug; and a data storage structure located on the cell contact plug and the cell isolation pattern. The peripheral region includes: a peripheral vertical active pattern; and a peripheral gate electrode having a side surface facing a side surface of the cell vertical active pattern. The system includes a side surface facing the side surface of the peripheral vertical active pattern; a peripheral upper source / drain pattern and a peripheral contact plug, the peripheral upper source / drain pattern and the peripheral contact plug being sequentially stacked on the peripheral vertical active pattern; a peripheral isolation pattern located on the side surface of the peripheral upper source / drain pattern and the side surface of the peripheral contact plug; and an upper wiring located on the peripheral contact plug and the peripheral isolation pattern, wherein the cell upper source / drain pattern includes a first cell upper source / drain pattern and a second cell upper source / drain pattern stacked sequentially, and wherein the peripheral upper source / drain pattern includes a first peripheral upper source / drain pattern and a second peripheral upper source / drain pattern stacked sequentially.

[0006] According to some example embodiments, a semiconductor device includes: a cell vertical active pattern and a peripheral vertical active pattern, the cell vertical active pattern and the peripheral vertical active pattern being spaced apart from each other; a cell on-cell source / drain pattern and a cell contact plug, the cell on-cell source / drain pattern and the cell contact plug being sequentially stacked on the cell vertical active pattern and self-aligned; a peripheral on-cell source / drain pattern and a peripheral contact plug, the peripheral on-cell source / drain pattern and the peripheral contact plug being sequentially stacked on the peripheral vertical active pattern and self-aligned; a cell isolation pattern, the cell isolation pattern being located on the side surface of the cell on-cell source / drain pattern and the side surface of the cell contact plug; and a peripheral isolation pattern, the peripheral isolation pattern being located on the side surface of the peripheral on-cell source / drain pattern and the peripheral contact plug. The peripheral contact plug has the following components: a side surface of the peripheral contact plug; an upper wiring connected to and located on the peripheral contact plug; an insulating pad located on the unit contact plug, the unit isolation pattern, and the upper wiring; and a data storage structure including a first electrode, a dielectric layer, and a second electrode, the first electrode being connected to the unit contact plug, penetrating the insulating pad, and extending upward, the dielectric layer being located on the first electrode, and the second electrode being located on the dielectric layer, wherein the insulating pad includes a first portion located on the upper surface of the unit isolation pattern and a second portion located on the upper surface of the upper wiring, and wherein the second portion of the insulating pad is at a height higher than the height of the first portion of the insulating pad.

[0007] According to some example embodiments, a semiconductor device includes a first structure and a second structure. The first structure includes a storage region and a peripheral region. The second structure overlaps the first structure perpendicularly and includes peripheral circuitry. The storage region includes: a cell vertical active pattern; a cell gate electrode having a side surface facing a side surface of the cell vertical active pattern; a cell on-source / drain pattern and a cell contact plug, the cell on-source / drain pattern and the cell contact plug being sequentially stacked on the cell vertical active pattern; a cell isolation pattern located on the side surface of the cell on-source / drain pattern and the side surface of the cell contact plug; and a data storage structure located on the cell contact plug and the cell isolation pattern. The peripheral region includes: a first peripheral vertical active pattern; a first peripheral gate electrode having a side surface facing a side surface of the first peripheral vertical active pattern; and a first peripheral on-source / drain pattern. The system comprises a first peripheral contact plug, wherein the first peripheral source / drain pattern and the first peripheral contact plug are sequentially stacked on the first peripheral vertical active pattern; a peripheral isolation pattern, wherein the peripheral isolation pattern is located on the side surface of the first peripheral source / drain pattern and the side surface of the first peripheral contact plug; and a first upper wiring, wherein the first upper wiring is located on the first peripheral contact plug and the peripheral isolation pattern, wherein the cell source / drain pattern comprises a first cell source / drain pattern and a second cell source / drain pattern stacked sequentially, wherein the first peripheral source / drain pattern comprises a first-1 peripheral source / drain pattern and a first-2 peripheral source / drain pattern stacked sequentially, wherein the storage region and the peripheral region further comprise insulating pads located on the cell contact plug, the cell isolation pattern and the first upper wiring, and wherein the peripheral circuitry comprises a first lower transistor perpendicularly overlapping the storage region and a second lower transistor perpendicularly overlapping the peripheral region. Attached Figure Description

[0008] The above and other aspects, features and advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 This is a perspective view illustrating a semiconductor device according to some exemplary embodiments of the present disclosure; Figure 2 This is a circuit diagram illustrating the memory region of a semiconductor device according to some exemplary embodiments of the present disclosure; Figure 3 , Figure 4 , Figure 5A , Figure 5B and Figure 6This is a diagram illustrating examples of semiconductor devices according to some exemplary embodiments of the present disclosure; Figure 7 This is an enlarged view illustrating a portion of an example of a semiconductor device according to some exemplary embodiments of the present disclosure; Figure 8A and Figure 8B This is a diagram illustrating examples of semiconductor devices according to some exemplary embodiments of the present disclosure; Figure 9A and Figure 9B This is a diagram illustrating examples of semiconductor devices according to some exemplary embodiments of the present disclosure; Figure 10A and Figure 10B This is a diagram illustrating examples of semiconductor devices according to some exemplary embodiments of the present disclosure; Figure 11A and Figure 11B This is a diagram illustrating examples of semiconductor devices according to some exemplary embodiments of the present disclosure; Figure 12 , Figure 13A and Figure 13B This is a diagram illustrating examples of semiconductor devices according to some exemplary embodiments of the present disclosure; Figure 14A This is a cross-sectional view illustrating an example of a semiconductor device according to some exemplary embodiments of the present disclosure; Figure 14B This is a cross-sectional view illustrating an example of a semiconductor device according to some exemplary embodiments of the present disclosure; Figure 15A This is a cross-sectional view illustrating an example of a semiconductor device according to some exemplary embodiments of the present disclosure; Figure 15B This is a cross-sectional view illustrating an example of a semiconductor device according to some exemplary embodiments of the present disclosure; Figure 16 This is a cross-sectional view illustrating an example of a semiconductor device according to some exemplary embodiments of the present disclosure; Figure 17 It is a cross-sectional view illustrating an example of a semiconductor device according to some exemplary embodiments of the present disclosure; and Figures 18 to 37 This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to some exemplary embodiments of the present disclosure. Detailed Implementation

[0009] In the following text, in order to describe the elements in the specification, terms such as “upper,” “middle,” and “lower” may be replaced with other terms such as “first,” “second,” and “third.” Terms such as “first,” “second,” and “third” may be used to describe various elements, but these elements are not limited by these terms. For example, these terms are not intended to imply or require continuous inclusion, and “first element” may be referred to as “second element.”

[0010] It should be understood that an element and / or its property (e.g., structure, surface, orientation, etc.) that can be described as "perpendicular," "parallel," "coplanar," etc., to other elements and / or its property (e.g., structure, surface, orientation, etc.) can be "perpendicular," "parallel," "coplanar," etc., to other elements and / or its property, or can be "substantially perpendicular," "substantially parallel," "substantially coplanar," etc., to other elements and / or its property. An element and / or its property (e.g., structure, surface, orientation, etc.) that is "substantially perpendicular" to other elements and / or its property will be understood as being "perpendicular" to other elements and / or its property within manufacturing tolerances and / or material tolerances, and / or having a deviation from "perpendicular," etc., in magnitude and / or angle equal to or less than 10% (e.g., tolerance of ±10%).

[0011] In the following text, a semiconductor device according to some example embodiments will be described. Figure 1 This is a perspective view illustrating a semiconductor device according to some example embodiments.

[0012] refer to Figure 1 According to some example embodiments, the semiconductor device 1 may include a first structure ST1 and a second structure ST2 that is perpendicularly overlapped with the first structure ST1. The second structure ST2 may be disposed below the first structure ST1.

[0013] In some example embodiments, the first structure ST1 can be configured as a first chip structure including a storage region and a peripheral region, and the second structure ST2 can be configured as a second chip structure including a second peripheral circuit. The first structure ST1 and the second structure ST2 can be bonded to each other by a bonding process such as a wafer bonding process. Therefore, the first structure ST1 can contact and be bonded to the second structure ST2.

[0014] Semiconductor device 1 may include multiple memory banks BA and external peripheral region PERI.

[0015] The external peripheral area PERI may include peripheral area PERI1 located in the first structure ST1 and second peripheral area PERI2 located in the second structure ST2. The external peripheral area PERI may be configured as a peripheral area in which peripheral circuitry for inputting and outputting data or commands or inputting power / ground is provided.

[0016] Each of the multiple memory banks BA may include a first memory bank region BA1 located in the first structure ST1 and a second memory bank region BA2 located in the second structure ST2.

[0017] The first memory bank region BA1 located in the first structure ST1 may include memory cells. The second memory bank region BA2 located in the second structure ST2 may include peripheral circuitry, such as a sense amplifier and a sub-word line driver.

[0018] In the following description, reference will be made to Figure 2 Describe the circuitry located in the storage region of the first structure ST1. Figure 2 This is a circuit diagram illustrating the memory region of a semiconductor device according to some example embodiments.

[0019] refer to Figure 2 The storage region CR may include storage cells MC. The storage region CR may include storage cells MC arranged along a first direction X and a second direction Y, word lines WL connected to the storage cells MC and extending along the first direction X, and bit lines BL connected to the storage cells MC and extending along the second direction Y. The first direction X and the second direction Y may be perpendicular to each other.

[0020] The word line WL can cross the memory region CR in the first direction X. The bit line BL can cross the memory region CR in the second direction Y.

[0021] Each memory cell MC may include a data storage structure DS for data storage and a cell transistor cTR electrically connected to the data storage structure DS. In memories such as DRAM, the data storage structure DS may be configured as a cell capacitor capable of storing data.

[0022] The memory region CR may also include back gate lines BG. Each back gate line BG may be disposed between pairs of adjacent word lines WL in the second direction Y. Each back gate line BG may be disposed between the vertical channel regions of the cell transistor cTR.

[0023] Reference Figure 3 , Figure 4 , Figure 5A , Figure 5B and Figure 6 as well as Figure 1 and Figure 2 An example of a first portion ST1_A of a first structure ST1 of a semiconductor device according to some example embodiments is described. Figure 3 This is a top view illustrating a semiconductor device according to some example embodiments. Figure 4 It is illustrated along Figure 3 A cross-sectional view of the region intercepted by line I-I' in the diagram. Figure 5A It's a diagram. Figure 4 Enlarged views of regions "A" and "B" in the image. Figure 5B It's a diagram. Figure 4 Enlarged views of regions "C" and "D" in the image, and Figure 6 This is a perspective view illustrating an example of a bitline shielding structure 88.

[0024] refer to Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5A , Figure 5B and Figure 6 The first structure ST1 of the semiconductor device 1 may include a storage region CR and a peripheral region PR. In the following description, the storage region CR and the peripheral region PR in the first part ST1_A of the first structure ST1 of the semiconductor device 1 will be mainly described.

[0025] The storage region CR may include a cell vertical active pattern 21c, a cell gate electrode 27c, a cell source / drain pattern 35c, a cell contact plug 57c, and a cell isolation pattern 52a. The peripheral region PR may include a first peripheral vertical active pattern 21n, a first peripheral gate electrode 27n, a first peripheral source / drain pattern 35n, a first peripheral contact plug 57n, and a first peripheral isolation pattern 52c. The peripheral region PR may also include a second peripheral vertical active pattern 21p, a second peripheral gate electrode 27p, a second peripheral source / drain pattern 35p, a second peripheral contact plug 57p, and a second peripheral isolation pattern 52b.

[0026] Each cell vertical active pattern 21c may include a cell lower source / drain region 21c_L, a cell vertical channel region 21c_CH located on the cell lower source / drain region 21c_L, and a cell upper source / drain region 21c_U located on the cell vertical channel region 21c_CH. Each first peripheral vertical active pattern 21n may include a first peripheral lower source / drain region 21n_L, a first peripheral vertical channel region 21n_CH located on the first peripheral lower source / drain region 21n_L, and a first peripheral upper source / drain region 21n_U located on the first peripheral vertical channel region 21n_CH.

[0027] Unit gate electrode 27c can be a reference Figure 2 The word line WL is described. The cell gate electrode 27c may have a side surface facing the side surface of the cell vertical active pattern 21c. The first peripheral gate electrode 27n may have a side surface facing the side surface of the first peripheral vertical active pattern 21n. The second peripheral gate electrode 27p may have a side surface facing the side surface of the second peripheral vertical active pattern 21p.

[0028] Each cell source / drain pattern 35c may include a first cell source / drain pattern 36c and a second cell source / drain pattern 42c stacked sequentially. The side surfaces of the first cell source / drain pattern 36c and the second cell source / drain pattern 42c may be aligned. Each first peripheral source / drain pattern 35n may include a first-1 peripheral source / drain pattern 36n and a first-2 peripheral source / drain pattern 42n stacked sequentially. The side surfaces of the first-1 peripheral source / drain pattern 36n and the first-2 peripheral source / drain pattern 42n may be aligned. Each second peripheral source / drain pattern 35p may include a second-1 peripheral source / drain pattern 36p and a second-2 peripheral source / drain pattern 42p stacked sequentially. The side surfaces of the source / drain pattern 36p on the second-1 outer periphery and the side surfaces of the source / drain pattern 42p on the second-2 outer periphery can be aligned.

[0029] The source / drain pattern 35c on the unit cell can have N-type conductivity. The source / drain pattern 35n on the first periphery can have N-type conductivity. The source / drain pattern 35p on the second periphery can have P-type conductivity.

[0030] The impurity concentration of the source / drain pattern 42c in the second unit can be higher than the impurity concentration of the source / drain pattern 36c in the first unit. The impurity concentration of the source / drain pattern 36c in the first unit can be higher than the impurity concentration of the source / drain region 21c_U in the unit. The impurity concentration of the source / drain pattern 42n in the first-second outer periphery can be higher than the impurity concentration of the source / drain pattern 36n in the first-first outer periphery. The impurity concentration of the source / drain pattern 36n in the first-first outer periphery can be higher than the impurity concentration of the first outer periphery source / drain region 21n_U. The impurity concentration of the source / drain pattern 42p in the second-second outer periphery can be higher than the impurity concentration of the source / drain pattern 36p in the second-first outer periphery. The impurity concentration of the source / drain pattern 36p in the second-first outer periphery can be higher than the impurity concentration of the second outer periphery source / drain region 21p_U.

[0031] The upper source / drain patterns 35c, 35n, and 35p may overlap perpendicularly with and contact the vertical active patterns 21c, 21n, and 21p, respectively. The width of each of the upper source / drain patterns 35c, 35n, and 35p in the first horizontal direction may be greater than the width of each of the vertical active patterns 21c, 21n, and 21p in the first horizontal direction. The storage region CR and the peripheral region PR may also include dummy source / drain patterns 35D, which are disposed at the same height as the upper source / drain patterns 35c, 35n, and 35p, formed of the same material as the upper source / drain patterns 35c, 35n, and 35p, and have the same structure as the upper source / drain patterns 35c, 35n, and 35p. The dummy source / drain pattern 35D can be spaced apart from the vertical active patterns 21c, 21n and 21p.

[0032] Cell contact plugs 57c may be disposed on the cell source / drain pattern 35c. Each cell contact plug 57c may include a metal-semiconductor compound layer 53c in contact with the upper surface of the second cell source / drain pattern 42c and a plug pattern 56c located on the metal-semiconductor compound layer 53c. The cell source / drain patterns 35c and cell contact plugs 57c stacked in sequence may have side surfaces aligned with each other.

[0033] First peripheral contact plugs 57n may be disposed on first peripheral source / drain patterns 35n. Each first peripheral contact plug 57n may include a metal-semiconductor compound layer 53n in contact with the upper surface of the first-second peripheral source / drain patterns 42n and a plug pattern 56n located on the metal-semiconductor compound layer 53n. The first peripheral source / drain patterns 35n and first peripheral contact plugs 57n stacked sequentially may have side surfaces aligned with each other.

[0034] The second peripheral contact plug 57p may be disposed on the second peripheral source / drain pattern 35p. Each second peripheral contact plug 57p may include a metal-semiconductor compound layer 53p in contact with the upper surface of the second peripheral source / drain pattern 42p and a plug pattern 56p located on the metal-semiconductor compound layer 53p. The second peripheral source / drain pattern 35p and the second peripheral contact plug 57p stacked in sequence may have side surfaces aligned with each other.

[0035] Contact plugs 57c, 57n, and 57p can be aligned and contacted with the upper source / drain patterns 35c, 35n, and 35p, respectively. The storage region CR and the peripheral region PR may also include a dummy contact plug 57D aligned and contacted with the dummy source / drain pattern 35D. The dummy contact plug 57D can be positioned at the same height as contact plugs 57c, 57n, and 57p, can be formed of the same material as contact plugs 57c, 57n, and 57p, and can have the same structure as contact plugs 57c, 57n, and 57p.

[0036] Cell isolation pattern 52a may define the side surfaces of sequentially stacked cell source / drain patterns 35c and cell contact plugs 57c. First peripheral isolation pattern 52c may define the side surfaces of sequentially stacked first peripheral source / drain patterns 35n and first peripheral contact plugs 57n. Second peripheral isolation pattern 52b may define the side surfaces of sequentially stacked second peripheral source / drain patterns 35p and second peripheral contact plugs 57p. Cell isolation pattern 52a may surround the side surfaces of sequentially stacked cell source / drain patterns 35c and cell contact plugs 57c, first peripheral isolation pattern 52c may surround the side surfaces of sequentially stacked first peripheral source / drain patterns 35n and first peripheral contact plugs 57n, and second peripheral isolation pattern 52b may surround the side surfaces of sequentially stacked second peripheral source / drain patterns 35p and second peripheral contact plugs 57p. Cell isolation pattern 52a, first peripheral isolation pattern 52c, and second peripheral isolation pattern 52b may be disposed at the same height and may include the same insulating material.

[0037] The peripheral region PR may also include conductive patterns 63a, 63n, 63pn, and 63p set at the same height and made of the same material. The storage region CR and the peripheral region PR may also include an insulating pad 66.

[0038] The conductive patterns 63a, 63n, 63p and 63pn may include pad pattern 63a, first upper wiring 63n, second upper wiring 63p and upper connection wiring 63pn.

[0039] The first upper wiring 63n can connect to a portion of the first peripheral contact plug 57n. The second upper wiring 63p can connect to a portion of the second peripheral contact plug 57p. The upper connection wiring 63pn can electrically connect a portion of the first peripheral contact plug 57n to a portion of the second peripheral contact plug 57p. The pad pattern 63a may not overlap perpendicularly with the first peripheral contact plug 57n and the second peripheral contact plug 57p.

[0040] An insulating pad 66 may be disposed on the cell contact plug 57c, the cell isolation pattern 52a, and the conductive patterns 63a, 63n, 63pn, and 63p. The insulating pad 66 may cover the upper surface of the cell contact plug 57c and the upper surface of the cell isolation pattern 52a in the storage region CR, and may cover the upper and side surfaces of the conductive patterns 63a, 63n, 63pn, and 63p in the peripheral region PR. The insulating pad 66 may include an insulating material such as SiN, SiBN, SiCN, or a high-k dielectric.

[0041] The insulating pad 66 may include a first portion disposed on the upper surface of the unit isolation pattern 52a and a second portion disposed on the upper surface of the first upper wiring 63n and the upper surface of the second upper wiring 63p, and the second portion of the insulating pad 66 may be disposed at a height higher than the height of the first portion of the insulating pad 66.

[0042] The storage area CR and the peripheral area PR may also include the data storage structure DS and the insulating layer 70.

[0043] The data storage structure DS may include: a first electrode 68a connected to a cell plug pattern 57c in the storage region CR, penetrating an insulating pad 66 and extending in the vertical direction Z; a second electrode 68c located on the side and top surfaces of each first electrode 68a; and a dielectric layer 68b located between the first electrode 68a and the second electrode 68c. The data storage structure DS may be configured as a cell capacitor of a memory such as DRAM.

[0044] The insulating layer 70 may cover the data storage structure DS in the storage region CR and cover the insulating pad 66 in the peripheral region PR. The insulating layer 70 may include at least one of silicon oxide or a low-k dielectric.

[0045] The storage region CR and the peripheral region PR may include: lower source / drain patterns 78c, 78n and 78p connected below the vertical active patterns 21c, 21n and 21p respectively, and conductive patterns 83c, 83n and 83p aligned with the lower source / drain patterns 78c, 78n and 78p below the lower source / drain patterns 78c, 78n and 78p respectively.

[0046] The lower source / drain patterns 78c, 78n, and 78p may include a lower source / drain pattern 78c connected to the cell vertical active pattern 21c, a first peripheral lower source / drain pattern 78n connected to the first peripheral vertical active pattern 21n, and a second peripheral lower source / drain pattern 78p connected to the first peripheral vertical active pattern 21p.

[0047] Conductive patterns 83c, 83n, and 83p may include a bit line 83c that contacts and is aligned with the cell's lower source / drain pattern 78c, a first lower wiring 83n that contacts and is aligned with the first peripheral lower source / drain pattern 78n, and a second lower wiring 83p that contacts and is aligned with the second peripheral lower source / drain pattern 78p. Conductive patterns 83c, 83n, and 83p may each include a first conductive layer 81 and a second conductive layer 82 disposed below the first conductive layer 81. Bit line 83c may be a reference... Figure 2 The bit line BL is described.

[0048] The storage region CR may further include a cell gate dielectric layer 24c, a cell back gate electrode 16c, a cell back gate dielectric layer 14c, and insulating layers 18, 33, 30, and 75. The peripheral region PR may further include a first peripheral gate dielectric layer 24n, a first peripheral back gate electrode 16n, a first peripheral back gate dielectric layer 14n, a second peripheral gate dielectric layer 24p, a second peripheral back gate electrode 16p, a second peripheral back gate dielectric layer 14p, insulating layers 18, 33, 30, and 75, and insulating structures 54 and 56.

[0049] The unit back gate electrode 16c can be a reference. Figure 2 The back gate line BG is described. Each cell gate electrode 27c may extend in a second horizontal direction Y. The cell gate electrodes 27c may be spaced apart from each other in a first horizontal direction X perpendicular to the second horizontal direction Y. Each cell back gate electrode 16c may be configured as a line shape extending in the second horizontal direction Y.

[0050] In the unit gate electrode 27c, adjacent pairs of unit gate electrodes 27c along the first horizontal direction X can be disposed between adjacent pairs of unit back gate electrodes 16c along the first horizontal direction X. In the plane, each unit vertical active pattern 21c can be configured as a strip shape extending in the second horizontal direction Y. Each unit vertical active pattern 21c can be disposed between adjacent unit back gate electrodes 16c and unit gate electrodes 27c.

[0051] Each first peripheral gate electrode 27n may extend in a second horizontal direction Y. Each first peripheral back gate electrode 16n may be configured as a line extending in the second horizontal direction Y. Pairs of first peripheral gate electrodes 27n adjacent to each other along the first horizontal direction may be disposed between pairs of first peripheral back gate electrodes 16n adjacent along the first horizontal direction X. In the plane, each first peripheral vertical active pattern 21n may be configured as a strip extending in the second horizontal direction Y. Each first peripheral vertical active pattern 21n may be disposed between adjacent first peripheral back gate electrodes 16n and first peripheral gate electrodes 27n.

[0052] Each second peripheral gate electrode 27p may extend in a second horizontal direction Y. Each second peripheral back gate electrode 16p may be configured as a line extending in the second horizontal direction Y. Pairs of second peripheral gate electrodes 27p adjacent to each other along the first horizontal direction X may be disposed between pairs of second peripheral back gate electrodes 16p adjacent to each other along the first horizontal direction X. In the plane, each second peripheral vertical active pattern 21p may be configured as a strip extending in the second horizontal direction Y. Each second peripheral vertical active pattern 21p may be disposed between adjacent second peripheral back gate electrodes 16p and second peripheral gate electrodes 27p.

[0053] A cell gate dielectric layer 24c can be disposed between the side surface of the cell vertical active pattern 21c and the side surface of the cell gate electrode 27c. The cell gate dielectric layer 24c can extend to cover the lower surface of the cell gate electrode 27c. A first peripheral gate dielectric layer 24n can be disposed between the side surface of the first peripheral vertical active pattern 21n and the side surface of the first peripheral gate electrode 27n. The first peripheral gate dielectric layer 24n can extend to cover the lower surface of the first peripheral gate electrode 27n. A second peripheral gate dielectric layer 24p can be disposed between the side surface of the second peripheral vertical active pattern 21p and the side surface of the second peripheral gate electrode 27p. The second peripheral gate dielectric layer 24p can extend to cover the lower surface of the second peripheral gate electrode 27p.

[0054] The cell back gate dielectric layer 14c can be disposed between the cell vertical active pattern 21c and the cell back gate electrode 16c. The first peripheral back gate dielectric layer 14n can be disposed between the first peripheral vertical active pattern 21n and the first peripheral back gate electrode 16n. The second peripheral back gate dielectric layer 14p can be disposed between the second peripheral vertical active pattern 21p and the second peripheral back gate electrode 16p.

[0055] Insulating layer 18 can be disposed below the lower surfaces of back gate electrodes 16c, 16n, and 16p. Insulating layer 75 can be disposed on the upper surfaces of back gate electrodes 16c, 16n, and 16p. Insulating layer 33 can be disposed on the upper surfaces of gate electrodes 27c, 27n, and 27p. Each insulating layer 30 can be disposed between adjacent gate electrodes among gate electrodes 27c, 27n, and 27p, and can also be disposed between adjacent insulating layers among insulating layers 33. Insulating layer 22 can be disposed between the lower surfaces of gate dielectric layers 24c, 24n, and 24p and the lower source / drain patterns 78c, 78n, and 78p.

[0056] Insulating structures 54 and 56 can both be disposed between adjacent groups of a set of unit isolation patterns 52a, a set of first peripheral isolation patterns 52c, and a set of second peripheral isolation patterns 52b. Both insulating structures 54 and 56 can include an insulating pattern 56 and an insulating pad 54 covering the side and lower surfaces of the insulating pattern 56. The insulating pattern 56 can include oxides, and the insulating pad 54 can include nitrides. Pad pattern 63a can be disposed on the upper surface of insulating structures 54 and 56.

[0057] The storage region CR may also include a bit line shielding structure 88, and the storage region CR and the peripheral region PR may also include insulating structures 85 and 86 and an insulating layer 90.

[0058] Insulating structures 85 and 86 may include insulating pattern 86 and insulating pad 85. Insulating pad 85 may cover the upper surface of insulating pattern 86, the side surfaces of lower source / drain patterns 78c, 78n and 78p, and the side and lower surfaces of conductive patterns 83c, 83n and 83p.

[0059] Bit line shielding structure 88 may include a vertical portion disposed between bit lines 83c. Figure 6 88V in the middle) and the plate portion extending from the vertical portion 88V and perpendicularly overlapping with the bit line 83c ( Figure 6 (88P in the middle). The bit line shielding structure 88 can be spaced apart from the bit line 83c by an insulating pad 85. An insulating layer 90 can be disposed below the insulating structures 85 and 86 and the bit line shielding structure 88.

[0060] Vertical active patterns 21c, 21n, and 21p can include monocrystalline silicon.

[0061] The source / drain pattern 35c on the cell and the first peripheral source / drain pattern 35n may include a first polysilicon, for example, polysilicon with N-type conductivity. The second peripheral source / drain pattern 35p may include a second polysilicon, for example, polysilicon with P-type conductivity.

[0062] The lower source / drain pattern 78c and the first peripheral lower source / drain pattern 78n may include a third polysilicon, such as N-type polysilicon. The second peripheral lower source / drain pattern 78p may include a fourth polysilicon, such as P-type polysilicon.

[0063] The width of each of the upper source / drain patterns 35c, 35n and 35p in the first horizontal direction X can be greater than the width of each of the vertical active patterns 21c, 21n and 21p in the first horizontal direction X.

[0064] The upper source / drain SDcU of the cell may include an upper source / drain pattern 35c and an upper source / drain region 21c_U. The lower source / drain SDcL of the cell may include a lower source / drain pattern 78c and a lower source / drain region 21c_L. The upper source / drain SDcU and the lower source / drain SDcL of the cell may have N-type conductivity. The cell transistor TRc may include an upper source / drain SDcU, a lower source / drain SDcL, a vertical channel region 21c_CH, a gate dielectric layer 24c, and a gate electrode 27c.

[0065] The first peripheral upper source / drain SDnU may include a first peripheral upper source / drain pattern 35n and a first peripheral upper source / drain region 21n_U. The first peripheral lower source / drain SDnL may include a first peripheral lower source / drain pattern 78n and a first peripheral lower source / drain region 21n_L. The first peripheral upper source / drain SDnU and the first peripheral lower source / drain SDnL may have N-type conductivity. The first peripheral transistor TRn may include a first peripheral upper source / drain SDnU, a first peripheral lower source / drain SDnL, a first peripheral vertical channel region 21n_CH, a first peripheral gate dielectric layer 24n, and a first peripheral gate electrode 27n. The first peripheral transistor TRn may be configured as an NMOS transistor. Multiple first peripheral transistors TRn may be provided, and they may be configured in... Figure 3 The NMOS transistor regions NMOS1 and NMOS2 are shown in the figure.

[0066] The second peripheral upper source / drain SDpU may include a second peripheral upper source / drain pattern 35p and a second peripheral upper source / drain region 21p_U. The second peripheral lower source / drain SDpL may include a second peripheral lower source / drain pattern 78p and a second peripheral lower source / drain region 21p_L. The second peripheral upper source / drain SDpU and the second peripheral lower source / drain SDpL may have P-type conductivity. The second peripheral transistor TRp may include a second peripheral upper source / drain SDpU, a second peripheral lower source / drain SDpL, a second peripheral vertical channel region 21p_CH, a second peripheral gate dielectric layer 24p, and a second peripheral gate electrode 27p. The second peripheral transistor TRp may be configured as a PMOS transistor. Multiple second peripheral transistors TRp may be provided, and they may be configured in multiple ways. Figure 3 The diagram shows the PMOS transistor regions PMOS1 and PMOS2.

[0067] In the following description, various modifications to the elements of the above-described example embodiments will be described. Various modifications to the elements of the above-described example embodiments will be described below with respect to the modifications or substitutions. Here, reference may be made directly to the elements without detailed description, or description may be omitted. Furthermore, elements that can be modified or substituted will be described with reference to the accompanying drawings; however, elements that can be modified or substituted may be combined with each other or with the elements described above, and may be included in the semiconductor device according to some example embodiments.

[0068] Reference Figure 7 Examples of semiconductor devices described according to some example embodiments. Figure 7 It is illustrated with Figure 5A The region “Aa” in the text corresponds to the region “Aa1”, and Figure 5B The region "Ca" in the text corresponds to the region "Ca1", and... Figure 5B An enlarged view of the region "Da" corresponding to the region "Da1" in the diagram, thereby illustrating an example of a semiconductor device according to some example embodiments.

[0069] refer to Figure 7 , Figure 5A and Figure 5B The plug pattern in Figure 5A 56c in the middle) and Figure 5B The plug patterns 56n and 56p can be formed from a single conductive material. Figure 5A 56c in Figure 5BThe 56n and 56p in the original text can be replaced with plug patterns 56c1, 56n1, and 56p1 comprising at least two layers of conductive material. For example, plug patterns 56c1, 56n1, and 56p1 can each include a conductive material pattern 56b and a conductive pad 56a covering the side and bottom surfaces of the conductive material pattern 56b. For example, the conductive pad 56a can be considered a barrier layer. However, the example embodiment is not limited thereto.

[0070] Reference Figure 8A and Figure 8B Examples of semiconductor devices described according to some example embodiments. Figure 8A It can be with Figure 4 Corresponding cross-sectional views are provided to illustrate examples of semiconductor devices according to some exemplary embodiments, and Figure 8B It's a diagram. Figure 8A An enlarged view of region "E" in the image.

[0071] refer to Figure 8A and Figure 8B , Figure 4 The first part ST1_A of the first structure ST1 in the first part can be replaced with Figure 8A The first part of the first structure ST1, ST1_B. The outer region PR may also include the reference... Figure 4 , Figure 5A and Figure 5B The described insulating pad 66 is a buffer insulating layer 65 between the conductive patterns 63a, 63n, 63pn and 63p. However, the example embodiment is not limited thereto.

[0072] The buffer insulating layer 65 may comprise a material different from that of the insulating pad 66. For example, the insulating pad 66 may comprise a first insulating material comprising at least one of SiN, SiBN, SiCN, and / or a high-k dielectric, and the buffer insulating layer 65 may comprise a second insulating material comprising at least one of silicon oxide and / or a low-k dielectric. The buffer insulating layer 65 can reduce the parasitic capacitance between adjacent conductive patterns in the conductive patterns 63a, 63n, 63pn, and 63p. Therefore, the buffer insulating layer 65 can prevent or reduce the possibility of signal transmission speed reduction due to RC delay of the conductive patterns 63a, 63n, 63pn, and 63p.

[0073] Reference Figure 9A and Figure 9B Examples of semiconductor devices described according to some example embodiments. Figure 9A It can be with Figure 4 Corresponding cross-sectional views are provided to illustrate examples of semiconductor devices according to some exemplary embodiments, and Figure 9B It can be illustrated. Figure 9AEnlarged views of regions "A1" and "C1" in the image.

[0074] refer to Figure 9A and Figure 9B , Figure 4 The first part ST1_A of the first structure ST1 in the first part can be replaced with Figure 9A The first part of the first structure ST1, ST1_C. The storage area CR may also include cell pad pattern 163c. (See reference...) Figure 4 , Figure 5A and Figure 5B The described conductive pattern ( Figure 4 , Figure 5A and Figure 5B In this context, 63a, 63n, 63pn, and 63p can be replaced with, for example: Figure 9A and Figure 9B The conductive patterns 163a, 163n, 163pn, and 163p are included. Each of the conductive patterns 163a, 163n, 163pn, and 163p, and the unit pad pattern 163c, may include a first conductive layer 159 and a second conductive layer 162 stacked sequentially. (See reference...) Figure 4 , Figure 5A and Figure 5B The described plug patterns 56c, 56n, and 56p can be replaced with, for example... Figure 9A and Figure 9B The plug patterns 156c, 156n, and 156p are shown. A first conductive layer 159 may extend from the plug patterns 156c, 156n, and 156p. The first conductive layer 159 and the plug patterns 156c, 156n, and 156p may be integrated with each other. The conductive patterns 163a, 163n, 163pn, and 163p, as well as the unit pad pattern 163c, may have coplanar upper surfaces. However, the exemplary embodiment is not limited thereto.

[0075] Conductive patterns 163a, 163n, 163pn and 163p may include references respectively. Figure 4 , Figure 5A and Figure 5B The pad pattern 63a, the first upper routing 63n, the second upper routing 63p, and the upper connection routing 63pn described correspond to the pad pattern 163a, the first upper routing 163n, the second upper routing 163p, and the upper connection routing 163pn.

[0076] The storage region CR and the peripheral region PR may also include an upper isolation pattern 164. The upper isolation pattern 164 may be disposed between conductive patterns 163a, 163n, 163pn and 163p and the cell pad pattern 163c. The upper isolation pattern 164 may include an insulating material.

[0077] refer to Figure 4 , Figure 5A and Figure 5B The described insulating pad 66 can be replaced by an insulating pad 166 disposed on conductive patterns 163a, 163n, 163pn and 163p, unit pad pattern 163c and upper isolation pattern 164. The first electrode 68a of the data storage structure DS can penetrate the insulating pad 166 and can be connected to the unit pad pattern 163c.

[0078] Reference Figure 10A and Figure 10B Examples of semiconductor devices described according to some example embodiments. Figure 10A It can be with Figure 9A Corresponding cross-sectional views are provided to illustrate examples of semiconductor devices according to some exemplary embodiments, and Figure 10B It's a diagram. Figure 10A An enlarged view of region "F" in the image.

[0079] refer to Figure 10A and Figure 10B , Figure 9A The first part ST1_C of the first structure ST1 in the first part can be replaced with Figure 10A The first part of the first structure ST1, ST1_D. (See reference...) Figure 9A and Figure 9B The described upper connection wiring 163pn can be divided into a first upper wiring 163n and a second upper wiring 163p. The peripheral region PR may also include upper wiring structures 205, 225a, and 225pn located on the conductive patterns 163a, 163n, and 163p and the insulating pad 166. The upper wiring structures 205, 225a, and 225pn may include an interlayer insulating layer 205 and conductive patterns 225a and 225pn. The interlayer insulating layer 205 may be disposed on the insulating pad 166.

[0080] The conductive patterns 225a and 225pn may include pad structure 225a and upper connection wiring structure 225pn.

[0081] The pad structure 225a may include a passage 215 that penetrates the interlayer insulating layer 205 and the insulating pad 166 and connects to the pad pattern 163a, and a pad portion 220 disposed on the passage 215 and the interlayer insulating layer 205. The passage 215 may extend from the pad portion 220.

[0082] The upper connection wiring structure 225pn may include a first path 215n that penetrates the interlayer insulation layer 205 and the insulating pad 166 and is connected to the first upper wiring 163n, a second path 215p that penetrates the interlayer insulation layer 205 and the insulating pad 166 and is connected to the second upper wiring 163p, and a wiring portion 220pn that is connected to the first path 215n and the second path 215p and disposed on the interlayer insulation layer 205.

[0083] The wiring portion 220pn may overlap perpendicularly with the first upper wiring 163n and the second upper wiring 163p. The first path 215n and the second path 215p may extend from the wiring portion 220pn. The first path 215n and the second path 215p may be disposed between the wiring portion 220pn and the first upper wiring 163n and the second upper wiring 163p, and the wiring portion 220pn may be electrically connected to the first upper wiring 163n and the second upper wiring 163p.

[0084] Both conductive patterns 225a and 225pn may include a first conductive material layer 210 and a second conductive material layer 212 located on the first conductive material layer 210.

[0085] The storage area CR and the peripheral area PR may also include an insulating pad 166 and an upper insulating pad 230 disposed on the upper wiring structures 205, 225a and 225pn. The upper insulating pad 230 may be disposed on the insulating pad 166 and may cover the side and top surfaces of the upper wiring structures 205, 225a and 225pn.

[0086] The first electrode 68a of the data storage structure DS can penetrate the insulating pad 166 and the upper insulating pad 230, and can be connected to the cell pad pattern 163c.

[0087] Reference Figure 11A and Figure 11B Examples of semiconductor devices described according to some example embodiments. Figure 11A It can be with Figure 8A Corresponding cross-sectional views, thus illustrating examples of semiconductor devices according to some exemplary embodiments, Figure 11B It's a diagram. Figure 11A An enlarged view of region "F1" in the image.

[0088] refer to Figure 11A and Figure 11B , Figure 4 The first part ST1_A of the first structure ST1 in the first part can be replaced with Figure 11A The first part of the first structure ST1, ST1_E. (See reference...) Figure 8AThe described upper connection routing 63pn can be divided into a first upper routing 63n and a second upper routing 63p. The peripheral area PR may also include references. Figure 10A and Figure 10B The described upper wiring structures 205, 225a, and 225pn correspond to upper wiring structures 305, 325a, and 325pn. Upper wiring structures 305, 325a, and 325pn can be disposed on conductive patterns 63a, 63n, and 63p and insulating pad 66.

[0089] Each upper wiring structure 305, 325a and 325pn may include an interlayer insulating layer 305 and conductive patterns 325a and 325pn.

[0090] Interlayer insulation layer 305 can be disposed on insulating pad 66.

[0091] The conductive patterns 325a and 325pn may include pad structure 325a and upper connection wiring structure 325pn.

[0092] The pad structure 325a may include a passage 315 that penetrates the interlayer insulating layer 305 and the insulating pad 66 and connects to the pad pattern 63a, and a pad portion 320 disposed on the passage 315 and the interlayer insulating layer 305. The passage 315 may extend from the pad portion 320.

[0093] The upper connection wiring structure 325pn may include a first path 315n that penetrates the interlayer insulation layer 305 and the insulating pad 66 and is connected to the first upper wiring 63n; a second path 315p that penetrates the interlayer insulation layer 305 and the insulating pad 66 and is connected to the second upper wiring 63p; and a wiring portion 320pn that is connected to the first path 315n and the second path 315p and disposed on the interlayer insulation layer 305. The first path 315n and the second path 315p may extend from the wiring portion 320pn.

[0094] Both conductive patterns 325a and 325pn may include a first conductive material layer 310 and a second conductive material layer 312 located on the first conductive material layer 310.

[0095] The storage area CR and the peripheral area PR may also include an insulating pad 66 and an upper insulating pad 330 disposed on the upper wiring structures 305, 325a and 225pn. The upper insulating pad 330 may be disposed on the insulating pad 66 and may cover the side and top surfaces of the upper wiring structures 325a and 325pn.

[0096] The first electrode 68a of the data storage structure DS can penetrate the insulating pad 66 and the upper insulating pad 330, and can be connected to the cell contact plug 57c.

[0097] Reference Figure 12 , Figure 13A and Figure 13B Examples of semiconductor devices described according to some example embodiments. Figure 12 It can be with Figure 4 Corresponding cross-sectional views, thus illustrating examples of semiconductor devices according to some exemplary embodiments, Figure 13A It is an enlarged view illustrating areas "A2" and "B2", and Figure 13B This is an enlarged view illustrating areas "C2" and "D2".

[0098] refer to Figure 12 , Figure 13A and Figure 13B , Figure 4 The first part ST1_A of the first structure ST1 in the first part can be replaced with Figure 12 The first part of the first structure ST1, ST1_F. (See reference...) Figure 4 , Figure 5A and Figure 5B The described cell gate dielectric layer 24c, first peripheral gate dielectric layer 24n, second peripheral gate dielectric layer 24p, and insulating layers 18, 33, and 75 can be replaced with, for example... Figure 12 , Figure 13A and Figure 13B The unit gate dielectric layer 24c', the first peripheral gate dielectric layer 24n', the second peripheral gate dielectric layer 24p', and the insulating layers 18', 33', and 75' are included.

[0099] A cell gate dielectric layer 24c' can be disposed between the side surface of the cell vertical active pattern 21c and the side surface of the cell gate electrode 27c, and can extend to cover the upper surface of the cell gate electrode 27c. A first peripheral gate dielectric layer 24n' can be disposed between the side surface of the first peripheral vertical active pattern 21n and the side surface of the first peripheral gate electrode 27n, and can extend to cover the upper surface of the first peripheral gate electrode 27n. A second peripheral gate dielectric layer 24p' can be disposed between the side surface of the second peripheral vertical active pattern 21p and the side surface of the second peripheral gate electrode 27p, and can extend to cover the upper surface of the second peripheral gate electrode 27p.

[0100] Insulating layer 18' can be disposed on the upper surface of back gate electrodes 16c, 16n, and 16p. Insulating layer 75' can be disposed below the lower surface of back gate electrodes 16c, 16n, and 16p. Insulating layer 33' can be disposed below the lower surface of gate electrodes 27c, 27n, and 27p. Insulating layer 22' can be disposed on the upper surface of gate dielectric layers 24c', 24n', and 24p'.

[0101] In the following description, reference will be made to Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16 and Figure 17 Description Reference Figure 1 Various examples of semiconductor device 1 are described. Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16 and Figure 17 It is illustrated for reference. Figure 1 Figures illustrating various examples of the described semiconductor device 1.

[0102] refer to Figure 1 and Figure 14A Semiconductor device 1 may include and Figure 1 The first structure ST1a corresponding to the first structure ST1 in the first structure ST1 and the first structure ST1a with Figure 1 The second structure ST2a corresponds to the second structure ST2 in the first structure ST1a. The second structure ST2a can be disposed below the first structure ST1a, and can contact and join the first structure ST1a.

[0103] The first structure ST1a may include a first part ST1_1, which is related to the reference. Figures 4 to 13B The first part of the description, ST1_A, ST1_B, ST1_C, ST1_D, ST1_E, and ST1_F, is identical. For example, the first part ST1_1 can be the same as... Figure 4 The first part ST1_A is the same.

[0104] The first structure ST1a may also include an insulating layer 74 located on the first part ST1_1 and an insulating layer 95 located below the first part ST1_1.

[0105] The first structure ST1a may further include upper contact plugs 70a and 70c and upper wiring 72. Each contact plug 70a may include a conductive plug pattern 69b and a conductive pad 69a covering the side and lower surfaces of the conductive plug pattern 69b.

[0106] The upper contact plugs 70a and 70c may include a unit contact plug 70c that penetrates the insulating layer 70 and is connected to the second electrode 68c, and a connection contact plug 70a that penetrates the insulating layer 70 and the insulating pad 66 and is connected to the pad pattern 63a.

[0107] The upper wiring 72 can be connected to the contact plugs 70a and 70c and the insulating layer 70. The insulating layer 74 can be disposed on the insulating layer 70 and the upper wiring 72.

[0108] The first structure ST1a may also include lower contact plugs 93b, 93a, 93n1, 93n2, 93pn, 93p2 and 93p1 that penetrate the insulating layer 90 and extend upward.

[0109] The lower contact plugs 93b, 93a, 93n1, 93n2, 93pn, 93p2 and 93p1 may each include a conductive plug pattern 92 and a conductive pad 91 covering the lower surface and side surface of the conductive plug pattern 92.

[0110] The lower contact plugs 93b, 93a, 93n1, 93n2, 93pn, 93p2, and 93p1 may include: a contact plug 93a connected to and in contact with bit line 83c; a contact plug 93b connected to and in contact with pad pattern 63a; a contact plug 93n1 connected to and in contact with first upper wiring 63n; a contact plug 93n2 connected to and in contact with first lower wiring 83n; a contact plug 93pn connected to and in contact with upper connection wiring 63pn; a contact plug 93p2 connected to and in contact with second lower wiring 83p; and a contact plug 93p1 connected to and in contact with second upper wiring 63p.

[0111] The first structure ST1a may consist of: an insulating layer 95 disposed below the first portion ST1_1; a routing structure disposed in the insulating layer 95 and electrically connected to the lower contact plugs 93b, 93a, 93n1, 93n2, 93pn, 93p2, and 93p1; and a bonding pad 99 connected to the routing structure 97. The lower surface of the insulating layer 95 and the lower surface of the bonding pad 99 may be coplanar with each other.

[0112] The second structure ST2a may include a first peripheral circuit pTRa that overlaps perpendicularly with the storage region CR and a second peripheral circuit pTRb that overlaps perpendicularly with the peripheral region PR.

[0113] The second structure ST2a may include a substrate 403 and a device isolation region 406 defining an active region 409 on the substrate 403. The substrate 403 may be configured as a semiconductor substrate.

[0114] The first peripheral circuit pTRa and the second peripheral circuit pTRb can be disposed on the substrate 403.

[0115] Both the first peripheral circuit pTRa and the second peripheral circuit pTRb may include peripheral gate structures pGO and pGE disposed on the active region 409, peripheral source / drain regions pSD disposed on both sides of the peripheral gate structures pGO and pGE disposed in the active region 409, and a peripheral channel region pCH located between the peripheral source / drain regions pSD. The peripheral gate structures pGO and pGE may include a peripheral gate dielectric layer pGO and a peripheral gate electrode pGE stacked sequentially.

[0116] The first peripheral circuit pTRa and the second peripheral circuit pTRb may include a first peripheral circuit transistor pTRa that is perpendicularly overlapped with the storage region CR and a second peripheral circuit transistor pTRb that is perpendicularly overlapped with the peripheral region PR.

[0117] The second structure ST2a may further include a lower routing structure 420 disposed on the substrate 403 and electrically connected to the first peripheral circuit pTRa and the second peripheral circuit pTRb, a second bonding pad 425 disposed on the lower routing structure 420, and a lower insulating structure 415. The lower insulating structure 415 may be disposed on the substrate 403 and may have an upper surface coplanar with the upper surface of the second bonding pad 425. The upper surface of the second bonding pad 425 may be bonded to the lower surface of the first bonding pad 99, and the upper surface of the lower insulating structure 415 may be bonded to the lower surface of the insulating layer 95.

[0118] The lower routing structure 420 may include a first lower routing structure 420a electrically connected to the second bonding pad 425 and a second lower routing structure 420b not directly connected to the second bonding pad 425.

[0119] The second structure ST2a may further include an insulating layer 430 disposed below the substrate 403, a conductive through-path 440 penetrating the insulating layer 430 and the substrate 403 and connected to the second lower routing wiring structure 420b, an insulating spacer 435 disposed on the side surface of the conductive through-path 440, and an input / output pad 450 connected to the conductive through-path 440 below the insulating layer 430.

[0120] refer to Figure 1 and 14B , Figure 14A The first part ST1_1 in the code can be replaced with the first part ST1_2, which can be used with... Figure 10A The first part, ST1_D, is the same. Therefore, Figure 14A The connection contact plug 70a in the middle can be replaced with a connection contact plug 70a' that contacts and connects to the pad structure 225a. Therefore, a semiconductor device 1a including the first part ST1_2 can be provided.

[0121] refer to Figure 1 and Figure 15A You can choose not to set it. Figure 14A The first bonding pad 99 in the first structure ST1a. Figure 14A The second structure ST2a in the text can be replaced with Figure 15A The second structure ST2b in the text.

[0122] The second structure ST2b may include a first peripheral circuit pTRa that overlaps perpendicularly with the storage region CR and a second peripheral circuit pTRb that overlaps perpendicularly with the peripheral region PR.

[0123] The second structure ST2b may include a substrate 503 and a device isolation region 506 defining an active region 509 below the substrate 503. The substrate 503 may be configured as a semiconductor substrate.

[0124] The first peripheral circuit pTRa and the second peripheral circuit pTRb can be disposed below the substrate 503.

[0125] Both the first peripheral circuit pTRa and the second peripheral circuit pTRb may include peripheral gate structures pGO and pGE disposed below the active region 509, peripheral source / drain regions pSD disposed on both sides of the peripheral gate structures pGO and pGE disposed in the active region 509, and a peripheral channel region pCH located between the peripheral source / drain regions pSD. The peripheral gate structures pGO and pGE may include a peripheral gate dielectric layer pGO and a peripheral gate electrode pGE stacked sequentially in a downward direction.

[0126] The second structure ST2b may further include a lower routing structure 520 disposed below the substrate 503 and electrically connected to the first peripheral circuit pTRa and the second peripheral circuit pTRb, and a lower insulating structure 515 covering the lower routing structure 520.

[0127] The downstream routing structure 520 may include a first downstream routing structure 520a and a second downstream routing structure 520b.

[0128] The second structure ST2b may further include input / output pads 550 disposed below the lower insulating structure 515 and electrically connected to the second lower routing wiring structure 520b, and an insulating layer 530 disposed between the substrate 503 and the first structure ST1a. The insulating layer 530 and the insulating layer 95 may be bonded to each other.

[0129] The first structure ST1a and the second structure ST2b can be electrically connected to the first lower routing structure 520a and extend in the vertical direction Z. They can also include a conductive through-path 535 that penetrates the substrate 503 and the insulating layer 530 and contacts and connects to the routing structure 97, as well as an insulating spacer 534 located on the side surface of the conductive through-path 535. The conductive through-path 535 can include a conductive post 535a and a conductive pad layer 535b covering the side and top surfaces of the conductive post 535a.

[0130] Therefore, a semiconductor device 1b comprising a first structure ST1a and a second structure ST2b can be provided.

[0131] refer to Figure 1 and Figure 15B You don't have to set it. Figure 14B The first bonding pad 99 in the first structure ST1a. Figure 14B The second structure ST2a, located below the first structure ST1a, can be replaced with a reference. Figure 15A The second structure ST2b is described. The first structure ST1a and the second structure ST2b may include references. Figure 15A The example described uses the same conductive through-path 535 and insulating spacer 534. Therefore, a semiconductor device 1c comprising a first structure ST1a and a second structure ST2b can be provided.

[0132] refer to Figure 1 and Figure 16 According to some example embodiments, the semiconductor device 1d may include, Figure 1 The first structure ST1b corresponding to the first structure ST1 in the first structure ST1 and the first structure ST1b with Figure 1 The second structure ST2c corresponds to the second structure ST2 in the first structure ST1b. The second structure ST2c can be disposed on the first structure ST1b and can contact and join the first structure ST1b.

[0133] The first structure ST1b may include reference Figures 4 to 13B The first part ST1_3 is identical to one of the first parts ST1_A, ST1_B, ST1_C, ST1_D, ST1_E, and ST1_F. For example, the first part ST1_3 can be the same as... Figure 4 The first part ST1_A is the same.

[0134] The first structure ST1b may further include a first bonding pad 625 disposed on the first portion ST1_3 in the insulating layer 662, and the first bonding pad 625 is electrically connected to the routing wiring structure 660. The upper surface of the first bonding pad 625 may be coplanar with the upper surface of the insulating layer 662.

[0135] The aforementioned pad pattern 63a may include a first pad pattern 63a1 that is perpendicularly overlapping with the bit line 83c, a second pad pattern 63a2 that is perpendicularly overlapping with the first lower wiring 83n, and a third pad pattern 63a3 that is perpendicularly overlapping with the second lower wiring 83p.

[0136] The first structure ST1b may also include lower contact plugs 693a, 693n2 and 693p2 and upper contact plugs 670c, 670a, 670n2, 670n1, 670pn, 670p1 and 670p2.

[0137] The lower contact plugs 693a, 693n2, and 693p2 may include: a contact plug 693a that electrically connects the bit line 83c to the first pad pattern 63a1 between the bit line 83c and the first pad pattern 63a1; a contact plug 693n2 that electrically connects the first lower wiring 83n to the second pad pattern 63a2 between the first lower wiring 83n and the second pad pattern 63a2; and a contact plug 693p2 that electrically connects the second lower wiring 83p to the third pad pattern 63a3 between the second lower wiring 83p and the third pad pattern 63a3. Each of the lower contact plugs 693a, 693n2, and 693p2 may include a plug pattern 692 and conductive pads 691 covering the side and lower surfaces of the plug pattern 692.

[0138] The upper contact plugs 670c, 670a, 670n2, 670n1, 670pn, 670p1 and 670p2 can penetrate the insulation layer 70.

[0139] The upper contact plugs 670c, 670a, 670n2, 670n1, 670pn, 670p1, and 670p2 may include a contact plug 670c connected to the second electrode 68c, a contact plug 670a connected to the first pad pattern 63a1, a contact plug 670n2 connected to the second pad pattern 63a2, a contact plug 670p2 connected to the third pad pattern 63a3, a contact plug 670n1 connected to the first upper wiring 63n1, a contact plug 670p1 connected to the second upper wiring 63p1, and a contact plug 670pn electrically connected to the upper connection wiring 63pn. Depending on the circuit connection structure, the contact plug 670pn may not be provided.

[0140] Upper contact plugs 670a, 670n2, 670n1, 670pn, 670p1, and 670p2 can penetrate the insulating layer 70 and the insulating gasket 66. Upper contact plug 670c can penetrate the insulating layer 70. Upper contact plugs 670c, 670a, 670n2, 670n1, 670pn, 670p1, and 670p2 can be electrically connected to the routing cabling structure 660.

[0141] The second structure ST2c may include a first peripheral circuit pTRa that overlaps perpendicularly with the storage region CR and a second peripheral circuit pTRb that overlaps perpendicularly with the peripheral region PR.

[0142] The second structure ST2c may include a substrate 603 and a device isolation region 606 defining an active region 609 below the substrate 603. The substrate 603 may be configured as a semiconductor substrate.

[0143] The first peripheral circuit pTRa and the second peripheral circuit pTRb can be disposed below the substrate 603.

[0144] Both the first peripheral circuit pTRa and the second peripheral circuit pTRb may include peripheral gate structures pGO and pGE disposed below the active region 609, peripheral source / drain regions pSD disposed on both sides of the peripheral gate structures pGO and pGE disposed in the active region 609, and a peripheral channel region pCH located between the peripheral source / drain regions pSD. The peripheral gate structures pGO and pGE may include a peripheral gate dielectric layer pGO and a peripheral gate electrode pGE stacked sequentially in a downward direction.

[0145] The second structure ST2c may include a lower routing structure 620 disposed below the substrate 603 and electrically connected to the first peripheral circuit pTRa and the second peripheral circuit pTRb, a lower insulating structure 615 covering the lower routing structure 620, and a second bonding pad 699 having a lower surface coplanar with the lower surface of the lower insulating structure 615. The second bonding pad 699 may be bonded to the first bonding pad 625, and the lower insulating structure 615 may be bonded to the insulating layer 662.

[0146] The downstream routing structure 620 may include a first downstream routing structure 620a and a second downstream routing structure 620b.

[0147] The second structure ST2c may further include an insulating layer 630 on the substrate 603, input / output pads 650 on the insulating layer 630, a conductive pass-through 640 electrically connecting the input / output pads 650 to the second lower routing structure 620b, and an insulating spacer 635 on the side surface of the conductive pass-through 640. The conductive pass-through 640 can penetrate the insulating layer 630 and the substrate 603.

[0148] refer to Figure 1 and Figure 17 You don't have to set it. Figure 16 The first bonding pad 625 in the first structure ST1b. Figure 16 The second structure ST2c in the text can be replaced with Figure 17 The second structure ST2d in it.

[0149] The second structure ST2d may include a first peripheral circuit pTRa that overlaps perpendicularly with the storage region CR and a second peripheral circuit pTRb that overlaps perpendicularly with the peripheral region PR.

[0150] The second structure ST2d may include a substrate 703 and a device isolation region 706 defining an active region 709 on the substrate 703. The substrate 703 may be configured as a semiconductor substrate.

[0151] The first peripheral circuit pTRa and the second peripheral circuit pTRb can be disposed on the substrate 703.

[0152] Both the first peripheral circuit pTRa and the second peripheral circuit pTRb may include peripheral gate structures pGO and pGE disposed on the active region 709, peripheral source / drain regions pSD disposed on both sides of the peripheral gate structures pGO and pGE disposed in the active region 709, and a peripheral channel region pCH located between the peripheral source / drain regions pSD. The peripheral gate structures pGO and pGE may include a peripheral gate dielectric layer pGO and a peripheral gate electrode pGE stacked sequentially.

[0153] The second structure ST2d may further include a lower routing structure 720 disposed on the substrate 703 and electrically connected to the first peripheral circuit pTRa and the second peripheral circuit pTRb, and a lower insulating structure 715 covering the lower routing structure 720.

[0154] The downstream routing structure 720 may include a first downstream routing structure 720a and a second downstream routing structure 720b.

[0155] The second structure ST2d may further include input / output pads 750 disposed on the lower insulating structure 715 and electrically connected to the second lower routing wiring structure 720b, and an insulating layer 730 disposed between the substrate 703 and the first structure ST1b. The insulating layer 730 and the insulating layer 795 may be bonded to each other.

[0156] The first structure ST1b and the second structure ST2d can be electrically connected to the first lower routing structure 720a and can extend downwards. They may also include a conductive passage 735 that penetrates the substrate 703 and the insulating layer 730 and contacts and connects to the routing structure 797, as well as an insulating spacer 734 located on the side surface of the conductive passage 735. The conductive passage 735 may include a conductive post 735b and a conductive pad layer 735a covering the side and lower surfaces of the conductive post 735b.

[0157] Therefore, a semiconductor device 1e comprising a first structure ST1b and a second structure ST2d can be provided.

[0158] In the following description, reference will be made to Figures 18 to 37 Examples describing methods for manufacturing semiconductor devices according to some example embodiments. Figures 18 to 37 It is illustrated along Figure 3 The cross-sectional view of the region intercepted by line I-I' in the figure illustrates an example of a method for manufacturing a semiconductor device according to some example embodiments.

[0159] refer to Figure 3 and Figure 18 A sacrificial substrate 3, a sacrificial insulating layer 6, and a semiconductor layer 9 can be formed by sequentially stacking these components. The semiconductor layer 9 can be formed from a semiconductor material such as single-crystal silicon.

[0160] Trench 12 can be formed that penetrates the semiconductor layer 9 and the sacrificial insulating layer 6. The trench 12 can be formed in the memory region CR and the peripheral region PR. Each trench 12 can be configured as a line extending in the second horizontal direction Y. The semiconductor layers 9 can be spaced apart from each other in the first horizontal direction X via the trench 12.

[0161] The operation may include: forming a back gate dielectric layer 14 that conformally covers the inner wall of the trench 12; forming a back gate conductive layer on the back gate dielectric layer 14; forming a preliminary back gate electrode 16 that partially fills the trench 12 by etching a portion of the back gate conductive layer using an etch-back process; and forming a back gate covering insulating layer 18 on the preliminary back gate electrode 16 that fills the remaining portion of the trench 12. The back gate covering insulating layer 18 may be formed of an insulating material.

[0162] refer to Figure 3 and Figure 19 It can be achieved by modifying the semiconductor layer ( Figure 18 9) is patterned to form vertical active patterns 21c, 21n and 21p, and at the same time, the sacrificial insulating layer 6 can be exposed.

[0163] The vertical active patterns 21c, 21n and 21p may include a cell vertical active pattern 21c formed in the storage region CR, and a first peripheral active pattern 21n and a second peripheral active pattern 21p formed in the peripheral region PR.

[0164] In the vertical active patterns 21c, 21n and 21p, pairs of adjacent vertical active patterns can be formed on both sides of one of the initial back gate electrodes 16.

[0165] An insulating layer 22 can be formed on the exposed sacrificial insulating layer 6. The upper surface of the insulating layer 22 can be set at a height lower than the height of the upper surface of the initial back gate electrode 16.

[0166] refer to Figure 3 and Figure 20 Dielectric layers 24c, 24, 24n, and 24p, and gate electrodes 27c, 27n, and 27p, can be formed. Forming dielectric layers 24c, 24, 24n, and 24p, and gate electrodes 27c, 27n, and 27p, may include: forming dielectric layers 24c, 24, 24n, and 24p that conformally cover the exposed upper surface of the insulating layer 22 and the side surfaces perpendicular to the active patterns 21c, 21n, and 21p; forming a preliminary gate conductive layer that conformally covers the gate dielectric layers 24c, 24, 24n, and 24p; forming a gate conductive layer by anisotropically etching the preliminary gate conductive layer; forming an isolation insulating layer 30 on the dielectric layers 24c, 24, 24n, and 24p; forming gate electrodes 27c, 27n, and 27p by etching a portion of the gate conductive layer; and forming a gate covering insulating layer 33 on the gate electrodes 27c, 27n, and 27p.

[0167] Dielectric layers 24c, 24, 24n, and 24p may include a cell gate dielectric layer 24c, a first peripheral gate dielectric layer 24n, a second peripheral gate dielectric layer 24p, and dielectric layer 24. The cell gate dielectric layer 24c may contact the side surface of the cell vertical active pattern 21c. The first peripheral gate dielectric layer 24n may contact the side surface of the first peripheral vertical active pattern 21n. The second peripheral gate dielectric layer 24p may contact the side surface of the second peripheral vertical active pattern 21p. Dielectric layers 24 may be disposed between adjacent groups of a set of cell vertical active patterns 21c, a set of first peripheral vertical active patterns 21n, and a set of second peripheral vertical active patterns 21p.

[0168] The insulating layer 30 can be disposed between adjacent unit gate electrodes 27c, between adjacent first peripheral gate electrodes 27n, between adjacent second peripheral gate electrodes 27p, and on the dielectric layer 24.

[0169] The upper surfaces of the vertical active patterns 21c, 21n and 21p, the upper surface of the isolation insulating layer 30 and the upper surface of the gate covering insulating layer 33 can be coplanar with each other.

[0170] Subsequently, a first semiconductor layer 36 and a protective layer 39 located on the first semiconductor layer 36 can be formed. The lower surface of the first semiconductor layer 36 can contact the upper surface of the vertical active patterns 21c, 21n and 21p.

[0171] The vertical active patterns 21c, 21n, and 21p can be formed from monocrystalline silicon. For example, the vertical active patterns 21c, 21n, and 21p can be formed from undoped monocrystalline silicon.

[0172] In some example embodiments, the first semiconductor layer 36 may be formed of polysilicon. For example, the first semiconductor layer 36 may be formed of undoped polysilicon.

[0173] In some example embodiments, the first semiconductor layer 36 may be formed of epitaxial silicon.

[0174] refer to Figure 3 and Figure 21 By using the protective layer ( Figure 20 Patterning 39) in the first semiconductor layer 36 can expose the portion of the first semiconductor layer 36 that is in contact with the cell-perpendicular active pattern 21c and the first peripheral active pattern 21n, and can form a lower protective pattern 39a on the portion of the first semiconductor layer 36 that is in contact with the second peripheral active pattern 21p.

[0175] refer to Figure 3 and Figure 22 A second semiconductor layer 42 and an upper protective pattern 44 can be sequentially stacked on the first semiconductor layer 36 exposed by the protective pattern 39a. The second semiconductor layer 42 can be formed of polycrystalline silicon with N-type conductivity.

[0176] refer to Figure 3 and Figure 23 Lower protective pattern ( Figure 22 39a) in the first semiconductor layer 36 can be removed. Therefore, the portion of the first semiconductor layer 36 that contacts the second peripheral active pattern 21p can be exposed.

[0177] Third semiconductor layers 48_1 and 48_2 can be formed. The third semiconductor layers 48_1 and 48_2 may include a first portion 48_1 contacting the upper surface of the first semiconductor layer 36 (which contacts the second peripheral active pattern 21p) and a second portion 48_2 contacting the upper surface of the upper protective pattern 44. The second portion 48_2 can be formed at a height higher than the first portion 48_1. The third semiconductor layers 48_1 and 48_2 can be formed of polysilicon with P-type conductivity. An insulating layer can be formed on the third semiconductor layers 48_1 and 48_2, and the insulating layer can be planarized until the upper surface of the second portion 48_2 is exposed, thereby forming a buffer insulating pattern 50 remaining on the first portion 48_1.

[0178] refer to Figure 3 and Figure 24 The second portion 48_2 of the third semiconductor layers 48_1 and 48_2 can be removed by etching. Therefore, the first portion 48_1 of the third semiconductor layers 48_1 and 48_2 can be retained.

[0179] refer to Figure 3 and Figure 25The third semiconductor pattern 48a and the second semiconductor pattern 42a can be formed by planarizing the thickness of the first portion 48_1 of the third semiconductor layers 48_1 and 48_2 and the thickness of the second semiconductor layer 42. During planarization, the upper protective pattern 44 and the buffer insulating pattern 50 can be removed.

[0180] The third semiconductor pattern 48a and the second semiconductor pattern 42a can have substantially the same thickness.

[0181] refer to Figure 3 and Figure 26 An insulating layer 51 can be formed on the third semiconductor pattern 48a and the second semiconductor pattern 42a.

[0182] Isolation patterns 52a, 52b, and 52c can be formed. Isolation patterns 52a, 52b, and 52c can be formed from an insulating material different from the material of insulating layer 51. For example, insulating layer 51 can be formed from an insulating oxide such as silicon oxide, and isolation patterns 52a, 52b, and 52c can be formed from an insulating nitride such as silicon nitride.

[0183] The isolation patterns 52a, 52b, and 52c may include a unit isolation pattern 52a, a first peripheral isolation pattern 52c, and a second peripheral isolation pattern 52b. The isolation patterns 52a, 52b, and 52c may be spaced apart from the vertical active patterns 21c, 21n, and 21p, respectively.

[0184] Cell isolation pattern 52a can be formed in the memory region CR and can penetrate the insulating layer 51, the second semiconductor pattern 42a, and the first semiconductor layer 36. First peripheral isolation pattern 52c can be formed in the peripheral region PR and can penetrate the insulating layer 51, the second semiconductor pattern 42a, and the first semiconductor layer 36. Second peripheral isolation pattern 52b can be formed in the peripheral region PR and can penetrate the insulating layer 51, the third semiconductor pattern 48a, and the first semiconductor layer 36.

[0185] refer to Figure 3 and Figure 27 Insulation structures 54 and 56 can be formed. Insulation structures 54 and 56 can be arranged between adjacent groups of a set of unit isolation patterns 52a, a set of first peripheral isolation patterns 52c and a set of second peripheral isolation patterns 52b.

[0186] Insulating structures 54 and 56 can penetrate insulating layer 51 and second semiconductor pattern 42a and third semiconductor pattern 48a. Each insulating structure 54 and 56 may include an insulating pattern 56 and an insulating pad 54 covering the side and bottom surfaces of the insulating pattern 56. The insulating pattern 56 may include an oxide, and the insulating pad 54 may include a nitride.

[0187] Second semiconductor pattern ( Figure 26 The first impurity in (42a) can diffuse into the first semiconductor layer ( Figure 26 In the 36th region), the upper region of the vertical active pattern 21c and the upper region of the first peripheral vertical active pattern 21n. Therefore, the second semiconductor pattern ( Figure 26 The concentration of the first impurity in (42a) can be higher than that in the first semiconductor layer ( Figure 26 The concentration of the first impurity in (36) and the first semiconductor layer ( Figure 26 The concentration of the first impurity in (36) can be higher than the concentration of the first impurity in the upper region of the unit vertical active pattern 21c and the upper region of the first peripheral vertical active pattern 21n. The first impurity can be a group V element in the periodic table, such as P or As.

[0188] Third semiconductor pattern ( Figure 26 The second impurity in (48a) can diffuse into the first semiconductor layer ( Figure 26 In the upper region of the third semiconductor pattern (36) and the second peripheral vertical active pattern 21p. Therefore, the third semiconductor pattern ( Figure 26 The concentration of the second impurity in (48a) can be higher than that in the first semiconductor layer ( Figure 26 The concentration of the second impurity in (36) and the first semiconductor layer ( Figure 26 The concentration of the second impurity in (36) can be higher than the concentration of the second impurity in the upper region of the second peripheral vertical active pattern 21p. The second impurity can be configured as a Group III element in the periodic table, such as B or Al. The first semiconductor layer ( Figure 26 36) can be formed from polycrystalline silicon doped with group V and group III elements.

[0189] The first semiconductor layer defined by cell isolation pattern 52a Figure 26 36 in the middle) and the second semiconductor pattern ( Figure 26 42a) can be formed as the source / drain pattern 36c on the first cell and the source / drain pattern 42c on the second cell. The first semiconductor layer (defined by the first peripheral isolation pattern 52c) Figure 26 36 in the middle) and the second semiconductor pattern ( Figure 26 42a) can be formed as source / drain pattern 36n on the first-1 periphery and source / drain pattern 42n on the first-2 periphery. The first semiconductor layer defined by the second periphery isolation pattern 52b ( Figure 26 36) and the third semiconductor pattern ( Figure 26 48a) can be formed as source / drain pattern 36p on the second-1st periphery and source / drain pattern 42p on the second-2nd periphery.

[0190] The first cell source / drain pattern 36c and the second cell source / drain pattern 42c, stacked sequentially, can be included in the cell source / drain pattern 35c. The first-1 peripheral source / drain pattern 36n and the first-2 peripheral source / drain pattern 42n, stacked sequentially, can be included in the first peripheral source / drain pattern 35n. The second-1 peripheral source / drain pattern 36p and the second-2 peripheral source / drain pattern 42p, stacked sequentially, can be included in the second peripheral source / drain pattern 35p.

[0191] refer to Figure 3 and Figure 28 Insulation layer ( Figure 27 51) in the middle can be removed. Therefore, the upper surface of the source / drain pattern 42c of the second unit, the upper surface of the source / drain pattern 42n of the first-second periphery, the upper surface of the source / drain pattern 42p of the second-second periphery, the upper side surface and upper surface of the insulating structures 54 and 56, and the upper side surface and upper surface of the isolation patterns 52a, 52b and 52c can be exposed.

[0192] refer to Figure 3 and Figure 29 Contact plugs 57c, 57n, and 57p can be formed. Contact plugs 57c, 57n, and 57p may include a cell contact plug 57c formed on the upper surface of the source / drain pattern 42c on the second cell, a first peripheral contact plug 57n formed on the upper surface of the source / drain pattern 42n on the first-2 periphery, and a second peripheral contact plug 57p formed on the upper surface of the source / drain pattern 42p on the second-2 periphery.

[0193] Each cell contact plug 57c may include a metal-semiconductor compound layer 53c in contact with the upper surface of the source / drain pattern 42c of the second cell, and a plug pattern 56c located on the metal-semiconductor compound layer 53c. Each first peripheral contact plug 57n may include a metal-semiconductor compound layer 53n in contact with the upper surface of the source / drain pattern 42n of the first-second peripheral cell, and a plug pattern 56n located on the metal-semiconductor compound layer 53n. Each second peripheral contact plug 57p may include a metal-semiconductor compound layer 53p in contact with the upper surface of the source / drain pattern 42p of the second-second peripheral cell, and a plug pattern 56p located on the metal-semiconductor compound layer 53p.

[0194] refer to Figure 3 and Figure 30 Conductive structures 59 and 62 can be formed on contact plugs 57c, 57n and 57p, insulating structures 54 and 56, and isolation patterns 52a, 52b and 52c. Conductive structures 59 and 62 may include a first conductive layer 59 and a second conductive layer 62 stacked sequentially.

[0195] refer to Figure 3 and Figure 31 Conductive patterns 63a, 63n, 63pn, and 63p can be formed by patterning conductive structures 59 and 62. Conductive patterns 63a, 63n, 63pn, and 63p may include pad pattern 63a, first upper wiring 63n, second upper wiring 63p, and upper connection wiring 63pn.

[0196] The first upper wiring 63n can be connected to a portion of the first peripheral contact plugs 57n. The second upper wiring 63p can be connected to a portion of the second peripheral contact plugs 57p. The upper connecting wiring 63pn can electrically connect a portion of the first peripheral contact plugs 57n to a portion of the second peripheral contact plugs 57p. The pad pattern 63a can be provided on the insulating structures 54 and 56.

[0197] An insulating pad 66 can be formed that covers the upper and side surfaces of conductive patterns 63a, 63n, 63pn and 63p in the peripheral region PR and covers the upper surface of the cell contact plug 57c and the upper surface of the cell isolation pattern 52a in the storage region CR.

[0198] refer to Figure 3 and Figure 32 A data storage structure DS can be formed. The data storage structure DS may include: a first electrode 68a connected to the cell plug pattern 57c, penetrating the insulating pad 66 and extending in the vertical direction Z; a second electrode 68c located on each of the side surface and the top surface of the first electrode 68a; and a dielectric layer 68b located between the first electrode 68a and the second electrode 68c.

[0199] An insulating layer 70 can be formed that covers the data storage structure DS in the storage region CR and covers the insulating pad 66 in the peripheral region PR. The insulating pad 66 may include a material different from that of the insulating layer 70.

[0200] refer to Figure 3 and Figure 33 Contact plugs 70a and 70c can be formed. Each contact plug 70a may include a conductive plug pattern 69b and a conductive pad 69a covering the side and bottom surfaces of the conductive plug pattern 69b.

[0201] Contact plugs 70a and 70c may include: unit contact plug 70c that penetrates the insulating layer 70 and is connected to the second electrode 68c, and connection contact plug 70a that penetrates the insulating layer 70 and the insulating pad 66 and is connected to the pad pattern 63a.

[0202] Upper wiring 72 connected to the contact plugs 70a and 70c can be formed on the contact plugs 70a and 70c and the insulating layer 70. An insulating layer 74 can be formed on the insulating layer 70 and the upper wiring 72.

[0203] refer to Figure 3 and Figure 34 The insulating layer 74 can be disposed in a downward direction, and the sacrificial substrate 3 and the sacrificial insulating layer 6 can be removed. Back gate electrodes 16c, 16n, and 16p can be formed by etching the initial back gate electrode 16, and the insulating layer 75 can be formed on the back gate electrodes 16c, 16n, and 16p. The insulating layer 22 and the vertical active patterns 21c, 21n, and 21p can be exposed.

[0204] refer to Figure 3 and Figure 35 The second semiconductor pattern can be formed on the exposed insulating layer 22 and the exposed vertical active patterns 21c, 21n and 21p. Figure 25 42a) and the third semiconductor pattern ( Figure 25 The fifth semiconductor pattern 78 and the sixth semiconductor pattern 79 correspond to 48a in the diagram. The fifth semiconductor pattern 78 and the sixth semiconductor pattern 79 can be used in conjunction with the second semiconductor pattern ( Figure 25 42a) and the third semiconductor pattern ( Figure 25 The second semiconductor pattern (48a) is formed in the same manner. Figure 25 42a) and the fifth semiconductor pattern 78 can be formed from the same material, and the third semiconductor pattern ( Figure 25 48a) and the sixth semiconductor pattern 79 can be formed from the same material.

[0205] refer to Figure 3 and Figure 36 Conductive structures 81 and 82 can be formed on the fifth semiconductor pattern 78 and the sixth semiconductor pattern 79. Conductive structures 81 and 82 may include a first conductive layer 81 and a second conductive layer 82 stacked sequentially.

[0206] By patterning conductive structures 81 and 82, fifth semiconductor pattern 78 and sixth semiconductor pattern 79, conductive patterns 83c, 83n and 83p and lower source / drain patterns 78c, 78n and 78p can be formed.

[0207] The lower source / drain patterns 78c, 78n, and 78p may include a lower source / drain pattern 78c connected to the cell vertical active pattern 21c, a first peripheral lower source / drain pattern 78n connected to the first peripheral vertical active pattern 21n, and a second peripheral lower source / drain pattern 78p connected to the first peripheral vertical active pattern 21p.

[0208] Impurities in the lower source / drain pattern 78c of the cell can diffuse into the vertical active pattern 21c of the cell, thereby forming a source / drain region in the vertical active pattern 21c. Impurities in the first peripheral lower source / drain pattern 78n can diffuse into the first peripheral vertical active pattern 21n, thereby forming a source / drain region in the first peripheral vertical active pattern 21n. Impurities in the second peripheral lower source / drain pattern 78p can diffuse into the second peripheral vertical active pattern 21p, thereby forming a source / drain region in the second peripheral vertical active pattern 21p.

[0209] The conductive patterns 83c, 83n, and 83p may include: a bit line 83c that is in contact with and self-aligned to the cell lower source / drain pattern 78c, a first lower wiring 83n that is in contact with and self-aligned to the first peripheral lower source / drain pattern 78n, and a second lower wiring 83p that is in contact with and self-aligned to the second peripheral lower source / drain pattern 78p.

[0210] refer to Figure 3 and Figure 37 Insulating structures 85 and 86 and a bit line shielding structure 88 can be formed. Insulating structures 85 and 86 may include an insulating pattern 86 and an insulating pad 85, which covers the upper surface of the insulating pattern 86, the side surfaces of the lower source / drain patterns 78c, 78n, and 78p, and the side and lower surfaces of the conductive patterns 83c, 83n, and 83p. The bit line shielding structure 88 may be disposed between bit lines 83c and may be disposed below bit lines 83c. The bit line shielding structure 88 may be spaced apart from the bit lines 83c by the insulating pad 85.

[0211] An insulating layer 90 can be formed on insulating structures 85 and 86 and bit line shielding structure 88.

[0212] Contact plugs 93b, 93a, 93n1, 93n2, 93pn, 93p2 and 93p1 can be formed that penetrate the insulating layer 90 and extend downward.

[0213] Contact plugs 93b, 93a, 93n1, 93n2, 93pn, 93p2 and 93p1 may each include a conductive plug pattern 92 and a conductive pad 91 covering the lower and side surfaces of the conductive plug pattern 92. Contact plugs 93b, 93a, 93n1, 93n2, 93pn, 93p2, and 93p1 may include: a contact plug 93b connected to and in contact with bit line 83c; a contact plug 93a connected to and in contact with pad pattern 63a; a contact plug 93n1 connected to and in contact with first upper wiring 63n; a contact plug 93n2 connected to and in contact with first lower wiring 83n; a contact plug 93pn connected to and in contact with upper connection wiring 63pn; a contact plug 93p2 connected to and in contact with second lower wiring 83p; and a contact plug 93p1 connected to and in contact with second upper wiring 63p.

[0214] An insulating structure 95 formed on the contact plugs 93b, 93a, 93n1, 93n2, 93pn, 93p2, and 93p1 and the insulating layer 90, a routing structure 97 disposed in the insulating structure 95 and electrically connected to the contact plugs 93b, 93a, 93n1, 93n2, 93pn, 93p2, and 93p1, and a bonding pad 99 connected to the routing structure 97 can be formed. The upper surface of the insulating structure 95 and the upper surface of the bonding pad 99 can be coplanar with each other. Therefore, a structure such as Figure 14A The first structure ST1a is shown in the figure.

[0215] According to the foregoing example embodiments, a transistor may include a vertically arranged lower source / drain, a vertical channel region, and an upper source / drain. The upper source / drain may include an upper source / drain region disposed in the upper region of the vertical active pattern and an upper source / drain pattern disposed on the vertical active pattern. The lower source / drain may include a lower source / drain region disposed in the lower region of the vertical active pattern and a lower source / drain pattern disposed below the vertical active pattern. Both the lower source / drain pattern and the upper source / drain pattern can improve the leakage current properties of the transistor. By including the lower source / drain pattern and the upper source / drain pattern in the transistor, the performance of the transistor can be improved.

[0216] Additionally, an upper contact plug can be configured to be perpendicularly aligned with the upper source / drain, and a lower wiring can be configured to be perpendicularly aligned with the lower source / drain.

[0217] Additionally, an upper wiring can be provided on the upper contact plug, and an insulating pad can be provided to cover the upper wiring.

[0218] Therefore, performance and integration density can be improved by including transistors, upper contact plugs, upper wiring, lower wiring, and insulating pads.

[0219] While some exemplary embodiments have been described and illustrated above, it will be clear to those skilled in the art that modifications and variations can be made without departing from the scope of the exemplary embodiments as defined by the appended claims.

Claims

1. A semiconductor device, the semiconductor device comprising a storage region and a peripheral region, The storage area includes: Vertical active pattern of the unit; A unit gate electrode, the unit gate electrode having a side surface facing the side surface of the unit vertical active pattern; The cell has a source / drain pattern and a cell contact plug, which are stacked sequentially on the cell's vertical active pattern. A cell isolation pattern, wherein the cell isolation pattern is located on the side surface of the source / drain pattern on the cell and on the side surface of the cell contact plug; as well as A data storage structure is located on the unit contact plug and the unit isolation pattern. The peripheral area includes: Peripheral vertical active pattern; A peripheral gate electrode having a side surface facing the peripheral vertical active pattern; The peripheral source / drain pattern and the peripheral contact plug are stacked sequentially on the peripheral vertical active pattern; A peripheral isolation pattern, wherein the peripheral isolation pattern is located on the side surface of the peripheral source / drain pattern and the side surface of the peripheral contact plug; and Upper wiring, wherein the upper wiring is located on the peripheral contact plug and the peripheral isolation pattern, The cell source / drain pattern includes a first cell source / drain pattern and a second cell source / drain pattern located on the first cell source / drain pattern. The peripheral source / drain pattern includes a first peripheral source / drain pattern and a second peripheral source / drain pattern located on the first peripheral source / drain pattern.

2. The semiconductor device according to claim 1, wherein, The concentration of impurities in the second peripheral source / drain pattern is higher than the concentration of impurities in the first peripheral source / drain pattern.

3. The semiconductor device according to claim 2, in, The peripheral vertical active pattern includes: Peripheral lower source / drain region; A peripheral vertical channel region, wherein the peripheral vertical channel region is located on the peripheral lower source / drain region; and The peripheral source / drain region is located on the peripheral vertical channel region. The peripheral source / drain pattern is in contact with the peripheral source / drain region of the peripheral vertical active pattern.

4. The semiconductor device according to claim 3, wherein, The concentration of impurities in the second peripheral source / drain pattern is higher than the concentration of impurities in the peripheral source / drain region.

5. The semiconductor device according to claim 1, in, The unit's vertical active pattern includes a first monocrystalline silicon. The peripheral vertical active pattern includes a second monocrystalline silicon. The source / drain pattern on the unit includes a first polysilicon, and The peripheral source / drain pattern includes a second polysilicon.

6. The semiconductor device according to claim 1, wherein, Each of the unit contact plug and the peripheral contact plug is a single conductive layer.

7. The semiconductor device according to claim 1, wherein, Each of the unit contact plug and the peripheral contact plug includes a plug pattern and a barrier layer covering the lower and side surfaces of the plug pattern.

8. The semiconductor device according to claim 1, wherein, The storage area and the peripheral area also include insulating pads located on the cell contact plug, the cell isolation pattern, and the upper wiring.

9. The semiconductor device according to claim 8, wherein, The insulating pad covers the upper and side surfaces of the upper wiring.

10. The semiconductor device according to claim 8, wherein, The data storage structure includes: The first electrode contacts the unit contact plug, penetrates the insulating gasket, and extends upward; A dielectric layer, the dielectric layer being located on the first electrode and the insulating pad; and The second electrode is located on the dielectric layer.

11. The semiconductor device according to claim 8, further comprising: A buffer insulation layer is located between the insulating pad and the upper wiring.

12. The semiconductor device according to claim 1, in, The storage area also includes: The cell's lower source / drain pattern, wherein the cell's lower source / drain pattern is located below the cell's vertical active pattern; and Bit lines, the bit lines being located below the source / drain pattern of the cell, and The peripheral area also includes: A peripheral lower source / drain pattern, wherein the peripheral lower source / drain pattern is located below the peripheral vertical active pattern; and The lower wiring is located below the peripheral lower source / drain pattern.

13. A semiconductor device, said semiconductor device comprising: The unit vertical active pattern and the peripheral vertical active pattern are spaced apart from each other; The cell has a source / drain pattern and a cell contact plug, which are sequentially stacked on the cell's vertical active pattern and are self-aligned. The peripheral source / drain pattern and the peripheral contact plug are stacked sequentially on the peripheral vertical active pattern and are self-aligned. A cell isolation pattern, wherein the cell isolation pattern is located on the side surface of the source / drain pattern on the cell and on the side surface of the cell contact plug; A peripheral isolation pattern, wherein the peripheral isolation pattern is located on the side surface of the peripheral source / drain pattern and the side surface of the peripheral contact plug; Upper wiring, the upper wiring being connected to and located on the peripheral contact plug; An insulating pad is located on the unit contact plug, the unit isolation pattern, and the upper wiring; as well as The data storage structure includes a first electrode, a dielectric layer, and a second electrode. The first electrode is connected to the unit contact plug, penetrates the insulating gasket, and extends upward. The dielectric layer is located on the first electrode, and the second electrode is located on the dielectric layer. The insulating pad includes a first portion located on the upper surface of the unit isolation pattern and a second portion located on the upper surface of the upper wiring. The second portion of the insulating pad is located at a higher height than the first portion of the insulating pad.

14. The semiconductor device according to claim 13, wherein, The insulating pad covers the upper and side surfaces of the upper wiring.

15. The semiconductor device of claim 13, further comprising: The lower source / drain pattern of the cell is located below the vertical active pattern of the cell; Bit lines are located below the lower source / drain pattern of the cell; The peripheral lower source / drain pattern is located below the peripheral vertical active pattern; as well as The lower wiring is located below the peripheral lower source / drain pattern. The cell source / drain pattern includes a first cell source / drain pattern and a second cell source / drain pattern located on the first cell source / drain pattern. The peripheral source / drain pattern includes a first peripheral source / drain pattern and a second peripheral source / drain pattern located on the first peripheral source / drain pattern.

16. A semiconductor device comprising a first structure and a second structure, the first structure including a storage region and a peripheral region, the second structure perpendicularly overlapping the first structure and including peripheral circuitry. in, The storage area includes: Vertical active pattern of the unit; A unit gate electrode, the unit gate electrode having a side surface facing the side surface of the unit vertical active pattern; The cell has a source / drain pattern and a cell contact plug, which are stacked sequentially on the cell's vertical active pattern. Cell isolation patterns, the cell isolation patterns being located on the side surfaces of the source / drain patterns on the cell and the side surfaces of the cell contact plugs; and A data storage structure is located on the unit contact plug and the unit isolation pattern. The peripheral area includes: First peripheral vertical active pattern; A first peripheral gate electrode, the first peripheral gate electrode having a side surface facing the side surface of the first peripheral vertical active pattern; The first peripheral source / drain pattern and the first peripheral contact plug are stacked sequentially on the first peripheral vertical active pattern; A peripheral isolation pattern, wherein the peripheral isolation pattern is located on the side surface of the source / drain pattern on the first peripheral periphery and on the side surface of the first peripheral contact plug; and The first upper wiring is located on the first peripheral contact plug and the peripheral isolation pattern. The source / drain pattern on the cell includes a first cell source / drain pattern and a second cell source / drain pattern stacked sequentially. The first peripheral source / drain pattern includes a first-1 peripheral source / drain pattern and a first-2 peripheral source / drain pattern stacked sequentially. The storage area and the peripheral area further include insulating pads located on the cell contact plug, the cell isolation pattern, and the first upper wiring. The peripheral circuit includes a first lower transistor that overlaps perpendicularly with the storage region and a second lower transistor that overlaps perpendicularly with the peripheral region.

17. The semiconductor device according to claim 16, in, The unit vertical active pattern includes: Lower source / drain regions of the cell; A vertical channel region for the cell, wherein the vertical channel region is located on the lower source / drain region of the cell; and The source / drain region on the cell is located on the vertical channel region of the cell. Wherein, the source / drain pattern on the cell is in contact with the source / drain region of the cell's vertical active pattern, and The side surface of the source / drain pattern on the unit is aligned with the side surface of the unit contact plug.

18. The semiconductor device according to claim 16, wherein, The insulating pad covers the upper and side surfaces of the first upper wiring.

19. The semiconductor device according to claim 16, in, The peripheral area includes: Second peripheral vertical active pattern; A second peripheral gate electrode, the second peripheral gate electrode having a side surface facing the side surface of the second peripheral vertical active pattern; and The second peripheral source / drain pattern and the second peripheral contact plug are sequentially stacked on the second peripheral vertical active pattern. The first upper wiring extends to the second peripheral contact plug and electrically connects the first peripheral contact plug and the second peripheral contact plug to each other.

20. The semiconductor device according to claim 16, in, The peripheral area includes: Second peripheral vertical active pattern; The second peripheral gate electrode has a side surface facing the side surface of the second peripheral vertical active pattern; The second peripheral source / drain pattern and the second peripheral contact plug are sequentially stacked on the second peripheral vertical active pattern; The second upper wiring is located on the second peripheral contact plug; and An upper connection wiring structure is provided, which connects to the first upper wiring and the second upper wiring. The upper connection wiring structure includes: The wiring portion overlaps perpendicularly with the first upper wiring and the second upper wiring; An interlayer insulating layer is located below the wiring portion; A first path, the first path penetrating the interlayer insulation layer and connecting the first upper wiring to the wiring portion; and The second path penetrates the interlayer insulation layer and connects the second upper wiring to the wiring portion.

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