A semiconductor structure and a method of fabricating the same

Abstract

The present disclosure relates to the technical field of semiconductor, and provides a semiconductor structure and a preparation method thereof, which are used for improving the problems of gate-induced drain leakage (GIDL) and row hammer effect. The semiconductor structure comprises a substrate, and a word line structure located on the substrate and extending along a first direction, the word line structure comprising a first word line layer, a second word line layer and a spacer layer located between the first word line layer and the second word line layer arranged from bottom to top along a second direction, wherein the first direction is parallel to the surface of the substrate, the second direction is parallel to the thickness direction of the substrate, and the work function of the second word line layer is different from that of the first word line layer. In this way, the first word line layer and the second word line layer cooperate with each other and are coordinated with each other, which is conducive to improving the electrical performance stability and reliability of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for preparing the same. Background Technology

[0002] With technological advancements, semiconductor devices are continuously evolving towards miniaturization and higher integration. Dynamic Random Access Memory (DRAM), as an important semiconductor device, can be used to store data or programs for data processing in electronic devices. However, while the size and linewidth of DRAM continue to decrease, many problems in its manufacturing process still need to be addressed. Summary of the Invention

[0003] This disclosure provides a semiconductor structure, the semiconductor structure comprising:

[0004] Substrate;

[0005] A word line structure is located on the substrate and extends along a first direction. The word line structure includes a first word line layer, a second word line layer, and a spacer layer located between the first word line layer and the second word line layer, arranged from bottom to top along a second direction.

[0006] Wherein, the first direction is parallel to the surface of the substrate, the second direction is parallel to the thickness direction of the substrate, and the work function of the second word line layer is different from that of the first word line layer.

[0007] In some embodiments, along the first direction, the first word line layer includes a first end, the second word line layer includes a second end, the first end and the second end are located on the same side of the substrate, and along the first direction, the sidewall of the first end of the first word line layer protrudes outward relative to the sidewall of the second end of the second word line layer.

[0008] In some embodiments, the semiconductor structure further includes:

[0009] The lead-out portion extends along the second direction and is located on the side where the first end of the first word line layer is located, and the lead-out portion is connected to the first word line layer;

[0010] A first contact plug is connected to the lead-out portion;

[0011] The second contact plug is connected to the second word line layer.

[0012] In some embodiments, the substrate includes at least one active region, the word line structure passes through at least the active region, the active region includes a doped region along a third direction, the doped region is located on both sides of the word line structure, the third direction is parallel to the surface of the substrate and intersects the first direction, and the doping type of the doped region is either P-type or N-type.

[0013] In some embodiments, when the doping type of the doped region is N-type, the work function of the second word line layer is in the range of 3.7 eV to 4.35 eV; when the doping type of the doped region is P-type, the work function of the second word line layer is in the range of 4.75 eV to 5.45 eV.

[0014] In some embodiments, along the second direction, the ratio of the height of the second word line layer to the height of the first word line layer is between 1 / 3 and 1 / 2.

[0015] In some embodiments, the thickness of the spacer layer ranges from 3 nm to 10 nm.

[0016] In some embodiments, when the doping type of the doped region is N-type, the material of the first word line layer includes titanium nitride, wherein...

[0017] The material of the second word line layer includes N-type doped polysilicon; and / or,

[0018] The material of the second word line layer includes doped titanium nitride and / or doped tungsten, wherein the doping element in the doped titanium nitride includes at least one of lanthanum, niobium, and gallium, and the doping element in the doped tungsten includes at least one of lanthanum, niobium, and gallium; and / or,

[0019] The material of the second word line layer includes at least one of lanthanum, niobium, and gallium; and / or,

[0020] The second word line layer includes a first sub-layer and a second sub-layer. The first sub-layer is located on the spacer layer and, along the third direction, has a U-shaped cross-section. The bottom of the U-shaped structure covers the surface of the spacer layer, and the sidewalls of the U-shaped structure cover the sidewalls of the upper region of the active region. The second sub-layer covers the surface of the first sub-layer and fills the internal region of the U-shaped structure. The material of the first sub-layer includes at least one of lanthanum, niobium, gallium, lanthanum oxide, niobium oxide, and gallium oxide. The material of the second sub-layer includes titanium nitride.

[0021] In some embodiments, when the material of the second word line layer is doped titanium nitride and / or doped tungsten, the atomic percentage of the doping element ranges from 10% to 50%.

[0022] In some embodiments, the substrate includes at least one active region, the word line structure passes through at least the active region, and the word line structure further includes a first gate oxide layer and a second gate oxide layer, wherein...

[0023] The first gate oxide layer covers the bottom and sidewalls of the first word line layer and is located between the active region and the first word line layer;

[0024] The second gate oxide layer covers the sidewalls and bottom of the second word line layer. The second gate oxide layer covering the sidewalls of the second word line layer is located between the second word line layer and the active region. The second gate oxide layer covering the bottom of the second word line layer is located between the second word line layer and the first word line layer. The portion of the second gate oxide layer located between the first word line layer and the second word line layer in the second direction constitutes the spacer layer.

[0025] In some embodiments, if a programming operation is performed, a first voltage applied to the first word line layer is equal to a second voltage applied to the second word line layer, and the first voltage and the second voltage are equal to the drive voltage of the word line structure required when the programming operation is performed; and / or,

[0026] If the word line structure is not selected, the voltage applied to the first word line layer is different from the voltage applied to the second word line layer.

[0027] This disclosure also provides a method for fabricating a semiconductor structure, the method comprising:

[0028] Provide substrate;

[0029] A word line structure is formed on the substrate, the word line structure extends along a first direction, and the word line structure includes a first word line layer, a second word line layer, and a spacer layer located between the first word line layer and the second word line layer arranged from bottom to top along a second direction;

[0030] Wherein, the first direction is parallel to the surface of the substrate, the second direction is parallel to the thickness direction of the substrate, and the work function of the second word line layer is different from that of the first word line layer.

[0031] In some embodiments, forming the word line structure includes:

[0032] The substrate is etched to form a first word trench extending along the first direction on the substrate;

[0033] A first character line material layer is formed, and the first character line material layer fills the first character line groove;

[0034] A portion of the first letter line material layer located within the first letter line groove is removed to form a second letter line groove, and the remaining at least portion of the first letter line material layer constitutes the first letter line layer, with at least a portion of the first letter line layer located below the second letter line groove;

[0035] A spacer material layer is formed, the spacer material layer being located on at least a portion of the top surface of the first letter bar layer and covering the sidewalls and bottom of the second letter bar groove;

[0036] A second letter bar layer is formed, which covers the surface of the spacer material layer and fills at least a portion of the area of ​​the second letter bar groove that is not covered by the spacer material layer; wherein, along the second direction, the portion of the spacer material layer located between the first letter bar layer and the second letter bar layer constitutes the spacer layer.

[0037] In some embodiments, forming the word line structure further includes: after forming the first word line trench and before forming the first word line material layer, forming a gate oxide material layer, the gate oxide material layer covering the sidewalls and bottom of the first word line trench;

[0038] In the same step of removing part of the first word line material layer or after removing part of the first word line material layer and before forming the spacer material layer, at least a portion of the thickness of the portion of the gate oxide material layer not covered by the sidewalls of the first word line layer is removed, and the gate oxide material layer covering the bottom and sidewalls of the first word line layer constitutes the first gate oxide layer.

[0039] The gate oxide material layer located on the sidewall of the second word line trench and the spacer material layer together constitute the second gate oxide layer, and the thickness of at least a portion of the second gate oxide layer located on the sidewall of the second word line layer is greater than the thickness of the first gate oxide layer located on the sidewall of the first word line layer.

[0040] In some embodiments, along the first direction, the first word line layer includes a first end, the second word line layer includes a second end, the first end and the second end are located on the same side of the substrate, and along the first direction, the sidewall of the first end of the first word line layer protrudes outward relative to the sidewall of the second end of the second word line layer.

[0041] The removal of a portion of the first character line material layer located within the first character line groove includes:

[0042] A portion of the first character line material layer is removed, and the remaining first character line material layer includes a portion covering the lower region of the first character line groove, which constitutes the first character line layer. The remaining first character line material layer also includes a portion located above the first end of the first character line layer, which constitutes a lead-out portion. The lead-out portion extends along the second direction and is connected to the first character line layer.

[0043] After forming the second word line layer, the preparation method further includes:

[0044] A first contact plug is formed, and the first contact plug is connected to the lead-out portion;

[0045] A second contact plug is formed, and the second contact plug is connected to the second word line layer.

[0046] The semiconductor structure and its fabrication method provided in this disclosure include: a substrate; a word line structure located on the substrate and extending along a first direction, the word line structure including a first word line layer, a second word line layer, and a spacer layer located between the first word line layer and the second word line layer arranged from bottom to top along a second direction; wherein the first direction is parallel to the surface of the substrate, the second direction is parallel to the thickness direction of the substrate, and the work function of the second word line layer is different from that of the first word line layer.

[0047] In the semiconductor structure of this disclosure embodiment, the word line structure includes a first word line layer and a second word line layer arranged from bottom to top. This allows the process of applying voltage to the two word line layers to be set independently, providing high flexibility. Furthermore, the different work functions of the first and second word line layers allow for flexible selection of their work functions as needed. For example, the work function of the second word line layer can be selected based on the requirement to reduce the voltage applied to the second word line layer when the transistor structure is turned off, thus choosing a suitable material type. By setting the work function of the second word line layer, the threshold voltage for transistor structure turn-off can be adjusted. By controlling the voltage applied to the second word line layer, the gate-induced drain leakage (GIDL) current of the semiconductor structure can be effectively reduced, effectively improving the GIDL phenomenon in the semiconductor structure. This can increase the data retention time in the memory cells of the semiconductor structure, improve fault tolerance, and reduce power consumption.

[0048] Furthermore, as semiconductor structures shrink in size, filling word lines, which typically involve multiple material layers, becomes difficult, potentially leading to the use of single-layer word lines. Compared to situations where filling only a single layer of word line material exacerbates the "row hammer effect" and where using word line material with a passive work function increases GIDL, the embodiments of this disclosure, by configuring the word line structure as a first word line layer, a second word line layer, and a spacer layer located between the first and second word line layers arranged from bottom to top along a second direction, can meet the requirements of size reduction while allowing for selection of the material composition and voltage application of word line layers at different locations based on performance improvement needs, thereby effectively mitigating the aforementioned adverse effects.

[0049] Meanwhile, the work function of the material in the first word line layer can be set according to the needs of noise reduction, which helps to reduce the possibility of bit flipping in surrounding memory cells caused by repeated activation of a certain row of memory cells, that is, to reduce the "row hammer effect". The first word line layer and the second word line layer work together and cooperate with each other to improve the electrical performance stability and reliability of the semiconductor structure.

[0050] Details of one or more embodiments of this disclosure are set forth in the following drawings and description. Other features and advantages of this disclosure will become apparent from the specification and drawings. Attached Figure Description

[0051] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 A detailed cross-sectional view of a semiconductor structure taken along one direction, as provided in an embodiment of this disclosure;

[0053] Figure 2 A detailed cross-sectional view taken along one direction for another semiconductor structure provided in an embodiment of this disclosure;

[0054] Figure 3 for Figure 2 The structure shown is a detailed cross-sectional view taken in another direction in one embodiment.

[0055] Figure 4 for Figure 2 The structure shown is a detailed cross-sectional view taken in another embodiment along another direction;

[0056] Figure 5A schematic diagram illustrating the relationship between the magnitude of the GIDL leakage current and the applied voltage of the word line structure in a semiconductor structure provided in this embodiment of the disclosure;

[0057] Figure 6 A flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure;

[0058] Figure 7 This is one of the schematic diagrams of a semiconductor structure during the fabrication process provided in an embodiment of this disclosure;

[0059] Figure 8 A second schematic diagram of the semiconductor structure during the fabrication process provided in an embodiment of this disclosure;

[0060] Figure 9 This is the third schematic diagram of the semiconductor structure during the fabrication process according to an embodiment of the present disclosure; wherein, Figure 9 Figure (1) is a cross-sectional view of the semiconductor structure provided in this embodiment, taken along one direction during the fabrication process. Figure 9 Figure (2) is a cross-sectional view of the semiconductor structure provided in this embodiment of the present disclosure, taken along another direction during the fabrication process;

[0061] Figure 10 Fourth schematic diagram of the semiconductor structure during the fabrication process provided in one embodiment of this disclosure; Figure 10 Figure (1) is a cross-sectional view of the semiconductor structure provided in this embodiment, taken along one direction during the fabrication process. Figure 10 Figure (2) is a cross-sectional view of the semiconductor structure provided in this embodiment of the present disclosure, taken along another direction during the fabrication process;

[0062] Figure 11 Fifth schematic diagram of the semiconductor structure during the fabrication process provided in one embodiment of this disclosure; Figure 11 Figure (1) is a cross-sectional view of the semiconductor structure provided in this embodiment, taken along one direction during the fabrication process. Figure 11 Figure (2) is a cross-sectional view of the semiconductor structure provided in this embodiment of the present disclosure, taken along another direction during the fabrication process;

[0063] Figure 12 This is the sixth schematic diagram of the semiconductor structure during the fabrication process provided in one embodiment of the present disclosure; Figure 12 Figure (1) is a cross-sectional view of the semiconductor structure provided in this embodiment, taken along one direction during the fabrication process. Figure 12 Figure (2) is a cross-sectional view of the semiconductor structure provided in this embodiment of the present disclosure, taken along another direction during the fabrication process;

[0064] Figure 13 Seventh schematic diagram of the semiconductor structure during the fabrication process provided in an embodiment of this disclosure; Figure 13 Figure (1) is a cross-sectional view of the semiconductor structure provided in this embodiment, taken along one direction during the fabrication process. Figure 13 Figure (2) is a cross-sectional view of the semiconductor structure provided in this embodiment of the present disclosure, taken along another direction during the fabrication process;

[0065] Figure 14 Eighth schematic diagram of the semiconductor structure during the fabrication process provided in an embodiment of this disclosure; Figure 14 Figure (1) is a cross-sectional view of the semiconductor structure provided in this embodiment, taken along one direction during the fabrication process. Figure 14 Figure (2) is a cross-sectional view of the semiconductor structure provided in this embodiment of the present disclosure, taken along another direction during the fabrication process;

[0066] Figure 15 This is one of the schematic diagrams of the semiconductor structure during the fabrication process provided in another embodiment of this disclosure;

[0067] Figure 16 This is a second schematic diagram of the semiconductor structure during the fabrication process, provided as another embodiment of this disclosure. Detailed Implementation

[0068] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0069] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0070] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0071] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0072] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0073] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0074] In semiconductor devices such as DRAM, the memory cell is a crucial component. The memory cell further comprises transistor and capacitor structures. During data reading and writing, a suitable voltage is typically applied to activate the transistor structure, allowing the data stored in the capacitor to be retrieved. However, with the continuous miniaturization of semiconductor devices, the memory cell still suffers from inconsistent electrical performance during data reading and writing.

[0075] Based on this, the following technical solutions for embodiments of this disclosure are proposed:

[0076] This disclosure provides a semiconductor structure, which includes:

[0077] Substrate;

[0078] A word line structure is located on the substrate and extends along a first direction. The word line structure includes a first word line layer, a second word line layer, and a spacer layer located between the first word line layer and the second word line layer, arranged from bottom to top along a second direction.

[0079] Wherein, the first direction is parallel to the surface of the substrate, the second direction is parallel to the thickness direction of the substrate, and the work function of the second word line layer is different from that of the first word line layer.

[0080] In the semiconductor structure of this disclosure embodiment, the word line structure includes a first word line layer and a second word line layer arranged from bottom to top. This allows the process of applying voltage to the two word line layers to be set independently, providing high flexibility. Furthermore, the different work functions of the first and second word line layers allow for flexible selection of their work functions as needed. For example, the work function of the second word line layer can be selected based on the requirement to reduce the voltage applied to the second word line layer when the transistor structure is turned off, thus choosing a suitable material type. By setting the work function of the second word line layer, the threshold voltage for transistor structure turn-off can be adjusted. By controlling the voltage applied to the second word line layer, the gate-induced drain leakage (GIDL) current of the semiconductor structure can be effectively reduced, effectively improving the GIDL phenomenon in the semiconductor structure. This can increase the data retention time in the memory cells of the semiconductor structure, improve fault tolerance, and reduce power consumption.

[0081] Furthermore, as semiconductor structures shrink in size, filling word lines, which typically involve multiple material layers, becomes difficult, potentially leading to the use of single-layer word lines. Compared to situations where filling only a single layer of word line material exacerbates the "row hammer effect" and where using word line material with a passive work function increases GIDL, the embodiments of this disclosure, by configuring the word line structure as a first word line layer, a second word line layer, and a spacer layer located between the first and second word line layers arranged from bottom to top along a second direction, can meet the requirements of size reduction while allowing for selection of the material composition and voltage application of word line layers at different locations based on performance improvement needs, thereby effectively mitigating the aforementioned adverse effects.

[0082] Meanwhile, the work function of the material in the first word line layer can be set according to the needs of noise reduction, which helps to reduce the possibility of bit flipping in surrounding memory cells caused by repeated activation of a certain row of memory cells, that is, to reduce the "row hammer effect". The first word line layer and the second word line layer work together and cooperate with each other to improve the electrical performance stability and reliability of the semiconductor structure.

[0083] To make the above-mentioned objects, features, and advantages of this disclosure more apparent and understandable, the specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. In describing the embodiments of this disclosure in detail, for ease of explanation, the schematic diagrams may be partially enlarged without adhering to general proportions, and the schematic diagrams are merely examples and should not limit the scope of protection of this disclosure.

[0084] Figure 1 A detailed cross-sectional view of a semiconductor structure taken along one direction, as provided in an embodiment of this disclosure; Figure 2 A detailed cross-sectional view taken along one direction for another semiconductor structure provided in an embodiment of this disclosure; Figure 3 and Figure 4 for Figure 2 The structure shown is a detailed cross-sectional view taken in another direction in a different embodiment. Figure 5 This is a schematic diagram illustrating the relationship between the magnitude of the GIDL leakage current and the applied voltage of the word line structure in the semiconductor structure provided in this embodiment of the disclosure.

[0085] The semiconductor structure provided in the embodiments of this disclosure will now be described in further detail with reference to the accompanying drawings.

[0086] like Figures 1 to 4 As shown, the semiconductor structure includes:

[0087] Substrate 10;

[0088] The word line structure WL is located on the substrate 10 and extends along a first direction. The word line structure WL includes a first word line layer WL1, a second word line layer WL2, and a spacer layer 131 located between the first word line layer WL1 and the second word line layer WL2 arranged from bottom to top along a second direction.

[0089] The first direction is parallel to the surface of the substrate 10, the second direction is parallel to the thickness direction of the substrate 10, and the work function of the second word line layer WL2 is different from that of the first word line layer WL1.

[0090] Understandably, as the size of semiconductor structures continues to shrink, materials with passive work functions struggle to improve electrical performance, such as reducing gate-induced drain leakage (GIDL) and mitigating row hammer effects (where repeated activation of a particular row of memory cells can cause bit flips in surrounding rows, leading to inaccurate data storage). However, in this embodiment, by splitting the word line structure into a first word line layer WL1 and a second word line layer WL2, independent control of the two word line layers can be achieved, providing favorable conditions for improving electrical performance, such as mitigating GIDL leakage and row hammer effects.

[0091] In some embodiments, along the second direction, the ratio of the height of the second word line layer WL2 to the height of the first word line layer WL1 is between 1 / 3 and 1 / 2 (including the endpoint values), for example, 0.35, 0.4, 0.45, etc.

[0092] In some embodiments, the thickness of the spacer layer 131 ranges from 3 nm to 10 nm (including the endpoint values), such as 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, etc.

[0093] In some embodiments, the thickness of the spacer layer 131 is 6 nm.

[0094] In some embodiments, the material of the spacer layer 131 may include, but is not limited to, a low dielectric constant material, such as an oxide, such as silicon oxide.

[0095] However, this is not the only limitation. In some embodiments, the material of the spacer layer 131 can also be a high dielectric constant material, such as aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), or zirconium silicon oxide (ZrSi). x O y Hafnium oxide (HfO2), Hafnium silicon oxide (HfS) ix O yHafnium silicon nitride oxide (HfSiON), hafnium zirconate (HfZrO4), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAl) x O y ), lanthanum hafnium oxide (LaHf) x O y ), Hafnium aluminum oxide (HfAl) x O y ) and / or praseodymium oxide (Pr2O3), etc.

[0096] In some embodiments, such as Figure 3 As shown, along the first direction, the first word line layer WL1 includes a first end D1, and the second word line layer WL2 includes a second end D2. The first end D1 and the second end D2 are located on the same side of the substrate 10, and along the first direction, the sidewall of the first end D1 of the first word line layer WL1 protrudes outward relative to the sidewall of the second end D2 of the second word line layer WL2.

[0097] Continue to refer to Figure 3 In some embodiments, the semiconductor structure further includes: lead-out portion A, which extends along a second direction and is located on the side where the first end D1 of the first word line layer WL1 is located, and lead-out portion A is connected to the first word line layer WL1;

[0098] The first contact plug C1 is connected to the lead-out portion A;

[0099] The second contact plug C2 is connected to the second word line layer WL2.

[0100] Understandably, the presence of lead-out section A reduces the difficulty of connecting the first word line layer WL1 and the first contact plug C1, and the height of the first contact plug C1 can be significantly reduced, which helps to reduce the difficulty and complexity of the process.

[0101] In some embodiments, the material of the lead-out portion A and the first word line layer WL1 may be the same, and the lead-out portion is in contact with the surface of the first end D1.

[0102] In some embodiments, the lead-out portion A and the first end D1 of the first word line layer WL1 are a continuous structure.

[0103] In actual operation, the material of the first word line layer WL1, the second word line layer WL2, and the spacer layer 131 can be filled with the material of the first word line layer WL1. Then, after performing a process to remove part of the material of the first word line layer WL1, the remaining material layer is "L" shaped. The material layer in the lower region constitutes the first word line layer WL1, and the material portion above the first end D1 of the first word line layer WL1 constitutes the lead-out portion A.

[0104] In other embodiments, such as Figure 4 As shown, when the semiconductor structure does not include the lead-out portion, the first contact plug C1 can pass through the second word line layer WL2 to reach the area where the first word line layer WL1 is located, so as to realize the connection between the first contact plug C1 and the first word line layer WL1.

[0105] exist Figure 4 In the embodiment shown, the first contact plug C1 can be formed by sequentially forming the materials constituting the first word line layer WL1 and the second word line layer WL2, and then by removing a portion of the materials of the first word line layer WL1 located at the first end D1 and the second word line layer WL2 located at the second end D2, and then filling with conductive material.

[0106] In some embodiments, the materials of the first contact plug C1 and the second contact plug C2 include, but are not limited to, polycrystalline silicon, metal silicides, conductive metals, conductive metal nitrides, and combinations thereof. Specifically, metal silicides may include, but are not limited to, cobalt silicide (CoSix); conductive metals may include, but are not limited to, tungsten (W); and conductive metal nitrides may include, but are not limited to, titanium nitride (TiN).

[0107] In some embodiments, the substrate 10 includes at least one active region AA, and the word line structure WL passes through at least the active region AA. The active region AA includes a doped region D along a third direction. The doped region D is located on both sides of the word line structure WL. The third direction is parallel to the surface of the substrate 10 and intersects with the first direction. The doping type of the doped region D is either P-type or N-type.

[0108] In some embodiments, the active region AA further includes a channel region (not shown) surrounding the word line structure WL and located between the word line structure WL and the substrate 10. Doped regions D are located on either side of the channel region (not shown) along a third-order upward direction.

[0109] In some embodiments, the channel region (not shown in the figure) can be either P-type doped or N-type doped. Accordingly, when the channel region (not shown in the figure) can be P-type, the doped region D can be N-type doped, and when the channel region (not shown in the figure) can be N-type, the doped region D can be P-type.

[0110] In some embodiments, the dopant atoms used to form an N-type doping effect may include, but are not limited to, phosphorus (P), arsenic (As) or antimony (Sb), one or a combination of other N-type dopant atoms; similarly, the dopant atoms used to form a P-type doping effect may include, but are not limited to, at least one or a combination of, boron, indium, other p-type dopant atoms.

[0111] In this embodiment, a portion of the word line structure WL and the active region AA can constitute a transistor structure. The portion of the word line structure WL covering the active region AA can function as a gate. The channel region (not shown in the figure) included in the active region AA can be used as a channel structure, and the doped region D included in the active region AA can be used as either a source or a drain. Since the channel region (not shown in the figure) and the doped region D have different doping types in the same transistor structure, a junction region is formed at the junction of the channel region (not shown in the figure) and the doped region.

[0112] When the transistor structure is NMOS, a large electric field can easily occur at the gate-drain overlap region due to various possible reasons when the transistor is in the off state, leading to severe band bending. If this band bending is not addressed and mitigated in time, current leakage can occur, known as gate-induced drain leakage (GIDL). This phenomenon increases the power consumption of the semiconductor structure, reduces the data retention capability of the memory cells, and affects the electrical performance stability and reliability of the semiconductor structure. Furthermore, as semiconductor structures continue to shrink in size, the filling performance of multiple materials used as word lines is challenged. Using only a single material type can easily reduce the performance of the final semiconductor structure. For example, in an NMOS structure, using only titanium nitride (TIN) as a word line is more likely to exacerbate the row hammer effect than using only tungsten (W). The row hammer effect can be understood as the tendency for repeated activation of a particular row of memory cells to cause bit flips in surrounding rows, resulting in inaccurate stored data.

[0113] It is understandable that when a product contains a PMOS structure and the PMOS is part of the memory cell, it can also be understood that when the transistor structure in the memory cell is a PMOS, the gate-induced drain leakage (GIDL) phenomenon is likely to occur near the drain region. Through research, the researchers have discovered that when the transistor structure is NMOS, if the work function of the word line structure WL near the junction region (i.e., the second word line layer WL2) is close to the conduction band energy level of the material contained in the active region AA, it can improve the band bending and reduce the leakage current value of gate-induced drain leakage (GIDL). This is because when the work function of the word line structure WL near the junction region is close to the conduction energy level of the material contained in the active region AA, it can effectively reduce the surface electric field intensity at the junction of the drain and the gate, reduce the gate's control over the channel region (not shown in the figure) and the drain junction region, and help reduce the surface electric field intensity, thereby effectively improving the band bending. It is equivalent to "flattening" the bent band, making it less likely for tunneling effects caused by band bending to occur, thus effectively reducing the leakage current value of gate-induced drain leakage (GIDL).

[0114] In some embodiments, when the doping type of the doped region D is N-type, the work function of the second word line layer WL2 ranges from 3.7 eV to 4.35 eV (inclusive), such as 3.8 eV, 3.9 eV, 4 eV, 4.1 eV, 4.2 eV, 4.3 eV, etc.; when the doping type of the doped region D is P-type, the work function of the second word line layer WL2 ranges from 4.75 eV to 5.45 eV (inclusive), such as 4.8 eV, 4.9 eV, 5 eV, 5.1 eV, 5.2 eV, 5.3 eV, 5.4 eV, etc.

[0115] Based on the above, it can be concluded that since the conduction band energy level of the active region AA in an NMOS structure is around 4 eV, selecting a material with a work function within this range for the second word line layer WL2 helps to improve gate-induced drain leakage (GIDL). For details, please refer to... Figure 5 V is applied to the drain electrode d Under the condition of a voltage of 1.5V, Figure 5 The data related to 1-WL represents the gate-induced drain leakage (GIDL) situation in the semiconductor structure when the work function in the word line structure is not adjusted. Figure 5The data related to 2-WL can be understood as the performance of gate-induced drain leakage (GIDL) in the semiconductor structure after adjusting the work function of the word line structure WL. It can be seen that after effectively adjusting the work function of the word line structure WL, the GIDL leakage phenomenon in the semiconductor structure is significantly reduced.

[0116] In some embodiments of NMOS, the work function of the second word line layer (WL) is appropriately configured to improve data retention capability, fault tolerance, and electrical performance stability, thereby reducing the probability of bit flips in the memory cell. Simultaneously, the work function of the first word line layer (WL) can be selected using a material with the largest possible work function. This helps to increase the threshold voltage of the transistor structure, thereby reducing the impact of noise on data in adjacent rows during repeated activation of a row, reducing bit flips, and thus mitigating row hammer effect. Through mutual cooperation, the two material layers contribute to improving data retention time, retention capability, and fault tolerance, thereby reducing bit flips in the memory cell and jointly improving the electrical performance stability and reliability of the semiconductor structure.

[0117] Furthermore, in products incorporating PMOS structures, where the PMOS is part of the memory cell, the researchers have discovered that when the transistor structure is PMOS, a larger work function of the word line structure WL near the junction region, i.e., the second word line layer WL2, can improve the leakage current value of gate-induced drain leakage (GIDL) due to band bending. This is because a larger work function of the word line structure WL near the junction region, i.e., the second word line layer WL2, helps to increase the threshold voltage, weakening the gate's control over the channel region. Consequently, the electric field in the drain junction region may weaken, effectively improving band bending and reducing the likelihood of tunneling. This is equivalent to "flattening" the bent band, making it less prone to tunneling due to band bending, thus effectively reducing the leakage current value of gate-induced drain leakage (GIDL).

[0118] Similarly, in the PMOS structure, due to the need to reduce the channel control capability, a material layer with a higher work function is required. Therefore, when the work function of the second word line layer WL2 can be selected within the above range, it helps to reduce the gate-induced drain leakage (GIDL) leakage.

[0119] In some embodiments, in PMOS, the material selection for the first word line layer WL1 can also be a material with a high work function, but it is not limited thereto. Since the second word line layer WL2 itself has a high work function, the material selection for the first word line layer WL1 can also be flexibly handled according to other performance improvement requirements, and no specific limitation is made here.

[0120] Furthermore, in any of the above embodiments, it is understood that even if the first word line layer WL1 is configured with a larger work function or other functional improvements based on performance enhancement requirements, its distance from the junction region is greater than that of the second word line layer WL2. This avoids the risk of worsening gate-induced drain leakage (GIDL) due to material selection factors such as a larger work function. Simultaneously, during operation, the two word line layers (first word line layer WL1 and second word line layer WL2) can be independently energized, which improves the flexibility of the control process.

[0121] In some embodiments, if a programming operation is performed, a first voltage applied to the first word line layer WL1 is equal to a second voltage applied to the second word line layer WL2, and the first voltage and the second voltage are equal to the drive voltage of the word line structure WL required when the programming operation is performed; and / or,

[0122] If the word line structure WL is unselected, the voltage applied to the first word line layer WL1 is different from the voltage applied to the second word line layer WL2. In some embodiments, when operating the transistor structure, taking NMOS as an example, the same voltage needs to be applied to the first word line layer WL1 and the second word line layer WL2 during the transistor turn-on process, for example, V. WL1 = V WL2 =V PP , where V PP This is the turn-on voltage for the word line structure, used to enable the transistor structure to turn on. When turning off the transistor structure, V can be used. WL2 =2V, V WL1 Applying a voltage of 0V helps reduce gate-induced drain leakage (GIDL).

[0123] In some embodiments, when the doping type of the doped region D is N-type, the material of the first word line layer WL1 includes titanium nitride, wherein...

[0124] The material of the second word line layer WL2 includes N-type doped polysilicon; and / or,

[0125] The material of the second word line layer WL2 includes doped titanium nitride and / or doped tungsten, wherein the doping element in the doped titanium nitride includes at least one of lanthanum, niobium, and gallium, and the doping element in the doped tungsten includes at least one of lanthanum, niobium, and gallium; and / or,

[0126] The material of the second word line layer WL2 includes at least one of lanthanum, niobium, and gallium; and / or,

[0127] like Figure 2 , Figure 3 and Figure 4 As shown, in some embodiments, the second word line layer WL2 includes a first sublayer 111 and a second sublayer 112. The first sublayer 111 is located on the spacer layer 131. Along the third direction, the cross-section of the first sublayer 111 is U-shaped. The bottom of the U-shaped structure covers the surface of the spacer layer 131, and the sidewalls of the U-shaped structure cover the sidewalls of the upper region of the active region AA. The second sublayer 112 covers the surface of the first sublayer 111 and fills the internal region of the U-shaped structure. The material of the first sublayer 111 includes at least one of lanthanum, niobium, gallium, lanthanum oxide, niobium oxide, and gallium oxide. The material of the second sublayer 112 includes titanium nitride.

[0128] Understandably, when the doping type of the doped region D is N-type, that is, when the transistor containing the doped region D is an NMOS structure, and the material of the second word line layer WL2 is doped polysilicon, doped titanium nitride, and / or doped tungsten, the work function value can be changed. For example, the work function of undoped titanium nitride (TIN) can be around 4.8 eV, which is a relatively large value, and the work function of undoped tungsten (W) is around 4.55 eV, which is also a relatively large value. The work function of the doped N-type polysilicon can be adjusted to around 4 eV (e.g., 4.02 eV). At the same time, the work function values ​​of doped titanium nitride and / or doped tungsten can be adjusted to lower values. Since the conduction band energy level of the material contained in the active region AA in the NMOS structure is around 4eV, when the second word line layer WL2 uses the aforementioned material, the work function of the second word line layer WL2 can be close to the conduction band energy level. This can reduce gate-induced drain leakage (GIDL) and thus increase the data retention time in the memory cell of the semiconductor structure, improve fault tolerance, and reduce power consumption.

[0129] In some embodiments, the work function of lanthanum (La)-doped polycrystalline silicon can be around 4 eV. In addition, this doping method can also effectively reduce the resistance of the material.

[0130] Understandably, when the second word line layer WL2 contains two sub-layers and has a U-shaped cross-section, it can effectively increase the length of the channel region (not shown in the figure) located around the first sub-layer 111 and the second sub-layer 112. This is beneficial to increasing the control capability of the word line material over the channel region (not shown in the figure), thereby reducing leakage current and improving data retention time.

[0131] In addition, according to the appendix Figure 1 To be continued Figure 4 As can be seen, the U-shaped cross-section of the two word line layers in the word line structure WL provided in this embodiment can also increase the control capability of the channel region (not shown in the figure) and increase the length of the channel region (not shown in the figure), thereby achieving the purpose of reducing leakage current and improving data retention time.

[0132] In some embodiments where the second word line layer WL2 comprises two sub-layers, the thickness of both the first and second sub-layers can be between 1 and 5 nm (inclusive), such as 1.5 nm, 2 nm, 2.5 nm, 3 nm, 3.5 nm, 4 nm, 4.5 nm, etc. The thickness of the two word line layers can be the same, but is not limited to this and can be flexibly set.

[0133] In some embodiments, the first sublayer 111 may be thicker than the second sublayer 112. For example, when the former is about 1 nm thicker than the latter, the resulting structure can have good performance.

[0134] In some embodiments, when the material of the second word line layer WL2 is doped titanium nitride and / or doped tungsten, the atomic percentage of the doping element ranges from 10% to 50% (including endpoint values), such as 15%, 20%, 25%, 30%, 35%, 40%, 45%, etc.

[0135] In some embodiments, the substrate 10 includes at least one active region AA, the word line structure WL passes through at least the active region AA, and the word line structure WL further includes a first gate oxide layer L1 and a second gate oxide layer L2, wherein...

[0136] The first gate oxide layer L1 covers the bottom and sidewalls of the first word line layer WL1 and is located between the active region AA and the first word line layer WL1.

[0137] The second gate oxide layer L2 covers the sidewalls and bottom of the second word line layer WL2. The second gate oxide layer L2 covering the sidewalls of the second word line layer WL2 is located between the second word line layer WL2 and the active region AA. The second gate oxide layer L2 covering the bottom of the second word line layer WL2 is located between the second word line layer WL2 and the first word line layer WL1. The portion of the second gate oxide layer L2 located in the second direction between the first word line layer WL1 and the second word line layer WL2 constitutes the spacer layer 131.

[0138] In some embodiments, the second gate oxide layer L2 consists of two parts: a spacer material layer 13 and a first sub-part 122 covering the sidewall of the second word line layer WL2. A portion of the spacer material layer 13 is located between the first sub-part 122 and the second word line layer WL2, and surrounds the sidewall and bottom of the second word line layer WL2. The portion of the spacer material layer 13 located at the bottom of the second word line layer WL2 constitutes a spacer layer 131. The first sub-part 122 and the second sub-part 121, which is the first gate oxide layer L1, are a continuous structure. The first sub-part 122 and the second sub-part 121 are arranged from top to bottom.

[0139] In some embodiments, the thickness of the first gate oxide layer L1 can be between 3 and 8 nm (including the endpoint values), such as 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, etc., and the thickness of the second gate oxide layer L2 can be between 3 and 8 nm (including the endpoint values), such as 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, etc.

[0140] In some embodiments, the thickness of at least a portion of the second gate oxide layer L2 may be greater than the thickness of the first gate oxide layer L1.

[0141] In some specific embodiments, such as Figure 3 As shown, in the embodiment where the semiconductor structure includes lead-out portion A, except for the second gate oxide layer L2 located between lead-out portion A and the second word line layer WL2 along the first direction, the thickness of the second gate oxide layer L2 located on the sidewall of the second word line layer WL2 at other locations is greater than the thickness of the first gate oxide layer L1 located on the sidewall of the first word line layer WL1.

[0142] In some specific embodiments, such as Figure 2 and Figure 4 As shown, in embodiments where the semiconductor structure does not include lead-out portion A, the thickness of the second gate oxide layer L2 located on the sidewall of the second word line layer WL2 is greater than the thickness of the first gate oxide layer L1 located on the sidewall of the first word line layer WL1.

[0143] In some embodiments, at locations where the size of the second gate oxide layer L2 is larger than that of the first gate oxide layer L1, the size difference between the second gate oxide layer L2 and the first gate oxide layer L1 can be between 0.5 and 1 nm (including the endpoint value), for example, 0.6 nm, 0.7 nm, 0.8 nm, 0.9 nm, 1 nm, etc.

[0144] It should be noted that, Figure 1 and Figure 2 The structure shown may include lead-out portion A or may not include lead-out portion A. The above figures may be used as an auxiliary illustration to illustrate the dimensional relationship between the first gate oxide layer and the second gate oxide layer when viewed from different directions. They are merely illustrative and do not constitute a limitation.

[0145] In some embodiments, the first gate oxide layer L1 and the second gate oxide layer L2 may be made of the same material, for example, either a low dielectric constant or a high dielectric constant. For details, please refer to the aforementioned material description of the spacer layer 131, which will not be repeated here.

[0146] In some embodiments, the semiconductor structure further includes a capping layer 14 located above the word line structure WL, which may be made of a nitride, such as silicon nitride, to protect the word line structure WL.

[0147] In some embodiments, along the second direction, the sum of all dimensions including the depth dimension of the first word line layer WL1, the depth dimension of the second word line layer WL2, the thickness dimension of the portion of the first gate oxide layer L1 located at the bottom of the first word line layer WL1 along the second direction, and the thickness dimension of the spacer layer is defined as the first depth. The ratio of the depth of the second word line layer WL2 to the first depth ranges from 15% to 35% (including endpoint values), such as 20%, 25%, 30%, etc. In this way, the function of the second word line layer WL2 can be effectively utilized.

[0148] In some embodiments, the sum of the thickness of the cap layer 14 in the second direction and the first depth is defined as the second depth, and the ratio of the first depth to the second depth is approximately 90%. This allows the word line structure WL to have good performance. This disclosure also provides a method for fabricating a semiconductor structure, such as... Figure 6 As shown, the preparation method includes:

[0149] Step S101: Provide a substrate;

[0150] Step S102: Form a word line structure on the substrate. The word line structure extends along a first direction and includes a first word line layer, a second word line layer, and a spacer layer located between the first word line layer and the second word line layer, arranged from bottom to top along a second direction.

[0151] The first direction is parallel to the surface of the substrate, the second direction is parallel to the thickness direction of the substrate, and the work function of the second word line layer is different from that of the first word line layer.

[0152] Figures 7 to 14 This is a schematic diagram of the semiconductor structure during the fabrication process according to an embodiment of the present disclosure; wherein, Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 as well as Figure 14 Figure (1) is a cross-sectional view of the semiconductor structure provided in this embodiment, taken along one direction during the fabrication process. Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 as well as Figure 14 Figure (2) is a cross-sectional view of the semiconductor structure provided in this embodiment of the present disclosure, taken along another direction during the fabrication process; Figure 15 and Figure 16 This is a schematic diagram illustrating the fabrication process of a semiconductor structure according to another embodiment of this disclosure. The fabrication method of the semiconductor structure provided in this embodiment will now be described in further detail with reference to the accompanying drawings.

[0153] First, execute step S101, as follows: Figure 7 As shown, a substrate 10 is provided.

[0154] Here, substrate 10 can be a semiconductor substrate; the material of the semiconductor substrate specifically includes elemental semiconductor materials (e.g., silicon (Si) substrates, germanium (Ge) substrates, etc.), or III-V compound semiconductor materials (e.g., gallium nitride (GaN) substrates, gallium arsenide (GaAs) substrates, indium phosphide (InP) substrates, etc.), or II-VI compound semiconductor materials, or organic semiconductor materials, or other semiconductor materials known in the art. In a specific embodiment, substrate 10 is a silicon substrate.

[0155] In this embodiment of the disclosure, the first direction intersects with the third direction and is parallel to the plane of the substrate 10.

[0156] In some embodiments, the first direction may be perpendicular to a third direction.

[0157] Then, proceed with step S102, as follows: Figures 7 to 14 ,as well as Figure 15 and Figure 16 As shown, a word line structure WL is formed on the substrate 10. The word line structure WL extends along a first direction and includes a first word line layer WL1, a second word line layer WL2, and a spacer layer 131 located between the first word line layer WL1 and the second word line layer WL2 arranged from bottom to top along a second direction.

[0158] The first direction is parallel to the surface of the substrate 10, the second direction is parallel to the thickness direction of the substrate 10, and the work function of the second word line layer WL2 is different from that of the first word line layer WL1.

[0159] In some embodiments, forming a word line structure WL includes:

[0160] Etching substrate 10 to form a first word line trench T1 extending along a first direction on substrate 10 (see details). Figure 7 );

[0161] A first character line material layer WL1a is formed, and the first character line material layer WL1a fills the first character line groove T1 (see details). Figure 9 (Figures (1) and (2) in the text).

[0162] A portion of the first letter line material layer WL1a located within the first letter line groove T1 is removed to form the second letter line groove T2. The remaining at least a portion of the first letter line material layer WL1a constitutes the first letter line layer WL1, which is located below the second letter line groove T2 (see details). Figure 10 (Figures (1) and (2) in the text).

[0163] A spacer material layer 13 is formed, which is located on at least a portion of the top surface of the first letter bar layer WL1 and covers the sidewalls and bottom of the second letter bar groove T2 (see details). Figure 12 (Figures (1) and (2) in the text).

[0164] A second word line layer WL2 is formed, which covers the surface of the spacer material layer 13 and fills at least a portion of the area of ​​the second word line groove T2 not covered by the spacer material layer 13; wherein, along the second direction, the portion of the spacer material layer 13 located between the first word line layer WL1 and the second word line layer WL2 constitutes a spacer layer 131 (see details). Figure 13 Figures (1) and (2) in the middle and Figure 15 ).

[0165] In this embodiment of the disclosure, by splitting the word line structure into a first word line layer WL1 and a second word line layer WL2, independent control of the two word line layers can be achieved, which is beneficial to improving electrical performance, such as reducing gate-induced drain leakage (GIDL) and improving the horizontal hammer effect.

[0166] In some embodiments, along the second direction, the ratio of the height of the second word line layer WL2 to the height of the first word line layer WL1 is between 1 / 3 and 1 / 2 (including the endpoint values), for example, 0.35, 0.4, 0.45, etc.

[0167] In some embodiments, when the doping type of the doped region D is N-type, the work function of the second word line layer WL2 ranges from 3.7 eV to 4.35 eV (inclusive), such as 3.8 eV, 3.9 eV, 4 eV, 4.1 eV, 4.2 eV, 4.3 eV, etc.; when the doping type of the doped region D is P-type, the work function of the second word line layer WL2 ranges from 4.75 eV to 5.45 eV (inclusive), such as 4.8 eV, 4.9 eV, 5 eV, 5.1 eV, 5.2 eV, 5.3 eV, 5.4 eV, etc. In some embodiments, when the doping type of the doped region D is P-type, the material of the second word line layer WL2 can be selected to be a material with a larger work function, which is beneficial to reducing gate-induced drain leakage (GIDL).

[0168] In some embodiments of NMOS, the work function of the second word line layer (WL) is appropriately configured to improve data retention capability, fault tolerance, and electrical performance stability, thereby reducing the probability of bit flips in the memory cell. Simultaneously, the work function of the first word line layer (WL) can be selected using a material with the largest possible work function. This helps to increase the threshold voltage of the transistor structure, thereby reducing the impact of noise on data in adjacent rows during repeated activation of a row, reducing bit flips, and thus mitigating row hammer effect. Through mutual cooperation, the two material layers contribute to improving data retention time, retention capability, and fault tolerance, thereby reducing bit flips in the memory cell and jointly improving the electrical performance stability and reliability of the semiconductor structure.

[0169] Similarly, in PMOS, and in products incorporating PMOS structures where the PMOS is part of the memory cell, the researchers have found that when the transistor structure is PMOS, a larger work function in the word line structure WL near the junction region, i.e., the second word line layer WL2, can improve the leakage current value of gate-induced drain leakage (GIDL) due to band bending. Furthermore, in PMOS structures, materials with high work functions can be used for the first word line layer WL1, but this is not a limitation. Since the second word line layer WL2 itself has a high work function, the material selection for the first word line layer WL1 can be flexibly handled according to other performance improvement requirements, and is not specifically limited here.

[0170] Furthermore, in the embodiments disclosed herein, it is understood that even if the first word line layer WL1 is configured with a larger work function or other functional improvements based on performance enhancement requirements, its distance from the junction region is greater than that of the second word line layer WL2. This avoids the risk of worsening gate-induced drain leakage (GIDL) due to material selection factors such as a larger work function. Simultaneously, during operation, the two word line layers (first word line layer WL1 and second word line layer WL2) can be independently voltage-applied, which improves the flexibility of the control process.

[0171] In some embodiments, forming the word line structure WL further includes: after forming the first word line trench T1 and before forming the first word line material layer WL1a, forming a gate oxide material layer L1a, wherein the gate oxide material layer L1a covers the sidewalls and bottom of the first word line trench T1 (see details). Figure 8 );

[0172] In the same step of removing a portion of the first word line material layer WL1a, or after removing a portion of the first word line material layer WL1a and before forming the spacer material layer 13, at least a portion of the thickness of the gate oxide material layer L1a not covered by the sidewalls of the first word line layer WL1 is removed. The gate oxide material layer L1a covering the bottom and sidewalls of the first word line layer WL1 constitutes the first gate oxide layer L1 (see details). Figure 11 (Figures (1) and (2) in the text).

[0173] Among them, such as Figure 12 As shown in Figures (1) and (2), the gate oxide material layer L1a located on the sidewall of the second word line trench T2 and the spacer material layer 13 together constitute the second gate oxide layer L2, and the thickness of at least part of the second gate oxide layer L2 located on the sidewall of the second word line layer WL2 is greater than the thickness of the first gate oxide layer L1 located on the sidewall of the first word line layer WL1.

[0174] Here, the relationship between the thickness of the second gate oxide layer L2 and the thickness of the first gate oxide layer L1 may include different situations in different embodiments, which will be explained in detail later with reference to the accompanying drawings.

[0175] Here, after removing at least a portion of the thickness of the portion of the gate oxide material layer L1a not covered by the sidewall of the first word line layer WL1, the gate oxide material layer L1a can be divided into a second sub-part 121 located in the lower region of the first word line trench T1, and a first sub-part 122 located in the upper region of the first word line trench T1 where a thinning process is performed. The second sub-part 121 can constitute the first gate oxide layer L1, and the first sub-part 122 located on the sidewall of the second word line trench T2 can together with the spacer material layer 13 constitute the second gate oxide layer L2.

[0176] In some embodiments, the second gate oxide layer L2 consists of two parts: a first sub-part 122 and a spacer material layer 13, wherein the portion of the spacer material layer 13 located at the bottom of the second word line layer WL2 constitutes a spacer layer 131, and the first sub-part 122 and the second sub-part 121, which is the first gate oxide layer L1, are a continuous structure, and the first sub-part 122 and the second sub-part 121 are arranged from top to bottom.

[0177] In some embodiments, the thickness of the first gate oxide layer L1 can be between 3 and 8 nm (including the endpoint values), such as 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, etc., and the thickness of the second gate oxide layer L2 can be between 3 and 8 nm (including the endpoint values), such as 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, etc.

[0178] In some embodiments, the thickness of at least a portion of the second gate oxide layer L2 may be greater than the thickness of the first gate oxide layer L1.

[0179] In this embodiment, such as Figure 13 As shown in Figures (1) and (2), in the embodiment where the semiconductor structure includes lead-out portion A, except for the second gate oxide layer L2 located between lead-out portion A and second word line layer WL2 along the first direction, the thickness of the second gate oxide layer L2 located on the sidewall of the second word line layer WL2 at other locations is greater than the thickness of the first gate oxide layer L1 located on the sidewall of the first word line layer WL1.

[0180] In some embodiments, such as Figure 15 As shown, in embodiments where the semiconductor structure does not include lead-out portion A, the thickness of the second gate oxide layer L2 located on the sidewall of the second word line layer WL2 is greater than the thickness of the first gate oxide layer L1 located on the sidewall of the first word line layer WL1.

[0181] In some embodiments, at locations where the size of the second gate oxide layer L2 is larger than that of the first gate oxide layer L1, the size difference between the second gate oxide layer L2 and the first gate oxide layer L1 can be between 0.5 and 1 nm (including the endpoint value), for example, 0.6 nm, 0.7 nm, 0.8 nm, 0.9 nm, 1 nm, etc.

[0182] In some embodiments, along a first direction, a first word line layer WL1 includes a first end D1, and a second word line layer WL2 includes a second end D2. The first end D1 and the second end D2 are located on the same side of the substrate 10, and along the first direction, the sidewall of the first end D1 of the first word line layer WL1 protrudes outward relative to the sidewall of the second end D2 of the second word line layer WL2.

[0183] The removal of a portion of the first word line material layer WL1a located within the first word line groove T1 includes:

[0184] Continue to refer to Figure 10 In Figures (1) and (2), after removing part of the first word line material layer WL1a, the remaining first word line material layer WL1a includes a portion covering the lower region of the first word line groove T1. This portion of the first word line material layer WL1a constitutes the first word line layer WL1. The remaining first word line material layer WL1a also includes a portion located above the first end D1 of the first word line layer WL1. This portion of the first word line material layer WL1a constitutes the lead-out portion A. The lead-out portion A extends along the second direction and is connected to the first word line layer WL1.

[0185] After forming the second word line layer WL2, the preparation method also includes:

[0186] like Figure 14 As shown in Figures (1) and (2), a first contact plug C1 is formed, and the first contact plug C1 is connected to the lead-out portion A;

[0187] A second contact plug C2 is formed, and the second contact plug C2 is connected to the second word line layer WL2.

[0188] Understandably, the presence of the lead-out portion A reduces the connection difficulty between the first word line layer WL1 and the first contact plug C1, allowing for a significant reduction in the height of the first contact plug C1, which helps to reduce manufacturing difficulty and complexity. In other embodiments, such as Figure 15 and Figure 16 As shown, along the first direction, the first word line layer WL1 includes a first end D1, forming a second word line layer WL2, which includes:

[0189] An initial second word line layer WL2a is formed, which fills at least a portion of the area of ​​the second word line trench T2 that is not covered by the spacer material layer 13; the initial second word line layer WL2a includes an initial second end D2a, and the initial second end D2a of the initial second word line layer WL2a and the first end D1 of the first word line layer WL1 are located on the same side of the substrate 10.

[0190] At least a portion of the initial second word line layer WL2a and a portion of the spacer material layer 13 located on the side where the initial second end D2a is located are removed to form a via structure (not shown in the figure) that exposes the first word line layer WL1. The remaining initial second word line layer WL2a constitutes the second word line layer WL2. The end of the second word line layer WL2 located on the same side of the substrate 10 as the first end D1 of the first word line layer WL1 is defined as the second end D2.

[0191] An insulating material L3 and a conductive material are sequentially filled into a through-hole structure (not shown) to form a first contact plug C1. The first contact plug C1 extends along a second direction and is connected to the first word line layer WL1.

[0192] In this embodiment, the step of forming the second contact plug C2 can be combined with... Figure 14 The method is the same as in the previous section, so it will not be repeated here.

[0193] In this embodiment, the method of obtaining the contact plug directly by etching and filling without forming the lead-out portion A helps to simplify the process of etching the first word line material layer WL1a to form the first word line layer WL1, thereby improving production efficiency.

[0194] In this embodiment, such as Figure 2 and Figure 15 As shown, in an embodiment where the semiconductor structure does not include lead-out portion A, the thickness of the second gate oxide layer L2 located on the sidewall of the second word line layer WL2 is greater than the thickness of the first gate oxide layer L1 located on the sidewall of the first word line layer WL1, both in the first direction and in the third direction.

[0195] Furthermore, in this embodiment, the thicknesses of the first gate oxide layer L1 and the second gate oxide layer L2 can be the same as those of the second gate oxide layer L2. Figure 13 The embodiment shown is the same, and the size of the second gate oxide layer L2 can be larger than that of the first gate oxide layer L1. The thickness difference between the two gate oxide layers can also be referenced. Figure 13 The content of the illustrated embodiment. It should be noted that... Figure 1 and Figure 2 The structure shown may include lead-out portion A or may not include lead-out portion A. The above figures may be used as an auxiliary illustration to illustrate the dimensional relationship between the first gate oxide layer and the second gate oxide layer when viewed from different directions. They are merely illustrative and do not constitute a limitation.

[0196] The technical features described in the embodiments provided in this disclosure can be arbitrarily combined without conflict.

[0197] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a substrate; a word line structure located on the substrate and extending along a first direction, the word line structure comprising a first word line layer, a second word line layer and a spacer layer located between the first word line layer and the second word line layer arranged from bottom to top along a second direction; along the first direction, the first word line layer comprises a first end, the second word line layer comprises a second end, the first end and the second end are located on the same side of the substrate, and along the first direction, the sidewall of the first end of the first word line layer protrudes outward relative to the sidewall of the second end of the second word line layer; a lead-out portion extending along the second direction and located on the side where the first end of the first word line layer is located, the lead-out portion being connected with the first word line layer; a first contact plug connected with the lead-out portion; a second contact plug connected with the second word line layer; wherein the first direction is parallel to the surface of the substrate, the second direction is parallel to the thickness direction of the substrate, and the work function of the second word line layer is different from that of the first word line layer.

2. The semiconductor structure of claim 1, wherein, The substrate comprises at least one active region, the word line structure at least passes through the active region, the active region comprises a doped region, along a third direction, the doped region is located on both sides of the word line structure, the third direction is parallel to the surface of the substrate and intersects with the first direction, and the doping type of the doped region is one of P type or N type.

3. The semiconductor structure of claim 2, wherein, When the doping type of the doped region is N type, the work function of the second word line layer ranges from 3.7 eV to 4.35 eV; when the doping type of the doped region is P type, the work function of the second word line layer ranges from 4.75 eV to 5.45 eV.

4. The semiconductor structure according to any of claims 1 to 3, characterized in that Along the second direction, the ratio of the height of the second word line layer to the height of the first word line layer ranges from 1 / 3 to 1 / 2.

5. The semiconductor structure of any of claims 1-3, wherein the semiconductor structure is a semiconductor-on-insulator structure. The thickness of the spacer layer ranges from 3 nm to 10 nm.

6. The semiconductor structure of claim 2 or 3, wherein, When the doping type of the doped region is N type, the material of the first word line layer comprises titanium nitride, wherein the material of the second word line layer comprises N type doped polysilicon; and / or, the material of the second word line layer comprises doped titanium nitride and / or doped tungsten, the doping elements in the doped titanium nitride comprise at least one of lanthanum, niobium and gallium, and the doping elements in the doped tungsten comprise at least one of lanthanum, niobium and gallium; and / or, the material of the second word line layer comprises at least one of lanthanum, niobium and gallium; and / or, the second word line layer comprises a first sub-layer and a second sub-layer, the first sub-layer is located on the spacer layer, along the third direction, the cross section of the first sub-layer is in a U-shaped structure, the bottom of the U-shaped structure covers the surface of the spacer layer, the sidewall of the U-shaped structure covers the sidewall of the upper region of the active region, and the second sub-layer covers the surface of the first sub-layer and fills the internal region of the U-shaped structure, the material of the first sub-layer comprises at least one of lanthanum, niobium, gallium, lanthanum oxide, niobium oxide and gallium oxide, and the material of the second sub-layer comprises titanium nitride.

7. The semiconductor structure of claim 6, wherein, When the material of the second word line layer is doped titanium nitride and / or doped tungsten, the atomic percentage of the doping element ranges between 10% and 50%.

8. The semiconductor structure of claim 4, wherein, The substrate comprises at least one active region, the word line structure at least passes through the active region, and the word line structure further comprises a first gate oxide layer and a second gate oxide layer, wherein, The first gate oxide layer covers the bottom and sidewall of the first word line layer and is located between the active region and the first word line layer; The second gate oxide layer covers the sidewall and bottom of the second word line layer, the second gate oxide layer covering the sidewall of the second word line layer is located between the second word line layer and the active region, and the second gate oxide layer covering the bottom of the second word line layer is located between the second word line layer and the first word line layer; the part of the second gate oxide layer between the first word line layer and the second word line layer in the second direction constitutes the spacer layer.

9. The semiconductor structure of any of claims 1-3, wherein, If a programming operation is performed, the first voltage applied to the first word line layer is equal to the second voltage applied to the second word line layer, and the first voltage and the second voltage are equal to the driving voltage of the word line structure required when the programming operation is performed; and / or, If the word line structure is in an unselected state, the voltage applied to the first word line layer is different from the voltage applied to the second word line layer.

10. A method of fabricating a semiconductor structure, characterized by, The method comprises: providing a substrate; forming a word line structure on the substrate, the word line structure extending along a first direction, the word line structure comprising a first word line layer, a second word line layer arranged from bottom to top along a second direction, and a spacer layer located between the first word line layer and the second word line layer; along the first direction, the first word line layer comprises a first end, and the second word line layer comprises a second end, the first end and the second end are located on the same side of the substrate, and along the first direction, the sidewall of the first end of the first word line layer protrudes outward relative to the sidewall of the second end of the second word line layer; forming a lead-out portion while forming the first word line layer, the lead-out portion extending along the second direction and being located on the side where the first end of the first word line layer is located, the lead-out portion being connected with the first word line layer; forming a first contact plug connected with the lead-out portion; forming a second contact plug connected with the second word line layer; wherein the first direction is parallel to the surface of the substrate, the second direction is parallel to the thickness direction of the substrate, and the work function of the second word line layer is different from that of the first word line layer.

11. The method of claim 10, wherein, forming the word line structure comprises: etching the substrate to form a first word line trench extending along the first direction on the substrate; forming a first word line material layer, the first word line material layer filling the first word line trench; removing part of the first word line material layer located in the first word line trench to form a second word line trench, and the remaining at least part of the first word line material layer constitutes the first word line layer, at least part of the first word line layer being located below the second word line trench; forming a spacer material layer on at least part of top surface of the first word line layer and covering sidewalls and bottom of the second word line trench; forming a second word line layer covering surface of the spacer material layer and filling at least part of area of the second word line trench not covered by the spacer material layer; wherein along the second direction, part of the spacer material layer between the first word line layer and the second word line layer constitutes the spacer layer.

12. The method of claim 11, wherein, forming the word line structure further comprises: after forming the first word line trench and before forming the first word line material layer, forming a gate oxide material layer covering sidewalls and bottom of the first word line trench; removing at least part of thickness of part of the gate oxide material layer not covered by sidewalls of the first word line layer before forming the spacer material layer in the same step of removing part of the first word line material layer or after removing part of the first word line material layer, the gate oxide material layer covering bottom and sidewalls of the first word line layer constitutes a first gate oxide layer; wherein the gate oxide material layer on sidewalls of the second word line trench and the spacer material layer together constitute a second gate oxide layer, and thickness of at least part of the second gate oxide layer on sidewalls of the second word line layer is greater than thickness of the first gate oxide layer on sidewalls of the first word line layer.

13. The production method according to claim 11 or 12, characterized by, removing part of the first word line material layer within the first word line trench and forming the lead-out portion at the same time of forming the first word line layer comprises: removing part of the first word line material layer, remaining first word line material layer includes part covering lower area of the first word line trench, which constitutes the first word line layer, and remaining first word line material layer further includes part above the first end of the first word line layer, which constitutes a lead-out portion; the lead-out portion extends along the second direction and is connected with the first word line layer; forming the first contact plug after forming the second word line layer, and forming the second contact plug.

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