Semiconductor device, manufacturing method and memory system

Abstract

The embodiment of the invention provides a semiconductor device, a manufacturing method and a memory system. The semiconductor device comprises a laminated structure, wherein the laminated structure comprises interlayer insulating layers and conductive layers which are alternately stacked; the channel structure penetrates through the laminated structure in the stacking direction; the channel structure comprises a storage function layer and a channel layer, and the storage function layer is located between the channel layer and the interlayer insulating layer and the conductive layer which are alternately stacked in the direction perpendicular to the stacking direction; the storage function layer comprises a ferroelectric material layer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device, manufacturing method, and memory system. Background Technology

[0002] With the advancement of semiconductor technology, the feature size of semiconductor devices is shrinking and their integration density is increasing. However, as the feature size of semiconductor devices approaches the lower limit of process technology, the manufacturing processes and technologies for semiconductor devices are becoming increasingly challenging. This makes it difficult to further increase the density of memory cells in semiconductor devices, posing a serious challenge to the semiconductor memory industry. Summary of the Invention

[0003] In view of the above, embodiments of this disclosure provide a semiconductor device, a manufacturing method, and a memory system.

[0004] To achieve the above objectives, the technical solution disclosed herein is implemented as follows:

[0005] In a first aspect, embodiments of this disclosure provide a semiconductor device, comprising: a stacked structure including alternating stacked interlayer insulating layers and conductive layers; a channel structure extending through the stacked structure along a stacking direction; the channel structure including a storage functional layer and a channel layer, wherein, along a direction perpendicular to the stacking direction, the storage functional layer is located between the channel layer and the alternating stacked interlayer insulating layers and conductive layers; the storage functional layer includes a ferroelectric material layer.

[0006] In some embodiments, the channel structure further includes a high dielectric constant (high k) dielectric layer; the high k dielectric layer is located between the ferroelectric material layer and the alternately stacked interlayer insulating and conductive layers in a direction perpendicular to the stacking direction.

[0007] In some embodiments, the channel structure further includes at least one dielectric layer located between the ferroelectric material layer and the channel layer, and / or between the ferroelectric material layer and the alternately stacked interlayer insulating and conductive layers, along a direction perpendicular to the stacking direction.

[0008] In some embodiments, the channel structure further includes a first dielectric layer located between the high-k dielectric layer and the interlayer insulating layer; the high-k dielectric layer is in contact with the conductive layer in a direction perpendicular to the stacking direction.

[0009] In some embodiments, the storage functional layer further includes at least one dielectric layer, which is located between the ferroelectric material layer and the alternately stacked interlayer insulating and conductive layers in a direction perpendicular to the stacking direction; or, the dielectric layer is located between the ferroelectric material layer and the alternately stacked interlayer insulating and conductive layers, and between the ferroelectric material layer and the channel layer.

[0010] In some embodiments, each of the conductive layers includes a gate layer and an adhesive layer located between the gate layer and at least one of the interlayer insulating layers.

[0011] In some embodiments, the ferroelectric material layer is made of hafnium-based ferroelectric materials, lead zirconate titanate, strontium bismuth tantalate, and zirconium oxide.

[0012] In some embodiments, the dielectric constant of the high-k dielectric layer is greater than 5.

[0013] In a second aspect, this application provides a method for manufacturing a semiconductor device, comprising: forming an initial stacked structure, the initial stacked structure including alternately stacked interlayer insulating layers and sacrificial layers; forming a channel via penetrating the initial stacked structure; sequentially forming a storage functional layer and a channel layer within the channel via; the storage functional layer being located between the channel layer and the alternately stacked interlayer insulating layers and sacrificial layers in a direction perpendicular to the stacking direction, the storage functional layer including a ferroelectric material layer; and replacing the sacrificial layer with a conductive layer.

[0014] In some embodiments, before the storage functional layer and the channel layer are sequentially formed in the channel via, the method further includes: forming a high dielectric constant (high k) dielectric layer in the channel via, the high k dielectric layer being in contact with the alternately stacked interlayer insulating layer and sacrificial layer.

[0015] In some embodiments, forming a storage functional layer within the channel hole includes: sequentially forming a second dielectric layer and a ferroelectric material layer within the channel hole to form a storage functional layer; the second dielectric layer is located between the ferroelectric material layer and the alternately stacked interlayer insulating layer and sacrificial layer in a direction perpendicular to the stacking direction.

[0016] In some embodiments, after the second dielectric layer and the ferroelectric material layer are sequentially formed in the channel hole, the method further includes: forming a third dielectric layer in the channel hole, the third dielectric layer being located between the ferroelectric material layer and the channel layer.

[0017] In some embodiments, forming a storage functional layer within the channel hole includes: sequentially forming a ferroelectric material layer and a third dielectric layer within the channel hole to form a storage functional layer; the third dielectric layer is located between the ferroelectric material layer and the channel layer.

[0018] In some embodiments, before the storage functional layer and the channel layer are sequentially formed in the channel hole, the method further includes: sequentially forming a first dielectric layer and a high-k dielectric layer in the channel hole; the first dielectric layer is located between the high-k dielectric layer and the alternately stacked interlayer insulating layer and sacrificial layer in a direction perpendicular to the stacking direction.

[0019] In some embodiments, replacing the sacrificial layer with a conductive layer includes: removing the sacrificial layer to form a first gap between a plurality of interlayer insulating layers; the first gap exposing a portion of the first dielectric layer; removing the first dielectric layer exposed in the first gap to form a second gap; and forming a conductive layer within the second gap.

[0020] In some embodiments, replacing the sacrificial layer with a conductive layer includes: removing the sacrificial layer to form a first gap between the plurality of interlayer insulating layers; and forming a conductive layer within the first gap.

[0021] In some embodiments, forming a high-k dielectric layer within the channel hole includes: forming a high-k dielectric material layer within the channel hole; and subjecting the high-k dielectric material layer to high-temperature annealing to form the high-k dielectric layer.

[0022] In some embodiments, after the storage functional layer and the channel layer are sequentially formed in the channel hole, the method further includes: forming a dielectric filling layer in the channel hole to fill the channel hole.

[0023] In some embodiments, forming a storage functional layer within the channel aperture includes: forming a ferroelectric material layer within the channel aperture, wherein the material of the ferroelectric material layer includes hafnium-based ferroelectric material, lead zirconate titanate, strontium bismuth tantalate, and zirconium oxide.

[0024] In some embodiments, the dielectric constant of the high-k dielectric layer is greater than 5.

[0025] Thirdly, embodiments of this disclosure provide a memory system, including: a semiconductor device as described in any of the above embodiments, and a controller coupled to the semiconductor device, the controller being configured to control the semiconductor device.

[0026] This disclosure provides a semiconductor device, a manufacturing method, and a memory system. The semiconductor device includes: a stacked structure comprising alternating layers of insulating and conductive layers; a channel structure extending through the stacked structure along a stacking direction; the channel structure includes a storage functional layer and a channel layer, wherein, along a direction perpendicular to the stacking direction, the storage functional layer is located between the channel layer and the alternating layers of insulating and conductive layers; the storage functional layer includes a ferroelectric material layer. In this disclosure, the storage functional layer of the channel structure includes a ferroelectric material layer, which exhibits ferroelectric properties and can be used to store data. Because the ferroelectric material layer maintains stable ferroelectricity even at very small thicknesses, compared to the storage functional layer of an ONO structure, the storage functional layer composed of a ferroelectric material layer has a smaller thickness, and the size of the channel structure can also be smaller. This increases the number of channel structures arranged per unit area on the semiconductor substrate, thereby improving storage density. Attached Figure Description

[0027] Figure 1 A cross-sectional view of a semiconductor device provided in an embodiment of this disclosure;

[0028] Figure 2 Partial magnification of the semiconductor device provided in the embodiments of this disclosure Figure 1 ;

[0029] Figure 3 Partial magnification of the semiconductor device provided in the embodiments of this disclosure Figure 2 ;

[0030] Figure 4 Partial magnification of the semiconductor device provided in the embodiments of this disclosure Figure 3 ;

[0031] Figure 5 Partial magnification of the semiconductor device provided in the embodiments of this disclosure Figure 4 ;

[0032] Figure 6 Partial magnification of the semiconductor device provided in the embodiments of this disclosure Figure 5 ;

[0033] Figure 7 Partial magnification of the semiconductor device provided in the embodiments of this disclosure Figure 6 ;

[0034] Figure 8 Partial magnification of the semiconductor device provided in the embodiments of this disclosure Figure 7 ;

[0035] Figure 9 Partial magnification of the semiconductor device provided in the embodiments of this disclosure Figure 8 ;

[0036] Figure 10 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this disclosure;

[0037] Figures 11A to 11D A method for manufacturing a semiconductor device provided in this disclosure embodiment;

[0038] Figures 12A to 12C Another method for manufacturing a semiconductor device provided in this disclosure embodiment;

[0039] Figure 13 A block diagram of a memory system provided in an embodiment of this disclosure. Detailed Implementation

[0040] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0041] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0042] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0043] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0044] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0045] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0046] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0047] With the continuous development of semiconductor technology, there is an increasing demand for higher storage density in 3D NAND flash memory. In one example, the charge blocking layer, charge trapping layer, and tunneling layer in the channel hole (CH) of a 3D NAND flash memory together constitute the storage functional layer, namely the ONO structure storage functional layer, used to store data. However, the structure of this ONO structure storage functional layer is complex, and its thickness is difficult to reduce. Therefore, it is also difficult to further increase the storage density of the memory.

[0048] Therefore, there is an urgent need to provide a semiconductor device to improve the storage density of memory.

[0049] This disclosure provides a semiconductor device, including: a stacked structure comprising alternating interlayer insulating layers and conductive layers; a channel structure extending through the stacked structure along a stacking direction; the channel structure comprising a storage functional layer and a channel layer, wherein, along a direction perpendicular to the stacking direction, the storage functional layer is located between the channel layer and the alternating interlayer insulating layers and conductive layers; the storage functional layer comprises a ferroelectric material layer.

[0050] Before introducing the semiconductor device and its manufacturing method provided in the embodiments of this disclosure, the various directions that may be involved in the embodiments of this disclosure are first defined. The stacking direction is defined as the Z direction, and the X and Y directions are defined in a plane perpendicular to the Z direction. The X and Y directions may intersect. In a specific embodiment, the X and Y directions may be perpendicular to each other, so that the X, Y, and Z directions are mutually perpendicular.

[0051] refer to Figure 1 and Figure 2 , Figure 1 A cross-sectional view of a semiconductor device provided in an embodiment of this disclosure. Figure 2 Partial magnification of the semiconductor device provided in the embodiments of this disclosure Figure 1 .

[0052] like Figure 1 As shown, the semiconductor device 100 includes a semiconductor substrate 101, a stacked structure 102 and a channel structure 103 located on the semiconductor substrate 101, wherein the stacked structure 102 includes alternately stacked interlayer insulating layers 104 and conductive layers 105. The channel structure 103 extends through the stacked structure 102 into the semiconductor substrate 101 along the Z direction.

[0053] In this embodiment of the disclosure, the storage functional layer includes a ferroelectric material layer. For example, refer to... Figure 2 , Figure 2 It indicates Figure 1 A magnified view of the area within the dashed box. (See image below.) Figure 2 As shown, the channel structure 201 includes a ferroelectric material layer 202 and a channel layer 203, wherein, in the radial direction of the channel, that is, in any direction in the plane containing the X-axis and Y-axis, the ferroelectric material layer 202 is located between the channel layer 203 and the alternately stacked interlayer insulating layer 210 and conductive layer 220.

[0054] In this embodiment, a ferroelectric material layer 202 is used as a storage functional layer, and the ferroelectricity of the ferroelectric material layer 202 is utilized for data storage. Specifically, a certain electric field is applied to the ferroelectric material layer 202, and the central atoms of the ferroelectric material move under the action of the electric field and reach a stable state; when the electric field is removed, the central atoms of the ferroelectric material will still remain in their original positions, so that the memory has non-volatile storage characteristics.

[0055] In this embodiment of the disclosure, the ferroelectric material layer 202 is made of hafnium-based ferroelectric material, lead zirconate titanate, strontium bismuth tantalate, and zirconium oxide.

[0056] When a ferroelectric material layer is used as a storage functional layer, it has a smaller thickness compared to an ONO structure storage functional layer while still maintaining good ferroelectricity. Therefore, in this embodiment, using a ferroelectric material to form the storage functional layer instead of the ONO structure storage functional layer in the example allows for a further reduction in the thickness of the storage functional layer, thereby reducing the channel structure size and increasing the number of channel structures per unit area, thus improving storage density. Simultaneously, the gate operating voltage of the channel structure formed by storage functional layers of different materials differs. Specifically, the gate operating voltage of the channel structure formed by a storage functional layer including a ferroelectric material layer is lower than that of the channel structure formed by the ONO structure storage functional layer in the example. Therefore, in the peripheral circuit, this embodiment can use more low-cost, low-voltage CMOS transistors to replace at least some of the higher-cost, high-voltage CMOS transistors, thereby significantly reducing manufacturing costs.

[0057] In this embodiment of the disclosure, the material of the channel layer 203 includes, but is not limited to, amorphous silicon, polycrystalline silicon, or monocrystalline silicon.

[0058] In this embodiment of the disclosure, the channel structure 201 further includes a dielectric filling layer 204, which can fill the channel structure 201 and provide support for it. In this case, in the radial direction of the channel, a channel layer 203 surrounds the dielectric filling layer 204, and the channel layer 203 is located between the dielectric filling layer 204 and the ferroelectric material layer 202. In some embodiments, the material of the dielectric filling layer 204 includes silicon oxide.

[0059] In this embodiment of the disclosure, the channel structure further includes a high dielectric constant (high k) dielectric layer; along a direction perpendicular to the stacking direction, the high k dielectric layer is located between the ferroelectric material layer and the alternately stacked interlayer insulating layer and conductive layer.

[0060] like Figure 2 As shown, the channel structure 201 includes a dielectric filling layer 204, a channel layer 203, a ferroelectric material layer 202, and a high-k dielectric layer 205. The ferroelectric material layer 202 serves as a storage functional layer. Along the radial direction of the channel, the channel layer 203 surrounds the dielectric filling layer 204 and is located between the dielectric filling layer 204 and the ferroelectric material layer 202. The ferroelectric material layer 202 is located between the channel layer 203 and the high-k dielectric layer 205. The high-k dielectric layer 205 is located between the ferroelectric material layer 202 and alternatingly stacked interlayer insulating layers 210 and conductive layers 220.

[0061] In this embodiment of the disclosure, the dielectric constant of the high-k dielectric layer 205 is greater than 5.

[0062] In this embodiment of the disclosure, the high-k dielectric layer 205 is made of hafnium oxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), and hafnium nitride (HfSiON).

[0063] In this embodiment of the disclosure, each conductive layer includes a gate layer and an adhesive layer located between the gate layer and at least one interlayer insulating layer.

[0064] like Figure 2 As shown, the conductive layer 220 includes a gate layer 221 and an adhesive layer 222 located between the gate layer 221 and at least one interlayer insulating layer 210, and the adhesive layer 222 is located between the channel structure 201 and the gate layer 221.

[0065] It should be noted that in existing processes, to improve gate leakage current, a high-k dielectric layer can be formed as the gate dielectric layer in contact with the conductive layer, i.e., a high-k metal gate structure is formed. However, for the memory functional layer of the ONO structure in the aforementioned example, its thickness is difficult to reduce, making it difficult to integrate the high-k dielectric layer within the channel structure. Therefore, the high-k dielectric layer is typically formed between interlayer insulating layers during the gate replacement process, forming a conductive layer together with the gate layer. (Reference) Figure 2 In this embodiment, a ferroelectric material layer is used as the storage functional layer, which allows the high-k dielectric layer to be integrated into the channel structure without increasing the channel structure size. This not only improves the gate leakage current problem but also reduces the thickness of the conductive layer, allowing for a greater number of conductive layers in a stacked structure of a given height, thereby effectively increasing the storage density.

[0066] In this embodiment, the material of the gate layer 221 includes, but is not limited to, one or more combinations of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, and silicides, or may be other suitable materials. The adhesive layer is configured to improve the adhesion between the gate layer and other contact structures to enhance the reliability of the semiconductor structure. The adhesive layer 222 may be a conductive material, including, but not limited to, metals (e.g., titanium (Ti), tantalum (Ta), chromium (Cr), tungsten (W), etc.) and metal compounds (e.g., titanium nitride (TiN)). x ), Tantalum nitride (TaN) x ), Chromium nitride (CrN) x ), Tungsten nitride (WN) x (etc.) and metal alloys (e.g., TiSi) x N y TaSi x N y CrSi x N y WSi x N y At least one of (etc.). In practice, the specific material of the adhesive layer 222 can be determined based on the material of the gate layer 221 in order to improve the overall conductivity of the gate layer 221 and the adhesive layer 222.

[0067] In this embodiment of the present disclosure, the interlayer insulating layer 210 may include an insulating material, including but not limited to silicon oxide (SiO2), silicon nitride (SiN), and silicon oxynitride (SiN2). x O y ), or other suitable materials.

[0068] In this embodiment of the disclosure, the channel structure further includes at least one dielectric layer, which is located between the ferroelectric material layer and the channel layer along a direction perpendicular to the stacking direction, and / or between the ferroelectric material layer and the alternately stacked interlayer insulating layer and conductive layer.

[0069] refer to Figure 3 , Figure 3 Partial magnification of the semiconductor device provided in the embodiments of this disclosure Figure 2 .

[0070] like Figure 3As shown, the channel structure 301 includes a dielectric filling layer 302, a channel layer 303, a ferroelectric material layer 304, a high-k dielectric layer 305, and a dielectric layer 306. The ferroelectric material layer 304 serves as the storage function layer. Along the radial direction of the channel, the channel layer 303 surrounds the dielectric filling layer 302, and is located between the dielectric filling layer 302 and the ferroelectric material layer 304. The ferroelectric material layer 304 is located between the channel layer 303 and the high-k dielectric layer 305. The high-k dielectric layer 305 is located between the ferroelectric material layer 304 and the dielectric layer 306. The dielectric layer 306 is located between the high-k dielectric layer 305 and alternating stacked interlayer insulating layers 310 and conductive layers 320. The dielectric layer 306 and the high-k dielectric layer 305 together form the gate dielectric layer, thereby improving gate leakage current.

[0071] refer to Figure 4 , Figure 4 Partial magnification of the semiconductor device provided in the embodiments of this disclosure Figure 3 .

[0072] like Figure 4 As shown, the channel structure 401 includes a dielectric filling layer 402, a channel layer 403, a ferroelectric material layer 404, a high-k dielectric layer 405, and a dielectric layer 406. Here, the dielectric layer 406 located between the ferroelectric material layer 404 and the alternately stacked interlayer insulating layer 410 and conductive layer 420 is defined as the second dielectric layer 4062. The ferroelectric material layer 404 and the second dielectric layer 4062 together form a storage functional layer. Specifically, along the radial direction of the channel, the channel layer 403 surrounds the dielectric filling layer 402, the channel layer 403 is located between the dielectric filling layer 402 and the ferroelectric material layer 404, the ferroelectric material layer 404 is located between the channel layer 403 and the second dielectric layer 4062, the second dielectric layer 4062 is located between the ferroelectric material layer 404 and the high-k dielectric layer 405, and the high-k dielectric layer 405 is located between the second dielectric layer 4062 and the alternately stacked interlayer insulating layer 410 and conductive layer 420. Figure 4 In this process, the second dielectric layer 4062 can serve as an interface buffer layer to improve the bonding force between the ferroelectric material layer 404 and the high-k dielectric layer 405. Simultaneously, the second dielectric layer 4062 can release the stress generated during the formation of the ferroelectric material layer, which is beneficial for improving the quality of subsequent processes. Furthermore, it can prevent the diffusion of ferroelectric material from the ferroelectric material layer 404 into the high-k dielectric layer 405.

[0073] refer to Figure 5 , Figure 5 Partial magnification of the semiconductor device provided in the embodiments of this disclosure Figure 4 .

[0074] like Figure 5As shown, the channel structure 501 includes a dielectric filling layer 502, a channel layer 503, a ferroelectric material layer 504, a high-k dielectric layer 505, and a dielectric layer 506. Here, the dielectric layer 506 located between the channel layer 503 and the ferroelectric material layer 504 is defined as the third dielectric layer 5063, and the ferroelectric material layer 504 and the third dielectric layer 5063 together form a storage functional layer. Specifically, along the radial direction of the channel, the channel layer 503 surrounds the dielectric filling layer 502, the channel layer 503 is located between the dielectric filling layer 502 and the third dielectric layer 5063, the third dielectric layer 5063 is located between the channel layer 503 and the ferroelectric material layer 504, the ferroelectric material layer 504 is located between the third dielectric layer 5063 and the high-k dielectric layer 505, and the high-k dielectric layer 505 is located between the ferroelectric material layer 504 and the alternately stacked interlayer insulating layer 510 and conductive layer 520. Figure 5 In this process, the third dielectric layer 5063 can serve as an interface buffer layer to improve the bonding force between the channel layer 503 and the ferroelectric material layer 504.

[0075] refer to Figure 6 , Figure 6 Partial magnification of the semiconductor device provided in the embodiments of this disclosure Figure 5 .

[0076] like Figure 6 As shown, the channel structure 601 includes a dielectric filling layer 602, a channel layer 603, a ferroelectric material layer 604, a high-k dielectric layer 605, and a dielectric layer 606. The dielectric layer 606 includes a second dielectric layer 6062 and a third dielectric layer 6063. The ferroelectric material layer 604, the second dielectric layer 6062, and the third dielectric layer 6063 together form the storage functional layer. In this design, along the radial direction of the channel, the channel layer 603 surrounds the dielectric filling layer 602. The channel layer 603 is located between the dielectric filling layer 602 and the third dielectric layer 6063. The third dielectric layer 6063 is located between the channel layer 603 and the ferroelectric material layer 604. The ferroelectric material layer 604 is located between the third dielectric layer 6063 and the second dielectric layer 6062. The second dielectric layer 6062 is located between the ferroelectric material layer 604 and the high-k dielectric layer 605. The high-k dielectric layer 605 is located between the second dielectric layer 6062 and the alternately stacked interlayer insulating layer 610 and conductive layer 620. Here, the third dielectric layer 6063 and the second dielectric layer 6062 can serve as interface buffer layers, thereby preventing the ferroelectric material of the ferroelectric material layer 604 located between the third dielectric layer 6063 and the second dielectric layer 6062 from diffusing into the channel layer 603 and the high-k dielectric layer 605, respectively.

[0077] In this embodiment of the disclosure, the material of the dielectric layer 606 includes silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof.

[0078] In this embodiment of the disclosure, the channel structure further includes a first dielectric layer located between the high-k dielectric layer and the interlayer insulating layer; the high-k dielectric layer is in contact with the conductive layer in a direction perpendicular to the stacking direction.

[0079] refer to Figure 7 , Figure 7 Partial magnification of the semiconductor device provided in the embodiments of this disclosure Figure 6 .

[0080] like Figure 7 As shown, the channel structure 701 includes a dielectric filling layer 702, a channel layer 703, a ferroelectric material layer 704, a high-k dielectric layer 705, and a first dielectric layer 706. The ferroelectric material layer 704 serves as a storage layer. Along the radial direction of the channel, the channel layer 703 surrounds the dielectric filling layer 702 and is located between the dielectric filling layer 702 and the ferroelectric material layer 704. The ferroelectric material layer 704 is located between the channel layer 703 and the high-k dielectric layer 705. The first dielectric layer 706 is located between the high-k dielectric layer 705 and the interlayer insulating layer 710. It should be noted that the high-k dielectric layer 705 is in contact with the conductive layer 720, but not with the interlayer insulating layer 710.

[0081] In this embodiment of the disclosure, there may be no obvious interface between the first dielectric layer 706 and the interlayer insulating layer 710.

[0082] In this embodiment of the disclosure, the material of the first dielectric layer 706 includes silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof.

[0083] In some embodiments of this disclosure, the channel structure may not include a high-k dielectric layer. In embodiments of this disclosure, the storage functional layer further includes at least one dielectric layer, which is located between the ferroelectric material layer and the alternately stacked interlayer insulating and conductive layers along a direction perpendicular to the stacking direction; or, the dielectric layer is located between the ferroelectric material layer and the alternately stacked interlayer insulating and conductive layers, and between the ferroelectric material layer and the channel layer.

[0084] refer to Figure 8 , Figure 8 Partial magnification of the semiconductor device provided in the embodiments of this disclosure Figure 7 .

[0085] like Figure 8As shown, the channel structure 801 includes a dielectric filling layer 802, a channel layer 803, a ferroelectric material layer 804, and a dielectric layer 806. Here, the dielectric layer 806 is a second dielectric layer 8062. The ferroelectric material layer 804 and the second dielectric layer 8062 together form a storage functional layer. Along the radial direction of the channel, the channel layer 803 surrounds the dielectric filling layer 802, and the channel layer 803 is located between the dielectric filling layer 802 and the ferroelectric material layer 804. The ferroelectric material layer 804 is located between the channel layer 803 and the second dielectric layer 8062, and the second dielectric layer 8062 is located between the ferroelectric material layer 804 and the alternately stacked interlayer insulating layer 810 and conductive layer 820. Here, the second dielectric layer 8062 can serve as an interface buffer layer to improve the bonding force between the ferroelectric material layer 804 and the alternately stacked interlayer insulating layer 810 and conductive layer 820.

[0086] refer to Figure 9 , Figure 9 Partial magnification of the semiconductor device provided in the embodiments of this disclosure Figure 8 .

[0087] like Figure 9 As shown, the channel structure 901 includes a dielectric filling layer 902, a channel layer 903, a ferroelectric material layer 904, and a dielectric layer 906. The dielectric layer 906 includes a second dielectric layer 9062 and a third dielectric layer 9063. The ferroelectric material layer 904, the second dielectric layer 9062, and the third dielectric layer 9063 together form a storage functional layer. Along the radial direction of the channel, the channel layer 903 surrounds the dielectric filling layer 902, and is located between the dielectric filling layer 902 and the third dielectric layer 9063. The third dielectric layer 9063 is located between the channel layer 903 and the ferroelectric material layer 904. The ferroelectric material layer 904 is located between the third dielectric layer 9063 and the second dielectric layer 9062. The second dielectric layer 9062 is located between the ferroelectric material layer 904 and alternatingly stacked interlayer insulating layers 910 and conductive layers 920. Here, the third dielectric layer 9063 and the second dielectric layer 9062 can serve as interface buffer layers to prevent the ferroelectric material of the ferroelectric material layer 904 located between the third dielectric layer 9063 and the second dielectric layer 9062 from diffusing into the channel layer 903, the conductive layer 920 and the interlayer insulating layer 910, respectively.

[0088] In this embodiment of the disclosure, because the gate operating voltage of the channel structure formed by the storage functional layer including the ferroelectric material layer is low, therefore, for Figure 8 and Figure 9 In semiconductor devices, even without a high-k dielectric layer in the channel structure, the gate leakage current can be controlled within the normal range.

[0089] refer to Figure 10 , Figure 10A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this disclosure.

[0090] like Figure 10 As shown in the embodiments of this disclosure, a method for manufacturing a semiconductor device is also provided, comprising:

[0091] Step S101: Form an initial stacked structure, which includes alternating stacked interlayer insulating layers and sacrificial layers.

[0092] Step S102: Form a channel hole that penetrates the initial stacked structure.

[0093] Step S103: A storage functional layer and a channel layer are sequentially formed in the channel hole; along the direction perpendicular to the stacking direction, the storage functional layer is located between the channel layer and the alternately stacked interlayer insulating layer and sacrificial layer, and the storage functional layer includes a ferroelectric material layer.

[0094] Step S104: Replace the sacrificial layer with a conductive layer.

[0095] In this embodiment of the disclosure, the interlayer insulating layer, the sacrificial layer, and the storage functional layer and channel layer within the channel vias can all be formed by one or more deposition processes. The deposition processes may include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or any combination thereof.

[0096] In this embodiment of the disclosure, the process for forming the channel hole that penetrates the initial stacked structure includes a dry etching process.

[0097] In some embodiments of this disclosure, before the storage functional layer and the channel layer are sequentially formed in the channel via, the method for manufacturing the semiconductor device further includes: forming a high dielectric constant (high k) dielectric layer in the channel via, wherein the high k dielectric layer is in contact with alternately stacked interlayer insulating layers and sacrificial layers.

[0098] For details, please refer to Figure 2 A high-k dielectric layer 205, a ferroelectric material layer 202, and a channel layer 203 are sequentially formed within the channel hole. The high-k dielectric layer 205 is in contact with the alternately stacked interlayer insulating layer 210 and sacrificial layer.

[0099] In this embodiment of the disclosure, the dielectric constant of the high-k dielectric layer 205 is greater than 5.

[0100] In this embodiment of the present disclosure, forming a high-k dielectric layer in the channel hole includes: forming a high-k dielectric material layer in the channel hole; and performing high-temperature annealing on the high-k dielectric material layer to form the high-k dielectric layer.

[0101] refer to Figure 2 In this embodiment of the present disclosure, a high-k dielectric layer 205 with a higher process temperature is first formed in the channel hole, and then a ferroelectric material layer 202 with a lower process temperature is formed. This can avoid the ferroelectric material layer 202 being affected by the high-temperature process of forming the high-k dielectric layer 205, thereby ensuring that the structure of the ferroelectric material layer 202 is not damaged.

[0102] In this embodiment of the present disclosure, forming a storage functional layer within a channel hole includes: sequentially forming a second dielectric layer and a ferroelectric material layer within the channel hole to form a storage functional layer; the second dielectric layer is located between the ferroelectric material layer and alternately stacked interlayer insulating layers and sacrificial layers in a direction perpendicular to the stacking direction.

[0103] For details, please refer to Figure 4 or Figure 8 . Figure 4 In this structure, a high-k dielectric layer 405, a second dielectric layer 4062, a ferroelectric material layer 404, and a channel layer 403 are sequentially formed within the channel hole. The second dielectric layer 4062 and the ferroelectric material layer 404 together form the storage functional layer. Along the radial direction of the channel, the second dielectric layer 4062 is located between the ferroelectric material layer 404 and the high-k dielectric layer 405. Figure 8 In this structure, a second dielectric layer 8062, a ferroelectric material layer 804, and a channel layer 803 are sequentially formed within the channel hole. The second dielectric layer 8062 and the ferroelectric material layer 804 together form the storage functional layer. Along the radial direction of the channel, the second dielectric layer 8062 is located between the ferroelectric material layer 804 and the alternately stacked interlayer insulating layer 810 and sacrificial layer.

[0104] In this embodiment of the present disclosure, after the second dielectric layer and the ferroelectric material layer are sequentially formed in the channel hole, the method further includes: forming a third dielectric layer in the channel hole, wherein the third dielectric layer is located between the ferroelectric material layer and the channel layer.

[0105] For details, please refer to Figure 6 or Figure 9 . Figure 6 In this structure, a high-k dielectric layer 605, a second dielectric layer 6062, a ferroelectric material layer 604, a third dielectric layer 6063, and a channel layer 603 are sequentially formed within the channel hole. The second dielectric layer 6062, the third dielectric layer 6063, and the ferroelectric material layer 604 together form the storage functional layer. Along the radial direction of the channel, the third dielectric layer 6063 is located between the ferroelectric material layer 604 and the channel layer 603. Figure 9In this structure, a second dielectric layer 9062, a ferroelectric material layer 904, a third dielectric layer 9063, and a channel layer 903 are sequentially formed within the channel hole. The second dielectric layer 9062, the third dielectric layer 9063, and the ferroelectric material layer 904 together form the storage functional layer. Along the radial direction of the channel, the third dielectric layer 9063 is located between the ferroelectric material layer 904 and the channel layer 903.

[0106] In this embodiment of the present disclosure, forming a storage functional layer within a channel hole includes: sequentially forming a ferroelectric material layer and a third dielectric layer within the channel hole to form a storage functional layer; the third dielectric layer is located between the ferroelectric material layer and the channel layer.

[0107] refer to Figure 5 A high-k dielectric layer 505, a ferroelectric material layer 504, a third dielectric layer 5063, and a channel layer 503 are sequentially formed within the channel hole. The third dielectric layer 5063 and the ferroelectric material layer 504 together form the storage functional layer. Along the radial direction of the channel, the third dielectric layer 5063 is located between the ferroelectric material layer 504 and the channel layer 503.

[0108] In other embodiments of this disclosure, before the storage functional layer and the channel layer are sequentially formed in the channel hole, the method further includes: sequentially forming a first dielectric layer and a high-k dielectric layer in the channel hole; the first dielectric layer is located between the high-k dielectric layer and alternately stacked interlayer insulating layers and sacrificial layers in a direction perpendicular to the stacking direction.

[0109] refer to Figures 11A to 11D , Figures 11A to 11D This disclosure provides a method for manufacturing a semiconductor device.

[0110] like Figure 11A As shown, an initial stacked structure 1107, consisting of an interlayer insulating layer 1105 and a sacrificial layer 1106 alternately stacked, is formed on a semiconductor substrate (not shown). Etching forms a channel via 1100 that penetrates the initial stacked structure 1107 and extends into the semiconductor substrate. Within the channel via 1100, a first dielectric layer 1101, a high-k dielectric layer 1102, a ferroelectric material layer 1103, and a channel layer 1104 are sequentially formed. The ferroelectric material layer 1103 is a storage layer. Along the radial direction of the channel, the first dielectric layer 1101 is located between the high-k dielectric layer 1102 and the alternately stacked interlayer insulating layer 1105 and sacrificial layer 1106.

[0111] In one embodiment of this disclosure, replacing the sacrificial layer with a conductive layer includes: removing the sacrificial layer to form a first gap between a plurality of interlayer insulating layers; exposing a portion of a first dielectric layer in the first gap; removing the first dielectric layer exposed in the first gap to form a second gap; and forming a conductive layer within the second gap.

[0112] like Figure 11BAs shown, a wet etching process is used to remove the sacrificial layer 1106 in the initial stacked structure 1107 to form a first gap 1108 between multiple interlayer insulating layers 1105. At this time, a portion of the side surface of the first dielectric layer 1101 is exposed in the first gap 1108.

[0113] In this embodiment of the disclosure, the first dielectric layer 1101 can serve as a barrier layer to protect the channel structure 1109 from damage during the etching process of removing the sacrificial layer 1106.

[0114] like Figure 11C As shown, an etching process is used to remove a portion of the first dielectric layer 1101 exposed in the first gap 1108 to form the second gap 1110. At this time, a portion of the side of the high-k dielectric layer 1102 is exposed in the second gap 1110. In other words, the first dielectric layer 1101 is partially removed, and only the portion of the first dielectric layer 1101 located between the high-k dielectric layer 1102 and the interlayer insulating layer 1105 remains.

[0115] like Figure 11D As shown, an adhesive layer 1111 and a gate layer 1112 are sequentially formed within the second gap using a deposition process to form a conductive layer 1113. At this point, the gate replacement process is complete. It should be noted that at this time, the adhesive layer 1111 is in contact with a portion of the high-k dielectric layer 1102, and the gate layer 1112, the adhesive layer 1111, and the high-k dielectric layer 1102 together form a high-k metal gate structure.

[0116] In another embodiment of this disclosure, replacing the sacrificial layer with a conductive layer includes: removing the sacrificial layer to form a first gap between a plurality of interlayer insulating layers; and forming a conductive layer within the first gap.

[0117] refer to Figures 12A to 12C , Figures 12A to 12C Another method for manufacturing a semiconductor device provided in this disclosure.

[0118] like Figure 12A As shown, an initial stacked structure 1207, consisting of an interlayer insulating layer 1205 and a sacrificial layer 1206 alternately stacked, is formed on a semiconductor substrate (not shown). Etching penetrates the initial stacked structure 1207 to form a channel via 1200 extending into the semiconductor substrate. Within the channel via 1200, a first dielectric layer 1201, a high-k dielectric layer 1202, a ferroelectric material layer 1203, and a channel layer 1204 are sequentially formed. The ferroelectric material layer 1203 serves as a storage layer. Along the radial direction of the channel, the first dielectric layer 1201 is located between the high-k dielectric layer 1202 and the alternately stacked interlayer insulating layer 1205 and sacrificial layer 1206.

[0119] like Figure 12BAs shown, a wet etching process is used to remove the sacrificial layer 1206 to form a first gap 1208 between multiple interlayer insulating layers 1205. The first dielectric layer 1201 serves as a barrier layer. At this time, a portion of the side surface of the first dielectric layer 1201 is exposed in the first gap 1208.

[0120] like Figure 12C As shown, an adhesive layer 1211 and a gate layer 1212 are sequentially formed within the first gap 1208 using a deposition process to form a conductive layer 1213. At this time, the adhesive layer 1211 contacts a portion of the first dielectric layer 1201, and the gate layer 1212, adhesive layer 1211, first dielectric layer 1201, and high-k dielectric layer 1202 together form a high-k metal gate structure.

[0121] It is important to note that Figures 11A to 11D Only the corresponding Figure 7 The manufacturing method of semiconductor devices, and Figures 12A to 12C Only the corresponding Figure 3 The method for manufacturing semiconductor devices. It is understood that, according to the above manufacturing method, semiconductor devices can also be formed separately. Figure 2 , Figure 4 , Figure 5 , Figure 6 , Figure 8 and Figure 9 The corresponding semiconductor device.

[0122] In this embodiment of the disclosure, after the storage functional layer and the channel layer are sequentially formed in the channel hole, the method further includes: forming a dielectric filling layer in the channel hole to fill the channel hole.

[0123] like Figure 12A As shown, a filling material is deposited within the channel hole 1200 to form a dielectric filling layer 1214. The dielectric filling layer 1214 can fill the channel hole 1200 and provide support for the channel structure 1209. At this time, the channel layer 1204 surrounds the dielectric filling layer 1214.

[0124] In this embodiment of the disclosure, forming a storage functional layer within the channel hole includes: forming a ferroelectric material layer 1203 within the channel hole, wherein the material of the ferroelectric material layer 1203 includes hafnium-based ferroelectric material, lead zirconate titanate, strontium bismuth tantalate, and zirconium oxide.

[0125] refer to Figure 13 , Figure 13 Block diagram of a memory system provided in the embodiments of this disclosure

[0126] like Figure 13As shown, this disclosure also provides a memory system 1300, including: a semiconductor device 1301 as described in any of the above embodiments, and a controller 1302 coupled to the semiconductor device 1301, the controller 1302 being configured to control the semiconductor device 1301.

[0127] In this embodiment of the disclosure, the semiconductor device 1301 may be a memory. The semiconductor device 1301 may also be part of a memory, that is, the semiconductor device 1301 includes a memory cell array, and the memory cell array and peripheral circuitry may together form a memory.

[0128] In this embodiment of the disclosure, the memory system 1300 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). That is, the memory system can be applied to and packaged into different types of electronic products, such as mobile phones (e.g., cell phones), desktop computers, tablets, laptops, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, power banks, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device having storage therein.

[0129] In some embodiments, the controller 1302 is configured to operate in a low duty cycle environment, such as an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones.

[0130] In other embodiments, controller 1302 is configured to operate in a high duty cycle environment in an SSD or eMMC, which is used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays.

[0131] In this embodiment of the disclosure, controller 1302 can be configured to control memory operations, such as read, erase, and program operations. Controller 1302 can also be configured to manage various functions relating to data stored or to be stored in memory, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, controller 1302 is also configured to process error correction codes relating to data read from or written to memory. Controller 1302 can also perform any other suitable functions, such as formatting memory. Controller 1302 can communicate with external devices (e.g., host 1303) according to specific communication protocols. For example, controller 1302 can communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0132] This disclosure provides a semiconductor device, a manufacturing method, and a memory system. The semiconductor device includes: a stacked structure comprising alternating layers of insulating and conductive layers; a channel structure extending through the stacked structure along a stacking direction; the channel structure includes a storage functional layer and a channel layer, wherein, along a direction perpendicular to the stacking direction, the storage functional layer is located between the channel layer and the alternating layers of insulating and conductive layers; the storage functional layer includes a ferroelectric material layer. In this disclosure, the storage functional layer of the channel structure includes a ferroelectric material layer, which exhibits ferroelectric properties and can be used to store data. Because the ferroelectric material layer maintains stable ferroelectricity even at very small thicknesses, compared to an ONO structure storage functional layer, the storage functional layer composed of a ferroelectric material layer has a smaller thickness, and the size of the channel structure can also be smaller. This increases the number of channel structures arranged per unit area on the semiconductor substrate, thereby improving storage density.

[0133] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0134] The above description is only a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. All equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: A stacked structure comprising alternating stacked interlayer insulating layers and conductive layers; A channel structure extends through the stacked structure along the stacking direction; the channel structure includes a storage functional layer and a channel layer, wherein, along a direction perpendicular to the stacking direction, the storage functional layer is located between the channel layer and the alternately stacked interlayer insulating and conductive layers; the storage functional layer includes a ferroelectric material layer.

2. The semiconductor device according to claim 1, characterized in that, The channel structure further includes a high dielectric constant (high k) dielectric layer; along a direction perpendicular to the stacking direction, the high k dielectric layer is located between the ferroelectric material layer and the alternately stacked interlayer insulating and conductive layers.

3. The semiconductor device according to claim 2, characterized in that, The channel structure further includes at least one dielectric layer, which is located between the ferroelectric material layer and the channel layer, and / or between the ferroelectric material layer and the alternately stacked interlayer insulating and conductive layers, along a direction perpendicular to the stacking direction.

4. The semiconductor device according to claim 2, characterized in that, The channel structure further includes a first dielectric layer located between the high-k dielectric layer and the interlayer insulating layer; the high-k dielectric layer is in contact with the conductive layer in a direction perpendicular to the stacking direction.

5. The semiconductor device according to claim 1, characterized in that, The storage functional layer further includes at least one dielectric layer, which is located between the ferroelectric material layer and the alternately stacked interlayer insulating and conductive layers along a direction perpendicular to the stacking direction; or... The dielectric layer is located between the ferroelectric material layer and the alternately stacked interlayer insulating and conductive layers, and between the ferroelectric material layer and the channel layer.

6. The semiconductor device according to claim 1, characterized in that, Each of the conductive layers includes a gate layer and an adhesive layer located between the gate layer and at least one of the interlayer insulating layers.

7. The semiconductor device according to claim 1, characterized in that, The materials of the ferroelectric material layer include hafnium-based ferroelectric materials, lead zirconate titanate, strontium bismuth tantalate, and zirconium oxide.

8. The semiconductor device according to claim 2, characterized in that, The dielectric constant of the high-k dielectric layer is greater than 5.

9. A method for manufacturing a semiconductor device, characterized in that, include: An initial stacked structure is formed, the initial stacked structure comprising alternating stacked interlayer insulating layers and sacrificial layers; Forming a channel hole that penetrates the initial stacked structure; A storage functional layer and a channel layer are sequentially formed within the channel hole; along a direction perpendicular to the stacking direction, the storage functional layer is located between the channel layer and the alternately stacked interlayer insulating layer and sacrificial layer, and the storage functional layer includes a ferroelectric material layer; The sacrificial layer is replaced with a conductive layer.

10. The method for manufacturing a semiconductor device according to claim 9, characterized in that, Before the storage functional layer and the channel layer are sequentially formed within the channel hole, the method further includes: A high dielectric constant (high k) dielectric layer is formed within the channel hole, and the high k dielectric layer is in contact with the alternating stacked interlayer insulating layer and sacrificial layer.

11. The method for manufacturing a semiconductor device according to claim 9 or 10, characterized in that, The formation of a storage functional layer within the channel aperture includes: A second dielectric layer and a ferroelectric material layer are sequentially formed within the channel hole to form a storage functional layer; the second dielectric layer is located between the ferroelectric material layer and the alternately stacked interlayer insulating layer and sacrificial layer in a direction perpendicular to the stacking direction.

12. The method for manufacturing a semiconductor device according to claim 11, characterized in that, After the second dielectric layer and the ferroelectric material layer are sequentially formed within the channel hole, the method further includes: A third dielectric layer is formed within the channel hole, the third dielectric layer being located between the ferroelectric material layer and the channel layer.

13. The method for manufacturing a semiconductor device according to claim 10, characterized in that, The formation of a storage functional layer within the channel aperture includes: A ferroelectric material layer and a third dielectric layer are sequentially formed within the channel hole to form a storage functional layer; the third dielectric layer is located between the ferroelectric material layer and the channel layer.

14. The method for manufacturing a semiconductor device according to claim 9, characterized in that, Before the storage functional layer and the channel layer are sequentially formed within the channel hole, the method further includes: A first dielectric layer and a high-k dielectric layer are sequentially formed within the channel hole; along a direction perpendicular to the stacking direction, the first dielectric layer is located between the high-k dielectric layer and the alternately stacked interlayer insulating layer and sacrificial layer.

15. The method for manufacturing a semiconductor device according to claim 14, characterized in that, The step of replacing the sacrificial layer with a conductive layer includes: The sacrificial layer is removed to form a first gap between the plurality of interlayer insulating layers; the first gap exposes a portion of the first dielectric layer; Remove the first dielectric layer exposed in the first gap to form a second gap; A conductive layer is formed within the second gap.

16. The method for manufacturing a semiconductor device according to claim 9, characterized in that, The step of replacing the sacrificial layer with a conductive layer includes: Remove the sacrificial layer to form a first gap between the plurality of interlayer insulating layers; A conductive layer is formed within the first gap.

17. The method for manufacturing a semiconductor device according to claim 10 or 14, characterized in that, The formation of a high-k dielectric layer within the channel hole includes: A high-k dielectric material layer is formed within the channel hole; The high-k dielectric material layer is subjected to high-temperature annealing to form a high-k dielectric layer.

18. The method for manufacturing a semiconductor device according to claim 9, characterized in that, After the storage functional layer and the channel layer are sequentially formed within the channel hole, the method further includes: A medium-filling layer is formed inside the channel hole to fill the channel hole.

19. The method for manufacturing a semiconductor device according to claim 9, characterized in that, The formation of a storage functional layer within the channel aperture includes: A ferroelectric material layer is formed within the channel hole, and the material of the ferroelectric material layer includes hafnium-based ferroelectric material, lead zirconate titanate, strontium bismuth tantalate, and zirconium oxide.

20. The method for manufacturing a semiconductor device according to claim 10, characterized in that, The dielectric constant of the high-k dielectric layer is greater than 5.

21. A memory system, characterized in that, include: The semiconductor device as claimed in any one of claims 1 to 8, and, A controller coupled to the semiconductor device, the controller being configured to control the semiconductor device.

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