Semiconductor device structures and related methods

Abstract

The invention relates to a semiconductor device structure and a related method. Methods and structures for performing an isolation patterning process include defining a plurality of active regions extending in a first direction in a top view. The method further includes forming a plurality of dummy gate structures over the plurality of active regions, the plurality of dummy gate structures extending in a top view along a second direction, the second direction being perpendicular to the first direction. The method further includes forming a plurality of source / drain features in a source / drain region adjacent to and on both sides of each of the plurality of dummy gate structures. The method further includes replacing the plurality of dummy gate structures with a plurality of high-K / metal gate stacks. The method further includes forming an isolation structure within the high-K / metal gate stack, wherein the isolation structure has a first source / drain feature and a second source / drain feature disposed on either side of the isolation structure.

Description

Technical Field

[0001] This disclosure relates to semiconductor device structures and related methods. Background Technology

[0002] The electronics industry is driven by a growing demand for smaller, faster electronic devices capable of supporting increasingly complex and sophisticated functions. Consequently, a persistent trend in the semiconductor industry is the manufacture of low-cost, high-performance, and low-power integrated circuits (ICs). To date, these goals have been largely achieved by shrinking the size of semiconductor ICs (e.g., minimizing feature size), thereby increasing production efficiency and reducing associated costs. However, this shrinkage also increases the complexity of semiconductor manufacturing processes. Therefore, continued advancements in semiconductor ICs and devices require similar progress in semiconductor manufacturing processes and technologies.

[0003] Recently, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and minimizing short-channel effect (SCE). One such multi-gate device is the FinFET (Fin Field-Effect Transistor). The name FinFET comes from its fin-like structure, which extends from the substrate forming it and is used to create the FET channel. Another multi-gate device is the gate-all-around (GAA) transistor, which was developed in part to address the performance challenges associated with FinFETs. The name GAA transistor comes from its gate structure, which extends entirely around the channel, providing better electrostatic control than FinFETs. Both FinFETs and GAA transistors are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes, and their three-dimensional structure allows for significant scaling while maintaining gate control and reducing SCE.

[0004] Typically, GAA transistors can be implemented when performance requirements, for example, FinFETs, can no longer be met. However, the fabrication of GAA transistors introduces new challenges to semiconductor manufacturing processes and leads to reliability issues in related devices. Therefore, existing technologies have not yet proven to be completely satisfactory in all aspects. Summary of the Invention

[0005] According to one embodiment of this disclosure, a method for manufacturing a semiconductor device is provided, comprising: defining a plurality of active regions in a substrate, the plurality of active regions extending along a first direction in a top view; forming a plurality of dummy gate structures over the plurality of active regions, the plurality of dummy gate structures extending along a second direction in the top view, the second direction being perpendicular to the first direction; forming a plurality of source / drain features in source / drain regions adjacent to and located on both sides of each of the plurality of dummy gate structures; replacing the plurality of dummy gate structures with a plurality of high-K / metal gate stacks; and forming a first isolation structure within a first high-K / metal gate stack of the plurality of high-K / metal gate stacks, wherein the first isolation structure has a first source / drain feature and a second source / drain feature disposed on both sides of the plurality of source / drain features.

[0006] According to one embodiment of this disclosure, a method of manufacturing a semiconductor device is provided, comprising: defining a plurality of active regions in a substrate, the plurality of active regions extending along a first direction in a top view; forming a plurality of dummy gate structures over the plurality of active regions, the plurality of dummy gate structures extending along a second direction in the top view, the second direction being perpendicular to the first direction; forming a plurality of source / drain features in source / drain regions adjacent to and located on both sides of each of the plurality of dummy gate structures; after forming the plurality of source / drain features, forming a first isolation structure and a second isolation structure within corresponding first and second dummy gate structures in the plurality of dummy gate structures, wherein the first isolation structure and the second isolation structure are disposed on opposite sides of the source / drain features in the plurality of source / drain features; and after forming the first isolation structure and the second isolation structure, replacing the plurality of dummy gate structures with a plurality of high-K / metal gate stacks.

[0007] According to one embodiment of this disclosure, a semiconductor device is provided, comprising: a plurality of active regions located in a substrate, the plurality of active regions extending along a first direction in a top view and providing a repeating shape array; a plurality of high-K / metal gate stacks located above the plurality of active regions, the plurality of high-K / metal gate stacks extending along a second direction in the top view, the second direction being perpendicular to the first direction; a plurality of source / drain features located in source / drain regions adjacent to and on both sides of each of the plurality of high-K / metal gate stacks; and an isolation structure disposed within the high-K / metal gate stacks, wherein the isolation structure has a first source / drain feature and a second source / drain feature disposed on both sides of the isolation structure among the plurality of source / drain features. Attached Figure Description

[0008] The various aspects of this disclosure can be best understood by reading the following detailed description in conjunction with the accompanying drawings. Note that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0009] Figure 1 A simplified top view layout diagram of a multi-gate device according to some embodiments is provided;

[0010] Figure 2 Exemplary circuit diagrams of SRAM cells according to some embodiments are provided;

[0011] Figure 3 This is a flowchart of a method for manufacturing a storage device according to one or more aspects of this disclosure;

[0012] Figure 4A , Figure 4B , Figure 4C , Figure 4D and Figure 4E Embodiments of storage devices according to some embodiments are provided in accordance with Figure 3 Top view of each manufacturing stage of the method;

[0013] Figure 5 This is a flowchart of an alternative method for manufacturing a storage device according to one or more aspects of this disclosure;

[0014] Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 6E , Figure 6F , Figure 6G and Figure 6H Embodiments of storage devices according to some embodiments are provided in accordance with Figure 5 Top view of each manufacturing stage of the method;

[0015] Figure 7 This is a flowchart of a method for manufacturing a semiconductor device according to one or more aspects of this disclosure;

[0016] Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A and Figure 13A Examples of semiconductor devices are provided in accordance with Figure 7 The various manufacturing stages of the method are along with Figure 1 A cross-sectional view of a plane that is substantially parallel to the plane defined by section AA';

[0017] Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B and Figure 13B The figure illustrates an embodiment of a semiconductor device according to Figure 7 The various manufacturing stages of the method are along with Figure 1 A cross-sectional view of a plane that is substantially parallel to the plane defined by the cross section BB';

[0018] Figure 14 This is a flowchart of an alternative method for manufacturing a semiconductor device according to one or more aspects of this disclosure;

[0019] Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A , Figure 21A , Figure 22A , Figure 23A , Figure 24A , Figure 25A , Figure 26A , Figure 27A , Figure 28A , Figure 29A , Figure 30A and Figure 31A Examples of semiconductor devices are provided in accordance with Figure 14 The various manufacturing stages of the method are along with Figure 1 A cross-sectional view of a plane that is substantially parallel to the plane defined by section AA';

[0020] Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B , Figure 20B , Figure 21B , Figure 22B , Figure 23B , Figure 24B , Figure 25B , Figure 26B , Figure 27B , Figure 28B , Figure 29B , Figure 30B and Figure 31B Examples of semiconductor devices are provided in accordance with Figure 14 The various manufacturing stages of the method are along with Figure 1 A cross-sectional view of a plane that is substantially parallel to the plane defined by the cross section BB'. Detailed Implementation

[0021] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature can include embodiments where the first and second features are formed in direct contact, and can also include embodiments where an additional feature can be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0022] Furthermore, this document may use spatially relevant terms (e.g., "below," "below," "lower than," "higher than," "upper," etc.) to readily describe the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially relevant terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relevant descriptors used herein may be interpreted accordingly.

[0023] Furthermore, in the following discussion, the dimensions of a given layer or other feature (e.g., thickness, width, length, etc.) may sometimes be described using terms such as “substantially equal,” “equal,” or “approximately,” where these terms are understood to mean that the value is within + / - 10% or between comparison values. For example, if dimension A is described as “substantially equal” to dimension B, it will be understood that dimension A is within + / - 10% of dimension B. As another example, if a layer is described as having a thickness of approximately 100 nm, it will be understood that the thickness of the layer could be in the range of 90-110 nm.

[0024] It should also be noted that embodiments of multi-gate transistors are presented herein, which can be used in any of a variety of device types and / or circuit types. Multi-gate transistors include transistors in which gate structures are formed on at least two sides of a channel region. These multi-gate devices may include P-type transistors or N-type transistors. Specific examples may be proposed herein based on their finned structures or referred to herein as fin field-effect transistors (FinFETs). FinFET devices may include fins (or nanostructures extending from a substrate) wherein the fins are composed of substantially uniform components. Embodiments of a class of multi-gate transistors referred to herein as gate-all-around (GAA) transistors are also proposed herein. GAA transistors include any device in which a gate structure or a portion thereof is formed on four sides of a channel region (e.g., around a portion of the channel region). Devices proposed herein also include embodiments having channel regions disposed in various nanostructures, such as one or more nanosheet channels, one or more nanowire channels, one or more strip channels, and / or other suitable channel configurations. Embodiments of devices proposed herein may have one or more nanostructured channel regions (e.g., nanowires / nanosheets) associated with a single continuous gate structure. GAA devices may include multiple stacked channel layers (e.g., multiple stacked nanosheets) that form the channels of the GAA transistor. However, those skilled in the art will recognize that the teachings disclosed herein are applicable to a single channel (e.g., a single nanowire / nanosheet) or any number of channels. Other examples of semiconductor devices that may benefit from the aspects of this disclosure will be recognized by those skilled in the art.

[0025] This disclosure generally relates to minimizing layout-dependent effects (LDEs) in state-of-the-art CMOS circuits to meet demanding scaling requirements. More specifically, aspects of this disclosure relate to forming isolation structures in a highly symmetric process environment to minimize LDEs. During the fabrication of semiconductor circuits, various isolation patterning processes can be performed to isolate metal lines and / or active regions to define circuit patterns. In some prior art implementations, isolation patterning processes are not optimal and lead to increased LDEs. For example, during the fabrication of static random access memory (SRAM) circuits, active regions (where device channels are formed) may be cut (isolated) before the formation of dummy multi-gates, resulting in an asymmetric or non-uniform wafer environment composed of broken active regions. This asymmetry generates stress and leads to deterioration of the line edge roughness (LER) of the active regions. Dummy multi-gates can then be formed over the asymmetric or cut active regions, which leads to deterioration of the polysilicon LER. Subsequently, epitaxial source / drain features can be formed, wherein these source / drain features can be designed to provide stress to the device channels. However, due to the asymmetric or non-uniform wafer environment in which epitaxial source / drain features are formed, the stress applied to the source / drain features may be lost, and device performance may degrade accordingly. After forming the epitaxial source / drain features, dummy multiple gates can be replaced with metal gate stacks. However, in some cases, metal gate stacks may suffer from metal gate tilting due to the asymmetric or non-uniform wafer environment. A metal gate patterning process (metal gate dicing process) can then be performed to form isolation regions that isolate different portions of the different metal gate stacks. This gate patterning process can lead to high parasitic capacitance, for example, because the metal layers of adjacent metal gate stacks located on opposite sides of the respective isolation regions are very close. Therefore, the prior art has not yet proven to be completely satisfactory in all aspects.

[0026] The embodiments disclosed herein offer advantages over the prior art, but it should be understood that other embodiments may offer different advantages, not all of which are necessarily discussed herein, and no particular advantage is necessary for all embodiments. For example, embodiments discussed herein include methods and structures for performing isolation patterning processes in highly scaled CMOS circuits to address various existing challenges, such as minimizing LDEs. While not limited thereto, aspects of this disclosure can be used to perform isolation structures in SRAM circuits, thereby patterning SRAM circuits. In various embodiments, the disclosed isolation patterning processes can be performed using a diffused edge continuous metal (CMODE) patterning process, a diffused edge continuous polysilicon (CPODE) patterning process, or a combination of a CPODE patterning process and a cut metal gate (CMG) patterning process. As part of the CMODE process, and after the formation of the metal gate stack, trenches may be formed as a portion of the metal gate stack and extend into the substrate, and the trenches are filled with a dielectric material to provide isolation between adjacent portions of the metal gate stack. As part of the CPODE process, after forming the dummy multi-gate and before forming the metal gate stack, a trench can be formed to extend through a portion of the dummy multi-gate and into the substrate, and the trench is filled with a dielectric material to provide isolation between adjacent portions of the dummy multi-gate. In some cases, after performing the CPODE process and replacing the dummy multi-gate with a metal gate stack, a CMG process can be performed to remove the high-k gate dielectric portion from the metal line-end regions of the metal gate stack in order to reduce parasitic capacitance by minimizing the metal boundary effect (MBE).

[0027] Reconsidering the example of fabricating SRAM circuits, according to some embodiments, the fabrication process employing CMODE patterning includes: (i) not patterning (not dicing) the active region prior to forming the dummy multi-gate, thereby maintaining a symmetrical or uniform wafer environment on which the dummy multi-gate is formed and providing an improved polysilicon LER; (ii) forming epitaxial source / drain features in a symmetrical or uniform wafer environment, which minimizes the loss of stress exerted by the source / drain features; (iii) replacing the dummy multi-gate with a metal gate stack; and (iv) CMODE patterning to provide isolation between adjacent portions of the metal gate stack. Due to the symmetrical or uniform wafer environment including the metal gate stack, the risk of metal gate tilt is also minimized.

[0028] In another example of SRAM circuit fabrication, according to some embodiments, the fabrication process employing the CPODE patterning process includes: (i) not patterning the active region prior to forming the dummy multi-gate to maintain a symmetrical or uniform wafer environment on which the dummy multi-gate is formed, thereby providing an improved polysilicon LER; (ii) forming epitaxial source / drain features in a symmetrical or uniform wafer environment, which minimizes the loss of stress exerted by the source / drain features; (iii) CPODE patterning to provide isolation between adjacent portions of the dummy multi-gate; (iv) replacing the dummy multi-gate with a metal gate stack; and (iv) optionally performing CMG patterning to remove high-k gate dielectric portions from the metal line-end regions of the metal gate stack in order to reduce parasitic capacitance by minimizing MBE. Therefore, embodiments of this disclosure effectively reduce LDE compared to prior art. Other embodiments and advantages will be apparent to those skilled in the art upon reading this disclosure.

[0029] Since one or more embodiments described herein use multi-gate transistors (e.g., FinFET or GAA devices) and SRAM devices for illustrative purposes, the following description incorporates... Figure 1 and Figure 2 A description of such devices is provided. However, it should be understood that the descriptions given below in conjunction with multi-gate transistors and SRAM devices are merely exemplary, and other types of devices and / or circuits may benefit from one or more embodiments described herein.

[0030] Figure 1 A simplified top view of a multi-gate device 100 is provided. In various embodiments, the multi-gate device 100 may include a FinFET device, a GAA device, or other types of multi-gate devices. The multi-gate device 100 may include a plurality of fin elements 104 extending from a substrate, a gate structure 108 disposed on and around the fin elements 104, and source / drain regions 105, 107, wherein the source / drain regions 105, 107 are formed within, on, and / or around the fin elements 104. A channel region of the multi-gate device 100 is disposed within the fins 104, below the gate structure 108, and along the... Figure 1 The plane defined by the AA' cross section is a substantially parallel plane. When the multi-gate device 100 includes a FinFET device, the channel region may include fins (or nanostructures) extending from the substrate, wherein the fins (or nanostructures) are composed of a substantially uniform composition. When the multi-gate device 100 includes a GAA device, the channel region may include multiple semiconductor channel layers (e.g., multiple stacked nanostructures or stacked nanosheets). In some embodiments, sidewall spacers may also be formed on the sidewalls of the gate structure 108. The following is in conjunction with... Figure 3 , Figure 5 , Figure 7 and Figure 14 The method will be discussed in more detail regarding various other features of the multi-gate device 100.

[0031] refer to Figure 2 The illustration shows an exemplary circuit diagram of an SRAM cell 200 according to various aspects of the present disclosure, which can be implemented in the memory cells of an SRAM array. Although Figure 2 A single-port SRAM cell is shown, but it will be understood that the various embodiments disclosed can also be implemented in multi-port SRAM cells (e.g., dual-port SRAM cells) without departing from the scope of this disclosure. Simplifications have been made for clarity. Figure 2 This is to better understand the inventive concept of this disclosure. Other features may be added to the SRAM cell 200, and some features described below may be replaced, modified, or eliminated in other embodiments of the SRAM cell 200.

[0032] SRAM cell 200 includes six transistors: pass-gate transistor PG-1, pass-gate transistor PG-2, pull-up transistor PU-1, pull-up transistor PU-2, pull-down transistor PD-1, and pull-down transistor PD-2. Therefore, in some examples, SRAM cell 200 may be referred to as a 6T SRAM cell. During operation, pass-gate transistors PG-1 and PG-2 access a storage portion of SRAM cell 200, which includes a pair of cross-coupled inverters, inverter 210 and inverter 220. Inverter 210 includes pull-up transistor PU-1 and pull-down transistor PD-1, and inverter 220 includes pull-up transistor PU-2 and pull-down transistor PD-2. In some embodiments, pull-up transistors PU-1 and PU-2 are configured as P-type transistors (e.g., FinFET or GAA devices), and pull-down transistors PD-1 and PD-2 are configured as N-type transistors (e.g., FinFET or GAA devices). In some implementations, the transfer gate transistors PG-1 and PG-2 are also configured as N-type transistors (e.g., FinFET or GAA devices).

[0033] The gate of pull-up transistor PU-1 is located between its source (electrically coupled to the power supply voltage (VDD)) and the first common drain (CD1), and the gate of pull-down transistor PD-1 is located between its source (electrically coupled to the power supply voltage (VSS)) and the first common drain. The gate of pull-up transistor PU-2 is located between its source (electrically coupled to the power supply voltage (VDD)) and the second common drain (CD2), and the gate of pull-down transistor PD-2 is located between its source (electrically coupled to the power supply voltage (VSS)) and the second common drain. In some embodiments, the first common drain (CD1) is a storage node (SN) that stores data in physical form, and the second common drain (CD2) is a storage node (SNB) that stores data in complementary form. The gates of pull-up transistor PU-1 and pull-down transistor PD-1 are coupled to the second common drain, and the gates of pull-up transistor PU-2 and pull-down transistor PD-2 are coupled to the first common drain. The gate of transfer gate transistor PG-1 is located between its source (electrically coupled to bit line BL) and drain, the drain being electrically coupled to a first common drain. The gate of transfer gate transistor PG-2 is located between its source (electrically coupled to complementary bit line BLB) and drain, the drain being electrically coupled to a second common drain. The gates of transfer gate transistors PG-1 and PG-2 are electrically coupled to word line WL. In some embodiments, transfer gate transistors PG-1 and PG-2 can access memory nodes SN and SNB during read and / or write operations. For example, transfer gate transistors PG-1 and PG-2 couple memory nodes SN and SN-B to bit lines BL and BLB, respectively, in response to a voltage applied to the gates of transfer gate transistors PG-1 and PG-2 by WL.

[0034] Based on the above references Figure 1 and Figure 2 Following the discussion, various embodiments of this disclosure will now be described. It will be understood that the accompanying drawings and any related descriptions given are merely exemplary and not intended to limit the scope beyond what is specifically set forth in the following claims. Furthermore, the drawings shown and described have been simplified for clarity to better understand the inventive concept of this disclosure, and various features may be added, substituted, modified, or eliminated without departing from the scope of this disclosure.

[0035] Now for reference Figure 3 The illustration depicts a semiconductor manufacturing method 300 according to various embodiments, including fabricating a memory device 400 (e.g., including SRAM circuitry) using a CMODE patterning process. References below... Figures 4A-4E Description method 300, Figures 4A-4EAn embodiment of the memory device 400 is provided with top views at various manufacturing stages according to method 300. It will be understood that aspects of method 300 can be applied to devices or circuits implemented using various types of multi-gate devices, such as FinFETs, GAA transistors (or nanosheet transistors), other types of advanced transistor devices, or combinations thereof, without departing from the scope of this disclosure. In some embodiments, method 300 can be used to manufacture the above-referenced... Figure 1 The multi-gate device 100 or more references Figure 2 The SRAM cell 200 is described above. Therefore, one or more aspects discussed above with reference to the multi-gate device 100 or the SRAM cell 200 are also applicable to method 300 and memory device 400. It will be understood that method 300 includes steps characteristic of CMOS technology process flows, and therefore these steps are described only briefly herein. Furthermore, additional steps may be performed before, after, and / or during method 300.

[0036] It should also be noted that in some embodiments, the storage device 400 may include various other devices and features, such as other types of devices like additional transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses, and / or other logic circuits, etc., but these are simplified to better understand the inventive concept of this disclosure. In some embodiments, the storage device 400 may include multiple semiconductor devices (e.g., transistors) that may be interconnected to form a circuit, such as an SRAM circuit. Furthermore, it should be noted that the process steps of method 300 (including any descriptions given with reference to the accompanying drawings) are merely exemplary and are not intended to be limiting beyond what is specifically set forth in the following claims.

[0037] Method 300 begins at block 302, where an active region is defined in the substrate. (See reference) Figure 4AIn the embodiment of block 302, active regions 402 and 404 are defined. In the example, active regions 402 and 404 extend along the X direction, as shown. Active regions 402 and 404 include regions in which transistor channels and epitaxial source / drain features will be formed. In the illustrated example, active region 402 may be formed in N-type device region 403, and active region 404 may be formed in P-type device region 405. In various embodiments, the respective active regions in active regions 402 and 404 may be separated from each other by shallow trench isolation (STI) features. In some cases, such as when FinFET is used to fabricate memory device 400, active regions 402 and 404 may include fins (or nanostructures) extending from the substrate, wherein the fins are composed of a substantially uniform composition. In other examples, such as when a GAA transistor (or nanosheet transistor) is used to fabricate memory device 400, active regions 402, 404 may include multiple stacked channel layers (or multiple stacked nanosheets) stacked on a substrate to form the channels of the GAA transistor. Also note that after forming active regions 402, 404, active regions 402, 404 are not patterned (or cut). Therefore, as... Figure 4A As shown in the top view, active regions 402 and 404 provide a symmetrical pattern in both the X and Y directions on the substrate below. In other words, the process environment (including the terrain defined by the features formed on the substrate below) is symmetrical. In this example, the symmetrical process environment (such as...) Figure 4A The top view (shown herein) includes an array of repeating shapes (or repeating patterns) consisting of active regions 402, 404. During processing of the storage device 400 and according to the embodiments disclosed herein, the symmetrical process environment can effectively reduce LDE compared to prior art implementations.

[0038] Memory device 400 and active regions 402, 404 may be formed on a substrate, as described above. In some embodiments, the substrate may be a semiconductor substrate, such as a silicon substrate. The substrate may include various layers, including conductive or insulating layers formed on the semiconductor substrate. The substrate may include various doping configurations, depending on design requirements known in the art. The substrate may also include other semiconductors, such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. Alternatively, the substrate may include compound semiconductors and / or alloy semiconductors. Furthermore, the substrate may optionally include an epitaxial layer (epi layer), which may be strained to improve performance, and may include a silicon-on-insulator (SOI) structure, and / or have other suitable enhancing features.

[0039] Method 300 continues to block 304, where a dummy gate structure is formed. (See reference) Figure 4A and Figure 4BIn the embodiment of block 304, a plurality of dummy gate structures 406 are formed over the active regions 402, 404. As shown, the dummy gate structures 406 extend in the Y direction, which is perpendicular to the direction (X direction) in which the active regions 402, 404 extend. In some embodiments, the dummy gate structures 406 each include a dummy gate dielectric and a dummy gate electrode. The dummy gate dielectric includes a dielectric material, such as silicon oxide, a high-k dielectric material, other suitable dielectric materials, or combinations thereof. The dummy gate electrode includes a suitable dummy gate material, such as polysilicon. In various embodiments, the dummy gate structures 406 will have good polysilicon line edge roughness (LER) due to the symmetrical process environment provided by the symmetrical pattern of the active regions 402, 404 on which the dummy gate structures 406 are formed. The dummy gate structures 406 are replaced with a high-k / metal gate stack in a later processing stage, for example, as part of a gate replacement process. Note that after the formation of the dummy gate structures 406, as Figure 4B As shown in the top view, the dummy gate structure 406 and active regions 402, 404 maintain a symmetrical pattern in both the X and Y directions. In other words, the process environment remains symmetrical after the formation of the dummy gate structure 406 and continues to benefit subsequent processing, as described below. In this example, the symmetrical process environment (such as...) Figure 4B The top view shows a first repeating shape array (composed of active regions 402 and 404) and a second repeating shape array (composed of a dummy gate structure 406).

[0040] Method 300 continues to box 306, where source / drain features are formed. (See reference) Figure 4B and Figure 4C In the embodiment of block 306, after forming the dummy gate structure 406, source / drain features are formed in the source / drain regions adjacent to and located on both sides of the dummy gate structure 406. For example, source / drain features 408 may be formed in the N-type device region 403 above the active region 402, on both sides of the dummy gate structure 406, and in contact with the channel region of the N-type transistor (e.g., an N-type FinFET or an N-type GAA device) formed in the N-type device region 403. Similarly, source / drain features 410 may be formed in the P-type device region 405 above the active region 404, on both sides of the dummy gate structure 406, and in contact with the channel region of the P-type transistor (e.g., a P-type FinFET or a P-type GAA device) formed in the P-type device region 405. More specifically, a symmetrical process environment is maintained by forming source / drain features (source / drain feature 408 or source / drain feature 410) on the corresponding active regions 402, 404 on both sides of each dummy gate structure 406.

[0041] In some embodiments, source / drain features 408, 410 are formed by epitaxially growing a semiconductor material layer in the source / drain region. In various embodiments, the semiconductor material layer grown to form source / drain features 408, 410 may include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable materials. Source / drain features 408, 410 may be formed by one or more epitaxial (epi) processes. In some embodiments, source / drain features 408, 410 may be in-situ doped during the epitaxial process. For example, in some embodiments, epitaxially grown SiGe source / drain features may be doped with boron. In some cases, epitaxially grown Si epitaxial source / drain features may be doped with carbon to form Si:C source / drain features, doped with phosphorus to form Si:P source / drain features, or doped with both carbon and phosphorus to form SiCP source / drain features. In some embodiments, the source / drain features 408 and 410 are not doped in situ, but rather doped by an implantation process.

[0042] In various embodiments, due to the symmetrical process environment provided by the symmetrical patterning of the dummy gate structure 406 and the active regions 402, 404, the formation of the source / drain features 408, 410 can be performed with minimal stress loss applied to the channel regions of the corresponding transistors in the N-type and P-type transistors by the source / drain features 408, 410. After the formation of the source / drain features 408, 410, as Figure 4C As shown in the top view, the source / drain features 408, 410, the dummy gate structure 406, and the active regions 402, 404 maintain a symmetrical pattern in both the X and Y directions. In other words, the process environment remains symmetrical after the source / drain features 408, 410 are formed. In this example, the symmetrical process environment (such as...) Figure 4C The top view shows a first repeating shape array (composed of active regions 402 and 404), a second repeating shape array (composed of a dummy gate structure 406), and a third repeating shape array (composed of source / drain features 408 and 410).

[0043] Method 300 continues to block 308, where a gate replacement process is performed. (See reference...) Figure 4C and Figure 4DIn the embodiment of block 308, after forming the source / drain features 408, 410, the dummy gate structure 406 is replaced with a high-k / metal gate stack. For example, the dummy gate structures 406 (including the respective dummy gate electrode and dummy gate dielectric of each dummy gate structure 406) can initially be removed using an appropriate etching process. In some examples, the dummy gate electrode and dummy gate dielectric of each dummy gate structure 406 can be removed using an appropriate etching process (e.g., wet etching, dry etching, or a combination thereof). In some cases, such as in embodiments forming GAA transistors, a channel release process can be performed after removing the dummy gate structure 406 to remove the dummy epitaxial layer (e.g., Si layer) disposed between the channel epitaxial layers (e.g., Si layer). After removing the dummy gate structure 406, in another embodiment of block 308, a high-k / metal gate stack 412 is formed in the substrate region previously occupied by the dummy gate structure 406. In some embodiments, the high-k / metal gate stack 412 includes an interface layer (IL) and a high-k dielectric layer 414 formed on the IL. The high-k gate dielectric used and described herein includes dielectric materials having a high dielectric constant, for example, a high dielectric constant greater than that of thermally oxidized silicon (~3.9).

[0044] In some embodiments, the IL may include a dielectric material, such as silicon oxide (SiO2), HfSiO, or silicon oxynitride (SiON). In some embodiments, the high-K dielectric layer 414 may include hafnium oxide (HfO2). Alternatively, the high-K dielectric layer 414 may include other high-K dielectrics, such as TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3 (BST), Al2O3, Si3N4, silicon oxynitride (SiON), combinations thereof, or other suitable materials. In various embodiments, the IL and high-k dielectric layer 414 may be formed by thermal oxidation, ALD, physical vapor deposition (PVD), pulsed laser deposition (PLD), CVD and / or other suitable methods.

[0045] In another embodiment of block 308, the high-k / metal gate stack 412 further includes a metal gate comprising a metal layer 416 formed over the gate dielectric (e.g., over the IL and high-k dielectric layer 414). The metal layer 416 may comprise a metal, a metal alloy, or a metal silicide. Furthermore, the formation of the gate dielectric / metal gate stack may include deposition to form various gate materials, one or more pad layers, and one or more CMP processes. In some embodiments, the metal layer 416 may comprise a single-layer or multi-layer structure, such as a metal layer having a selected work function to improve device performance (work function metal layer), a pad layer, a wetting layer, an adhesion layer, a metal alloy, or a combination of metal silicides. For example, the metal layer 416 may comprise Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, Re, Ir, Co, Ni, other suitable metallic materials, or combinations thereof. In various embodiments, metal layer 416 can be formed by ALD, PVD, CVD, electron beam evaporation, or other suitable processes. Furthermore, metal layer 416 can be formed separately for use in N-type and P-type transistors that can utilize different metal layers. Additionally, metal layer 416 can provide N-type or P-type work function, can be used as a transistor gate electrode, and in at least some embodiments, metal layer 416 may comprise a polysilicon layer.

[0046] After forming the high-K / metal gate stack 412, as Figure 4D As shown in the top view, the high-k / metal gate stack 412, source / drain features 408, 410, and active regions 402, 404 maintain a symmetrical pattern in both the X and Y directions. In other words, the process environment remains symmetrical after the high-k / metal gate stack 412 is formed. In this example, the symmetrical process environment (such as...) Figure 4D The top view (shown) includes a first repeating shape array (composed of active regions 402, 404), a third repeating shape array (composed of source / drain features 408, 410), and a fourth repeating shape array (composed of a high-K / metal gate stack 412). Furthermore, due to the metallic stiffness of the metal layer 416, potential wafer deformation caused by subsequent patterning processes (e.g., CMODE patterning process) can be avoided.

[0047] Method 300 continues to box 310, where the CMODE patterning process is performed. (See reference) Figure 4D and Figure 4EIn the embodiment of block 310, following the gate replacement process of block 308, the high-k / metal gate stack 412 is patterned to define a circuit pattern for the memory device 400 (e.g., a circuit pattern for defining SRAM circuitry). Specifically, the metal layer 416 of the high-k / metal gate stack is diced / patterned to define the circuit pattern. For example, as part of a CMODE patterning process, an isolation structure 420 is formed. Typically, in various embodiments, the CMODE patterning process includes forming trenches through portions of the high-k / metal gate stack 412, the trenches extending into the underlying substrate. The trenches are then filled with one or more dielectric materials (e.g., low-k dielectric materials in some embodiments) to form the isolation structure 420, thereby providing isolation between adjacent portions of the metal layer 416 of the respective high-k / metal gate stack 412. In some embodiments, the CMODE patterning process may be performed as part of a middle-end-of-line (MEOL) process. References are made below. Figure 7 The method describes a more detailed process flow for the CMODE patterning process. As described in further detail below, the isolation structure 420 can extend deeper into the underlying substrate than the STI features used to separate adjacent active regions 402, 404. Due to the symmetrical process environment and the metallic stiffness of the metal layer 416 present prior to the CMODE patterning process, potential wafer warping (e.g., metal gate tilt) can be reduced.

[0048] In some embodiments, for example, compared to isolation structures formed using CMG patterning, the isolation structure 420 formed by CMODE patterning provides a much larger distance between adjacent portions of the metal layer 416 of the corresponding high-k / metal gate stack 412, thereby reducing parasitic capacitance. Figure 4EAs shown in the example, the isolation structure 420 extends a distance D1 in the Y direction, which is the same direction in which the high-K / metal gate stack 412 extends. In some examples, distance D1 is equal to or greater than distance D2, which can be the distance that adjacent source / drain features (which, depending on the location where the isolation structure 420 is formed, could be source / drain feature 410 or source / drain feature 408) extend in the Y direction. In other words, the dimension of the isolation structure 420 in the Y direction (e.g., the distance D1 that the isolation structure 420 extends in the Y direction) is equal to or greater than the dimension of adjacent source / drain features in the Y direction (e.g., the distance D2 that adjacent source / drain features extend in the Y direction). Since capacitance is inversely proportional to the distance between metal layers, the increased distance D1 provided by the isolation structure 420 can reduce parasitic capacitance between some portions of the metal layers 416 disposed on both sides of the isolation structure 420 (e.g., in the Y direction). Also note that in some embodiments, the width W2 of the isolation structure 420 can be substantially equal to the width of the high-K / metal gate stack 412. In some embodiments, the width of the high-K / metal gate stack 412 may further include the width of spacers (sidewall spacers) formed on the sidewalls of the high-K / metal gate stack 412. In an example, the width W2 may be in the range of about 10-20 nm. In some alternative embodiments, the width of the isolation structure 420 is not equal to the width of the high-K / metal gate stack 412. For example, the width of the isolation structure 420 may be greater than the width of the high-K / metal gate stack 412 because at least some sidewall spacer loss may occur during the etching process. For example, in some cases, the ratio of the width of the isolation structure 420 to the width of the high-K / metal gate stack 412 may be in the range of about 1.5 to 2.5.

[0049] Following the CMODE patterning process of box 310, different portions of the circuit (e.g., SRAM circuitry) are defined. For example, as Figure 4E As shown, inverter 422 can be defined. Each inverter 422 includes a pull-up (PU) transistor 424 and a pull-down (PD) transistor 426, similar to the reference above. Figure 2 The inverters 210 (composed of PU-1 and PD-1) and 220 (composed of PU-2 and PD-2) are described. The PU transistor 424 is configured as a P-type transistor (e.g., a FinFET or GAA transistor), and the PD transistor 426 is configured as an N-type transistor (e.g., a FinFET or GAA transistor). Specifically, the PU transistor 424 is formed within a P-type device region 405 formed over the active region 404 and with source / drain features 410 on both sides of the high-K / metal gate stack 412. Similarly, the PD transistor 426 is formed within an N-type device region 403 formed over the active region 402 and with source / drain features 408 on both sides of the high-K / metal gate stack 412. Furthermore, still referring to… Figure 4E This can define the transfer gate (PG) transistor 428. The PG transistor 428 is similar to the one referenced above. Figure 2 The PG-1 and PG-2 mentioned above. Each PG transistor 428 is configured as an N-type transistor (e.g., a FinFET or GAA transistor). Specifically, the PG transistor 428 is formed within an N-type device region 403 formed on the active region 402 and with source / drain features 408 on both sides of the high-k / metal gate stack 412. Although Figure 4E The example illustrates a PG transistor 428 formed in an N-type device region 403 having a single active region 402, but other embodiments are possible. For example, if the N-type device region 403 instead has two active regions 402, a CMODE / CPODE patterning process or a CMG patterning process can be used to separate the portion of the high-k / metal gate stack between the two active regions 402. In some embodiments, a similar process can be used to form a PG transistor in a P-type device region 405. Furthermore, in some embodiments, if an N-type transistor is used for the PG transistor, the P-type PG transistor can be disabled / electrically isolated using a CMODE / CPODE patterning process; and vice versa if a P-type transistor is used for the PG transistor.

[0050] Method 300 continues to block 312, where further processing is performed. For example, in an embodiment of block 312, back-end-of-line (BEOL) routing may be performed. BEOL routing may include forming various conductive features to interconnect portions of a circuit (e.g., portions of an SRAM circuit) previously patterned / defined by a CMODE patterning process. Specifically, BEOL routing may include forming a multilevel interconnect (MLI) structure that includes various conductive features, which may be vertical interconnects (e.g., contacts and / or vias) and / or horizontal interconnects (e.g., conductive lines). In some embodiments, BEOL routing may be used to reference... Figure 2 The inverter 422 and PG transistor 428 are connected in the manner shown and described to define the SRAM cell. Consider the N-type and P-type transistor arrays provided in the memory device 400, such as... Figure 4EAs shown, memory device 400 can obviously be composed of multiple SRAM cells. Furthermore, it will be understood that in some embodiments, certain source / drain characteristics may be shared between adjacent transistors. Moreover, while the exemplary SRAM described above is shown and described as a 6T SRAM, other embodiments are possible. Typically, in various embodiments, different numbers of inverters (e.g., inverter 422), with or without pass-gate transistors, can be formed to create other types of memory devices (e.g., 4T SRAM, 8T SRAM, etc.) and other types of logic devices and / or logic circuits.

[0051] As previously described, the memory device 400 can be implemented using various types of multi-gate devices, such as FinFETs, GAA transistors (or nanosheet transistors), and other types of advanced transistor devices. Also as discussed, when a FinFET is used to fabricate the memory device 400, the active regions 402, 404 may include fins (composed of substantially uniform composition) extending from the substrate, and when a GAA transistor (or nanosheet transistor) is used to fabricate the memory device 400, the active regions 402, 404 may include multiple stacked channel layers (or multiple stacked nanosheets) stacked on the substrate to form the channels of the GAA transistor.

[0052] To elaborate on this discussion, in various embodiments, SRAM operating margin and performance may be degraded due to the mismatch between the N-type and P-type transistors used as pull-down (N-type), pull-up (P-type), and pass-gate (N-type) transistors. In some cases, this mismatch can occur due to differences between electron and hole mobilities. Therefore, in some embodiments, and in order to improve SRAM operating margin and performance, it is desirable to adjust the transistor dimensions based on the mobility ratio between the N-type and P-type transistors to match the N-type and P-type transistors. Depending on whether FinFET or GAA transistors are used to manufacture the memory device 400, the N-type and P-type transistor matching can be performed differently.

[0053] Consider the example of FinFETs being used in the manufacture of memory device 400, in such... Figure 4EBefore N / P matching in the example, each of the N-type and P-type transistors includes a single fin (e.g., a single active region 402, 404 for each transistor). To provide N / P matching, if the mobility ratio of the N-type and P-type transistors is approximately X:Y, the area ratio of the N-type fin to the P-type fin can be adjusted to approximately Y:X. As just an example, if the mobility ratio of the N-type and P-type transistors is approximately 3:2, the area ratio of the N-type fin to the P-type fin can be adjusted to approximately 2:3 to provide N / P matching. In the case of FinFET, this area ratio adjustment can be achieved by changing the number of fins (the number of active regions) used to implement the respective N-type and P-type transistors. Therefore, for example, when the mobility ratio of N-type and P-type transistors is approximately 3:2, an N-type transistor (e.g., for pull-down and transfer gate transistors) can be implemented using two fins (two parallel active regions 402, a single high-K / metal gate stack 412, and single source / drain features 408 on either side of the single high-K / metal gate stack 412, which are combined across multiple fins), and a P-type transistor (e.g., for pull-up transistors) can be implemented using three fins (three parallel active regions 404, a single high-K / metal gate stack 412, and single source / drain features 410 on either side of the single high-K / metal gate stack 412, which are combined across multiple fins) to provide N / P matching by ensuring an N / P area ratio of 2:3.

[0054] Consider the example of GAA transistors being used in the manufacture of memory device 400, in such cases... Figure 4E Prior to N / P matching in the example, each of the N-type and P-type transistors includes a stacked nanosheet (e.g., active regions 402, 404 with width W1) having a width W1. To provide N / P matching, if the mobility ratio of the N-type and P-type transistors is approximately X:Y, the area ratio of the nanosheets of the N-type and P-type devices can be adjusted to approximately Y:X. As just one example, if the mobility ratio of the N-type and P-type transistors is approximately 3:2, the area ratio of the nanosheets of the N-type and P-type devices can be adjusted to approximately 2:3 to provide N / P matching. In the case of GAA transistors, this area ratio adjustment can be achieved by changing the width W1 of the stacked nanosheets used to implement the respective N-type and P-type transistors. Thus, for example, when the mobility ratio of the N-type and P-type transistors is approximately 3:2, the N-type transistor (e.g., for pull-down and transfer gate transistors) and the P-type transistor can be implemented using nanosheets with a stacked nanosheet width ratio of approximately 2:3 to provide N / P matching.

[0055] refer to Figure 5The illustration depicts a semiconductor manufacturing method 500 according to various embodiments, including fabricating a memory device 600 (e.g., including SRAM circuitry) using a CPODE patterning process. References below... Figures 6A-6H Description method 500, Figures 6A-6H An embodiment of the memory device 600 is provided with top views at various manufacturing stages according to method 500. It will be understood that aspects of method 500 can be applied to devices or circuits implemented using various types of multi-gate devices, such as FinFETs, GAA transistors (or nanosheet transistors), other types of advanced transistor devices, or combinations thereof, without departing from the scope of this disclosure. In some embodiments, method 500 can be used to manufacture the above-referenced... Figure 1 The multi-gate device 100 or more references Figure 2 The SRAM cell 200 is described above. Therefore, one or more aspects discussed above with reference to the multi-gate device 100 or the SRAM cell 200 are also applicable to method 500 and memory device 600. It will be understood that method 500 includes steps characteristic of CMOS technology process flows, and therefore these steps are described only briefly herein. Furthermore, additional steps may be performed before, after, and / or during method 500.

[0056] It should also be noted that in some embodiments, the storage device 600 may include various other devices and features, such as other types of devices, such as additional transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses, and / or other logic circuits, etc., but these are simplified to better understand the inventive concept of this disclosure. In some embodiments, the storage device 600 may include multiple semiconductor devices (e.g., transistors) that may be interconnected to form a circuit, such as an SRAM circuit. Furthermore, it should be noted that the process steps of method 500 (including any descriptions given with reference to the accompanying drawings) are merely exemplary and are not intended to be limiting beyond what is specifically set forth in the following claims. Moreover, method 500 is similar in various respects to method 300 discussed above. Therefore, some aspects of method 500 that have been previously described in the discussion of method 300 are described only briefly below. Furthermore, for clarity of discussion, reference numerals used in the discussion of method 300 may be repeated hereinafter in the discussion of method 500.

[0057] Method 500 begins with the execution of step sequence 502. Step sequence 502 may include blocks 302, 304, and 306 of method 300 discussed above. Therefore, refer to Figure 6A In the embodiment of block 302 of step sequence 502, active region 402 and active region 404 are initially defined, as discussed above with reference to method 300. Figure 6A In the top view, as in Figure 4AIn the top view (corresponding to block 302 of method 300), the symmetrical process environment includes a repeating shape array (or repeating pattern) composed of active regions 402, 404. Next, refer to... Figure 6B In the embodiment of block 304 of step sequence 502, a plurality of dummy gate structures 406 are formed over the active regions 402, 404, as discussed above with reference to method 300. As previously described, the dummy gate structures 406 will have a good polysilicon LER due to the symmetrical process environment provided by the symmetrical pattern of the active regions 402, 404 on which the dummy gate structures 406 are formed. Figure 6B In the top view, as in Figure 4B In the top view (corresponding to block 304 of method 300), the symmetrical process environment includes a first repeating shape array (composed of active regions 402, 404) and a second repeating shape array (composed of dummy gate structure 406). Hereafter, refer to... Figure 6C In the embodiment of block 306 of step sequence 502, source / drain features 408, 410 are formed in the source / drain regions adjacent to and located on both sides of the dummy gate structure 406 within the N-type device region 403 and the P-type device region 405, as discussed above with reference to method 300. As previously described, due to the symmetrical process environment provided by the symmetrical pattern of the dummy gate structure 406 and the active regions 402, 404, the formation of the source / drain features 408, 410 can be performed with minimal stress loss applied to the channel regions of the corresponding transistors in the N-type and P-type transistors by the source / drain features 408, 410. Figure 6C In the top view, as in Figure 4C In the top view (corresponding to block 306 of method 300), the symmetrical process environment includes a first repeating shape array (composed of active regions 402, 404), a second repeating shape array (composed of dummy gate structure 406), and a third repeating shape array (composed of source / drain features 408, 410). Therefore, in step sequence 502 of method 500 ( Figure 6C After that, storage device 600 appears to be in block 306 of method 300. Figure 4C The storage devices 400 and later are basically the same.

[0058] Following step sequence 502, instead of performing the replacement gate process as in method 300, method 500 continues to block 504, where a CPODE patterning process is performed. (See reference...) Figure 6C and Figure 6DIn the embodiment of block 504, after forming source / drain features 408, 410, the dummy gate structure 406 is patterned to define a circuit pattern for the memory device 600 (e.g., a circuit pattern for defining SRAM circuitry). For example, as part of a CPODE patterning process, an isolation structure 420 is formed. In various embodiments, the isolation structure 420 can be substantially the same as that discussed above with reference to method 300. However, compared to method 300 (CMODE patterning process), the isolation structure 420 is formed at a different processing stage in method 500 (CPODE patterning process). Typically, for example, the CPODE patterning process includes forming trenches through portions of the dummy gate structure 406, the trenches extending into the underlying substrate. Subsequently, the trenches are filled with one or more dielectric materials to form the isolation structure 420, thereby providing isolation between adjacent portions of the respective dummy gate structures 406, which are later replaced by high-k / metal gate stacks in a later processing stage. In some embodiments, the CPODE patterning process may be performed as part of the MEOL process. The following references... Figure 14 The method describes a more detailed process flow for the CPODE patterning process. In some cases, because the isolation structure 420 is formed prior to the gate replacement process, there may be a risk of potential wafer deformation (e.g., metal gate tilt).

[0059] In some embodiments, for example, compared to isolation structures formed using CMG patterning, the isolation structure 420 formed by the CPODE patterning process provides an increased distance between adjacent portions of the respective dummy gate structure 406 (and thus an increased distance between portions of the metal layer 416 of the corresponding high-K / metal gate stack 412 that replaces the dummy gate structure 406 in a later processing stage), thereby reducing parasitic capacitance. Figure 6D As illustrated in the example and as described in the above-referenced method 300, the isolation structure 420 extends a distance D1 in the Y direction, which is the same direction in which the dummy gate structure 406 extends. Also as previously stated, the dimension of the isolation structure 420 in the Y direction (e.g., the distance D1 that the isolation structure 420 extends in the Y direction) is equal to or greater than the dimension of the adjacent source / drain features in the Y direction (e.g., the distance D2 that the adjacent source / drain features extend in the Y direction). Since capacitance is inversely proportional to the distance between metal layers, the increased distance D1 provided by the isolation structure 420 can reduce parasitic capacitance between some portions of the metal layers 416 formed during subsequent processing and disposed on both sides of the isolation structure 420 (e.g., in the Y direction). However, since the gate replacement process is performed after the formation of the isolation structure 420 in method 500 (CPODE patterning process), some undesirable metal boundary effects may exist, as described below.

[0060] After performing the CPODE patterning process, method 500 continues to perform step sequence 506. Step sequence 506 may include blocks 308 and 312 of method 300 discussed above. Step sequence 506 may also optionally include block 508, which is performed after block 308 and before block 312, as discussed in more detail below. Therefore, refer to Figure 6D and Figure 6E In the embodiment of block 308 of step sequence 506, a replacement gate process is initially performed in a manner similar to that discussed in reference method 300 above, so as to replace the dummy gate structure 406 with a high-k / metal gate stack. For example, the dummy gate structure 406 may be replaced with a high-k / metal gate stack 412 formed in the substrate region previously occupied by the dummy gate structure 406. As previously described, the high-k / metal gate stack 412 includes an IL, a high-k dielectric layer 414 formed over the IL, and a metal gate including a metal layer 416 formed over the gate dielectric (e.g., over the IL and the high-k dielectric layer 414).

[0061] like Figure 6E As shown in the top view, the high-K / metal gate stack 412 and the isolation structure 420 are joined (or contacted) to each other along opposite sides of the respective isolation structure 420 within region 602. Specifically, since the dummy gate structure 406 is replaced by the high-K / metal gate stack 412 after the isolation structure 420 is formed, the high-K dielectric layer 414 wraps around the metal line end region of the metal layer 416, such that the high-K dielectric layer 414 is disposed along the entire interface between the high-K / metal gate stack 412 and the isolation structure 420. In some embodiments, the portion of the high-K dielectric layer 414 disposed along the entire interface between the high-K / metal gate stack 412 and the isolation structure 420 may lead to an increase in metal boundary effect (MBE), for example, an increase in parasitic capacitance between portions of the metal layer 416 disposed on opposite sides of the respective isolation structure 420. This MBE can be reduced by using an optional CMG patterning process, as referenced in [reference]. Figures 6F-6H As stated above.

[0062] If the optional CMG patterning process is to be performed, the method continues to block 508 of step sequence 506. (See reference) Figure 6E and Figures 6F-6HIn the embodiment of block 508, a CMG patterning process is used to remove a portion of the high-k dielectric layer 414 disposed within region 602 to reduce parasitic capacitance. For example, the CMG patterning process may include forming a diced metal gate trench through a portion of the high-k / metal gate stack 412 in region 602. The formation of the diced metal gate trench removes a portion of the high-k dielectric layer 414 within region 602 that is disposed along the entire interface between the high-k / metal gate stack 412 and the isolation structure 420. The diced metal gate trench is then refilled with a dielectric material (e.g., in some embodiments, including a low-k dielectric material) to form a diced metal gate (CMG) isolation structure. Therefore, parasitic capacitance induced by MBE can be effectively reduced. Different embodiments of the CMG patterning process may be implemented depending on the specific application and scaling constraints imposed by advanced processing nodes.

[0063] For example, in the first embodiment and referring to Figure 6F For example, a first elongated CMG isolation structure 604 and a plurality of second elongated CMG isolation structures 606 can be formed. As shown, the first elongated CMG isolation structure 604 is longer than the second elongated CMG isolation structure 606. Furthermore, each of the first elongated CMG isolation structure 604 and the second elongated CMG isolation structure 606 extends along the X direction, perpendicular to the isolation structure 420 and the high-k / metal gate stack 412, both of which extend along the Y direction. In the illustrated embodiment, the first elongated CMG isolation structure 604 extends through eight (8) different regions 602 corresponding to eight (8) different isolation structures 420, thereby removing a portion of the high-k dielectric layer 414 disposed on one side of each of the eight (8) different isolation structures 420. Furthermore, a plurality of source / drain features 410 corresponding to various different transistors of the memory device 600 are disposed on both sides of the first elongated CMG isolation structure 604. Each of the second elongated CMG isolation structures 606 extends through one or two different regions 602 corresponding to one or two different isolation structures 420. Each of the plurality of second elongated CMG isolation structures 606 is used to remove a portion of the high-k dielectric layer 414 disposed on one side of one or two different isolation structures 420. In addition, at least one pair of source / drain features 408, 410 are disposed on both sides of each second elongated CMG isolation structure 606 or adjacent to each second elongated CMG isolation structure 606. Thus, by combining the first elongated CMG isolation structure 604 and the second elongated CMG isolation structure 606, each isolation structure 420 will cause a portion of the high-k dielectric layer 414 disposed in the regions 602 on both sides of the corresponding isolation structure 420 to be removed and replaced with CMG dielectric material to reduce parasitic capacitance.

[0064] In the second embodiment and referenced Figure 6G For example, multiple CMG isolation structures 608 can be formed, where the CMG isolation structures 608 are via structures. As shown, each CMG isolation structure 608 can be similar in size and can have a width W that is substantially equal to the width of the high-k / metal gate stack 412. In the illustrated embodiment, the CMG isolation structures 608 are formed on the opposite side of each isolation structure 420 in region 602, thereby removing a portion of the high-k dielectric layer 414 disposed on each side of the isolation structure 420. In other words, each isolation structure 420 will cause a portion of the high-k dielectric layer 414 disposed in region 602 on both sides of the corresponding isolation structure 420 to be removed and replaced with CMG dielectric material to reduce parasitic capacitance. Furthermore, since the CMG isolation structures 608 do not extend beyond the width of the high-k / metal gate stack 412 and are therefore not adjacent to any source / drain features 408, 410, the probability of the CMG patterning process damaging the source / drain features 408, 410 is reduced.

[0065] In the third embodiment and referring to Figure 6H For example, multiple elongated CMG isolation structures 610 can be formed. In some embodiments, the multiple elongated CMG isolation structures 610 may be similar to the second elongated CMG isolation structure 606 discussed above. Furthermore, Figure 6H Examples can be similar to those discussed above. Figure 6F Examples. However, in Figure 6H In the example, the first elongated CMG isolation structure 604 ( Figure 6F In fact, it is replaced by multiple shorter CMG isolation structures 610 (which may be a second elongated CMG isolation structure 606). This is achieved through the use of... Figure 6H This configuration can reduce proximity effects. Note that due to scaling limitations imposed by advanced processing nodes, there may not be enough space in some cases to perform optional CMG patterning processes and form the corresponding CMG isolation structures.

[0066] Following the gate replacement process (block 308) or an optional CMG patterning process (block 508), method 500 continues to block 312 of step sequence 506, where further processing (e.g., BEOL wiring) is performed. Similar to memory device 400, memory device 600 will also include various inverters (e.g., similar to inverter 422) and PG transistors (e.g., similar to PG transistor 428), which are patterned / defined by a CPODE patterning process and completed by the gate replacement process, as described above. BEOL wiring may include forming various conductive features to interconnect portions of the previously defined circuitry (e.g., inverters and PG transistors). As previously described, BEOL wiring may include forming an MLI structure comprising various conductive features, which may be vertical interconnects (e.g., contacts and / or vias) and / or horizontal interconnects (e.g., conductive lines). BEOL wiring can be used for reference... Figure 2 The inverter and PG transistor of the memory device 600 are connected in the manner shown and described to define multiple SRAM cells.

[0067] Now for reference Figure 7 The illustration depicts a method 700 for fabricating a semiconductor device 800 using a CMODE patterning process according to various embodiments. In some embodiments, method 700 provides a CMODE patterning process, discussed above with reference to block 310 of method 300. The following references include semiconductor devices comprising GAA transistors to discuss method 700. However, it will be understood that aspects of method 700 are equally applicable to other types of multi-gate devices, such as the FinFET discussed above, without departing from the scope of this disclosure. The following references... Figure 8A / Figures 8B-13A / Figure 13B Description method 700, Figure 8A / Figures 8B-13A / Figure 13B Cross-sectional views of the semiconductor device 800 at various manufacturing stages according to method 700 are provided. Specifically, Figures 8A-13A Embodiments of semiconductor device 800 are provided along with Figure 1 A cross-sectional view of a plane substantially parallel to the plane defined by section AA'. Furthermore, Figures 8B-13B Embodiments of semiconductor device 800 are provided along with Figure 1 A cross-sectional view of a plane substantially parallel to the plane defined by section BB'. In some embodiments, method 700 can be used to manufacture the above reference. Figure 1 The multi-gate device 100 or more references Figure 2The SRAM cell 200 is described above. Therefore, one or more aspects discussed above with reference to the multi-gate device 100 or the SRAM cell 200 are also applicable to method 700 and semiconductor device 800. It will be understood that method 700 includes steps characteristic of CMOS technology process flows, and therefore these steps are described only briefly herein. Furthermore, additional steps may be performed before, after, and / or during method 700.

[0068] Method 700 begins at block 702, where a portion of the fabrication of a multi-gate device is provided. (See reference...) Figure 8A / Figure 8B In the embodiment of block 702, a partially fabricated semiconductor device 800 is provided. The semiconductor device 800 is formed on a substrate 802, which may be substantially the same as described above in the reference memory device 400. The substrate 802 may include active regions having a plurality of stacked nanosheet channel layers 806 disposed on the substrate 802. In some embodiments, the active regions may be the active regions 402, 404 discussed above.

[0069] In some embodiments, the nanosheet channel layer 806 may comprise silicon (Si). However, in some embodiments, the nanosheet channel layer 806 may comprise other materials, such as germanium, compound semiconductors (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), alloy semiconductors (e.g., SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP), or combinations thereof. For example, the nanosheet channel layer 806 may be epitaxially grown using molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes.

[0070] In various embodiments, each active region includes a substrate portion 802A formed by a substrate 802 and a plurality of stacked nanosheet channel layers 806. Note that while the semiconductor device 800 is shown as including three (3) nanosheet channel layers 806, this is for illustrative purposes only and is not intended to be limiting beyond what is specifically set forth in the claims. It will be understood that any number of nanosheet channel layers 806 can be formed, wherein, for example, the number of nanosheet channel layers 806 depends on the desired number of channel regions of the GAA device. In some embodiments, the number of nanosheet channel layers 806 is between 3 and 10.

[0071] Shallow trench isolation (STI) feature 817 may also be formed between adjacent active regions. In some embodiments, STI feature 817 comprises SiO2, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric, combinations thereof, and / or other suitable materials known in the art. In various examples, the dielectric layer used to form STI feature 817 may be deposited by CVD processes, subatmospheric pressure CVD (SACVD) processes, flowable CVD processes, ALD processes, PVD processes, and / or other suitable processes.

[0072] The semiconductor device 800 also includes a gate structure in the form of a high-k / metal gate stack, which may be similar to the high-k / metal gate stack 412 described above. In some embodiments, the gate structure may form a gate associated with a multi-channel provided by a nanosheet channel layer 806 in the channel region of the respective GAA device. The gate structure may include a gate dielectric 808 comprising an IL and a high-k gate dielectric layer formed on the IL. In some embodiments, the total thickness of the gate dielectric 808 is about 1-5 nm. Furthermore, in various embodiments, the IL and the high-k gate dielectric may include one or more of the material compositions described above for the reference memory device 400. In some embodiments, the gate structure may also include a metal gate having a metal layer 812 formed on the gate dielectric 808. In some cases, the metal layer 812 may be substantially the same as the metal layer 416 described above. In this example, the gate structure includes a portion between each nanosheet channel layer 806, wherein each nanosheet channel layer 806 provides a semiconductor channel layer for the respective GAA transistor. Furthermore, in some examples, another metal layer (e.g., a selectively grown tungsten (W) layer) may be formed on top of metal layer 812. In some cases, the selectively grown W layer may include a fluorine-free W (FFW) layer. In various examples, the selectively grown W layer can be used as an etch stop layer and may also provide reduced contact resistance (e.g., contact resistance with metal layer 812).

[0073] In some embodiments, a spacer layer 815 may be formed on the sidewall at the top of each gate structure. The spacer layer 815 may be formed prior to forming the high-k / metal gate stack of the gate structure. For example, in some cases, the spacer layer 815 may be formed on the sidewall of a previously formed dummy (sacrificial) gate stack (which is removed and replaced with a high-k / metal gate stack, as described above) as part of a replacement gate (gate-last) process. In some embodiments, the spacer layer 815 may include a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, SiOHCN, low-k materials (e.g., dielectric constant "k" < 7), and / or combinations thereof. In some embodiments, the spacer layer 815 comprises multiple layers, such as a main spacer layer, a pad layer, etc.

[0074] In some embodiments, the internal spacer 819 may be disposed between adjacent channels of the nanosheet channel layer 806, at the lateral ends of the nanosheet channel layer 806, and in contact with portions of the gate structure between each nanosheet channel layer 806. In some embodiments, the internal spacer 819 comprises amorphous silicon. In some embodiments, the internal spacer 819 may comprise silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, low-k materials (e.g., dielectric constant "k" < 7), and / or combinations thereof. In various examples, the internal spacer 819 may extend below the aforementioned spacer layer 815 and be in contact with adjacent source / drain features, as described below.

[0075] In some embodiments, source / drain features 821 are formed in source / drain regions adjacent to and located on either side of the gate structure of each GAA transistor. As shown, source / drain features 821 are in contact with the internal spacer 819 and nanosheet channel layer 806 of the respective GAA transistor. In various examples, source / drain features 821 can be formed by one or more epitaxial (epi) processes, can be formed in separate processing sequences for each of the N-type and P-type source / drain features, and can generally be similar to the source / drain features 408, 410 described above.

[0076] The semiconductor device 800 may also include an interlayer dielectric (ILD) layer 823. In some embodiments, a contact etch stop layer (CESL) 827 is formed prior to the formation of the ILD layer 823. In some embodiments, the CESL 827 comprises a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, and / or other materials known in the art. The CESL 827 may be formed by a plasma-enhanced chemical vapor deposition (PECVD) process and / or other suitable deposition or oxidation processes. In some embodiments, the ILD layer 823 comprises materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide (e.g., borosilicate glass (BPSG), FSG, phosphosilicate glass (PSG), boron-doped silicate glass (BSG)), and / or other suitable dielectric materials. The ILD layer 823 may be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, a hard mask layer 831 (e.g., SiN) may be formed over the semiconductor device 800.

[0077] Method 700 continues to box 704, where the hard mask layer is patterned. (See reference) Figure 8A / Figure 8B , Figure 9A / Figure 9B and Figure 10A / Figure 10B In the embodiment of frame 704, a three-layer masking element 902 is formed. In some embodiments, the three-layer masking element 902 includes a patterned photoresist material layer 904, an intermediate layer 906 (e.g., including a silicon-containing spin-coating material, such as spin-coated glass), and a bottom layer 908 (e.g., including an organic spin-coating material, such as spin-coated carbon). For example, the photoresist material 904 is patterned using a suitable photolithography process (e.g., coating, exposure, development, etc.). After forming the three-layer masking element 902 with the patterned photoresist material 904, an etching process can be performed to remove portions of the intermediate layer 906, the bottom layer 908, and the hard mask layer 831 below the openings in the masking element 902. The etching process may include a dry etching process (e.g., plasma etching). In some cases, the etching process may alternatively or additionally include a wet etching process. Figure 10A / Figure 10B As shown, the etching process is used to form openings 910 in the hard mask layer 831. After patterning the hard mask layer 831, the remaining portion of the masking element 902 can be removed.

[0078] Method 700 continues to box 706, where the CMODE cutting process is performed. (See reference...) Figure 10A / Figure 10B and Figure 11A / Figure 11BIn the embodiment of frame 706, an etching process is performed through openings 910 in the hard mask layer 831 to form trench 912. In various embodiments, the etching process may include dry etching, wet etching, or a combination thereof. As shown, the etching process forming trench 912 etches through portions of the gate structure, including metal layer 812, gate dielectric 808, and at least one active region having multiple stacked nanosheet channel layers 806. Therefore, in some cases, the CMODE dicing process may also be referred to as a nanosheet dicing process (or a wafer dicing process). In various embodiments, as shown, trench 912 extends into the underlying substrate 802. Furthermore, in some embodiments, trench 912 extends deeper into the underlying substrate 802 than the bottom surface of STI feature 817 (e.g., Figure 11B (As shown).

[0079] Method 700 continues to box 708, where the CMODE refill process and planarization process are performed. (See reference) Figure 11A / Figure 11B and Figure 12A / Figure 12B In the embodiment of block 708, a CMODE refill process is performed to fill the previously formed trench 912. As shown, the refill process of block 708 can form a multilayer structure including dielectric layers 914, 916, wherein the dielectric layers 914, 916 completely fill the trench 912 and are also formed on the top surface of the semiconductor device 800. In some embodiments, the dielectric layers 914, 916 include a nitride layer (e.g., SiN), SiO2, silicon oxynitride, FSG, a low-k dielectric, combinations thereof, and / or other suitable materials known in the art. In various examples, the dielectric layers 914, 916 can be deposited by CVD processes, SACVD processes, flowable CVD processes, ALD processes, PVD processes, and / or other suitable processes. Reference Figure 12A / Figure 12B and Figure 13A / Figure 13B In a further embodiment of block 708, after depositing dielectric layers 914, 916, a planarization process (e.g., CMP process) can be performed to remove excess material, including patterned hard mask layer 831. Therefore, the refilled trench 912 provides an isolation structure 920 that provides isolation between adjacent portions of the metal layer 812 of the respective gate structure. It will thus be understood that in some embodiments, the isolation structure 920 may be similar to the referenced above. Figure 4E The isolation structure 420 discussed herein and / or provides substantially the same functionality as the isolation structure 420. After the isolation structure 920 is formed, further processing can be performed as described in block 312 of the above-mentioned reference method 300.

[0080] Now for reference Figure 14 The illustration depicts a method 1400 for fabricating a semiconductor device 1500 using a CPODE patterning process according to various embodiments. In some embodiments, method 1400 provides a CPODE patterning process, discussed above with reference to block 504 of method 500. Furthermore, in some embodiments, method 1400 provides an alternative gate process and an optional CMG patterning process, discussed above with reference to blocks 308, 508 of method 500. The following references include semiconductor devices with GAA transistors for discussion of method 1400. However, it will be understood that aspects of method 1400 are equally applicable to other types of multi-gate devices, such as the FinFET discussed above, without departing from the scope of this disclosure. The following references... Figure 15A / Figures 15B-31A / Figure 31B Description method 1400, Figure 15A / Figures 15B-31A / Figure 31B Cross-sectional views of the semiconductor device 1500 at various manufacturing stages according to method 1400 are provided. Specifically, Figures 15A-31A Embodiments of semiconductor device 1500 are provided along with Figure 1 A cross-sectional view of a plane substantially parallel to the plane defined by section AA'. Furthermore, Figures 15B-31B Embodiments of semiconductor device 1500 are provided along with Figure 1 A cross-sectional view of a plane substantially parallel to the plane defined by section BB'. In some embodiments, method 1400 can be used to manufacture the above reference. Figure 1 The multi-gate device 100 or more references Figure 2 The SRAM cell 200 is described above. Therefore, one or more aspects discussed above with reference to the multi-gate device 100 or the SRAM cell 200 are also applicable to method 1400 and semiconductor device 1500. It will be understood that method 1400 includes steps characteristic of CMOS technology process flows, and therefore these steps are only briefly described herein. Furthermore, additional steps may be performed before, after, and / or during method 1400. Moreover, method 1400 is similar in many respects to method 700 discussed above. Therefore, some aspects of method 1400 that have previously been described in the discussion of method 700 are only briefly described below. Furthermore, for clarity of discussion, the reference numerals used in the discussion of method 700 will be repeated below in the discussion of method 1400.

[0081] Method 1400 begins at block 1402, where a portion of the fabrication of a multi-gate device is provided. (Reference) Figure 15A / Figure 15BIn the embodiment of block 1402, a partially fabricated semiconductor device 1500 is provided. The semiconductor device 1500 is formed on a substrate 802, which may be substantially the same as described above. The substrate 802 may include active regions having a plurality of stacked nanosheet channel layers 806 disposed on the substrate 802. Furthermore, since the device 1500 is provided prior to the gate replacement process, a plurality of dummy epitaxial layers 807 (e.g., SiGe layers) are interposed between the plurality of stacked nanosheet channel layers 806 (e.g., Si layers). In some embodiments, the active regions may be the active regions 402, 404 discussed above. In various embodiments, each active region includes a substrate portion 802A formed by the substrate 802 and the plurality of stacked nanosheet channel layers 806, and the plurality of dummy epitaxial layers 807 are interposed between the plurality of stacked nanosheet channel layers 806.

[0082] STI feature 817 may also be formed between adjacent active regions. In some embodiments, STI feature 817 comprises SiO2, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric, combinations thereof, and / or other suitable materials known in the art. In various examples, the dielectric layer used to form STI feature 817 may be deposited by CVD processes, subatmospheric pressure CVD (SACVD) processes, flowable CVD processes, ALD processes, PVD processes, and / or other suitable processes.

[0083] The semiconductor device 1500 also includes a dummy gate structure, which may be similar to the dummy gate structure 406 described above. As previously mentioned, the dummy gate structure is replaced by a high-k / metal gate stack in a later processing stage. The dummy gate structure may include a dummy gate dielectric 809 and a dummy gate electrode 813 (e.g., a polysilicon layer) formed on the dummy gate dielectric 809.

[0084] As shown, the semiconductor device 1500 also includes a spacer layer 815 formed on the sidewall at the top of each dummy gate structure. After a subsequent gate replacement process, the spacer layer 815 can remain on the sidewall at the top of the high-k / metal gate stack. In some examples, the spacer layer 815 is substantially the same as described above. The semiconductor device 1500 also includes internal spacers 819 disposed between adjacent channels of the nanosheet channel layer 806, at the lateral ends of the nanosheet channel layer 806. The internal spacers 819 can be substantially the same as described above. The semiconductor device 1500 may also include source / drain features 821 formed in source / drain regions adjacent to and located on either side of the dummy gate structure of each GAA transistor. In various embodiments, the source / drain features 821 can be substantially the same as described above.

[0085] The semiconductor device 1500 may also include an interlayer dielectric (ILD) layer 823. In some embodiments, a contact etch stop layer (CESL) 827 is formed prior to the formation of the ILD layer 823. In some examples, a nitrogen-containing layer 825 (e.g., a silicon nitride layer 825) is also formed over the ILD layer 823. The nitrogen-containing layer 825 may be formed by a CVD process, a PECVD process, and / or other suitable deposition processes. In some embodiments, a hard mask layer 831 (e.g., SiN) may be formed over the semiconductor device 1500. In various embodiments, the ILD layer 823, CESL 827, and hard mask layer 831 may be substantially the same as described above.

[0086] Method 1400 continues to box 1404, where the hard mask layer is patterned. (See reference) Figure 15A / Figure 15B , Figure 16A / Figure 16B and Figure 17A / Figure 17B In the embodiment of frame 1404, a three-layer masking element 902 is formed. In some embodiments, the three-layer masking element 902 includes a patterned photoresist material layer 904, an intermediate layer 906 (e.g., including a silicon-containing spin-coating material, such as spin-coated glass), and a bottom layer 908 (e.g., including an organic spin-coating material, such as spin-coated carbon), as described above. After forming the three-layer masking element 902 with the patterned photoresist material 904, an etching process can be performed to remove portions of the intermediate layer 906, the bottom layer 908, and the hard mask layer 831 below the openings in the masking element 902. The etching process may include a dry etching process (e.g., plasma etching). In some cases, the etching process may alternatively or additionally include a wet etching process. Figure 17A / Figure 17B As shown, the etching process is used to form openings 950 in the hard mask layer 831. After patterning the hard mask layer 831, the remaining portion of the masking element 902 can be removed.

[0087] Method 1400 continues to box 1406, where the CPODE cutting process is performed. (See reference) Figure 17A / Figure 17B , Figure 18A / Figure 18B , Figure 19A / Figure 19B and Figure 20A / Figure 20BIn the embodiment of block 1406, an etching process is performed through an opening 950 in the hard mask layer 831, as described below. In various embodiments, the etching process may include dry etching, wet etching, or a combination thereof. Initially, a first etching process may be performed to remove a portion of the dummy gate electrode 813 (e.g., a polysilicon layer), thereby forming a trench 952 exposing the dummy gate dielectric 809. Subsequently, a second etching process may be performed to remove the dummy gate dielectric 809 and form an extended trench 952A. As shown, the extended trench 952A exposes two active regions in which a plurality of dummy epitaxial layers 807 are interposed between a plurality of stacked nanosheet channel layers 806. More generally, at least one active region will be exposed. In some embodiments, a third etching process is then performed to remove the plurality of stacked nanosheet channel layers 806 and the plurality of dummy epitaxial layers 807 interposed therebetween from the exposed active regions, thereby forming a further enlarged trench 952B. In various embodiments, as shown, trench 952B extends into the underlying substrate 802. Furthermore, in some embodiments, trench 952B extends deeper into the underlying substrate 802 than the bottom surface of STI feature 817 (e.g., Figure 20B (As shown).

[0088] Method 1400 continues to box 1408, where the CPODE refill process and planarization process are performed. (See reference) Figure 20A / Figure 20B and Figure 21A / Figure 21B In the embodiment of block 1408, a CPODE refill process is performed to fill the previously formed trench 952B. As shown, the refill process of block 1408 can form a multilayer structure including dielectric layers 914, 916, wherein the dielectric layers 914, 916 completely fill the trench 952B and are also formed on the top surface of the semiconductor device 1500. In some embodiments, the dielectric layers 914, 916 include a nitride layer (e.g., SiN), SiO2, silicon oxynitride, FSG, a low-k dielectric, combinations thereof, and / or other suitable materials known in the art. In various examples, the dielectric layers 914, 916 can be deposited by CVD processes, SACVD processes, flowable CVD processes, ALD processes, PVD processes, and / or other suitable processes. Reference Figure 21A / Figure 21B and Figure 22A / Figure 22BIn a further embodiment of block 1408, after depositing dielectric layers 914, 916, a planarization process (e.g., CMP process) can be performed to remove excess material, including patterned hard mask layer 831. Therefore, the refilled trench 952B provides an isolation structure 960 that provides isolation between adjacent portions of a dummy gate electrode 813 of a corresponding gate structure (which will be replaced by a metal layer of a high-k / metal gate stack in a later processing stage). It will thus be understood that in some embodiments, the isolation structure 960 may be similar to the referenced above. Figure 6D The isolation structure 420 under discussion and / or provides substantially the same functionality as the isolation structure 420.

[0089] After performing the CPODE patterning process described above, method 1400 continues to block 1410, where a gate replacement process is performed. In some embodiments, the gate replacement process of block 1410 may be similar to the gate replacement process discussed above with reference to block 308 of method 500. (Refer to...) Figure 22A / Figure 22B , Figure 23A / Figure 23B , Figure 24A / Figure 24B and Figure 25A / Figure 25B In the embodiment of block 1410, a replacement gate process is performed in a similar manner to that described above to replace the dummy gate structure with a high-k / metal gate stack. Initially, in some embodiments, one or more etching processes are performed to remove the remainder of the dummy gate electrode 813 (e.g., a polysilicon layer) and the dummy gate dielectric 809 to form a trench 962 exposing an active region in which a plurality of dummy epitaxial layers 807 are interposed between a plurality of stacked nanosheet channel layers 806. In various examples, the etching process may include dry etching, wet etching, or a combination thereof.

[0090] In some embodiments, a channel release process may be performed after the removal of the dummy gate structure (including the dummy gate electrode 813 and the dummy gate dielectric 809) to remove the dummy epitaxial layer 807 disposed between the nanosheet channel layers 806. In some cases, a selective etching process (e.g., selective dry etching, wet etching, or a combination thereof) may be used to remove the dummy epitaxial layer 807 through the trench 962. As shown, removing the dummy epitaxial layer 807 also serves to form a gap 964 between adjacent nanosheet channel layers 806.

[0091] Following the channel release process and the formation of gap 964, a high-k / metal gate stack (e.g., the high-k / metal gate stack 412 described above) is formed in the substrate region previously occupied by the dummy gate structure. In some embodiments, the gate structure may form a gate associated with a multi-channel provided by a nanosheet channel layer 806 in the channel region of the corresponding GAA device. The gate structure may include a gate dielectric 808 comprising an IL and a high-k gate dielectric layer formed on the IL. In various embodiments, the IL and the high-k gate dielectric may include one or more of the material compositions described above. In some embodiments, the gate structure may also include a metal gate having a metal layer 812 formed on the gate dielectric 808. In some cases, the metal layer 812 may be substantially the same as the metal layer 416 described above. In this embodiment, the gate structure includes a portion between each nanosheet channel layer 806 (e.g., filling gap 964), wherein each nanosheet channel layer 806 provides a semiconductor channel layer for the corresponding GAA transistor. Furthermore, in some examples, another metal layer (e.g., a selectively grown tungsten (W) layer) can be formed on top of metal layer 812. In some cases, the selectively grown W layer may include an FFW layer. In various examples, the selectively grown W layer can serve as an etch stop layer and can also provide reduced contact resistance (e.g., contact resistance with metal layer 812). It should also be noted that the portion of the gate dielectric 808 formed at the interface 965 between metal layer 812 and isolation structure 960 may correspond to the portion of the high-K dielectric layer 414 within region 602 that is positioned along the entire interface between the high-K / metal gate stack 412 and isolation structure 420, such as... Figure 6E As shown.

[0092] Following the gate replacement process, method 1400 may optionally continue to block 1412, where a CMG patterning process is performed. Optional CMG patterning processes may be performed to reduce parasitic capacitance caused by MBE, as described above. In some embodiments, the CMG patterning process of block 1412 may be similar to the CMG patterning process discussed above with reference to block 508 of method 500. Reference Figure 25A / Figure 25B , Figure 26A / Figure 26B , Figure 27A / Figure 27B , Figure 28A / Figure 28B , Figure 29A / Figure 29B , Figure 30A / Figure 30B and Figure 31A / Figure 31BIn the embodiment of block 1412, a CMG patterning process is used to remove a portion (including the high-k dielectric layer) of the gate dielectric 808 formed at interface 965 to reduce parasitic capacitance. Initially, in some embodiments, a hard mask layer 967 is formed over the semiconductor device 1500. The hard mask layer 967 may be substantially the same as the hard mask layer 831 discussed above. Subsequently, a three-layer masking element 902 as described above may be formed over the hard mask layer 967. After forming the three-layer masking element 902, an etching process may be performed to remove the portions of the intermediate layer 906, the bottom layer 908, and the hard mask layer 967 below the openings in the masking element 902. The etching process may include a dry etching process (e.g., plasma etching). In some cases, the etching process may alternatively or additionally include a wet etching process. Figure 28B As shown, the etching process is used to form openings 970 of the exposed interface 965 in the hard mask layer 967. After patterning the hard mask layer 967, the remaining portion of the masking element 902 can be removed.

[0093] After forming an opening 970 in the hard mask layer 967, a CMG dicing process is performed. In some embodiments, the CMG dicing process can be performed through the opening 970 using dry etching, wet etching, or a combination thereof. Specifically, the CMG dicing process is performed to remove portions of the gate dielectric 808 (including the high-k dielectric layer) formed at the interface 965, as well as portions of the metal layer 812 and the isolation structure 960 located on both sides of the interface 965, thereby forming a trench 972. As shown, the trench 972 extends into the STI feature 817. However, the trench 972 does not extend beyond the bottom surface of the STI feature 817. Typically, the bottom surface of the STI feature 817 extends deeper into the substrate 802 than the trench 972 formed by the CMG dicing process. Furthermore, in various embodiments, the trench 952B (for forming the isolation structure 960) extends deeper into the underlying substrate 802 than both the bottom surface of the STI feature 817 and the bottom surface of the trench 972 (e.g., Figure 29B(As shown). After trench 972 is formed, a CMG refilling process and a planarization process are performed. For example, the CMG refilling process may include forming one or more dielectric layers 975 within trench 972 to completely fill trench 972. One or more dielectric layers 975 may also be formed over the top surface of semiconductor device 1500. In some embodiments, one or more dielectric layers 975 may include a nitride layer (e.g., SiN), SiO2, silicon oxynitride, FSG, low-k dielectric, combinations thereof, and / or other suitable materials known in the art. In various examples, one or more dielectric layers 975 may be deposited by a CVD process, SACVD process, flowable CVD process, ALD process, PVD process, and / or other suitable processes. Subsequently, in some embodiments, a planarization process (e.g., CMP process) may be performed to remove excess material, including a patterned hard mask layer 967. Thus, the refilled trench 972 provides a CMG isolation structure 977, which is effectively used to reduce parasitic capacitance caused by MBE. Therefore, it will be understood that in some embodiments, the CMG isolation structure 977 may be similar to the referenced above. Figures 6F-6H The CMG isolation structures 604, 606, 608, and 610 discussed herein and / or provide substantially the same functionality as those CMG isolation structures 604, 606, 608, and 610. After the formation of the CMG isolation structure 977, further processing can be performed as described above in block 312 of reference method 500. In some cases, if the optional CMG patterning process of block 1412 is skipped, method 1400 can proceed directly from block 1410 to performing further processing as described in block 312 of reference method 500.

[0094] Regarding the description provided herein, methods and structures for performing isolation patterning processes in highly scaled CMOS circuits to address various existing challenges, such as minimizing LDEs, are disclosed. While not limited thereto, aspects of this disclosure can be used to perform isolation structures in SRAM circuits, thereby patterning SRAM circuits. In various embodiments, the disclosed isolation patterning processes can be performed using CMODE patterning processes, CPODE patterning processes, or a combination of CPODE patterning processes and CMG patterning processes. As part of the CMODE process, and after the formation of the metal gate stack, a trench may be formed to extend through a portion of the metal gate stack and into the substrate, and the trench is filled with a dielectric material to provide isolation between adjacent portions of the metal gate stack. As part of the CPODE process, after the formation of the dummy multi-gate and before the formation of the metal gate stack, a trench may be formed to extend through a portion of the dummy multi-gate and into the substrate, and the trench is filled with a dielectric material to provide isolation between adjacent portions of the dummy multi-gate. In some cases, after performing the CPODE process and replacing the dummy multi-gate with a metal gate stack, a CMG process can be performed to remove the high-k gate dielectric portion from the metal line-end regions of the metal gate stack in order to reduce parasitic capacitance by minimizing the MBE. Therefore, embodiments of this disclosure effectively reduce LDE compared to prior art. Other embodiments and advantages will be apparent to those skilled in the art upon reading this disclosure.

[0095] Therefore, one embodiment of this disclosure describes a method comprising defining a plurality of active regions in a substrate, the plurality of active regions extending along a first direction in a top view. In some embodiments, the method further comprises forming a plurality of dummy gate structures over the plurality of active regions, the plurality of dummy gate structures extending along a second direction in a top view, the second direction being perpendicular to the first direction. In some embodiments, the method further comprises forming a plurality of source / drain features in source / drain regions adjacent to and located on both sides of each of the plurality of dummy gate structures. In some embodiments, the method further comprises replacing the plurality of dummy gate structures with a plurality of high-K / metal gate stacks. In some embodiments, the method further comprises forming a first isolation structure within a first high-K / metal gate stack of the plurality of high-K / metal gate stacks, wherein the first isolation structure has a first source / drain feature and a second source / drain feature disposed on both sides of the first isolation structure among the plurality of source / drain features.

[0096] In another embodiment, a method is discussed that includes defining a plurality of active regions in a substrate, the plurality of active regions extending along a first direction in a top view. In some embodiments, the method further includes forming a plurality of dummy gate structures over the plurality of active regions, the plurality of dummy gate structures extending along a second direction in a top view, the second direction being perpendicular to the first direction. In some embodiments, the method further includes forming a plurality of source / drain features in source / drain regions adjacent to and located on either side of each of the plurality of dummy gate structures. In some embodiments, the method further includes, after forming the plurality of source / drain features, forming a first isolation structure and a second isolation structure within corresponding first and second dummy gate structures of the plurality of dummy gate structures, wherein the first isolation structure and the second isolation structure are disposed on opposite sides of the source / drain features of the plurality of source / drain features. In some embodiments, the method further includes, after forming the first isolation structure and the second isolation structure, replacing the plurality of dummy gate structures with a plurality of high-K / metal gate stacks.

[0097] In another embodiment, a semiconductor device is discussed, comprising a plurality of active regions in a substrate extending along a first direction and providing a repeating shape array in a top view. In some embodiments, the semiconductor device further comprises a plurality of high-k / metal gate stacks over the plurality of active regions, the plurality of high-k / metal gate stacks extending along a second direction in a top view, the second direction being perpendicular to the first direction. In some embodiments, the semiconductor device further comprises a plurality of source / drain features located in source / drain regions adjacent to and on either side of each of the plurality of high-k / metal gate stacks. In some embodiments, the semiconductor device further comprises an isolation structure disposed within the high-k / metal gate stacks, wherein the isolation structure has a first source / drain feature and a second source / drain feature disposed on either side of the isolation structure.

[0098] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0099] Example 1 is a method of manufacturing a semiconductor device, comprising: defining a plurality of active regions in a substrate, the plurality of active regions extending along a first direction in a top view; forming a plurality of dummy gate structures over the plurality of active regions, the plurality of dummy gate structures extending along a second direction in the top view, the second direction being perpendicular to the first direction; forming a plurality of source / drain features in source / drain regions adjacent to and located on both sides of each of the plurality of dummy gate structures; replacing the plurality of dummy gate structures with a plurality of high-K / metal gate stacks; and forming a first isolation structure within a first high-K / metal gate stack of the plurality of high-K / metal gate stacks, wherein the first isolation structure has a first source / drain feature and a second source / drain feature disposed on both sides of the first isolation structure among the plurality of source / drain features.

[0100] Example 2 is the method of Example 1, wherein the plurality of active regions include fins extending from the substrate.

[0101] Example 3 is the method described in Example 1, wherein the plurality of active regions comprise a plurality of stacked nanosheets disposed on the substrate.

[0102] Example 4 is the method described in Example 1, wherein, prior to forming the plurality of dummy gate structures, the substrate includes a symmetrical process environment, which, in the top view, includes a repeating shape array composed of the plurality of active regions.

[0103] Example 5 is the method described in Example 1, wherein, prior to forming the plurality of source / drain features, the substrate includes a symmetrical process environment, which, in the top view, includes a first repeating shape array composed of the plurality of active regions and a second repeating shape array composed of the plurality of dummy gate structures.

[0104] Example 6 is the method of Example 1, wherein, before replacing the plurality of dummy gate structures with the plurality of high-K / metal gate stacks, the substrate includes a symmetrical process environment, which, in the top view, includes a first repeating shape array of the plurality of active regions, a second repeating shape array of the plurality of dummy gate structures, and a third repeating shape array of the plurality of source / drain features.

[0105] Example 7 is the method described in Example 1, wherein, prior to forming the first isolation structure, the substrate includes a symmetrical process environment, which, in the top view, includes a first repeating shape array composed of the plurality of active regions, a third repeating shape array composed of the plurality of source / drain features, and a fourth repeating shape array composed of the plurality of high-K / metal gate stacks.

[0106] Example 8 is the method of Example 1, wherein the plurality of active regions are separated by shallow trench isolation (STI) features, and wherein the first isolation structure extends deeper into the substrate than the bottom surface of the STI feature.

[0107] Example 9 is the method of Example 1, wherein the first isolation structure extends a first distance along the second direction in the top view, wherein the first source / drain feature and the second source / drain feature extend a second distance along the second direction in the top view, and wherein the first distance is equal to or greater than the second distance.

[0108] Example 10 is the method of Example 1, further comprising: forming a second isolation structure within a second high-K / metal gate stack of the plurality of high-K / metal gate stacks, wherein the first isolation structure and the second isolation structure are disposed on both sides of one of the first source / drain feature and the second source / drain feature.

[0109] Example 11 is the method of Example 1, wherein the first high-K / metal gate stack provides the gate for a transfer gate transistor, pull-down transistor, or pull-up transistor for a static random access memory (SRAM) device.

[0110] Example 12 is a method of manufacturing a semiconductor device, comprising: defining a plurality of active regions in a substrate, the plurality of active regions extending along a first direction in a top view; forming a plurality of dummy gate structures over the plurality of active regions, the plurality of dummy gate structures extending along a second direction in the top view, the second direction being perpendicular to the first direction; forming a plurality of source / drain features in source / drain regions adjacent to and located on both sides of each of the plurality of dummy gate structures; after forming the plurality of source / drain features, forming a first isolation structure and a second isolation structure within corresponding first and second dummy gate structures in the plurality of dummy gate structures, wherein the first isolation structure and the second isolation structure are disposed on opposite sides of the source / drain features in the plurality of source / drain features; and after forming the first isolation structure and the second isolation structure, replacing the plurality of dummy gate structures with a plurality of high-K / metal gate stacks.

[0111] Example 13 is the method of Example 12, wherein, prior to forming the plurality of dummy gate structures, the substrate includes a symmetrical process environment, which, in the top view, includes a repeating shape array composed of the plurality of active regions.

[0112] Example 14 is the method described in Example 12, wherein, prior to forming the plurality of source / drain features, the substrate includes a symmetrical process environment, which, in the top view, includes a first repeating shape array consisting of the plurality of active regions and a second repeating shape array consisting of the plurality of dummy gate structures.

[0113] Example 15 is the method described in Example 12, wherein, prior to forming the first isolation structure and the second isolation structure, the substrate includes a symmetrical process environment, which, in the top view, includes a first repeating shape array composed of the plurality of active regions, a second repeating shape array composed of the plurality of dummy gate structures, and a third repeating shape array composed of the plurality of source / drain features.

[0114] Example 16 is the method of Example 12, wherein the plurality of active regions are separated by shallow trench isolation (STI) features, and wherein the first isolation structure extends deeper into the substrate than the bottom surface of the STI feature.

[0115] Example 17 is the method of Example 12, further comprising: after replacing the plurality of dummy gate structures with the plurality of high-K / metal gate stacks, forming a third isolation structure extending along the first direction in the top view, the third isolation structure being formed within portions of the first high-K / metal gate stack and the second high-K / metal gate stack located at the interface between the first high-K / metal gate stack and the second high-K / metal gate stack and the corresponding first isolation structure and second isolation structure.

[0116] Example 18 is a semiconductor device comprising: a plurality of active regions located in a substrate, the plurality of active regions extending in a top view along a first direction and providing a repeating shape array; a plurality of high-K / metal gate stacks located above the plurality of active regions, the plurality of high-K / metal gate stacks extending in the top view along a second direction perpendicular to the first direction; a plurality of source / drain features located in source / drain regions adjacent to and on both sides of each of the plurality of high-K / metal gate stacks; and an isolation structure disposed within the high-K / metal gate stacks, wherein the isolation structure has a first source / drain feature and a second source / drain feature disposed on both sides of the isolation structure.

[0117] Example 19 is the semiconductor device described in Example 18, wherein the plurality of active regions are separated by a shallow trench isolation (STI) feature, and wherein the isolation structure extends deeper into the substrate than the bottom surface of the STI feature.

[0118] Example 20 is the semiconductor device described in Example 18, wherein the isolation structure extends a first distance along the second direction in the top view, wherein the first source / drain feature and the second source / drain feature extend a second distance along the second direction in the top view, and wherein the first distance is equal to or greater than the second distance.

Claims

1. A method for manufacturing a semiconductor device, comprising: A plurality of active regions are defined in the substrate, the plurality of active regions extending along a first direction in a top view; Multiple dummy gate structures are formed over the multiple active regions, and the multiple dummy gate structures extend along a second direction in the top view, the second direction being perpendicular to the first direction; Multiple source / drain features are formed in the source / drain regions adjacent to and located on both sides of each of the plurality of dummy gate structures; The plurality of dummy gate structures are replaced with a plurality of high-K / metal gate stacks; as well as A first isolation structure is formed within a first high-K / metal gate stack among the plurality of high-K / metal gate stacks, wherein the first isolation structure has a first source / drain feature and a second source / drain feature disposed on both sides of the plurality of source / drain features.

2. The method according to claim 1, wherein, The plurality of active regions include fins extending from the substrate.

3. The method according to claim 1, wherein, The plurality of active regions include a plurality of stacked nanosheets disposed on the substrate.

4. The method according to claim 1, wherein, Prior to forming the plurality of dummy gate structures, the substrate includes a symmetrical process environment, which, in the top view, includes a repeating shape array composed of the plurality of active regions.

5. The method according to claim 1, wherein, Prior to the formation of the plurality of source / drain features, the substrate includes a symmetrical process environment, which, in the top view, includes a first repeating shape array composed of the plurality of active regions and a second repeating shape array composed of the plurality of dummy gate structures.

6. The method according to claim 1, wherein, Before replacing the plurality of dummy gate structures with the plurality of high-K / metal gate stacks, the substrate includes a symmetrical process environment, which, in the top view, includes a first repeating shape array composed of the plurality of active regions, a second repeating shape array composed of the plurality of dummy gate structures, and a third repeating shape array composed of the plurality of source / drain features.

7. The method according to claim 1, wherein, Prior to forming the first isolation structure, the substrate includes a symmetrical process environment, which, in the top view, includes a first repeating shape array composed of the plurality of active regions, a third repeating shape array composed of the plurality of source / drain features, and a fourth repeating shape array composed of the plurality of high-K / metal gate stacks.

8. The method according to claim 1, wherein, The plurality of active regions are separated by shallow trench isolation (STI) features, wherein the first isolation structure extends deeper into the substrate than the bottom surface of the STI feature.

9. A method for manufacturing a semiconductor device, comprising: A plurality of active regions are defined in the substrate, the plurality of active regions extending along a first direction in a top view; Multiple dummy gate structures are formed over the multiple active regions, and the multiple dummy gate structures extend along a second direction in the top view, the second direction being perpendicular to the first direction; Multiple source / drain features are formed in the source / drain regions adjacent to and located on both sides of each of the plurality of dummy gate structures; After forming the plurality of source / drain features, a first isolation structure and a second isolation structure are formed in the corresponding first dummy gate structure and second dummy gate structure in the plurality of dummy gate structures, wherein the first isolation structure and the second isolation structure are disposed on opposite sides of the source / drain features in the plurality of source / drain features. as well as After forming the first isolation structure and the second isolation structure, the plurality of dummy gate structures are replaced with a plurality of high-K / metal gate stacks.

10. A semiconductor device, comprising: Multiple active regions are located in a substrate, the multiple active regions extending along a first direction in a top view and providing a repeating shape array; Multiple high-K / metal gate stacks are located above the multiple active regions, and the multiple high-K / metal gate stacks extend along a second direction in the top view, the second direction being perpendicular to the first direction; Multiple source / drain features are located in the source / drain regions adjacent to and on both sides of each of the multiple high-K / metal gate stacks; as well as An isolation structure is disposed within one of the plurality of high-K / metal gate stacks, wherein the isolation structure has a first source / drain feature and a second source / drain feature disposed on both sides of the plurality of source / drain features.

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