Manufacturing method of single-particle-radiation-resistant power MOSFET

Abstract

The invention discloses a manufacturing method of a single particle radiation resistant power MOSFET, and belongs to the field of semiconductor devices. According to the method, helium ion implantation is carried out after contact hole corrosion and before metal deposition so as to introduce defects; helium ion implantation uses a masking layer etched by a contact hole and is self-aligned implantation; and after metal deposition and metal etching, annealing is carried out to stabilize the defects. The position of the defect is located in the body region, below the contact hole and the source region and outside the space charge region of the working voltage, so that the leakage current of the device is not increased. The helium ion injection defect has the advantages of high position precision, good temperature stability, no electric activity and no influence on the doping concentration. According to the invention, defects are introduced into the power MOSFET body, the service life of carriers is shortened, the recombination of excess carriers is enhanced, and the recovery current of single-particle irradiation is reduced, so that single-particle reinforcement is realized, and the method has the advantages of simple process flow, low device power consumption and high switching speed.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a method for manufacturing a single-particle-resistant power MOSFET. Background Technology

[0002] VDMOS (Vertical Diffused Metal-Oxide Semiconductor field effect transistor) has advantages such as low power consumption, fast switching speed, strong drive capability, and negative temperature coefficient, and is widely used in power modules of satellite electronic systems. In the space ionizing radiation environment, the radiation effects on power MOSFET devices mainly include SEB (Single Event Burnout), SEGR (Single Event Gate Rupture), and total dose effects. Compared to conventional power MOSFET device structures, radiation-hardened power MOSFET device structures require special ruggedization designs.

[0003] SEB (Self-Impact Blowout) refers to the phenomenon where charged particles, upon entering a power device, generate a large number of electron-hole pairs along their trajectory. These excess carriers are removed through pumping and recombination mechanisms. Under the influence of an applied voltage, electrons move towards the anode, and holes move towards the cathode; this directional movement of carriers forms a recovery current due to single-particle irradiation. In regions where the current is concentrated, the lattice temperature of the material rises sharply, leading to device burnout. When high-energy particles enter the cellular region of a power device, the presence of parasitic transistors in the cell structure of a power MOSFET can trigger these transistors to conduct when the recovery current is sufficiently large, creating a positive feedback path and causing the power MOSFET to burn out.

[0004] Currently, the main hardening methods for power MOSFETs to resist SEB (Self-Abandoned Block) include: adding multiple buffer layers with different doping concentrations between the epitaxial layer and the substrate to reduce the dynamic avalanche current in the transistor's collector region; and increasing the bulk concentration to reduce the base resistance and suppress base-emitter junction conduction. However, these hardening methods reduce switching speed and increase power consumption: adding a buffer layer increases the reverse recovery time of the freewheeling diode, increasing the device's switching power consumption; increasing the bulk concentration increases the MOSFET's on-resistance, increasing the device's on-power consumption. Summary of the Invention

[0005] The purpose of this invention is to provide a method for manufacturing a single-particle radiation resistant power MOSFET to solve the problems of reduced switching speed and high power consumption in traditional radiation-resistant devices.

[0006] To address the aforementioned technical problems, this invention provides a method for manufacturing a single-event radiation resistant power MOSFET, comprising:

[0007] A bulk region is formed in the doped epitaxial layer of the substrate, and a source region of the first conductivity type is formed in the bulk region;

[0008] A gate dielectric and a polysilicon gate are formed on the device surface, a second conductivity type source region is formed in the bulk region, and an isolation metal front dielectric layer is deposited.

[0009] Photolithography and etching are performed on the device surface to form contact hole windows and then light ion implantation is performed to create defects in the bulk region.

[0010] Metal is deposited and etched to form the gate and source, and defects and metal alloying are stabilized simultaneously through annealing;

[0011] On the back side of the thinned substrate, metal is deposited to form a drain electrode.

[0012] In one embodiment, the light ion is a helium ion (He). 2+ The helium ion implantation dose is determined based on the desired minority carrier lifetime, with an implantation dose of 1×10⁻⁶. 11 ~1×10 12 cm -2 At that time, the lifetime of minority carriers ranged from 20 μs to 0.1 μs.

[0013] In one embodiment, the light ion implantation is located within the body region, below the contact hole and the source region, and outside the space charge region.

[0014] In one implementation, the annealing conditions for the defect need to balance lifetime control and high-temperature stability: when the implantation dose of light ions increases, the annealing temperature and time are increased; when the implantation dose of light ions decreases, the annealing temperature and time are decreased.

[0015] In one embodiment, the light ion implantation is a self-aligned process that utilizes photoresist and a masking layer on the contact holes of the substrate, eliminating the need for photolithography; after the contact holes are etched, no photoresist removal is performed, and light ion implantation is carried out directly; the photoresist is then removed after the light ion implantation is completed.

[0016] In one embodiment, the substrate is a heavily doped semiconductor of a first conductivity type, and a lightly doped epitaxial layer of the first conductivity type is formed on its surface; the body region is formed by photolithographically creating a body window in the lightly doped epitaxial layer of the first conductivity type and implanting impurities of the second conductivity type.

[0017] In one embodiment, the first conductivity type source region is formed by photolithographically etching a first conductivity type source region window in the body region and then implanting it; the second conductivity type source region is formed by photolithographically etching a second conductivity type source region window in the body region and then implanting it.

[0018] In one embodiment, the first conductivity type source region and the second conductivity type source region are in contact.

[0019] The present invention provides a method for manufacturing a single-particle irradiation-resistant power MOSFET, which utilizes light ion implantation to generate defects in the power MOSFET. These defects reduce carrier lifetime and enhance recombination of excess carriers, thereby reducing the recovery current of single-particle irradiation and achieving single-particle hardening. Attached Figure Description

[0020] Figure 1 This is a cross-sectional schematic diagram of the formation of the P-body region on a silicon wafer;

[0021] Figure 2 This is a schematic cross-sectional view of the formation of the N+ source region in the P-body region;

[0022] Figure 3 This is a cross-sectional schematic diagram of the implementation of thermal oxidation of the gate oxide and deposition of the polycrystalline gate;

[0023] Figure 4 This is a cross-sectional schematic diagram of the implementation of P+ source region and PMD;

[0024] Figure 5 This is a cross-sectional schematic diagram of the contact hole etching and helium ion implantation process.

[0025] Figure 6 This is a schematic diagram of the cell cross-section of the final single-event radiation resistant power MOSFET. Detailed Implementation

[0026] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of the manufacturing method of a single-event radiation-resistant power MOSFET proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0027] This invention provides a method for manufacturing a single-particle-resistant power MOSFET, comprising the following steps:

[0028] Step 1: Using a heavily doped semiconductor of the first conductivity type as a substrate, a lightly doped epitaxial layer of the first conductivity type is formed on its surface;

[0029] Step 2: In the lightly doped epitaxial layer of the first conductivity type, a photolithographic body window is formed, and an impurity of the second conductivity type is implanted to form a solid region;

[0030] Step 3: Photolithographically etch a first conductivity type source region window in the body region and perform implantation to form the first conductivity type source region;

[0031] Step 4: Form the gate dielectric on the device surface through thermal oxidation;

[0032] Step 5: Form a polycrystalline gate through polycrystalline deposition and polycrystalline etching;

[0033] Step 6: Photolithographically etch a second conductivity type source region window in the body region and perform implantation to form a second conductivity type source region;

[0034] Step 7: Deposit the media to isolate the PMD and densify it;

[0035] Step 8: Photolithographically etch the contact hole window on the device surface, etch it, and perform light ion implantation to form defects in the bulk region, then remove the resist;

[0036] Step 9: Deposit metal and etch to form the gate and source; stabilize defects by annealing;

[0037] Step 10: Thin the back side of the substrate and deposit metal on the back side to form a drain electrode.

[0038] Specifically, taking an N-type 600V operating voltage single-event radiation resistant power MOSFET as an example, the manufacturing method includes the following steps:

[0039] Step 1: Perform photolithography, implantation, and annealing on a silicon wafer to form the P-body region.

[0040] like Figure 1 As shown, a silicon wafer consists of n + Silicon substrate 1 and n on its surface - The epitaxial layer consists of 2 layers, n + The resistivity of silicon substrate 1 is 0.002–0.004 Ω·cm; n - The resistivity of epitaxial layer 2 is 15 Ω·cm and the thickness is 50 μm.

[0041] A resist is coated onto a silicon wafer, and a patterned window is exposed. Boron ions are then implanted at an energy of 100 keV and a dose of 1 × 10⁻⁶. 14 cm -2 Remove the glue, push the P-body region to form a knot, and the knot depth is 4μm.

[0042] Step 2: Perform photolithography and implantation in the P-body region to form the N+ source region.

[0043] like Figure 2 As shown, the injection method for N+ source region 4 is as follows:

[0044] The first step is phosphorus ion implantation, with an energy of 100 keV and a dose of 2 × 10⁻⁶. 14 cm -2 ;

[0045] The second step involves arsenic ion implantation at an energy of 70 keV and a dose of 4 × 10⁻⁶ keV. 15 cm -2 .

[0046] Step 3: In Figure 2 Thermal oxidation of the gate oxide and deposition of polycrystalline gates are implemented based on the structure.

[0047] like Figure 3 As shown, the thermal oxidation temperature is 900℃, forming a gate oxide 5 with a thickness of 100nm; the polysilicon deposition thickness is 0.6μm, and polysilicon etching is used to form the polysilicon gate 6. At this point, the MOSFET channel engineering is complete.

[0048] Step Four: In Figure 3 Based on the structure, P+ source region photolithography and implantation are performed to deposit the isolation dielectric PMD (metal front dielectric layer) to achieve density.

[0049] like Figure 4 As shown, the implantation conditions for P+ source region 7 are: boron ion implantation, energy of 35 keV, and dose of 3 × 10⁻⁶. 15 cm -2 P+ source region 7 is formed in P body region 3 and is in contact with N+ source region 4.

[0050] A PMD 8 dielectric was deposited across the entire surface, with an undoped SiO2 thickness of 200 nm and a boron-phosphorus SiO2 thickness of 600 nm. Densification was carried out at 900 °C for 30 minutes to stabilize the PMD etching rate and activate impurities.

[0051] Step 5: In Figure 4 Contact hole etching and helium ion implantation are performed based on the structure.

[0052] like Figure 5 As shown, the photoresist thickness of the contact hole is 1.8 μm. After photolithography, UV curing is performed, followed by thermal hardening after contact hole etching. Then, helium ions are implanted into the P-body region 3 to form defect 9. The energy is 750 keV (range Rp is 1.7 μm, longitudinal deviation ΔRp is 0.35 μm), and the dose is 6 × 10⁻⁶. 11 cm -2 .

[0053] Methods for introducing defects into devices include heavy metal diffusion, electron irradiation, and light ion irradiation (implantation). Among these, heavy metal diffusion and electron irradiation defects are difficult to localize; only light ion irradiation (implantation) can precisely control the defect location. (Protons (H)) +The defects implanted by helium ion implantation have poor thermal stability and cannot meet the device operating temperature of 150℃. Helium ion implantation significantly enhances SRH recombination by introducing deep-level defects such as double vacancies (V2) and helium-vacancy complexes (He-V). After annealing, the defects remain stable at 150℃, meeting the operating requirements of power devices.

[0054] He 2+ The implantation is self-aligned. Helium ion implantation directly utilizes the photoresist and masking layer of the contact holes; that is, the photoresist is not removed after the contact holes are etched, and helium ion implantation is performed directly. Assuming a bulk junction depth of 4 μm, the maximum depth of helium ion implantation in silicon is approximately 2 μm. Therefore, the masking layer needs to have a blocking capability greater than 2 μm. The masking layer after contact hole etching includes 1.2-1.8 μm of photoresist, 0.8 μm of SiO2 thickness in the PMD, and 0.6 μm of polysilicon gate thickness, which meets the masking layer thickness requirements for helium ion implantation and saves one photolithography step, thus reducing costs.

[0055] Defect 9 forms below N+ source region 4 and P+ source region 7, outside the space charge region. When a reverse bias voltage is applied to the device, the space charge region is mainly distributed on the side of the lightly doped epitaxial layer, typically tens of micrometers, and can reach hundreds of micrometers in high-voltage devices; the depletion region on the side of the heavily doped bulk region is smaller, typically 1–2 μm. To avoid increasing leakage current, the defect location is controlled outside the space charge region. The helium ion implantation depth is selected as: Rp + ΔRp = bulk junction depth - 2 μm, where Rp is the ion implantation range and ΔRp is the longitudinal deviation.

[0056] By using light ion implantation to generate defects in the power MOSFET, the defects reduce carrier lifetime and enhance recombination of excess carriers, thereby reducing the recovery current of single-particle irradiation and achieving single-particle hardening.

[0057] like Figure 6 As shown, in Figure 5 Based on the structure, metal deposition, metal lithography and etching are performed to form the source electrode and gate electrode of the power MOSFET.

[0058] like Figure 6 As shown, in removing Figure 5 The photoresist in the process deposits aluminum 10 on the surface to a thickness of 5 μm. Then, defect annealing is performed at 420°C for 30 minutes to stabilize the defects.

[0059] The defects introduced by helium ion implantation are mainly double vacancies (V2) and helium-vacancy complexes (He-V). Double vacancy levels are located in the middle of the band gap (Ec -0.23 eV and Ev +0.37 eV), exhibiting high defect concentration and a large trapping cross-section. These are strong recombination centers, dominating minority carrier lifetime and remaining stable below 500 °C. Helium-vacancy complexes, however, have a lower formation probability, accumulating at the implantation end. Their recombination efficiency is lower than that of V2, and they exhibit poor thermal stability due to helium atom diffusion at high temperatures. Therefore, defect annealing conditions are used at 300-500 °C for 30-60 minutes in an atmosphere of N2 or Ar. Defect annealing is performed after metal deposition; the defect annealing of light ion implantation is combined with the alloying annealing of the metal in one step, stabilizing the defects while simultaneously acting as a metal alloy.

[0060] The conditions for defect annealing need to balance lifetime control and high-temperature stability. Higher annealing temperatures result in better high-temperature stability but increase minority carrier lifetime; lower annealing temperatures result in worse high-temperature stability but decrease minority carrier lifetime. Therefore, when the implantation dose is large, the annealing temperature and time need to be increased, and when the implantation dose is small, the annealing temperature and time need to be decreased.

[0061] The back side of the silicon wafer is thinned to 200 μm; TiNiAg metal is deposited on the back side, with a thickness of 2 μm, to form the drain electrode 11.

[0062] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for manufacturing a single-event radiation resistant power MOSFET, characterized in that, include: A bulk region is formed in the doped epitaxial layer of the substrate, and a source region of the first conductivity type is formed in the bulk region; A gate dielectric and a polysilicon gate are formed on the device surface, a second conductivity type source region is formed in the bulk region, and an isolation metal front dielectric layer is deposited. Photolithography and etching are performed on the device surface to form contact hole windows and then light ion implantation is performed to create defects in the bulk region. Metal is deposited and etched to form the gate and source, and defects and metal alloying are stabilized simultaneously through annealing; On the back side of the thinned substrate, metal is deposited to form a drain electrode.

2. The method for manufacturing a single-event radiation resistant power MOSFET as described in claim 1, characterized in that, The light ion is helium ion (He). 2+ The helium ion implantation dose is determined based on the desired minority carrier lifetime, with an implantation dose of 1×10⁻⁶. 11 ~1×10 12 cm -2 At that time, the lifetime of minority carriers ranged from 20 μs to 0.1 μs.

3. The method for manufacturing a single-event radiation resistant power MOSFET as described in claim 1, characterized in that, The light ion implantation is located within the body region, below the contact hole and the source region, and outside the space charge region.

4. The method for manufacturing a single-event radiation resistant power MOSFET as described in claim 1, characterized in that, The annealing conditions for the aforementioned defects need to balance lifetime control and high-temperature stability: when the implantation dose of light ions increases, the annealing temperature and time should be increased; when the implantation dose of light ions decreases, the annealing temperature and time should be decreased.

5. The method for manufacturing a single-event radiation resistant power MOSFET as described in claim 1, characterized in that, The light ion implantation is a self-aligned process that utilizes photoresist and a masking layer on the contact holes of the substrate, eliminating the need for photolithography. After the contact holes are etched, no photoresist is removed; light ion implantation is performed directly, and the photoresist is removed after the light ion implantation is completed.

6. The method for manufacturing a single-event radiation resistant power MOSFET as described in claim 1, characterized in that, The substrate is a heavily doped semiconductor of the first conductivity type, and a lightly doped epitaxial layer of the first conductivity type is formed on its surface; the body region is formed by photolithographically etched body windows in the lightly doped epitaxial layer of the first conductivity type and implanting impurities of the second conductivity type for push junction formation.

7. The method for manufacturing a single-event radiation resistant power MOSFET as described in claim 1, characterized in that, The first conductivity type source region is formed by photolithographically etching a first conductivity type source region window in the body region and then implanting it; the second conductivity type source region is formed by photolithographically etching a second conductivity type source region window in the body region and then implanting it.

8. The method for manufacturing a single-event radiation resistant power MOSFET as described in claim 1, characterized in that, The first conductivity type source region and the second conductivity type source region are in contact.

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