Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, which can be applied to the technical field of semiconductors. The semiconductor device includes a semiconductor-on-insulator (SOI) substrate including a base substrate, an insulating layer on the base substrate, and an SOI layer on the insulating layer, the insulating layer including a ferroelectric layer, a buffer layer on the ferroelectric layer, and a topological insulating layer on the buffer layer; a gate stack on the SOI layer; and source / drain parts at two opposite ends of the gate stack on the SOI layer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor device based on a ferroelectric-topological heterojunction and a method for manufacturing the same. Background Technology

[0002] Fully depleted (FD) semiconductor-on-insulator (SOI) technology has gradually demonstrated its potential in quantum device research due to its excellent electrostatic control capabilities and compatibility with complementary metal-oxide-semiconductor (CMOS) processes. However, as research into quantum devices deepens, performance bottlenecks have emerged in practical applications of FDSOI-based quantum devices. Summary of the Invention

[0003] In view of this, this disclosure provides a semiconductor device based on a ferroelectric-topological heterojunction and a method for manufacturing the same.

[0004] One aspect of this disclosure provides a semiconductor device comprising: a semiconductor-on-insulator (SOI) substrate, including a base substrate, an insulating layer on the base substrate, and an SOI layer on the insulating layer, the insulating layer including a ferroelectric layer, a buffer layer on the ferroelectric layer, and a topological insulating layer on the buffer layer; a gate stack on the SOI layer; and source / drain portions at opposite ends of the gate stack on the SOI layer.

[0005] According to embodiments of the present disclosure, the semiconductor device further includes: a bias application structure disposed on a substrate, configured to apply a bias to the back side of an insulating layer.

[0006] According to embodiments of this disclosure, the ferroelectric material in the ferroelectric layer is configured to change its polarization state in response to a bias voltage.

[0007] According to embodiments of the present disclosure, the topological insulating layer is configured to change the electron distribution and spin state in the surface states in response to a bias voltage.

[0008] According to embodiments of this disclosure, the ferroelectric layer includes hafnium oxide doped with a target element, which includes at least one selected from aluminum, zirconium, yttrium, lanthanum, and strontium.

[0009] According to embodiments of this disclosure, the topological insulating layer includes one of Bi2Te3, Sb2Te3, and Bi2Se3.

[0010] According to embodiments of this disclosure, the buffer layer comprises Al2O3.

[0011] Another aspect of this disclosure provides a method for manufacturing a semiconductor device, comprising: forming a semiconductor-on-insulator (SOI) substrate, wherein the SOI substrate includes a base substrate, an insulating layer on the base substrate, and an SOI layer on the insulating layer, the insulating layer including a ferroelectric layer, a buffer layer on the ferroelectric layer, and a topological insulating layer on the buffer layer; forming a gate structure on the SOI substrate and forming source / drain portions at opposite ends of the gate structure.

[0012] According to embodiments of the present disclosure, forming an SOI substrate includes: sequentially forming a ferroelectric layer, a passivation layer, and a topological insulating layer on a substrate; and forming an SOI layer by bonding the topological insulating layer.

[0013] According to embodiments of this disclosure, forming an SOI layer by bonding it to a topological insulating layer includes: bonding a donor substrate to the topological insulating layer, wherein the donor substrate has cleavage sites defined by hydrogen ion implantation; performing plasma activation; peeling off the donor substrate based on the cleavage sites, leaving the donor substrate on the topological insulating layer to form the SOI layer; and performing low-temperature annealing.

[0014] According to embodiments of the present disclosure, the method further includes: forming a bias application structure on a substrate, the bias application structure being configured to apply a bias to the back side of an insulating layer.

[0015] According to embodiments of the present disclosure, the method further includes: forming an isolation layer on a substrate to form an active region and a hybrid region isolated from each other, wherein a bias application structure is formed in the hybrid region.

[0016] According to embodiments of this disclosure, a ferroelectric-topological heterojunction is formed using a ferroelectric layer, a buffer layer, and a topological insulating layer to replace the buried oxide layer in a conventional SOI substrate. Due to the excellent electric field modulation capability of the ferroelectric layer in its polarized state, an electric field gradient is generated. This electric field gradient can affect the electron distribution and spin state in the surface states of the topological insulating layer, thereby affecting the electron concentration and distribution in the channel. This change can affect the on / off state of the semiconductor device, thus affecting its current driving capability and switching speed. The buffer layer disposed between the ferroelectric layer and the topological insulating layer can reduce the interface defect density caused by lattice mismatch and suppress leakage current. Attached Figure Description

[0017] The above and other objects, features and advantages of this disclosure will become clearer from the following description of embodiments with reference to the accompanying drawings, in which: Figure 1 A schematic diagram illustrating the structure of a semiconductor device according to embodiments of the present disclosure is shown; and Figures 2 to 9 The illustrations schematically depict some stages in the process of manufacturing a semiconductor device according to embodiments of the present disclosure. Detailed Implementation

[0018] The embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0019] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0020] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0021] FDSOI technology relies on fabricating an ultrathin buried oxide layer (SiO2) on bulk silicon and constructing fully depleted transistor channels using an extremely thin silicon film. As integrated circuit feature sizes approach physical limits, the buried oxide layer in traditional FDSOI technology is gradually facing performance bottlenecks: traditional buried oxide layers only provide static insulation and cannot achieve dynamic electric field control, limiting further optimization of transistor gate capacitance, and the single dielectric property is insufficient to meet the requirements of new devices for non-volatile storage and spin degree of freedom manipulation.

[0022] In view of this, the present disclosure provides a semiconductor device based on a ferroelectric-topological heterojunction.

[0023] Figure 1 A schematic diagram of the structure of a semiconductor device according to an embodiment of the present disclosure is shown.

[0024] like Figure 1 As shown, the semiconductor device 100 according to this embodiment includes a semiconductor-on-insulator (SOI) substrate 110, a gate stack 120, a source portion 130, and a drain portion 140.

[0025] SOI substrate 110 includes a base substrate 111, an insulating layer 112 on the base substrate 111, and an SOI layer 113 on the insulating layer 112. Unlike SOI substrates in related technologies that include a buried oxide layer, the insulating layer 112 in the SOI substrate 110 according to this embodiment includes a ferroelectric layer 1121, a buffer layer 1122 on the ferroelectric layer 1121, and a topological insulating layer 1123 on the buffer layer 1122. Gate stack 120 is disposed on SOI layer 113. Source portion 130 and drain portion 140 are disposed at opposite ends of gate stack 120 on SOI layer 113.

[0026] According to embodiments of this disclosure, the ferroelectric layer may include a ferroelectric material, such as, but not limited to, hafnium oxide (HfO2) doped with a target element, including at least one of aluminum (Al), zirconium (Zr), yttrium (Y), lanthanum (La), and strontium (Sr). The topological insulating layer may include a topological insulating material, such as, but not limited to, bismuth telluride (Bi2Te3), antimony telluride (Sb2Te3), and bismuth selenide (Bi2Se3). The buffer layer may include a material for reducing lattice mismatch between the ferroelectric layer and the topological insulating layer (e.g., a material whose lattice constant is between that of the ferroelectric layer and the topological insulating layer), such as, but not limited to, aluminum oxide (Al2O3).

[0027] According to embodiments of this disclosure, a ferroelectric-topological heterojunction is formed using a ferroelectric layer, a buffer layer, and a topological insulating layer to replace the buried oxide layer in a conventional SOI substrate. Due to the excellent electric field modulation capability of the ferroelectric layer in its polarized state, an electric field gradient is generated. This electric field gradient can affect the electron distribution and spin state in the surface states of the topological insulating layer, thereby affecting the electron concentration and distribution in the channel. This change can affect the on / off state of the semiconductor device, thus affecting its current driving capability and switching speed. The buffer layer disposed between the ferroelectric layer and the topological insulating layer can reduce the interface defect density caused by lattice mismatch and suppress leakage current.

[0028] like Figure 1 As shown, the semiconductor device 100 may further include a bias application structure 150 disposed on the substrate 111, configured to apply a bias to the back side of the insulating layer 112.

[0029] Although the bias application structure 150 is shown in this embodiment as extending downward from the front side through the insulating layer to connect to the substrate 111, this disclosure is not limited thereto. According to other embodiments of this disclosure, the bias application structure 150 may also be connected to the substrate 111 from the back side.

[0030] According to embodiments of this disclosure, the ferroelectric material in the ferroelectric layer 1121 is configured to change its polarization state in response to a bias voltage. The topological insulating layer 1123 is configured to change the electron distribution and spin state in the surface states in response to a bias voltage.

[0031] According to embodiments of this disclosure, a back gate can be formed on the substrate 111, and a bias voltage is received via a bias voltage application structure 150. By applying a bias voltage to the back side of the insulating layer 112 through the bias voltage application structure 150, the polarization state of the ferroelectric material in the ferroelectric layer 1121 can be changed, thereby adjusting the electric field gradient generated by the ferroelectric layer 1121. The electron distribution and spin state in the surface states of the topological insulating layer 1123 can also be altered.

[0032] Based on the semiconductor device disclosed herein, this disclosure also provides a method for manufacturing a semiconductor device, comprising: forming a semiconductor on insulator (SOI) substrate, wherein the SOI substrate includes a base substrate, an insulating layer on the base substrate, and an SOI layer on the insulating layer, the insulating layer including a ferroelectric layer, a buffer layer on the ferroelectric layer, and a topological insulating layer on the buffer layer; forming a gate structure on the SOI substrate and forming source / drain portions at opposite ends of the gate structure.

[0033] According to embodiments of this disclosure, an SOI substrate can be formed by bonding. For example, a ferroelectric layer, a passivation layer, and a topological insulating layer can be sequentially formed on a substrate, and an SOI layer can be formed on the topological insulating layer by bonding.

[0034] According to embodiments of this disclosure, a smart-cut technique can be used to bond an SOI layer onto a topological insulating layer. For example, a donor substrate can be bonded to the topological insulating layer, wherein the donor substrate has cut sites defined by hydrogen ion implantation; plasma activation can be performed; the donor substrate can be peeled off based on the cut sites, leaving the donor substrate on the topological insulating layer to form the SOI layer; and low-temperature annealing can be performed.

[0035] According to embodiments of the present disclosure, the above method may further include: forming a bias application structure on a substrate, the bias application structure being configured to apply a bias to the back side of an insulating layer.

[0036] According to embodiments of this disclosure, the method may further include: forming an isolation layer on a substrate to form an active region and a hybrid region isolated from each other, wherein a bias application structure is formed in the hybrid region.

[0037] This disclosure may be presented in various forms, some of which will be described below. In the following description, the selection of various materials is discussed. The selection of materials takes into account not only their function (e.g., semiconductor materials for forming active regions, dielectric materials for forming electrical isolation) but also etch selectivity. In the following description, the desired etch selectivity may or may not be indicated. Those skilled in the art will understand that when the following references to etching a material layer, unless it is mentioned that other layers are also etched or not shown in the figures, then such etching may be selective, and the material layer may possess etch selectivity relative to other layers exposed to the same etch formulation.

[0038] Figures 2 to 9 The illustrations schematically depict some stages in the process of manufacturing a semiconductor device according to embodiments of the present disclosure.

[0039] like Figure 2 As shown, a substrate 111 may be provided. The substrate 111 may include a suitable semiconductor material, such as silicon (Si). An insulating layer 112 may be formed on the substrate 111. As described above, the insulating layer 112 may include a ferroelectric layer 1121, a buffer layer 1122 on the ferroelectric layer 1121, and a topological insulating layer 1123 on the buffer layer 1122. For example, the ferroelectric layer 1121 with a thickness of about 5-10 nm may be formed by atomic layer deposition (ALD), the buffer layer 1122 with a thickness of about 1-2 nm may be deposited, and the topological insulating layer 1123 with a thickness of about 3-5 nm may be formed by, for example, molecular beam epitaxy (MBE).

[0040] like Figure 3 As shown, a donor substrate 310 can be provided, and hydrogen (H) ions can be implanted into the donor substrate 310 by ion implantation to define the cutting position (as shown by the dotted line in the figure).

[0041] like Figure 4 and 5 As shown, Figure 3 The donor substrate 310 with a defined cutting position and Figure 2 The topological insulating layer 1123 is bonded. Plasma activation can be performed to enhance the bonding strength and ensure the interface quality between the insulating layer 112 and the SOI layer. Subsequently, based on a defined cutting position, the portion of the donor substrate 310 away from the topological insulating layer 1123 is peeled off, so that the donor substrate 310 remaining on the topological insulating layer 1123 forms the SOI layer 113. Low-temperature annealing can be performed, for example, at a temperature below 400°C, to repair crystal defects.

[0042] Thus, an SOI substrate according to an embodiment of the present disclosure is obtained. As described above, the SOI substrate may include a substrate 111, an insulating layer 112 on the substrate 111, and an SOI layer 113 on the insulating layer 112, wherein the insulating layer 112 includes a ferroelectric layer 1121, a buffer layer 1122 on the ferroelectric layer 1121, and a topological insulating layer 1123 on the buffer layer 1122.

[0043] Various SOI devices, such as FDSOI devices, can be fabricated on such SOI substrates. Various SOI processes exist in the art; only a few examples are described below.

[0044] like Figure 6 As shown, the active region AA and the hybrid region Hybrid can be defined on the SOI substrate by means of an isolation layer 610, such as shallow trench isolation (STI). According to other embodiments, the isolation layer 610 can also be formed by silicon local oxide isolation (LOCOS) or convex isolation (Mesa).

[0045] like Figure 7 and 8 As shown, in the hybrid region, the insulating layer can be removed using photolithography and etching to expose the substrate 111. On the exposed substrate 111, Si material can be grown, for example, epitaxially, and a corresponding device can subsequently be fabricated in the hybrid region. According to one embodiment of this disclosure, a bias application structure 150 can be formed in the hybrid region.

[0046] like Figure 9As shown, a gate stack 120 can be formed on the active region AA. The gate stack 120 may include a gate oxide layer 121, a gate dielectric layer 122, a capping layer 123, an etch barrier layer 124, a work function layer 125, and a metal interconnect layer 126. The gate oxide layer 121 may include an oxide, such as SiO2. The gate dielectric layer 122 may include a high-k material, such as HfO2. The capping layer 123 may include a nitride, such as titanium nitride (TiN). The capping layer 123 contacts the gate dielectric layer 122 and can form a dense interface with a thickness of about 2-3 nm through atomic layer deposition (ALD) to reduce the interface state density. The etch barrier layer 124 may include a nitride, such as tantalum nitride (TaN), and its thickness may be about 3-5 nm. The work function adjustment layer 125 may include a nitride, such as TiN, and functions to adjust the PMOS threshold voltage. The metal interconnect layer 126 may include a metallic material, such as tungsten (W), which can improve conductivity and reduce contact resistance. Sidewalls 127 may be formed on the sidewalls of the gate stack 120, and source portions 130 and drain portions 140 may be formed at opposite ends of the gate stack 120. Silicides 160, such as nickel-based silicides, may be formed on the surfaces of the source portions 130 and drain portions 140 to reduce contact resistance and improve device performance. The source portions 130 and drain portions 140 may include semiconductor layers such as SiGe formed epitaxially on an SOI layer.

[0047] The semiconductor devices according to embodiments of this disclosure can be applied to various electronic devices. For example, integrated circuits (ICs) can be formed based on such semiconductor devices, and electronic devices can be constructed therefrom. Such electronic devices may also include components such as display screens that cooperate with the integrated circuits and wireless transceivers that cooperate with the integrated circuits. Examples of such electronic devices include smartphones, computers, tablet computers, wearable smart devices, artificial intelligence devices, and power banks.

[0048] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0049] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A semiconductor device, comprising: A semiconductor-on-insulator (SOI) substrate includes a substrate, an insulating layer on the substrate, and an SOI layer on the insulating layer. The insulating layer includes a ferroelectric layer, a buffer layer on the ferroelectric layer, and a topological insulating layer on the buffer layer. Gate stacking on the SOI layer; as well as The source / drain portions at opposite ends of the gate stack on the SOI layer.

2. The semiconductor device according to claim 1, further comprising: A bias application structure disposed on the substrate is configured to apply a bias voltage to the back side of the insulating layer.

3. The semiconductor device according to claim 2, wherein, The ferroelectric material in the ferroelectric layer is configured to change its polarization state in response to the bias voltage.

4. The semiconductor device according to claim 2, wherein, The topological insulating layer is configured to change the electron distribution and spin state in the surface states in response to the bias voltage.

5. The semiconductor device according to claim 1, wherein, The ferroelectric layer includes hafnium oxide doped with a target element, which includes at least one of aluminum, zirconium, yttrium, lanthanum, and strontium.

6. The semiconductor device according to any one of claims 1 to 5, wherein, The topological insulating layer includes one of Bi2Te3, Sb2Te3, and Bi2Se3.

7. The semiconductor device according to any one of claims 1 to 5, wherein, The buffer layer comprises Al2O3.

8. A method for manufacturing a semiconductor device, comprising: A semiconductor-on-insulator (SOI) substrate is formed, wherein the SOI substrate includes a base substrate, an insulating layer on the base substrate, and an SOI layer on the insulating layer, and the insulating layer includes a ferroelectric layer, a buffer layer on the ferroelectric layer, and a topological insulating layer on the buffer layer; A gate structure is formed on the SOI substrate, and source / drain portions are formed at opposite ends of the gate structure.

9. The method according to claim 8, wherein, The formation of the SOI substrate includes: The ferroelectric layer, the passivation layer, and the topological insulating layer are sequentially formed on the substrate. The SOI layer is formed by bonding to the topological insulating layer.

10. The method according to claim 9, wherein, The process of forming the SOI layer by bonding it onto the topological insulating layer includes: The donor substrate is bonded to the topological insulating layer, wherein the donor substrate has cleavage sites defined by hydrogen ion implantation; Plasma activation was performed; The donor substrate is peeled off based on the cutting position, and the donor substrate remaining on the topological insulating layer forms the SOI layer; and Perform low-temperature annealing.

11. The method of claim 10, further comprising: A bias application structure is formed on the substrate, the bias application structure being configured to apply a bias to the back side of the insulating layer.

12. The method of claim 11, further comprising: An isolation layer is formed on the substrate to form an active region and a hybrid region that are isolated from each other, wherein the bias application structure is formed in the hybrid region.

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