A novel gate silicon carbide power device and a preparation method and chip thereof

Abstract

The application belongs to the technical field of power devices, and provides a novel gate silicon carbide power device, a preparation method thereof and a chip. A gallium nitride layer is formed on a current spreading layer, a P-type well region and an N-type heavily doped region. The gallium nitride layer covers the P-type well region and the current spreading layer. A gallium oxide layer is formed on the gallium nitride layer. A high-K dielectric layer is formed on the gallium oxide layer. A gate layer is formed on the high-K dielectric layer. A composite gate dielectric structure is formed by the gallium nitride layer, the gallium oxide layer and the high-K dielectric layer, which is beneficial to reducing the on-resistance of the device.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of power devices, and particularly relates to a novel gate silicon carbide power device and a preparation method and chip thereof. BACKGROUND

[0002] As a wide-bandgap semiconductor material, silicon carbide (SiC) has been widely used in the manufacture of power semiconductor devices under high-temperature, high-frequency, high-voltage and radiation-resistant environments due to its high bandgap, high thermal conductivity, high critical breakdown field, high saturation electron velocity and low intrinsic carrier concentration. However, although SiC material has so many excellent properties, the MOS device composed of SiC still faces many challenges in terms of channel electron mobility and reliability of high-K dielectric layer.

[0003] In traditional SiC power devices, silicon oxide is usually used as the gate dielectric, and there are a large number of interface defects between the gate dielectric and the SiC epitaxial layer, including interface traps on the surface of SiC semiconductor, near-interface traps in the transition layer and oxide layer traps in the silicon oxide gate dielectric. These defects lead to a decrease in the channel mobility of SiC power devices, affecting the characteristics of the device, and the near-interface traps can cause the threshold voltage of the device to drift, and the oxide layer traps in the silicon oxide gate dielectric can also reduce the reliability of the gate oxide of the device. SUMMARY

[0004] To solve the above technical problems, the application provides a novel gate silicon carbide power device and a preparation method and chip thereof, aiming to solve the problems of low channel electron mobility of SiC devices, dense gate oxide interface defects and difficulty in forming good lattice matching with high-K dielectric materials.

[0005] The first aspect of the application provides a novel gate silicon carbide power device, which comprises:

[0006] a silicon carbide substrate;

[0007] an N-type drift region formed on the front surface of the silicon carbide substrate;

[0008] a current spreading layer formed on the N-type drift region;

[0009] a P-type well region formed on the N-type drift region and located on both sides of the current spreading layer;

[0010] a P-type heavily doped region formed on the N-type drift region; wherein the P-type heavily doped region and the current spreading layer are separated by the P-type well region;

[0011] An N-type heavily doped region formed on the P-type well region; wherein the N-type heavily doped region is separated from the current spreading layer at adjacent positions by the P-type well region, the N-type heavily doped region is in contact with the corresponding P-type heavily doped region, and the thickness of the N-type heavily doped region is less than the thickness of the P-type well region;

[0012] A gallium nitride layer formed on the current spreading layer, the P-type well region, and the N-type heavily doped region, covering the P-type well region and the current spreading layer;

[0013] A gallium oxide layer formed on the gallium nitride layer;

[0014] A high-K dielectric layer formed on the gallium oxide layer; wherein the gallium nitride layer, the gallium oxide layer, and the high-K dielectric layer form a composite gate dielectric structure;

[0015] A gate layer formed on the high-K dielectric layer;

[0016] An interlayer dielectric layer forming a closed structure with the high-K dielectric layer to wrap the gate layer;

[0017] A first electrode layer covering the interlayer dielectric layer, the N-type heavily doped region, and the P-type heavily doped region;

[0018] A second electrode layer formed on the back surface of the silicon carbide substrate.

[0019] In some embodiments, the gallium oxide layer is a β-Ga2O3 thin film; and / or, the thickness of the gallium oxide layer is 50-100 nm.

[0020] In some embodiments, the thickness of the gallium nitride layer is 20-100 nm.

[0021] In some embodiments, the high-K dielectric layer is at least one of aluminum oxide, hafnium oxide, magnesium gallate, hafnium gallate, hafnium titanium oxide; and / or, the thickness of the high-K dielectric layer is 30-100 nm.

[0022] In some embodiments, the gallium nitride layer and the gallium oxide layer are also formed between the first electrode layer and the P-type heavily doped region, and between the first electrode layer and the N-type heavily doped region; the width of the gallium nitride layer and the gallium oxide layer is the same, and the width of the high-K dielectric layer is less than the width of the gallium nitride layer.

[0023] In some embodiments, the width of the gallium nitride layer, the gallium oxide layer, the high-K dielectric layer, and the interlayer dielectric layer is the same.

[0024] In some embodiments, the gallium nitride layer, the gallium oxide layer, and portions of the P-type heavily doped region and the N-type heavily doped region overlap.

[0025] The second aspect of the embodiments of the present application further provides a novel gate silicon carbide power device, which comprises:

[0026] a silicon carbide substrate;

[0027] an N-type drift region formed on the front surface of the silicon carbide substrate; the N-type drift region is a concave structure;

[0028] a P-type well region formed on both sides of the N-type drift region;

[0029] an N-type heavily doped region formed on the P-type well region;

[0030] a P-type heavily doped region formed on both sides of the N-type drift region;

[0031] a gallium nitride layer formed along the inner wall of the groove of the N-type drift region; the gallium nitride layer is in contact with the P-type well region and the N-type heavily doped region;

[0032] a gallium oxide layer formed on the surface of the gallium nitride layer;

[0033] a high-K dielectric layer formed on the surface of the gallium oxide layer; wherein the gallium nitride layer, the gallium oxide layer, and the high-K dielectric layer are in a U-shaped structure, and the gallium nitride layer, the gallium oxide layer, and the high-K dielectric layer form a composite gate dielectric structure;

[0034] a gate layer formed in the groove of the high-K dielectric layer;

[0035] an interlayer dielectric layer formed on the gate layer and the N-type heavily doped region, and forming a closed structure with the high-K dielectric layer to wrap the gate layer;

[0036] a first electrode layer covering the interlayer dielectric layer, the N-type heavily doped region, and the P-type heavily doped region;

[0037] a second electrode layer formed on the back surface of the silicon carbide substrate.

[0038] The third aspect of the embodiments of the present application further provides a preparation method of a novel gate silicon carbide power device, which comprises:

[0039] forming an N-type drift region on the front surface of a silicon carbide substrate;

[0040] forming a gallium nitride layer on the N-type drift region, and forming a gallium oxide layer on the gallium nitride layer;

[0041] P-type and N-type doping ions are implanted into the designated regions of the N-type drift region respectively in multiple times to form current spreading layer, P-type well region, P-type heavily doped region and N-type heavily doped region; wherein the N-type heavily doped region is separated from the current spreading layer at the adjacent position by the P-type well region, the N-type heavily doped region is in contact with the corresponding P-type heavily doped region, and the thickness of the N-type heavily doped region is less than the thickness of the P-type well region;

[0042] A high-K dielectric layer is formed on the gallium oxide layer;

[0043] A gate layer is formed on the high-K dielectric layer, and then an interlayer dielectric layer is formed; the interlayer dielectric layer and the high-K dielectric layer form a closed structure to wrap the gate layer;

[0044] A first electrode layer is formed covering the interlayer dielectric layer, the N-type heavily doped region and the P-type heavily doped region;

[0045] A second electrode layer is formed on the back surface of the silicon carbide substrate.

[0046] The fourth aspect of the embodiments of the present application further provides a chip comprising the novel gate silicon carbide power device as described in any of the above embodiments.

[0047] The beneficial effects of the embodiments of the present application are: by forming a gallium nitride layer on the current spreading layer, P-type well region and N-type heavily doped region, the gallium nitride layer covers the P-type well region and the current spreading layer, the gallium oxide layer is formed on the gallium nitride layer, the high-K dielectric layer is formed on the gallium oxide layer, and the gate layer is formed on the high-K dielectric layer, thereby forming a composite gate dielectric structure by the gallium nitride layer, the gallium oxide layer and the high-K dielectric layer, which is beneficial to reduce the on-resistance of the device. BRIEF DESCRIPTION OF DRAWINGS

[0048] Figure 1 is a structure diagram of the novel gate silicon carbide power device provided by the embodiments of the present application Figure 1 ;

[0049] Figure 2 is a structure diagram of the novel gate silicon carbide power device provided by the embodiments of the present application Figure 2 ;

[0050] Figure 3 is a structure diagram of the novel gate silicon carbide power device provided by the embodiments of the present application Figure 3 ;

[0051] Figure 4 is a structure diagram of the novel gate silicon carbide power device provided by the embodiments of the present application Figure 4 ;

[0052] Figure 5a is Figure 1A partial cross-sectional schematic diagram of the cross-section AA of the novel gate silicon carbide power device;

[0053] Figure 5b yes Figure 1 A partial cross-sectional schematic diagram of the cross-section AA of the novel gate silicon carbide power device;

[0054] Figure 5c yes Figure 1 A partial cross-sectional schematic diagram of the cross-section AA of the novel gate silicon carbide power device;

[0055] Figure 5d yes Figure 1 A partial cross-sectional schematic diagram of the cross-section AA of the novel gate silicon carbide power device;

[0056] Figure 5e yes Figure 1 A partial cross-sectional schematic diagram of the cross-section AA of the novel gate silicon carbide power device;

[0057] Figure 5f yes Figure 1 A partial cross-sectional schematic diagram of the cross-section AA of the novel gate silicon carbide power device;

[0058] Figure 5g yes Figure 1 A partial cross-sectional schematic diagram of the cross-section AA of the novel gate silicon carbide power device;

[0059] Figure 6 This is a schematic diagram of the structure of the novel gate silicon carbide power device provided in the embodiments of this application (Figure 5).

[0060] Figure 7 This is a schematic diagram of the structure of the novel gate silicon carbide power device provided in the embodiments of this application. Figure 6 ;

[0061] Figure 8 This is a schematic flowchart of the fabrication method of the novel gate silicon carbide power device provided in the embodiments of this application;

[0062] Figure 9 This is a partial schematic diagram of the fabrication method of the novel gate silicon carbide power device provided in the embodiments of this application. Detailed Implementation

[0063] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0064] In a conventional SiC power device, silicon oxide is usually used as the gate dielectric material. There are a large number of interface defects between the silicon oxide and the SiC substrate, including interface traps on the surface of the SiC semiconductor, near-interface traps in the transition layer, and oxide layer traps in the silicon oxide gate dielectric. These defects reduce the channel mobility of the SiC power device and affect the characteristics of the device. Near-interface traps can cause the threshold voltage of the device to drift, and oxide layer traps in the silicon oxide gate dielectric can also reduce the reliability of the gate oxide of the device.

[0065] To solve the above technical problems, the embodiments of the present application provide a new gate silicon carbide power device, which comprises a silicon carbide substrate 110, an N-type drift region 120, a current spreading layer 210, a P-type well region 310, a P-type heavily doped region 410, an N-type heavily doped region 510, a gallium nitride layer 631, a gallium oxide layer 632, a high-K dielectric layer 633, a gate layer 620, an interlayer dielectric layer 610, a first electrode layer 710, and a second electrode layer 720.

[0066] The N-type drift region 120 is formed on the front surface of the silicon carbide substrate 110, the current spreading layer 210 is formed on the N-type drift region 120, the P-type well region 310 is formed on the N-type drift region 120 and located on both sides of the current spreading layer 210. The P-type heavily doped region 410 is formed on the N-type drift region 120, and the P-type heavily doped region 410 is separated from the current spreading layer 210 by the P-type well region 310. The N-type heavily doped region 510 is formed on the P-type well region 310, and the N-type heavily doped region 510 is separated from the adjacent current spreading layer 210 by the P-type well region 310. The N-type heavily doped region 510 is in contact with the corresponding P-type heavily doped region 410, and the thickness of the N-type heavily doped region 510 is less than the thickness of the P-type well region 310.

[0067] The gallium nitride layer 631 is formed on the current spreading layer 210, the P-type well region 310, and the N-type heavily doped region 510, and covers the P-type well region 310 and the current spreading layer 210. The gallium oxide layer 632 is formed on the gallium nitride layer 631, and the high-K dielectric layer 633 is formed on the gallium oxide layer 632. The gallium nitride layer 631, the gallium oxide layer 632, and the high-K dielectric layer 633 form a composite gate dielectric structure. The gate layer 620 is formed on the high-K dielectric layer 633, and the interlayer dielectric layer 610 and the high-K dielectric layer 633 form a closed structure to wrap the gate layer 620. The first electrode layer 710 covers the interlayer dielectric layer 610, the N-type heavily doped region 510, and the P-type heavily doped region 410, and the second electrode layer 720 is formed on the back surface of the silicon carbide substrate 110.

[0068] In this embodiment, a gallium nitride (GaN) layer 631 is formed on the current spread layer 210, the P-type well region 310, and the N-type heavily doped region 510. The GaN layer 631 covers the P-type well region 310 and the current spread layer 210. A gallium oxide (GaO) layer 632 is formed on the GaN layer 631, a high-K dielectric layer 633 is formed on the GaO layer 632, and a gate layer 620 is formed on the high-K dielectric layer 633. Thus, a composite gate dielectric structure is formed by the GaN layer 631, the GaO layer 632, and the high-K dielectric layer 633. Compared with the traditional SiO2 / SiC structure, the interface defect density of the high-K dielectric layer 633 / Ga2O3 is significantly reduced, effectively solving the interface trap problem, significantly improving the channel mobility, and helping to reduce the on-resistance of the device. Furthermore, Ga2O3 has good lattice matching with high-k dielectric layers 633 (such as hafnium oxide, magnesium gallium oxide, zirconium gallium oxide, zirconium titanium oxide, etc.), which can form a stable MIS (metal-insulator-semiconductor) structure, effectively reducing gate leakage capacitance and improving the dynamic characteristics of the device.

[0069] In some embodiments, the gate layer 620 is an alloy material, which may be a TiN / TaN / Hf-based alloy.

[0070] In some embodiments, when the gate dielectric material is a high-K dielectric layer 633 (such as HfO2, ZrO2 or Al2O3), the gate layer 620 is a metal (such as TiN, TaN or Hf-based alloy) instead of conventional polycrystalline silicon material, to avoid chemical reaction between polycrystalline silicon material and high-K dielectric layer 633. Using a metal gate can effectively shield the long-range phonon scattering of high-K dielectric layer 633, eliminate the depletion effect of polycrystalline silicon, and enhance gate control capability.

[0071] In some embodiments, the gallium oxide layer 632 is a β-Ga2O3 thin film.

[0072] In this embodiment, the interface characteristics between the gate dielectric and the semiconductor substrate are effectively improved by adopting a high-k dielectric layer 633 / gallium oxide layer 632 / gallium nitride layer 631 / SiC structure. Compared with the traditional SiO2 / SiC structure, the interface defect density of the high-k dielectric layer 633 / β-Ga2O3 film is significantly reduced, and the interface state density can be controlled at 1-6E11 / cm² after annealing and passivation treatment. 2 This significantly improves channel mobility, effectively solving the interface trap problem and achieving a channel migration rate of 20-25cm. 2 Significant progress has been made in / (Vs).

[0073] In some embodiments, combined with Figure 1As shown, the gallium nitride layer 631 and the β-Ga2O3 film do not overlap with the N-type heavily doped region 510 and the P-type well region 310, the first electrode layer 710 is in contact with the SiC material surface, and the first electrode layer 710 is in contact with the interlayer dielectric layer 610, the N-type heavily doped region 510, and the P-type heavily doped region 410.

[0074] In some embodiments, the thickness of the gallium oxide layer 632 is 50-100 nm.

[0075] In some embodiments, the thickness of the gallium nitride layer 631 is 20-100 nm.

[0076] In the present embodiment, the novel gate silicon carbide power device is designed reasonably, the materials of each layer are selected optimally, and at a suitable thickness, the purposes of reducing the channel resistance, improving the channel mobility, and reducing the gate leakage are achieved simultaneously, the application requirements of high-performance power semiconductor devices are met, the Ga2O3 and the high-K dielectric layer 633 (such as hafnium oxide, magnesium gallium oxide, zirconium gallium oxide, zirconium titanium oxide, etc.) have good lattice matching degree, a stable MIS (metal-insulator-semiconductor) structure can be formed, the gate leakage capacitance is effectively reduced, and the dynamic characteristics of the device are improved.

[0077] In some embodiments, the high-K dielectric layer 633 is at least one of aluminum oxide, hafnium oxide, magnesium gallium oxide, gallium gallium oxide, and gallium titanium oxide.

[0078] In the present embodiment, the dielectric constant of the high-K dielectric layer 633 is greater than or equal to 3.9, the gallium oxide layer 632 and the high-K dielectric layer 633 (such as hafnium oxide, magnesium gallium oxide, zirconium gallium oxide, zirconium titanium oxide, etc.) have good lattice matching degree, a stable MIS (metal-insulator-semiconductor) structure can be formed, the gate leakage capacitance is effectively reduced, and the dynamic characteristics of the device are improved.

[0079] In some embodiments, the thickness of the high-K dielectric layer 633 is 30-100 nm.

[0080] In some embodiments, the combination of the gallium nitride layer 631 and the gallium oxide layer 632 is used. Figure 2 As shown, the gallium nitride layer 631 and the gallium oxide layer 632 overlap with part of the P-type heavily doped region 410 and the N-type heavily doped region 510.

[0081] In the embodiment, the gallium nitride layer 631 and the gallium oxide layer 632 are formed after the N-type drift region 120, and after the gallium nitride layer 631 and the gallium oxide layer 632 are formed, P-type and N-type doping ions are implanted into partial regions of the gallium oxide layer 632 by an ion implantation process to form the P-type heavily doped region 410 and the N-type heavily doped region 510, and at this time, the P-type and N-type doping ions are doped into the gallium nitride layer 631 and the gallium oxide layer 632, so that the gallium nitride layer 631 and the gallium oxide layer 632 overlap with partial regions of the P-type heavily doped region 410 and the N-type heavily doped region 510.

[0082] In some embodiments, in combination with Figure 3 As shown in FIG. 6, the gallium nitride layer 631 and the gallium oxide layer 632 are also formed between the first electrode layer 710 and the P-type heavily doped region 410, and between the first electrode layer 710 and the N-type heavily doped region 510; the gallium nitride layer 631 and the gallium oxide layer 632 have the same width, and the width of the high-K dielectric layer 633 is smaller than the width of the gallium nitride layer 631.

[0083] In the embodiment, the gallium oxide layer 632 is a β-Ga2O3 film, the gallium nitride layer 631 / β-Ga2O3 film overlaps with the N-type heavily doped region 510 and the P-type source region, and the first electrode layer 710 is connected to the surface of the β-Ga2O3 film.

[0084] In some embodiments, referring to Figure 1 As shown in FIG. 6, the gallium nitride layer 631, the gallium oxide layer 632, the high-K dielectric layer 633, and the interlayer dielectric layer 610 have the same width.

[0085] In some embodiments, the silicon carbide substrate 110 can be N-type doped, and at this time, the novel gate silicon carbide power device can be in a MOS structure, the first electrode layer 710 is a source electrode, and the second electrode 720 is a drain electrode.

[0086] In some embodiments, referring to Figure 4 As shown in FIG. 6, the silicon carbide substrate 110 can be P-type doped, and at this time, the novel gate silicon carbide power device can be in an IGBT structure, the first electrode layer 710 is an emitter electrode, and the second electrode 720 is a collector electrode.

[0087] In some embodiments, Figure 1 The cross section AA of the novel gate silicon carbide power device in FIG. 6 is as shown in FIG. 7. Figure 5a to Figure 5g Any pattern in FIG. 6.

[0088] In combination with Figure 5a As shown in FIG. 6, each current spreading layer 210 is provided with a P-type heavily doped region 410 on both sides, and each P-type heavily doped region 410 is provided with an N-type heavily doped region 510 on both sides.

[0089] In this embodiment, the first direction is perpendicular to the second direction. A P-type blocking region 311 is provided at the intersection of the current spreading layer 210 arranged along the first direction and the current spreading layer 210 arranged along the second direction. The increased area of ​​the P-type well region 310 increases the depletion region capacitance, resulting in a smaller Qgd and faster switching compared to a square structure. The P-type blocking region 311 (block region) and the P-type well region 310 together enclose the current spreading layer 210, providing a stronger depletion effect than other layouts. This reduces the reverse leakage current IDSS. Furthermore, the device can enter the saturation region earlier when turned on, clamping the saturation current and optimizing the short-circuit characteristics. Moreover, in the fabrication process, the P-type blocking region 311 (block region) and the conventional P-type well region 310 use the same photomask, requiring no additional cost.

[0090] In some embodiments, the doping concentrations of the P-type well region 310, the current spreading layer 210, and the P-type heavily doped region 410 are all approximately box-shaped.

[0091] In some embodiments, the P-type heavily doped region 410 and the N-type heavily doped region 510 are arranged in a single direction, that is, they can be arranged in the manner of N-type heavily doped region 510 / P-type heavily doped region 410 / N-type heavily doped region 510.

[0092] In some embodiments, the area of ​​the P-type blocking region 311 is approximately 10-30% of the area of ​​the P-type well region 310. The current spreading layer 210 and the P-type well region 310 form a lateral PN junction structure, that is, a superjunction-like structure in which the P-type well region 310 surrounds the N-type current spreading layer 210.

[0093] In this embodiment, the superjunction-like structure allows the current spreading layer 210 to be doped with higher donor impurities, thus effectively reducing the on-resistance while ensuring ideal BVDSS. The novel gate silicon carbide power device in this embodiment has a current density that is 34-40% higher than that of the strip layout and 10% higher than that of the square, staggered square, or hexagonal layouts.

[0094] In some embodiments, combined with Figure 5b As shown, the N-type heavily doped region 510 has an annular cross-sectional shape and is arranged around the P-type heavily doped region 410 in the horizontal cross-section.

[0095] In this embodiment, the N-type heavily doped region 510 has a ring-shaped square structure in the horizontal cross-section.

[0096] In some embodiments, combined with Figure 5c As shown, the intersection area of ​​the current spreading layer 210 arranged along the first direction and the current spreading layer 210 arranged along the second direction is a P-type blocking area 311 (block area).

[0097] In some embodiments, the P-type block region 311 is a hollow square structure.

[0098] In some embodiments, a central region in the P-type block region 311 is further provided with a current spreading layer 210 with a smaller area.

[0099] In some embodiments, the P-type heavily doped region 410 and the N-type heavily doped region 510 are arranged in a staggered manner. Figure 5d As shown in FIG. 6, the N-type heavily doped region 510 and the P-type heavily doped region 410 are arranged on both sides of the current spreading layer 210, and the intersection of the lines connecting the two adjacent N-type heavily doped regions 510 and the lines connecting the two adjacent P-type heavily doped regions 410 is located in the region between the two adjacent current spreading layers 210.

[0100] In this embodiment, the current spreading layer 210 has a rectangular shape in the horizontal cross-section, and the long sides of the current spreading layers 210 arranged in the first direction are parallel to the first direction, and the long sides of the current spreading layers 210 arranged in the second direction are perpendicular to the second direction. One long side of the current spreading layer 210 is provided with a P-type heavily doped region 410, and the other long side of the current spreading layer 210 is provided with an N-type heavily doped region 510. In this way, the N-type heavily doped region 510 and the P-type heavily doped region 410 are arranged diagonally to each other.

[0101] In some embodiments, as shown in FIG. 7, the cell has a rectangular structure, and three current spreading layers 210 are arranged in the second direction, and the long sides of the three current spreading layers 210 are parallel to the second direction. Each current spreading layer 210 in the second direction is provided with an N-type heavily doped region 510 / P-type heavily doped region 410 / N-type heavily doped region 510 structure on both sides, and a current spreading layer 210 arranged in the first direction is further arranged between each side of the adjacent N-type heavily doped region 510 / P-type heavily doped region 410 / N-type heavily doped region 510 structure. Figure 5e In some embodiments, as shown in FIG. 8, the P-type heavily doped region 410 has a hexagonal shape in the horizontal cross-section, and the N-type heavily doped region 510 also has a hexagonal structure.

[0102] Figure 5f In some embodiments, the plurality of current spreading layers 210 are sequentially arranged in the first direction, the second direction, and the third direction in the horizontal cross-section, and the angle between the first direction and the second direction is 120°, and the angle between the first direction and the third direction is 120°.

[0103] In some embodiments, the plurality of current spreading layers 210 are arranged in a plurality of directions, and the intersection region of the plurality of directions is provided with a current spreading layer 210.

[0104] In some embodiments, the plurality of current spreading layers 210 are arranged in a plurality of directions, and the intersection region of the plurality of directions is provided with a current spreading layer 210. ​

[0105] In some embodiments, the cross-sectional shape of the current spreading layer 210 in the intersection area of ​​multiple directions is square or triangular.

[0106] In some embodiments, such as Figure 5g As shown, in the case of a hexagonal cell layout, the block region is a hollow triangle, that is, the intersection area of ​​the first direction, the second direction and the third direction is filled by the triangular current extension layer 210.

[0107] In some embodiments, combined with Figure 5c As shown, multiple current extension layers 210 are arranged sequentially in a first direction and a second direction on a horizontal cross section. The first direction and the second direction are perpendicular. A square current extension layer 210 is provided in the intersection area between the multiple current extension layers 210 arranged in the first direction and the multiple current extension layers 210 arranged in the second direction. The area of ​​the square current extension layer 210 is smaller than the area of ​​the adjacent current extension layer 210, and the width of the square current extension layer 210 is smaller than the width of the adjacent current extension layer 210.

[0108] In some embodiments, combined with Figure 5c As shown, the P-type heavily doped region 410 has a square shape in the horizontal cross-section, the N-type heavily doped region 510 has a rectangular shape in the horizontal cross-section, and the current spreading layer 210 has a rectangular shape in the horizontal cross-section. The long sides of the P-type heavily doped region 410, the N-type heavily doped region 510, and the current spreading layer 210 are arranged in parallel. An N-type heavily doped region 510 is provided on each of the two long sides of the P-type heavily doped region 410.

[0109] This application also provides a novel gate silicon carbide power device. See [link to relevant documentation]. Figure 6As shown, the novel gate silicon carbide power device includes: a silicon carbide substrate 110, an N-type drift region 120, a P-type well region 310, an N-type heavily doped region 510, a P-type heavily doped region 410, a gallium nitride layer 631, a gallium oxide layer 632, a high-K dielectric layer 633, a gate layer 620, an interlayer dielectric layer 610, a first electrode layer 710, and a second electrode layer 720. The N-type drift region 120 is formed on the front surface of the silicon carbide substrate 110, and the N-type drift region 120 is a concave structure; the P-type well region 310 is formed on both sides of the N-type drift region 120, the N-type heavily doped region 510 is formed on the P-type well region 310, and the P-type heavily doped region 410 is formed on both sides of the N-type drift region 120; the gallium nitride layer 631 is formed along the inner wall of the groove of the N-type drift region 120, and the gallium nitride layer 631 is in contact with the P-type well region 310 and the N-type heavily doped region 510; the gallium oxide layer 632 is formed along the surface of the gallium nitride layer 631, and the high-K dielectric layer 633 is formed along the surface of the gallium oxide layer 632, wherein the gallium nitride layer 631, the gallium oxide layer 632, and the high-K dielectric layer 633 are U-shaped structures, and the gallium nitride layer 631, the gallium oxide layer 632, and the high-K dielectric layer 633 form a composite gate dielectric structure. The gate layer 620 is formed in the groove of the high-K dielectric layer 633, the interlayer dielectric layer 610 is formed on the gate layer 620 and the N-type heavily doped region 510, and the high-K dielectric layer 633 forms a closed structure to wrap the gate layer 620. The first electrode layer 710 covers and is in contact with the interlayer dielectric layer 610, the N-type heavily doped region 510, and the P-type heavily doped region 410, and the second electrode layer 720 is formed on the back surface of the silicon carbide substrate 110.

[0110] In this embodiment, the gate layer 620 penetrates into the N-type drift region 120, and a composite gate dielectric structure composed of the gallium nitride layer 631, the gallium oxide layer 632, and the high-K dielectric layer 633 is formed between the gate layer 620 and the N-type drift region 120. Compared with the traditional SiO2 / SiC structure, the defect density of the high-K dielectric layer 633 / Ga2O3 interface is significantly reduced, effectively solving the interface trap problem, significantly improving the channel mobility, and being beneficial to reducing the on-resistance of the device. Moreover, Ga2O3 has good lattice matching with the high-K dielectric layer 633 (such as hafnium oxide, magnesium gallium oxide, zirconium gallium oxide, zirconium titanium oxide, etc.), which can form a stable MIS (metal-insulator-semiconductor) structure, effectively reduce the gate leakage capacitance, and improve the dynamic characteristics of the device.

[0111] In some embodiments, in combination with Figure 6 As shown, the first electrode layer 710 penetrates at least half of the N-type drift region 120 from the outside of the P-type well region 310, and the P-type heavily doped region 410 is arranged between the first electrode layer 710 and the N-type drift region 120, thereby forming a double-trench MOS structure.

[0112] In some embodiments, in combination with Figure 7 As shown, the first electrode layer 710 is formed on the silicon carbide material, the N-type drift region 120 is a convex structure, a first side of the convex structure of the N-type drift region 120 is provided with the first P-type heavily doped region 411, a second side of the convex structure of the N-type drift region 120 is provided with the second P-type heavily doped region 412, and the width of the first P-type heavily doped region 411 is smaller than the width of the second P-type heavily doped region 412, thereby forming an asymmetric P-type trench MOS structure. In the asymmetric P-type trench MOS structure, a composite gate dielectric structure composed of a gallium nitride layer 631, a gallium oxide layer 632 and a high-K dielectric layer 633 is formed between the gate layer 620 and the N-type drift region 120. Compared with a traditional SiO2 / SiC structure, the interface defect density of the high-K dielectric layer 633 / Ga2O3 is significantly reduced, the interface trap problem is effectively solved, the channel mobility is significantly improved, and the on-resistance of the device is reduced. In addition, the Ga2O3 material has good lattice matching with the high-K dielectric layer 633 (such as hafnium oxide, magnesium gallium oxide, zirconium gallium oxide, zirconium titanium oxide, etc.), can form a stable MIS (metal-insulator-semiconductor) structure, effectively reduce the gate leakage capacitance, and improve the dynamic characteristics of the device.

[0113] In some embodiments, in combination with Figure 7 As shown, the gallium nitride layer 631, the gallium oxide layer 632 and the high-K dielectric layer 633 are in a U-shaped structure, the first side of the gallium nitride layer 631 is provided with a P-type well region 310 and an N-type heavily doped region 510 located on the P-type well region 310 between the first side of the gallium nitride layer 631 and the first P-type heavily doped region 411, the second side of the gallium nitride layer 631 and the bottom corner region of one side of the gallium nitride layer 631 are in contact with the second P-type heavily doped region 412, and the bottom corner region of the other side of the gallium nitride layer 631 is in contact with the N-type drift region 120.

[0114] The application also provides a preparation method of the new gate silicon carbide power device. The preparation method can be used to prepare the new gate silicon carbide power device in any one of the above embodiments. Figure 7 As shown, the preparation method in the embodiment includes steps S100 to S600.

[0115] In step S100, an N-type drift region 120 is formed on the front surface of a silicon carbide substrate 110.

[0116] In the embodiment, in combination with Figure 8 As shown in schematic structure (a), the silicon carbide substrate 110 can be a high-doped substrate.

[0117] In some embodiments, the doping concentration of the N-type drift region 120 is 3E15-1.5E16 cm -3 The thickness and concentration of the N-type drift region 120 depend on the voltage level of the device.

[0118] In step S200, a gallium nitride layer 631 is formed on the N-type drift region 120, and a gallium oxide layer 632 is formed on the gallium nitride layer 631.

[0119] In combination Figure 8 In the schematic structure (b), nanoscale GaN material can be grown on the SiC epitaxial layer (N-type drift region 120) by MOCVD / MBE / HVPE, and then β-Ga2O3 is grown on the GaN material.

[0120] In some embodiments, the gallium oxide layer 632 is a β-Ga2O3 thin film.

[0121] In some embodiments, the thickness of the gallium oxide layer 632 is 50-100 nm.

[0122] In some embodiments, the thickness of the gallium nitride layer 631 is 20-100 nm.

[0123] In step S300, P-type and N-type doping ions are injected into the designated regions of the N-type drift region 120 in multiple times, respectively, to form the current spreading layer 210, the P-type well region 310, the P-type heavily doped region 410, and the N-type heavily doped region 510.

[0124] In combination Figure 8 In the schematic structure (c), in the present embodiment, the ion implantation forms the device top layer structure and the annealing activation obtains the current spreading layer 210, the P-type well region 310, the P-type heavily doped region 410, and the N-type heavily doped region 510, the N-type heavily doped region 510 is isolated from the current spreading layer 210 in the adjacent position by the P-type well region 310, the N-type heavily doped region 510 contacts the corresponding P-type heavily doped region 410, and the thickness of the N-type heavily doped region 510 is less than the thickness of the P-type well region 310.

[0125] In step S400, a high-K dielectric layer 633 is formed on the gallium oxide layer 632.

[0126] In combination Figure 8 In the schematic structure (d), the high-K dielectric layer 633 can be formed by growing Al2O3 material or other High-k dielectric material on the β-Ga2O3 by MOCVD / MBE / HVPE, and the high-K dielectric layer 633 can be used as a gate insulating layer.

[0127] In the embodiment, by adopting the structure design of high-K dielectric layer 633 / gallium oxide layer 632 / gallium nitride layer 631 / SiC, the interface characteristics between the gate dielectric and the semiconductor substrate are effectively improved. Compared with the traditional SiO2 / SiC structure, the high-K dielectric layer 633 / β-Ga2O3 thin film interface defect density is significantly reduced, and the interface state density can be controlled in the order of 1-6E11 / cm 2 after annealing passivation treatment, effectively solving the interface trap problem, significantly improving the channel mobility, reaching 20-25 cm 2 / (Vs), and making significant progress.

[0128] In some embodiments, the high-K dielectric layer 633 is at least one of aluminum oxide, hafnium oxide, magnesium gallium oxide, gallium hafnium oxide, and gallium titanium oxide. Ga2O3 has good lattice matching degree with the high-K dielectric layer 633 (such as hafnium oxide, magnesium gallium oxide, zirconium gallium oxide, and zirconium titanium oxide), which can form a stable MIS (metal-insulator-semiconductor) structure, effectively reduce the gate leakage capacitance, and improve the dynamic characteristics of the device.

[0129] In some embodiments, the thickness of the high-K dielectric layer 633 is 30-100 nm. The dielectric constant of the high-K dielectric layer 633 is greater than or equal to 3.9, and the gallium oxide layer 632 has good lattice matching degree with the high-K dielectric layer 633 (such as hafnium oxide, magnesium gallium oxide, zirconium gallium oxide, and zirconium titanium oxide), which can form a stable MIS (metal-insulator-semiconductor) structure, effectively reduce the gate leakage capacitance, and improve the dynamic characteristics of the device.

[0130] In some embodiments, if the silicon carbide device structure as shown in Figure 6 or Figure 7 is to be formed, in step S200, a trench needs to be formed on the N-type drift region 120, which is used to form the gate layer 620. Then, the gallium nitride layer 631, the gallium oxide layer 632, and the high-K dielectric layer 633 are sequentially formed along the inner wall of the trench.

[0131] In step S500, the gate layer 620 is formed on the high-K dielectric layer 633, and then the interlayer dielectric layer 610 is formed.

[0132] In combination with the schematic structure (e) shown in Figure 8 In the embodiment, the metal alloy material is formed on the high-K dielectric layer 633 to form the gate layer 620, and then the interlayer dielectric layer 610 is formed to form a closed structure with the high-K dielectric layer 633 to wrap the gate layer 620.

[0133] In step S600, a first electrode layer 710 is formed on the interlayer dielectric layer 610, the N-type heavily doped region 510 and the P-type heavily doped region 410, and a second electrode layer 720 is formed on the back surface of the silicon carbide substrate 110.

[0134] In combination Figure 8 As shown in structure (f), when the silicon carbide substrate 110 is N-type doped, the silicon carbide device structure is a MOS structure, the first electrode layer 710 is a source electrode, the second electrode 720 is a drain electrode, and the source electrode and the gate electrode can be formed through a contact hole. The source electrode is etched to the surface of the SiC material, and the source electrode, the gate electrode, the drain electrode, the contact and the metal electrode are formed.

[0135] In some embodiments, in step S300, the implantation of the P-type doped ions and the N-type doped ions can be performed through different mask patterns, so as to form the current spreading layer 210, the P-type well region 310, the P-type heavily doped region 410 and the N-type heavily doped region 510 arranged as shown in structure (b). Figure 5a to Figure 5g

[0136] In some embodiments, in step S300, through different mask patterns, the depth and concentration of the P-type well region 310 and the JFET region are adjusted through process means to achieve the best combination, so as to form a super-junction-like structure, as shown in structure (c). Figure 5a Therefore, under the same mask, the on-resistance (Ron) of the new gate silicon carbide power device (oblong + P-type blocking region) using the new process is about 10% lower than that of the conventional process, and the breakdown voltage (BV) is consistent. Through the flow test, it can be seen that, under the condition of the same active area size, the BVDSS and Ron of the actual flow of different designs, the BVDSS of the structure (oblong + P-type blocking region) of the present application is 1675V, which is more than 200V higher than that of other conventional designs, and the on-resistance (Ron) is 44-54% lower than that of the bar structure, 10-15% lower than that of the square structure, and 6% lower than that of the hexagonal structure, which has the best BV-Ron trade-off relationship. Under the condition of 1200V voltage, the IDSS of other structures is lower than 400nA, and the IDSS of the new gate silicon carbide power device (oblong + P-type blocking region) and the bar structure in the present application is less than 10nA, which is far superior to the IDSS (<50μA) of the commercially available SiC MOSFET.

[0137] The embodiments of the present application also provide a chip comprising the new gate silicon carbide power device according to any one of the above embodiments.

[0138] ​In the embodiment, the chip comprises the novel gate silicon carbide power device of any one of the above embodiments, and the novel gate silicon carbide power device is formed by forming a gallium nitride layer 631 on the current spreading layer 210, the P-type well region 310 and the N-type heavily doped region 510, the gallium nitride layer 631 covering the P-type well region 310 and the current spreading layer 210, a gallium oxide layer 632 being formed on the gallium nitride layer 631, a high-K dielectric layer 633 being formed on the gallium oxide layer 632, and a gate layer 620 being formed on the high-K dielectric layer 633, so as to form a composite gate dielectric structure by the gallium nitride layer 631, the gallium oxide layer 632 and the high-K dielectric layer 633, which is beneficial to reducing the on-resistance of the device.

[0139] In some embodiments, the chip comprises a chip substrate, and one or more silicon carbide device structures are arranged on the substrate, and the silicon carbide device structure can comprise the silicon carbide device structure in any one of the above embodiments.

[0140] In a specific application embodiment, when the silicon carbide substrate 110 is N-type doped, the silicon carbide device structure can be a MOS structure, the first electrode layer 710 is a source electrode, and the second electrode 720 is a drain electrode. When the silicon carbide substrate 110 is P-type doped, the silicon carbide device structure can be an IGBT structure, the first electrode layer 710 is an emitter electrode, and the second electrode 720 is a collector electrode.

[0141] Other related semiconductor devices can also be integrated on the chip substrate, and the MOSFETs can constitute an integrated circuit.

[0142] In a specific application embodiment, the chip can be a switching chip or a driving chip.

[0143] It can be clearly understood by those skilled in the art that, for the convenience and brevity of description, only the above-mentioned doping regions and device divisions are exemplified, and in actual application, the above-mentioned functions can be completed by different doping regions and devices according to needs, that is, the internal structure of the device is divided into different doping regions to complete all or part of the above-mentioned functions. The doping regions and devices in the embodiments can be integrated in one unit, or each unit can exist physically alone, or two or more units can be integrated in one unit.

[0144] In addition, the specific names of the doping regions and devices are only for the convenience of mutual differentiation, and are not used to limit the protection scope of the present application.

[0145] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described or recorded in detail in a certain embodiment can be referred to the related description of other embodiments.

[0146] In addition, each doped region in each of the embodiments of the present application can be integrated in one unit, can be physically present separately in each unit, or can be integrated in two or more units in one unit.

[0147] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than limit them; although the foregoing embodiments of the present application are described in detail, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features can be replaced by equivalent ones; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A novel gate silicon carbide power device, characterized in that, The novel gate silicon carbide power device includes: silicon carbide substrate; An N-type drift region is formed on the front side of the silicon carbide substrate; A current spreading layer is formed on the N-type drift region; A P-type well region is formed on the N-type drift region and located on both sides of the current spreading layer; A P-type heavily doped region is formed on the N-type drift region; wherein the current spreading layers of the P-type heavily doped regions are isolated by the P-type well regions; An N-type heavily doped region is formed on the P-type well region; wherein the N-type heavily doped region is isolated from the adjacent current spreading layer by the P-type well region, the N-type heavily doped region is in contact with the corresponding P-type heavily doped region, and the thickness of the N-type heavily doped region is less than the thickness of the P-type well region. A gallium nitride layer is formed on the current spreading layer, the P-type well region, and the N-type heavily doped region, wherein the gallium nitride layer covers the P-type well region and the current spreading layer; A gallium oxide layer formed on the gallium nitride layer; A high-k dielectric layer is formed on the gallium oxide layer; wherein the gallium nitride layer, the gallium oxide layer, and the high-k dielectric layer form a composite gate dielectric structure; Gate layer formed on high-k dielectric layer; An interlayer dielectric layer forms a closed structure with the high-k dielectric layer to enclose the gate layer; A first electrode layer covering the interlayer dielectric layer, the N-type heavily doped region, and the P-type heavily doped region; A second electrode layer is formed on the back side of the silicon carbide substrate.

2. The novel gate silicon carbide power device as described in claim 1, characterized in that, The gallium oxide layer is a β-Ga2O3 thin film; and / or, the thickness of the gallium oxide layer is 50-100 nm.

3. The novel gate silicon carbide power device as described in claim 2, characterized in that, The thickness of the gallium nitride layer is 20-100 nm.

4. The novel gate silicon carbide power device as described in claim 2, characterized in that, The high-K dielectric layer is at least one of aluminum oxide, hafnium oxide, magnesium gallium oxide, zeolite gallium oxide, and zeolite titanium oxide; and / or the thickness of the high-K dielectric layer is 30-100 nm.

5. The novel gate silicon carbide power device as described in claim 1, characterized in that, The gallium nitride layer and the gallium oxide layer are also formed between the first electrode layer and the P-type heavily doped region, and the gallium nitride layer and the gallium oxide layer are also formed between the first electrode layer and the N-type heavily doped region; the gallium nitride layer and the gallium oxide layer have the same width, and the width of the high-k dielectric layer is smaller than the width of the gallium nitride layer.

6. The novel gate silicon carbide power device as described in claim 1, characterized in that, The gallium nitride layer, the gallium oxide layer, the high-K dielectric layer, and the interlayer dielectric layer have the same width.

7. The novel gate silicon carbide power device as described in claim 1, characterized in that, The gallium nitride layer, the gallium oxide layer, and a portion of the P-type heavily doped region and the N-type heavily doped region overlap.

8. A novel gate silicon carbide power device, characterized in that, The novel gate silicon carbide power device includes: silicon carbide substrate; An N-type drift region is formed on the front side of the silicon carbide substrate; the N-type drift region has a concave structure. P-type well regions are formed on both sides of the N-type drift region; An N-type heavily doped region formed on the P-type well region; P-type heavily doped regions formed on both sides of the N-type drift region; A gallium nitride layer is formed along the inner wall of the groove in the N-type drift region; the gallium nitride layer is in contact with the P-type well region and the heavily doped N-type region; A gallium oxide layer is formed along the surface of the gallium nitride layer; A high-k dielectric layer is formed along the surface of the gallium oxide layer; wherein the gallium nitride layer, the gallium oxide layer, and the high-k dielectric layer have a U-shaped structure, and the gallium nitride layer, the gallium oxide layer, and the high-k dielectric layer form a composite gate dielectric structure; A gate layer formed within a groove in a high-k dielectric layer; An interlayer dielectric layer is formed on the gate layer and the N-type heavily doped region, and forms a closed structure with the high-k dielectric layer to enclose the gate layer; A first electrode layer covering the interlayer dielectric layer, the N-type heavily doped region, and the P-type heavily doped region; A second electrode layer is formed on the back side of the silicon carbide substrate.

9. A method for fabricating a novel gate silicon carbide power device, characterized in that, The preparation method includes: An N-type drift region is formed on the front side of the silicon carbide substrate; A gallium nitride layer is formed on the N-type drift region, and a gallium oxide layer is formed on the gallium nitride layer; P-type dopant ions and N-type dopant ions are implanted into a designated area of ​​the N-type drift region multiple times to form a current spreading layer, a P-type well region, a heavily doped P-type region, and a heavily doped N-type region; wherein, the heavily doped N-type region is isolated from the adjacent current spreading layer by the P-type well region, the heavily doped N-type region is in contact with the corresponding heavily doped P-type region, and the thickness of the heavily doped N-type region is less than the thickness of the P-type well region. A high-k dielectric layer is formed on the gallium oxide layer; A gate layer is formed on the high-k dielectric layer, and then an interlayer dielectric layer is formed; the interlayer dielectric layer and the high-k dielectric layer form a closed structure to enclose the gate layer; A first electrode layer is formed covering the interlayer dielectric layer, the N-type heavily doped region, and the P-type heavily doped region, and a second electrode layer is formed on the back side of the silicon carbide substrate.

10. A chip, characterized in that, Including the novel gate silicon carbide power device as described in any one of claims 1-8.

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