Semiconductor process method, semiconductor device and electronic equipment

Abstract

The embodiment of the invention provides a semiconductor process method, a semiconductor device and electronic equipment. Relates to the technical field of semiconductor manufacturing. The invention provides a semiconductor process method capable of manufacturing a groove with a larger inclination angle on the side wall and a narrower line width. The semiconductor process method comprises the following steps: forming a layer to be etched on a substrate; forming a mask pattern layer with a first window on one side, deviating from the substrate, of the to-be-etched layer; forming a filling pattern layer with a second window in the first window, wherein the filling pattern layer covers at least part of the side wall of the first window; etching the to-be-etched layer to a first position by taking the mask pattern layer and the filling pattern layer as masks; removing the filling pattern layer; and etching a part of the mask pattern layer by taking the mask pattern layer as a mask, and etching the layer to be etched to a second position so as to form a groove of which the side wall is an inclined surface in the layer to be etched. By means of the method, the groove with the large inclination angle can be manufactured, the line width size cannot be limited, small line width can be manufactured, and large line width can also be manufactured.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor manufacturing process method that can produce a large tilt angle of the groove sidewall and a narrow linewidth, as well as semiconductor devices and electronic devices. Background Technology

[0002] With the development of communication technology, the field of radio frequency communication has put forward the requirements for semiconductor devices to have higher frequency, higher voltage, higher output power and higher efficiency.

[0003] Semiconductor devices based on compound semiconductor materials, such as gallium nitride (GaN)-based high electron mobility transistors (HEMTs), are increasingly being widely used in high-power radio frequency devices, high-voltage switching devices, and other fields due to their excellent physical properties such as wide bandgap, high electron drift velocity, radiation resistance, and high temperature resistance. For example, they have a wide range of applications in radar, wireless communication, navigation, satellite communication, and electronic countermeasures equipment systems.

[0004] like Figure 1 The GaN HEMT semiconductor device shown includes a substrate, a GaN layer fabricated using a first epitaxial growth technique, and the GaN layer may include a multilayer structure, such as a channel layer and a barrier layer. A trench is then formed in the GaN layer, and a source contact layer and a drain contact layer are fabricated within the trench using a second epitaxial growth technique, followed by the fabrication of a source metal layer and a drain metal layer.

[0005] See Figure 1 The tilt angle of the sidewall of the groove is a factor in evaluating the performance of the device. For example, a larger tilt angle θ is more conducive to the growth of the source and drain contact layers. The smaller the resistance R at the interface between the source contact layer and the GaN layer, the better the performance of the device will be.

[0006] However, in the relevant process technology, when the sidewall inclination angle of the obtained groove is large, the linewidth s of the source contact layer and the drain contact layer will become narrow, making it difficult to achieve a large inclination angle of the groove and a narrow linewidth of the contact layer. Summary of the Invention

[0007] This application provides a semiconductor processing method, a method for fabricating a semiconductor device, a semiconductor device fabricated using this method, and an electronic device. Using this processing method, the sidewall tilt angle of the recesses in the semiconductor device can be larger, and the linewidth narrower.

[0008] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0009] In one aspect, this application provides a method for fabricating a semiconductor device, for example, the process method can be a method for fabricating a high electron mobility field-effect transistor.

[0010] The method for fabricating this semiconductor device may include:

[0011] An etchable layer is formed on a substrate. The etchable layer includes a channel layer and a barrier layer. The channel layer is formed on the substrate, and the barrier layer is formed on the side of the channel layer away from the substrate.

[0012] A mask pattern layer with a first window is formed on the side of the barrier layer away from the channel layer;

[0013] A filling pattern layer having a second window is formed within the first window, the filling pattern layer covering at least a portion of the sidewall of the first window;

[0014] Using the mask pattern layer and the fill pattern layer as masks, the layer to be etched is etched down to the barrier layer;

[0015] Remove the fill pattern layer;

[0016] Using a mask pattern layer as a mask, a portion of the mask pattern layer is etched, and the layer to be etched is etched down to the channel layer to form a groove with inclined sidewalls in the layer to be etched.

[0017] In the semiconductor device fabrication method disclosed in this application, a mask pattern layer with a first opening is first formed, and then a filling pattern layer with a second opening (smaller than the first opening) is set in the first opening. The small second opening pattern is transferred to the layer to be etched, and a temporary groove with a size approximately equal to that of the second opening is etched. Then the filling pattern layer is removed. In this way, the sidewalls of the temporary groove and the sidewalls of the mask pattern layer can be connected to form a stepped surface. When the mask pattern layer and the layer to be etched are etched, the stepped surface is etched to form an inclined surface. As etching continues, the inclined surface extends into the layer to be etched, thereby forming a groove with an inclined sidewall in the layer to be etched.

[0018] When a semiconductor device is fabricated using the above method, the size of the filling pattern layer in the first direction (parallel to the surface of the substrate) can be adjusted to change the reduction value of the second opening relative to the first opening, thereby changing the tilt angle of the tilted surface of the groove. Therefore, a large tilt of the tilted surface can be achieved.

[0019] In addition, adjusting the size of the filling pattern layer in the first direction and changing the tilt angle of the inclined surface of the groove will not affect the size of the groove in the first direction. In this way, after filling the groove with the material used to form the circuit, the width of the formed line will not be affected, thus achieving a small line width.

[0020] In one feasible approach, using a mask pattern layer and a fill pattern layer as masks, etching the layer to be etched down to the barrier layer includes: the etching rate of the layer to be etched is V1, the etching rate of the fill pattern layer is V2, and V1 > V2; using the mask pattern layer as a mask, etching a portion of the mask pattern layer and etching the layer to be etched down to the channel layer includes: the etching rate of the layer to be etched is V3, the etching rate of the mask pattern layer is V4, and V3 > V4.

[0021] When the etching rate of the layer to be etched is greater than the etching rate of the filling pattern layer, a temporary groove can be formed in the layer to be etched; and when the etching rate of the layer to be etched is greater than the etching rate of the mask pattern layer, a groove with the required tilt angle can be etched in the layer to be etched.

[0022] In one feasible approach, the etching rate V4 of the mask pattern layer is greater than the etching rate V2 of the filling pattern layer.

[0023] In this way, when using the mask pattern layer and the fill pattern layer as masks, the fill pattern layer can be basically avoided during etching of the layer to be etched. When using the mask pattern layer as a mask, the step surface formed by the connection between the sidewall of the mask pattern layer and the sidewall of the layer to be etched can be etched away, forming an inclined surface. Under the action of this inclined surface, a groove with inclined sidewalls can be made.

[0024] In one possible scenario, V1 is equal to V3, or V1 is not equal to V3.

[0025] In one achievable manner, 1nm / min≤V1≤100nm / min, 1nm / min≤V3≤100nm / min.

[0026] In one feasible approach, using a mask pattern layer and a fill pattern layer as masks, etching the layer to be etched down to the barrier layer includes: an etching selectivity ratio of the layer to be etched to the fill pattern layer being P1; using a mask pattern layer as a mask, etching a portion of the mask pattern layer and etching the layer to be etched down to the channel layer includes: an etching selectivity ratio of the layer to be etched to the mask pattern layer being P2; P1 > P2.

[0027] In one feasible manner, P1≥5, P2≥5.

[0028] For example, when P2≥8, using the mask pattern layer as a mask, when etching part of the mask pattern layer and the layer to be etched, the uneven etching shape can be used to etch away the step surface connecting the mask pattern layer and the layer to be etched, forming an inclined surface.

[0029] In one possible implementation, the mask pattern layer comprises silicide; the fill pattern layer comprises photoresist.

[0030] For example, the mask pattern layer may include at least one of a silicon oxide (SiOx) layer, a silicon nitride (SiNx) layer, or a silicon oxynitride (SiON) layer.

[0031] In one possible implementation, a fill pattern layer having a second window is formed within a first window, the fill pattern layer covering at least a portion of the sidewall of the first window, comprising: filling a photoresist layer within the first window; etching a portion of the photoresist layer within the first window, retaining the photoresist layer on the sidewall of the first window, to form a fill pattern layer having a second window within the first window.

[0032] In this implementation, photoresist is used to create the filling pattern layer, which is compatible with existing process equipment and process steps and does not pose a challenge to the entire method.

[0033] In one possible approach, when filling the first window with a photoresist layer, the method further includes covering the surface of the mask pattern layer opposite to the layer to be etched with a photoresist layer.

[0034] The photoresist layer covering the mask pattern layer can protect the mask pattern layer. For example, when using the mask pattern layer and the fill pattern layer as masks, if the mask pattern layer is not covered by the photoresist layer when etching the layer to be etched, the mask pattern layer may be etched thinner or even etched through.

[0035] In one feasible approach, using a mask pattern layer and a fill pattern layer as masks, after etching the layer to be etched down to the barrier layer, a temporary groove is formed in the layer to be etched; after removing the mask pattern layer, a mask pattern layer with a first opening is formed, wherein at least a portion of the sidewalls of the first opening and at least a portion of the sidewalls of the temporary groove are connected to form a stepped surface.

[0036] In this way, the stepped surface can be etched in subsequent process steps to obtain an inclined surface.

[0037] In one feasible approach, etching a portion of the mask pattern layer and etching the layer to be etched down to the channel layer includes etching a step surface to form a sloping surface.

[0038] In one feasible manner, when the inclination angle of the inclined surface of the groove is θ and the depth dimension of the groove is H;

[0039] A filling pattern layer having a second opening is formed within a first opening, the filling pattern layer covering at least a portion of the sidewall of the first opening, including: the size of the filling pattern layer covering the sidewall of the first opening in a first direction is ΔW = H * tanθ;

[0040] Wherein, the inclination angle θ of the inclined surface is the angle between the inclined surface and the second direction;

[0041] The depth dimension H of the groove is the distance between the surface of the layer to be etched that faces away from the substrate and the bottom surface of the groove;

[0042] The first direction is parallel to the substrate surface, and the second direction is perpendicular to the substrate surface.

[0043] In the fabrication process, the desired tilt angle can be obtained by adjusting the dimension ΔW of the filling pattern layer in the first direction.

[0044] Secondly, this application provides a semiconductor device including a substrate and a field-effect transistor formed on the substrate, the field-effect transistor being fabricated using any of the above-described implementation methods.

[0045] The semiconductor device fabricated using the above method, for example, when the field-effect transistor of the semiconductor device is a high electron mobility field-effect transistor, can not only achieve a large tilt angle at the interface between the source / drain contact layer and the semiconductor layer, but also make the linewidth of the source / drain contact layer narrower.

[0046] In one possible implementation, the semiconductor device includes: a substrate, a gallium nitride layer formed on the substrate; the semiconductor device further includes an electrode contact layer formed within the gallium nitride layer, the electrode contact layer being either a source contact layer or a drain contact layer; the linewidth of the electrode contact layer in a first direction is less than or equal to 6 micrometers, the first direction being parallel to the substrate surface; the interface between the electrode contact layer and the gallium nitride layer is an inclined surface, the inclination angle α of the inclined surface being: 110°≤α≤150°; the inclination angle α is the angle between the inclined surface and a second direction, the second direction being perpendicular to the substrate surface.

[0047] In this example of a HEMT device, not only does the tilt angle reach 110°≤α≤150°, reducing the contact resistance at the interface between the electrode contact layer and the gallium nitride layer, but it also allows for a reduction in the linewidth of the source and drain contact layers, thus optimizing the device's performance.

[0048] Thirdly, this application provides a semiconductor process method, which may include:

[0049] Form the layer to be etched on the substrate;

[0050] A mask pattern layer with a first opening is formed on the side of the layer to be etched away from the substrate;

[0051] A filling pattern layer having a second window is formed within the first window, the filling pattern layer covering at least a portion of the sidewall of the first window;

[0052] Using the mask pattern layer and the fill pattern layer as masks, the layer to be etched is etched to the first position;

[0053] Remove the fill pattern layer;

[0054] Using a mask pattern layer as a mask, a portion of the mask pattern layer is etched, and the layer to be etched is etched to a second position to form a groove with inclined sidewalls in the layer to be etched.

[0055] This process can be used to fabricate semiconductor devices with grooves, such as HEMT devices. The resulting semiconductor devices allow for a larger tilt angle on the groove sidewalls and a narrower linewidth in the source / drain contact layer filling the groove.

[0056] For example, when forming a filling pattern layer with a second opening in the first opening, the size of the filling pattern layer in the first direction can be adjusted so that the sidewall tilt angle of the final groove meets the design size, and the process is simple; and, when adjusting the size of the filling pattern layer and changing the tilt angle, the width of the groove in the first direction will not be affected, so the linewidth of the source and drain contact layer will not be affected, thus achieving a narrow linewidth.

[0057] In one feasible approach, etching the layer to be etched to a first position using a mask pattern layer and a fill pattern layer as masks includes: the etching rate of the layer to be etched is V1, the etching rate of the fill pattern layer is V2, and V1 > V2; etching a portion of the mask pattern layer and etching the layer to be etched to a second position using the mask pattern layer as a mask includes: the etching rate of the layer to be etched is V3, the etching rate of the mask pattern layer is V4, and V3 > V4.

[0058] When the etching rate of the layer to be etched is greater than the etching rate of the filling pattern layer, a temporary groove can be formed in the layer to be etched; and when the etching rate of the layer to be etched is greater than the etching rate of the mask pattern layer, the required groove can be etched in the layer to be etched.

[0059] In one feasible approach, the etching rate V4 of the mask pattern layer is greater than the etching rate V2 of the filling pattern layer.

[0060] In this way, when using the mask pattern layer and the fill pattern layer as masks, the fill pattern layer can be basically avoided during etching of the layer to be etched. When using the mask pattern layer as a mask, the step surface formed by the connection between the sidewall of the mask pattern layer and the sidewall of the layer to be etched can be etched away, forming an inclined surface. Under the action of this inclined surface, a groove with inclined sidewalls can be made.

[0061] In one possible scenario, V1 is equal to V3, or V1 is not equal to V3.

[0062] In one achievable manner, 1nm / min≤V1≤100nm / min, 1nm / min≤V3≤100nm / min.

[0063] In one feasible approach, etching the layer to be etched to a first position using a mask pattern layer and a fill pattern layer as masks includes: an etching selection ratio of the layer to be etched to the fill pattern layer being P1; etching a portion of the mask pattern layer using a mask pattern layer as a mask, and etching the layer to be etched to a second position includes: an etching selection ratio of the layer to be etched to the mask pattern layer being P2; P1 > P2.

[0064] In one feasible manner, P1≥5, P2≥5.

[0065] For example, when P2≥8, using the mask pattern layer as a mask, when etching part of the mask pattern layer and the layer to be etched, the uneven etching shape can be used to etch away the step surface connecting the mask pattern layer and the layer to be etched, forming an inclined surface.

[0066] In one possible implementation, the mask pattern layer comprises silicide; the fill pattern layer comprises photoresist.

[0067] For example, the mask pattern layer may include at least one of a SiOx layer, a SiNx layer, or a SiON layer.

[0068] In one possible implementation, a fill pattern layer having a second window is formed within a first window, the fill pattern layer covering at least a portion of the sidewall of the first window, comprising: filling a photoresist layer within the first window; etching a portion of the photoresist layer within the first window, retaining the photoresist layer on the sidewall of the first window, to form a fill pattern layer having a second window within the first window.

[0069] In this implementation, photoresist is used to create the filling pattern layer, which is compatible with existing process equipment and process steps and does not pose a challenge to the entire method.

[0070] In one possible approach, when filling the first window with a photoresist layer, the method further includes covering the surface of the mask pattern layer opposite to the layer to be etched with a photoresist layer.

[0071] The photoresist layer covering the mask pattern layer can protect the mask pattern layer. For example, when using the mask pattern layer and the fill pattern layer as masks, if the mask pattern layer is not covered by the photoresist layer when etching the layer to be etched, the mask pattern layer may be etched thinner or even etched through.

[0072] In one feasible approach, using a mask pattern layer and a fill pattern layer as masks, after etching the layer to be etched to a first position, a temporary groove is formed in the layer to be etched; after removing the mask pattern layer, a mask pattern layer with a first opening is formed, wherein at least a portion of the sidewall of the first opening and at least a portion of the sidewall of the temporary groove are connected to form a stepped surface.

[0073] In this way, the stepped surface can be etched in subsequent process steps to obtain an inclined surface.

[0074] In one possible approach, etching a portion of the mask pattern layer and etching the layer to be etched to a second location includes: etching a step surface to form an inclined surface.

[0075] In one possible implementation, when the material of the mask pattern layer includes silicide and the material of the layer to be etched includes gallium nitride, etching a portion of the mask pattern layer and etching the layer to be etched to a second position includes: etching the mask pattern layer and the layer to be etched using a gas containing chlorine.

[0076] Using a gas containing chlorine to etch the mask pattern layer and GaN with a selective etching ratio, a mask is used for protection. Taking advantage of the etching non-uniformity, the right-angled sidewalls of the steps are etched away first, and then the sloping sidewalls are formed.

[0077] In one feasible manner, when the inclination angle of the inclined surface of the groove is θ and the depth dimension of the groove is H;

[0078] A filling pattern layer having a second opening is formed within a first opening, the filling pattern layer covering at least a portion of the sidewall of the first opening, including: the size of the filling pattern layer covering the sidewall of the first opening in a first direction is ΔW = H * tanθ;

[0079] Wherein, the inclination angle θ of the inclined surface is the angle between the inclined surface and the second direction;

[0080] The depth dimension H of the groove is the distance between the surface of the layer to be etched that faces away from the substrate and the bottom surface of the groove;

[0081] The first direction is parallel to the substrate surface, and the second direction is perpendicular to the substrate surface.

[0082] In the fabrication process, the desired tilt angle can be obtained by adjusting the dimension ΔW of the filling pattern layer in the first direction.

[0083] In one feasible approach, a semiconductor process is used to fabricate a field-effect transistor; the layer to be etched comprises a gallium nitride layer.

[0084] In other words, HEMT devices can be fabricated using this process.

[0085] In one feasible manner, forming the layer to be etched on the substrate includes: forming a buffer layer on the substrate; forming a channel layer on the buffer layer; forming an insertion layer on the channel layer; forming a barrier layer on the insertion layer; and forming a cap layer on the barrier layer.

[0086] The resulting HEMT device may include these stacked film structures, or it may include more layers.

[0087] In one feasible approach, etching the layer to be etched to a first position using a mask pattern layer and a fill pattern layer as masks includes: etching into a barrier layer using a mask pattern layer and a fill pattern layer as masks.

[0088] In other words, in feasible processes, when using a mask pattern layer and a fill pattern layer as masks, only the part of the layer to be etched needs to be etched, so that the depth of the temporary groove etched is less than the depth of the designed groove.

[0089] In one possible implementation, a mask pattern layer is used as a mask, a portion of the mask pattern layer is etched, and the layer to be etched is etched to a second position to form a groove with inclined sidewalls in the layer to be etched, including: the groove extending into the channel layer.

[0090] An ohmic contact can be achieved by filling the groove with a source-drain contact layer and fabricating a source-drain metal layer on the source-drain contact layer.

[0091] In one feasible approach, after forming a groove with inclined sidewalls within the layer to be etched, the semiconductor process further includes filling the groove with an electrode contact layer, wherein the electrode contact layer is a source contact layer or a drain contact layer.

[0092] In one possible implementation, after filling the groove with an electrode contact layer, the linewidth of the electrode contact layer in a first direction is less than or equal to 6 micrometers, and the first direction is parallel to the substrate surface; the tilt angle α of the interface between the electrode contact layer and the gallium nitride layer is: 110°≤α≤150°; the tilt angle α is the angle between the interface between the electrode contact layer and the gallium nitride layer and a second direction, and the second direction is perpendicular to the substrate surface.

[0093] In the HEMT device fabricated using this method, not only can the tilt angle α of the interface between the electrode contact layer and the gallium nitride layer reach 110°≤α≤150°, but the linewidth of the electrode contact layer in the first direction can also be reduced to less than or equal to 6 micrometers, achieving a large tilt angle and a small linewidth. The large tilt angle reduces the sidewall contact resistance of the source and drain contact layers, thus optimizing device performance.

[0094] In one feasible approach, after filling the groove with an electrode contact layer, the semiconductor process further includes: fabricating an electrode metal layer on the electrode contact layer, wherein the electrode metal layer is a source metal layer or a drain metal layer; and fabricating the gate of a field-effect transistor.

[0095] Fourthly, this application also provides an electronic device, which includes a processor and a semiconductor device, wherein the processor is electrically connected to the semiconductor device; the semiconductor device includes: a substrate and a gallium nitride layer formed on the substrate; the semiconductor device further includes an electrode contact layer, which is formed within the gallium nitride layer, and the electrode contact layer is either a source contact layer or a drain contact layer; the linewidth of the electrode contact layer in a first direction is less than or equal to 6 micrometers, and the first direction is parallel to the substrate surface; the interface between the electrode contact layer and the gallium nitride layer is an inclined surface, and the inclination angle α of the inclined surface is: 110°≤α≤150°; the inclination angle α is the angle between the inclined surface and a second direction, and the second direction is perpendicular to the substrate surface.

[0096] In one possible implementation, the gallium nitride layer includes a buffer layer, a channel layer, an insertion layer, a barrier layer, and a cap layer; the buffer layer is formed on a substrate, the channel layer is formed on the buffer layer, the insertion layer is formed on the channel layer, the barrier layer is formed on the insertion layer, and the cap layer is formed on the barrier layer.

[0097] In the electronic device provided in this application, the semiconductor device connected to the processor has a large tilt angle at the interface between the electrode contact layer and the gallium nitride layer, a small interface contact resistance, and a narrow linewidth of the electrode contact layer. Attached Figure Description

[0098] Figure 1 This is a partial structural diagram of a semiconductor device in related technologies;

[0099] Figure 2 This is a partial structural diagram of a base station provided in an embodiment of this application;

[0100] Figure 3 This is a partial structural diagram of a mobile phone provided in an embodiment of this application;

[0101] Figure 4 This is a schematic diagram showing the structure after each step in the manufacturing process of a semiconductor device, which is related to the technology.

[0102] Figure 5 A flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application;

[0103] Figures 6A to 6L This is a schematic diagram showing the structure after each step in the manufacturing process of a semiconductor device provided in an embodiment of this application.

[0104] Figure 7 A top view of a semiconductor device provided in an embodiment of this application;

[0105] Figures 8A to 8DThis is a schematic diagram showing the structure after each step in the manufacturing process of a semiconductor device provided in this application embodiment. Detailed Implementation

[0106] The solutions involved in the embodiments of this application will be described below with reference to the accompanying drawings.

[0107] This application provides an electronic device that may include communication devices (such as base stations, mobile phones, tablets, wearable devices, smart screens, and wireless headphones), wireless charging devices, medical devices, radar, navigation devices, radio frequency (RF) plasma lighting devices, RF induction and microwave heating devices, etc. This application does not impose any special limitations on the specific form of the above-mentioned electronic device.

[0108] The aforementioned electronic devices almost all include semiconductor devices, such as power amplifiers (PAs). The main function of a PA is to amplify radio frequency signals. Taking a base station as an example... Figure 2 A simplified structural diagram of a base station is provided. This base station includes a control unit, which comprises a radio transceiver, antennas, and related signal processing circuits. The control unit mainly consists of four components: a cell controller, a voice channel controller, a signaling channel controller, and a multiplexer interface for expansion. The base station control unit typically controls several base station transceivers. Through remote commands from the transceivers and mobile stations, the base station control unit is responsible for all mobile communication interface management, primarily the allocation, release, and management of radio channels.

[0109] Continue to combine Figure 2 The base station also includes a transmission unit, which is connected to the core network. Control signaling, voice calls, or data service information from the core network side are sent to the base station's control unit through the transmission unit, and the control unit processes these services.

[0110] Combined Figure 2 The base station also includes a baseband unit and a radio frequency (RF) unit. The baseband unit mainly performs functions such as baseband modulation and demodulation, radio resource allocation, call processing, power control, and soft handover. The RF unit mainly performs the conversion between the air radio frequency channel and the baseband digital channel, then amplifies the signal through a power amplifier (PA), and then sends it to the antenna for transmission via the RF feeder. Terminal devices, such as mobile phones and tablets, receive the radio waves transmitted by the antenna through the wireless channel and then demodulate their own signal.

[0111] Continue to combine Figure 2 The base station also includes a power supply unit, which can be used to supply power to structures such as the transmission unit, baseband unit, and control unit.

[0112] Figure 3 A structural diagram of another electronic device is given, taking a mobile phone as an example. The mobile phone has a circuit board (e.g., a printed circuit board PCB) with various functional devices arranged on the circuit board, such as radio frequency front-end, transceiver, baseband and processor, etc. The mobile phone also has an antenna.

[0113] like Figure 3 In the receiving process, the antenna receives the signal, which is matched and amplified by the radio frequency front end, and then down-converted and filtered by the transceiver before the demodulated signal is output to the baseband processing. Finally, the baseband transmits the processed data to the processor for use.

[0114] For example Figure 3 During the transmission process, the processor transmits data to the baseband, the baseband transmits the encoded signal to the transceiver, the transceiver modulates the signal and then amplifies it through the radio frequency front end before transmitting it to the antenna for transmission.

[0115] In semiconductor devices such as the aforementioned radio frequency front-ends, transceivers, basebands, and processors, it is possible to use field-effect transistors (MISFETs) with a metal-insulator-semiconductor structure.

[0116] With the development of mobile communication technology, the functional requirements for the aforementioned radio frequency semiconductor devices are becoming increasingly higher, such as higher frequency, higher voltage, higher output power, and higher efficiency.

[0117] Among the available semiconductor materials, gallium nitride (GaN) has become a key material for fabricating radio frequency semiconductor devices due to its high thermal conductivity, high breakdown field strength, and high saturation electron mobility. For example, high electron mobility transistors (HEMTs) based on gallium nitride (GaN) are fabricated from GaN epitaxial single-crystal thin films grown on a single-crystal substrate. The single-crystal substrate is typically made of materials such as sapphire, silicon carbide (SiC), or silicon (Si). For instance, when the substrate is made of silicon single-crystal material, the resulting HEMT can be called a gallium nitride-on-silicon (GaN-on-Si) HEMT device. In other examples, the substrate can be a composite substrate formed from the above-mentioned different materials.

[0118] To obtain high-performance GaN-based semiconductor devices, low resistance is required at the interface between the source contact layer and the GaN layer, and low resistance is also required at the interface between the drain contact layer and the GaN layer. Figure 4 The paper presents a process method that can reduce interface resistance.

[0119] See Figure 4 In section (A), a GaN layer is fabricated on a substrate, which may include a channel layer and a barrier layer. Alternatively, it may include more layers.

[0120] See Figure 4 In section (B), photoresist is prepared on the GaN layer, and patterns and / or lines are photolithographically formed.

[0121] See Figure 4 In the middle (C), by changing the post-baking temperature and time of the photoresist, the edges of the photoresist are made to form beveled or inclined arc surfaces.

[0122] See Figure 4 In the middle (D), the GaN layer is etched using a photoresist mask to transfer the pattern onto the GaN layer.

[0123] See Figure 4 In the middle (E), the photoresist is removed, and then grooves with inclined surfaces are etched in the GaN layer.

[0124] In a process that can be implemented, such as Figure 4 As shown in (B), when using a photoresist with a thickness of h, the following can be obtained: Figure 4 The device shown in (E) has a groove with an inclination angle of β and a line width of d.

[0125] To reduce the resistance at the interface between the source / drain contact layer and the GaN layer of this device, the tilt angle β of the groove can be increased.

[0126] With the increasing integration and superior performance of semiconductor devices, it is necessary not only to reduce the contact resistance at the interface between the source / drain contact layer and the GaN layer, and increase the tilt angle at the interface between the source / drain contact layer and the GaN layer, but also to narrow the linewidth of the source / drain contact layer in the device.

[0127] If using Figure 4 When fabricating devices with a larger tilt angle β using the method shown, it is necessary to increase the thickness h of the photoresist. However, the larger the thickness h of the photoresist, the wider the linewidth d of the fabricated device will be. Therefore, utilizing... Figure 4 The method shown is difficult to meet the requirements of scenarios with large tilt angles and narrow line widths.

[0128] In addition, using Figure 4 When the semiconductor device is fabricated using the method shown, the photoresist reflow method is employed. Figure 4In step (C), photoresist deformation can cause a large deviation between the etched pattern size and the design size, resulting in a difference in performance between the final product and the designed product.

[0129] This application provides several semiconductor processing methods. In one embodiment, this semiconductor processing method can not only increase the tilt angle of the groove sidewalls but also achieve a narrow linewidth. When this method is used to fabricate GaN-based semiconductor devices, it can not only reduce the contact resistance between the source / drain contact layer and GaN but also achieve a narrow linewidth for the source / drain contact layer. The following structural drawings describe the achievable process steps in detail.

[0130] Figure 5 This is a process flow diagram of a semiconductor manufacturing method provided in an embodiment of this application. The steps are as follows:

[0131] S1: Form the layer to be etched on the substrate.

[0132] S2: A mask pattern layer with a first opening is formed on the side of the layer to be etched away from the substrate.

[0133] The first window extends through the mask pattern layer along its thickness direction.

[0134] S3: A filling pattern layer having a second window is formed within the first window, the filling pattern layer covering at least a portion of the sidewall of the first window.

[0135] This process step utilizes a filling pattern layer covering the sidewall of the first window to reduce the size of the first window in the first direction, forming a filling pattern layer with a second window. That is, the size of the second window in the first direction is smaller than the size of the first window in the first direction. The first direction is a direction parallel to the substrate.

[0136] The direction parallel to the substrate surface mentioned in the embodiments of this application can be understood as an extension direction parallel to the substrate surface. The extension direction of the substrate surface can be, for example, the extension direction of the surface of the substrate that carries the layer to be etched and the mask pattern layer.

[0137] S4: Using the mask pattern layer and the fill pattern layer as masks, etch the layer to be etched to the first position.

[0138] This can be understood as transferring a small-sized second window pattern to the layer to be etched. In other words, a temporary groove of the same size as the second window is etched within the layer to be etched.

[0139] The fact that the size of the temporary groove is equal to the size of the second window should be understood as: the size of the temporary groove in the first direction is basically equal to the size of the second window in the first direction. In actual processes, there is a certain process error between the size of the temporary groove after etching the layer to be etched and the size of the second window in the first direction, which should fall within the range of "the size of the temporary groove of the layer to be etched is equal to the size of the second window".

[0140] S5: Remove the fill pattern layer.

[0141] After removing the fill pattern layer, the mask pattern layer with the first window will be revealed.

[0142] S6: Using the mask pattern layer as a mask, etch part of the mask pattern layer and etch the layer to be etched to the second position to form a groove with inclined sidewalls in the layer to be etched.

[0143] In some examples, the first position shown in S4 and the second position shown in S6 can be the same position; in other examples, the first position and the second position can be different positions, for example, the second position is closer to the substrate than the first position in a direction perpendicular to the substrate surface.

[0144] In step S6, a mask pattern layer is used as a mask. In this process step, the mask pattern layer has a first opening of a relatively large size. Using the mask pattern layer with the first opening as a mask, a portion of the mask pattern layer and the layer to be etched are etched.

[0145] Etching the layer to be etched can be understood as continuing to etch the temporary groove obtained in step S4, and after performing step S6, the depth of the temporary groove can be extended, and the sidewall of the etched groove will become an inclined wall.

[0146] In one embodiment, the above Figure 5 The process steps shown can be implemented in the following ways.

[0147] like Figures 6A to 6E It is one of the implementation methods, and Figures 6A to 6L The diagram shows the process structure corresponding to the completion of each process step.

[0148] like Figure 6A The layer to be etched is formed on the substrate. In one embodiment, the layer to be etched may include a GaN layer.

[0149] For example, in some implementations, the GaN layer includes stacked channel layers and barrier layers.

[0150] For example, the channel layer may include gallium nitride (GaN) material.

[0151] For example, the barrier layer may comprise aluminum gallium nitride (AlGaN) material, or it may be composed of at least one of indium aluminum nitride (AlInN) or gallium indium aluminum (AlInGaN) combined with AlGaN. The barrier layer is used to cooperate with the channel layer to generate a two-dimensional electron gas (2DEG) between the channel layer and the barrier layer through polarization, thereby conducting current.

[0152] In other examples, the layer to be etched includes not only the substrate, channel layer, and barrier layer, but also other functional layer structures. For example, ... Figure 6A The GaN layer may also include a buffer layer, an insertion layer, and a cap layer, wherein the buffer layer is stacked on the substrate, the insertion layer is stacked between the channel layer and the barrier layer, and the cap layer is stacked on the barrier layer.

[0153] For example, the buffer layer is formed of a compositionally graded group II IA nitride material. For instance, the buffer layer may include Al xGa(1-x)N, where x may gradually decrease along the growth direction (i.e., along the direction away from the substrate), for example, x may decrease from a value of 1 to a value of 0.

[0154] For example, the intercalation layer may include aluminum nitride (AlN) material. The polarization effect of aluminum gallium nitride (AlGaN), aluminum nitride (AlN), and gallium nitride (GaN) structures can generate a higher two-dimensional electron gas concentration and reduce the penetration of the two-dimensional electron gas into the barrier layer. The intercalation layer can reduce the disorder scattering of the alloy, thereby improving the mobility and improving the output characteristics of the device.

[0155] For example, the cap layer can contain GaN material. When the cap layer contains GaN, the resulting surface morphology can be smoother and have fewer surface defects compared to a surface formed without a cap layer. In addition, using GaN material to terminate the growth of the epitaxial layer also facilitates subsequent chemical treatment of the epitaxial layer surface.

[0156] like Figure 6B A mask layer is formed on the side of the layer to be etched that is away from the substrate.

[0157] The mask layer can have high hardness; for example, it can be a silicide, such as at least one of SiOx, SiNx, or SiON layers.

[0158] In some examples, the thickness of the mask layer can be less than or equal to 100 nm or greater than or equal to 10 nm.

[0159] In some feasible processes, the mask layer can be fabricated using deposition processes, such as ion-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), sputtering, evaporation, and other thin film deposition methods.

[0160] like Figure 6C A photoresist layer is formed on the mask layer, and the photoresist is exposed and developed to reveal the desired pattern and / or lines. For example, exposure reveals a photoresist layer with a first window.

[0161] The photoresist layer in this application can be a relatively thick photoresist layer, for example, greater than 6 μm, or a relatively thin photoresist layer, for example, less than 2 μm. This application does not limit the thickness of the photoresist layer.

[0162] like Figure 6D Using the above Figure 6C A patterned photoresist layer is etched onto a mask layer to transfer the pattern to the mask layer, forming a mask pattern layer with a first opening.

[0163] In some examples, "transfer" can be understood as an etching process. For example, transferring a pattern to a mask layer can be understood as using an etching process to etch a pattern on the mask layer that is the same size as the pattern on the photoresist layer.

[0164] Using patterned photoresist as a mask, a patterned mask layer is formed, which is called a mask pattern layer.

[0165] In some feasible processes, fluorine-based gas etching mask layers can be used, but not limited to reactive ion etching (RIE), inductively coupled plasma etching (ICP), ion beam etching (IBE), advanced oxide etching (AOE), and neutral loop discharge (NLD).

[0166] like Figure 6E Remove the photoresist layer. This exposes the mask pattern layer with the first window.

[0167] like Figure 6F This forms a photoresist layer. Among them, the above... Figure 6E The first opening in the mask pattern layer shown is filled with a photoresist layer, and the surface of the mask pattern layer opposite to the layer to be etched is covered with a photoresist layer.

[0168] The photoresist layer in this application can be a relatively thick photoresist layer, for example, greater than 6 μm, or a relatively thin photoresist layer, for example, less than 2 μm. This application does not limit the thickness of the photoresist layer.

[0169] like Figure 6G The photoresist layer located within the first window is etched, while the photoresist layer on the sidewall of the first window is retained. In this way, a filling pattern layer with a second window is formed within the first window.

[0170] exist Figure 6G In the example, the photoresist layer located within the first window, forming the pattern of the second window, is called the filling pattern layer.

[0171] In this example, a photoresist layer is prepared and etched to retain the photoresist layer on the sidewall of the first window, thereby reducing the size of the first window in the first direction to obtain the second window.

[0172] In other feasible processes, the filled pattern layer with the second window can be formed in other ways.

[0173] contrast Figure 6E and Figure 6G The first window has a dimension of W1 in the first direction, and the second window has a dimension of W2 in the first direction, where W1 is greater than W2.

[0174] like Figure 6H Using the mask pattern layer and the fill pattern layer as masks, the layer to be etched is etched to the first position.

[0175] This can be understood as using a mask pattern layer and a fill pattern layer as masks to etch a temporary groove in the layer to be etched. The size of the temporary groove in the first direction is approximately equal to the size of the second window in the first direction.

[0176] In this application example, the first direction can be understood as a direction parallel to the substrate surface. Here, parallelism can be considered as approximately parallel.

[0177] In this embodiment, such as Figure 6G and Figure 6H The surface of the mask pattern layer facing away from the layer to be etched is also covered by a photoresist layer. This photoresist layer can protect the mask pattern layer, for example, see... Figure 6HWhen etching the etched layer, the photoresist layer can protect the mask pattern layer. If the mask pattern layer is exposed and not covered by the photoresist layer, it may be etched to the mask pattern layer, causing the mask pattern layer to be thinned or even etched through. This will affect the masking function of the mask pattern layer in subsequent processes.

[0178] In some feasible processes, but not limited to reactive ion etching (RIE), inductively coupled plasma etching (ICP), ion beam etching (IBE), AOE, NLD, and other chlorine-based gas etching methods can be used to etch the layer to be etched.

[0179] In this example, the etching rate of the layer to be etched is V1, and the etching rate of the pattern filling layer is V2, where V1 > V2.

[0180] In some process flows, the etching rate V1 of the layer to be etched is: 1nm / min ≤ V1 ≤ 100nm / min. For example, V1 = 10nm / min, V1 = 20nm / min, V1 = 30nm / min, V1 = 40nm / min, V1 = 50nm / min, V1 = 60nm / min, V1 = 70nm / min, V1 = 80nm / min, V1 = 90nm / min, or V1 = 100nm / min.

[0181] In some processes, the etching selectivity ratio between the layer to be etched and the pattern filling layer is P1, where P1 can be greater than or equal to 5. For example, P1 = 5, P1 = 6, P1 = 7, P1 = 8, P1 = 9, or P1 = 10.

[0182] In the examples provided in this application, the material for the pattern-filling layer can be photoresist. Photoresist has a higher hardness than the layer to be etched, and thus... Figure 6H The photoresist is basically not etched away, and the sidewalls of the temporary grooves obtained by etching are basically perpendicular to the substrate surface.

[0183] See Figure 6H For example, the layer to be etched includes stacked buffer layers, channel layers, insertion layers, barrier layers, and cap layers. When etching the layer to be etched, etching can be performed up to the barrier layer, or it can be performed up to the insertion layer.

[0184] like Figure 6I Remove the fill pattern layer. This reveals the mask pattern layer with the first window.

[0185] In this example, the photoresist layer located within the first window can be removed, as can the photoresist layer located on the mask pattern layer.

[0186] Since the dimension of the first window in the first direction is larger than the dimension of the temporary recess in the first direction, see Figure 6IThe side walls of the first window and the second window can be connected to form a stepped surface.

[0187] like Figure 6J Using a mask pattern layer with a first opening as a mask, a portion of the mask pattern layer is etched, and the layer to be etched is etched to a second position to form a groove with inclined sidewalls in the layer to be etched.

[0188] In some feasible processes, but not limited to reactive ion etching (RIE), inductively coupled plasma etching (ICP), ion beam etching (IBE), AOE, NLD, and other chlorine-based gas etching techniques can be used to etch the mask pattern layer and the layer to be etched.

[0189] For example, plasma etching with chlorine-based gas is used to etch the entire surface. The etching selectivity of chlorine-based gas on the mask pattern layer and GaN layer is used for mask protection. Due to the non-uniformity of plasma etching, the right-angle sidewalls of the steps will be etched away first, and then the sloping sidewalls will be formed.

[0190] See Figure 6J The layer to be etched includes stacked buffer layers, channel layers, insertion layers, barrier layers, and cap layers. During etching, the etching can proceed down to the channel layer.

[0191] In the method of this application example, Figure 6H In the middle, from the bottom surface of the temporary groove to the first position, in Figure 6J In the process, the bottom surface of the groove is finally formed to the second position. The first position and the second position are different positions, with the second position being closer to the substrate than the first position.

[0192] In some examples, the depth dimension of the groove can be greater than or equal to 10 nm and less than or equal to 150 nm.

[0193] Depend on Figures 6I to 6J In the process flow shown, it can be followed Figure 6J1 and Figure 6J2 Understanding. For example, in Figure 6J1 During the etching process, when etching part of the mask pattern layer and the layer to be etched, the mask pattern layer and the layer to be etched will be etched away. Figure 6J1 The dashed box shown is the part that can be... Figure 6I The stepped surface shown is etched into the shape of... Figure 6J2 The inclined surface shown can be referred to as the guiding inclined surface.

[0194] exist Figure 6J1 In the process, when the mask pattern layer is etched, part of the surface of the mask pattern layer is etched away, and the sidewalls of the mask pattern layer that form the first window are etched into slopes, and the walls of the layer to be etched that form the temporary groove are etched into slopes.

[0195] Combination Figure 6J2 and Figure 6J Under the guidance of the inclined plane, the etching layer can be etched to obtain a groove with inclined sidewalls.

[0196] In performing the above Figure 6H In the process shown, the etching rate of the layer to be etched is V1, and the etching rate of the pattern filling layer is V2, where V1 > V2.

[0197] In performing the above Figure 6J In the process shown, the etching rate of the layer to be etched is V3, and the etching rate of the pattern filling layer is V4, where V3 > V4.

[0198] In some examples, V1 can be equal to V3, or V1 can be different from V3.

[0199] In some process flows, the etching rate V3 of the layer to be etched is: 1nm / min≤V1≤100nm / min. For example, V1=10nm / min, V1=20nm / min, V1=30nm / min, V1=40nm / min, V1=50nm / min, V1=60nm / min, V1=70nm / min, V1=80nm / min, V1=90nm / min, or V1=100nm / min.

[0200] In some examples, V4 > V2.

[0201] In performing the above Figure 6H In the process shown, the etching selectivity ratio of the layer to be etched to the pattern filling layer is P1.

[0202] In performing the above Figure 6J In the process shown, the etching selectivity ratio between the layer to be etched and the mask pattern layer is P2; P1 > P2. For example, P2 can be greater than or equal to 5. For example, P1 = 5, P1 = 6, P1 = 7, P1 = 8, P1 = 9, or P1 = 10.

[0203] For example, when the device produced is a HEMT semiconductor device, see... Figure 6K An electrode contact layer is formed within the groove. This electrode contact layer can be either a source contact layer or a drain contact layer.

[0204] In some feasible processes, the electrode contact layer can be fabricated using epitaxial growth techniques. For example, the electrode contact layer can be fabricated using metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).

[0205] To reduce the contact resistance between the source / drain contact layer and the GaN layer, the electrode contact layer can be made of highly doped n++ GaN. Doping elements can include Si, Ge, In, etc. The doping concentration can be 1*10⁻⁶. 19 cm -3 above.

[0206] In some processes, such as when using MOCVD or MBE to fabricate the electrode contact layer, the surface of the electrode contact layer will protrude from the surface of the mask pattern layer.

[0207] like Figure 6L Remove the mask pattern layer.

[0208] For example, a wet etching process can be used to remove the mask pattern layer. This can be achieved using solutions such as buffered oxide etchant (BOE), hydrofluoric acid (HF), or tetramethylammonium hydroxide (TMAH).

[0209] Alternatively, in some processes, the mask pattern layer can be removed by wet process, the source and drain metal patterns can be photolithographically printed after coating, and then the metal can be grown and stripped to prepare ohmic metal, or the source and drain metal can be grown first and then photolithographically and ion-etched to prepare ohmic contacts.

[0210] use Figures 6A to 6L The semiconductor devices fabricated by the process shown can not only have a large tilt angle for the grooves, but also achieve a narrower linewidth.

[0211] For example, return to Figure 6E and Figure 6G When the required inclination angle of the sidewall of the groove is θ, when forming the filling pattern layer with the second opening, the dimension ΔW of the filling pattern layer covering the sidewall of the first opening in the first direction is ΔW = H * tanθ; where the inclination angle θ of the inclined surface is the angle between the inclined surface and the second direction, and H is the distance between the surface of the layer to be etched away from the substrate and the bottom surface of the groove; the first direction is parallel to the substrate surface, and the second direction is perpendicular to the substrate surface. Here, parallel and perpendicular can be understood as basically parallel and basically perpendicular.

[0212] Based on this, when fabricating the semiconductor device, the size ΔW of the filling pattern layer covering the first window sidewall in the first direction can be determined according to the required tilt angle θ, and the target tilt angle can be obtained.

[0213] In addition, in the execution steps such as Figure 6C He Ru Figure 6FAt this time, the thickness of the photoresist layer can be relatively large or relatively small. The thickness of the photoresist layer does not affect the tilt angle of the groove, nor does it affect the linewidth. It will not be like... Figure 4 As shown, when the photoresist layer is thick, a groove with a large tilt angle can be made, but a narrow linewidth cannot be achieved.

[0214] Therefore, the preparation method provided in this application can achieve not only a large tilt angle but also a narrow linewidth. Of course, it can also achieve a large tilt angle and a wide linewidth.

[0215] When the angle of the prepared groove is large, the inclined sidewalls are more conducive to the growth of highly doped n++GaN when epitaxially growing inside and outside the groove. This can reduce the contact resistance between the source / drain contact layer and the GaN layer interface and optimize the performance of the device.

[0216] The linewidth accuracy of the source-drain contact layer obtained using the method described in this application is also relatively high, unlike the methods mentioned above. Figure 4 As shown, the linewidth dimension error is relatively large when using the photoresist reflow method.

[0217] In addition, the inclination angle of the sidewall of the groove is decoupled from the groove depth. Therefore, the method of this application can not only achieve large inclination angles, but also produce shallow or deep grooves.

[0218] exist Figure 6K and Figure 6L In this context, the tilt angle of the interface between the source / drain contact layer and the GaN layer is α, which can be understood as the tilt angle θ of the sidewall of the aforementioned groove.

[0219] The following is combined Figure 6L and Figure 7 The line widths in the example of this application are explained.

[0220] The linewidth of the electrode contact layer located within the groove can be understood as the dimension of the electrode contact layer in the first direction located on the surface of the layer to be etched (which could be the surface of the GaN layer). For example, in Figure 6L and Figure 7 In this model, the linewidth of both the source and drain contact layers is S.

[0221] See Figure 7 As shown, both the source and drain contact layers are strip-shaped structures. An electron migration region exists between the source and drain contact layers. When etching a groove with an inclined surface, the inclined surface can be the side of the source contact layer closest to the electron migration region, and the inclined surface can also be the side of the drain contact layer closest to the electron migration region. Alternatively, as... Figure 7It can be that the two opposite surfaces of the source contact layer in the first direction (width direction) are both inclined surfaces, and the two opposite surfaces of the drain contact layer in the first direction (width direction) are both inclined surfaces.

[0222] As mentioned above Figure 6E and Figure 6G A filling pattern layer with a second window is formed within the first window, the filling pattern layer covering at least a portion of the sidewall of the first window. Here, "at least a portion of the sidewall" can be understood as including at least the wall surface near the electron migration region of the first window. For example, in... Figure 6E In this process, a filling pattern layer can be formed on the wall surface M1 of the first window, or a filling pattern layer can be formed on both wall surface M1 and wall surface M2.

[0223] If HEMT semiconductor devices are required, the following process steps can also be performed.

[0224] like Figure 8A A source metal layer is formed on the source contact layer, and a drain metal layer is formed on the drain contact layer. This forms an ohmic contact.

[0225] In some processes, source and drain metal layers can be prepared by sputtering, evaporation, or electroplating.

[0226] The source and drain metals may be selected from at least one of nickel (Ni) and gold (Au), or at least one of platinum (Pt), titanium (Ti), and gold (Au), or at least one of tungsten (W), titanium (Ti), and gold (Au), or at least one of titanium nitride (TiN) and copper (Cu).

[0227] like Figure 8B A passivation layer is formed on the surface of the GaN layer. For example, in... Figure 8B In this process, a passivation layer can be formed on the surface of the cap layer.

[0228] The passivation layer can be a single layer or a stacked multilayer structure. For example, it can be at least one of SiN, SiO2, and SiON layers; for instance, it can be a single SiN layer. Alternatively, it can be a multilayer structure, where one layer can be a layer of aluminum oxide (Al2O3) or aluminum nitride (AlN), and another layer can be a layer of SiNy, SiO2, or SiON.

[0229] like Figure 8C A gate accommodating trench is etched within the passivation layer, located between the source and drain contact layers. This gate accommodating trench extends to the surface of the GaN layer.

[0230] like Figure 8DA gate is fabricated within a gate accommodating trench, allowing the gate to contact the GaN layer. This process then yields a HEMT semiconductor device.

[0231] In another process step, a gate dielectric layer can be formed before the gate is formed, and then the gate can be formed on the gate dielectric layer.

[0232] The gate metal may be made of at least one of Ni and Au, or at least one of Pt, Ti, and Au, or at least one of W, Ti, and Au, or at least one of TiN and Cu.

[0233] In one process, a metal pattern can be formed by photolithography after coating with a photoresist and then metal growth followed by stripping to prepare the gate metal, or metal can be grown first and then photolithography and ion etching can be used to prepare the gate metal.

[0234] like Figure 8D As shown, in the HEMT semiconductor device, for example, the interface between the source contact layer and the GaN layer is an inclined surface, and the interface between the drain contact layer and the GaN layer is an inclined surface. The inclination angle α of the inclined surface can be less than or equal to 110°, or it can be 110°≤θ≤150°. For example, it can be θ=110°, θ=120°, θ=130°, θ=140° or θ=150°.

[0235] This can be understood as follows: the semiconductor process method described in this application can be used to fabricate grooves with small tilt angles or grooves with large tilt angles.

[0236] Additionally, see Figure 8D The linewidth S of the source and drain contact layers can be less than or equal to 6 micrometers, for example, less than or equal to 3 micrometers. Linewidth S = 4 micrometers, linewidth S = 3 micrometers, or linewidth S = 2 micrometers.

[0237] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0238] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A semiconductor manufacturing process, characterized in that, include: Form the layer to be etched on the substrate; A mask pattern layer with a first opening is formed on the side of the layer to be etched away from the substrate; A filling pattern layer having a second opening is formed within the first opening, the filling pattern layer covering at least a portion of the sidewall of the first opening; Using the mask pattern layer and the filling pattern layer as masks, the layer to be etched is etched to the first position; Remove the fill pattern layer; Using the mask pattern layer as a mask, a portion of the mask pattern layer is etched, and the layer to be etched is etched to a second position to form a groove with inclined sidewalls in the layer to be etched.

2. The semiconductor process method according to claim 1, characterized in that, Using the mask pattern layer and the fill pattern layer as masks, etching the layer to be etched to the first position includes: The etching rate of the layer to be etched is V1, and the etching rate of the pattern filling layer is V2, where V1 > V2; Using the mask pattern layer as a mask, etching a portion of the mask pattern layer, and etching the layer to be etched to the second position, includes: The etching rate of the layer to be etched is V3, and the etching rate of the mask pattern layer is V4, where V3 > V4.

3. The semiconductor process method according to claim 2, characterized in that, V4 > V2.

4. The semiconductor process method according to claim 2 or 3, characterized in that, 1nm / min≤V1≤100nm / min, 1nm / min≤V3≤100nm / min.

5. The semiconductor process method according to any one of claims 1-4, characterized in that, Using the mask pattern layer and the fill pattern layer as masks, etching the layer to be etched to the first position includes: The etching selectivity ratio between the layer to be etched and the filling pattern layer is P1; Using the mask pattern layer as a mask, etching a portion of the mask pattern layer, and etching the layer to be etched to the second position, includes: The etching selectivity ratio between the layer to be etched and the mask pattern layer is P2; P1 > P2.

6. The semiconductor process method according to claim 5, characterized in that, P1≥5, P2≥5.

7. The semiconductor process method according to any one of claims 1-6, characterized in that, The second position is closer to the substrate than the first position.

8. The semiconductor process method according to any one of claims 1-7, characterized in that, The mask pattern layer includes silicide; The filling pattern layer includes photoresist.

9. The semiconductor process method according to any one of claims 1-8, characterized in that, A filling pattern layer having a second opening is formed within the first opening, the filling pattern layer covering at least a portion of the sidewall of the first opening, including: A photoresist layer is filled into the first window; A portion of the photoresist layer within the first opening is etched, while the photoresist layer on the sidewall of the first opening is retained, to form the filling pattern layer having the second opening within the first opening.

10. The semiconductor process method according to claim 9, characterized in that, When filling the first window with a photoresist layer, the method further includes covering the surface of the mask pattern layer opposite to the layer to be etched with the photoresist layer.

11. The semiconductor process method according to any one of claims 1-10, characterized in that, Using the mask pattern layer and the filling pattern layer as masks, after etching the layer to be etched to the first position, a temporary groove is formed in the layer to be etched. After removing the mask pattern layer, the mask pattern layer with the first opening is formed, and at least a portion of the sidewall of the first opening and at least a portion of the sidewall of the temporary groove are connected to form a stepped surface.

12. The semiconductor process method according to claim 11, characterized in that, Etching a portion of the mask pattern layer, and etching the layer to be etched to the second location, includes: The stepped surface is etched to form an inclined surface.

13. The semiconductor process method according to any one of claims 1-12, characterized in that, When the material of the mask pattern layer includes silicide and the material of the layer to be etched includes gallium nitride, etching a portion of the mask pattern layer and etching the layer to be etched to the second position includes: The mask pattern layer and the layer to be etched are etched using a gas containing chlorine.

14. The semiconductor process method according to any one of claims 1-13, characterized in that, When the inclination angle of the inclined surface of the groove is θ and the depth dimension of the groove is H; A filling pattern layer having a second window is formed within the first window, the filling pattern layer covering at least a portion of the sidewall of the first window, including: The dimension ΔW of the filling pattern layer covering the sidewall of the first window in the first direction is H*tanθ; Wherein, the inclination angle θ of the inclined surface is the angle between the inclined surface and the second direction; The depth H of the groove is the distance between the surface of the layer to be etched that is away from the substrate and the bottom surface of the groove; The first direction is parallel to the substrate surface, and the second direction is perpendicular to the substrate surface.

15. The semiconductor process method according to any one of claims 1-14, characterized in that, The semiconductor process method is used to fabricate a field-effect transistor; The layer to be etched contains a gallium nitride layer.

16. The semiconductor process method according to claim 15, characterized in that, Forming the layer to be etched on the substrate includes: A buffer layer is formed on the substrate; A channel layer is formed on the buffer layer; An insertion layer is formed on the channel layer; A barrier layer is formed on the insertion layer; A cap layer is formed on the barrier layer.

17. The semiconductor process method according to claim 16, characterized in that, Using the mask pattern layer and the fill pattern layer as masks, etching the layer to be etched to the first position includes: Using the mask pattern layer and the filling pattern layer as masks, etching is performed into the barrier layer.

18. The semiconductor process method according to claim 16 or 17, characterized in that, Using the mask pattern layer as a mask, etching a portion of the mask pattern layer, and etching the layer to be etched to the second position to form a groove with inclined sidewalls within the layer to be etched, including: The groove extends into the channel layer.

19. The semiconductor process method according to any one of claims 15-18, characterized in that, After forming the groove with inclined sidewalls within the layer to be etched, the semiconductor process further includes: An electrode contact layer is filled in the groove, which is either a source contact layer or a drain contact layer.

20. The semiconductor process method according to claim 19, characterized in that, After the electrode contact layer is filled into the groove, the linewidth of the electrode contact layer in a first direction is less than or equal to 6 micrometers, and the first direction is parallel to the substrate surface; The tilt angle α at the interface between the electrode contact layer and the gallium nitride layer is: 110°≤α≤150°; The tilt angle α is the angle between the interface between the electrode contact layer and the gallium nitride layer and the second direction, which is perpendicular to the substrate surface.

21. The semiconductor process method according to claim 19 or 20, characterized in that, After filling the groove with the electrode contact layer, the semiconductor process further includes: An electrode metal layer is formed on the electrode contact layer, wherein the electrode metal layer is a source metal layer or a drain metal layer; The gate of the field-effect transistor is obtained.

22. A semiconductor device, characterized in that, include: Substrate; A field-effect transistor formed on the substrate, the field-effect transistor being fabricated using the semiconductor process method according to any one of claims 1-21.

23. An electronic device, characterized in that, include: A processor and a semiconductor device, wherein the processor is electrically connected to the semiconductor device; The semiconductor device includes: Substrate, gallium nitride layer formed on the substrate; The semiconductor device further includes an electrode contact layer, which is formed within the gallium nitride layer, and the electrode contact layer is either a source contact layer or a drain contact layer. The linewidth of the electrode contact layer in a first direction is less than or equal to 6 micrometers, and the first direction is parallel to the substrate surface; The interface between the electrode contact layer and the gallium nitride layer is an inclined surface, and the inclination angle α of the inclined surface is: 110°≤α≤150°; the inclination angle α is the angle between the inclined surface and the second direction, and the second direction is perpendicular to the substrate surface.

24. The electronic device according to claim 23, characterized in that, The gallium nitride layer includes a buffer layer, a channel layer, an insertion layer, a barrier layer, and a cap layer; The buffer layer is formed on the substrate, the channel layer is formed on the buffer layer, the insertion layer is formed on the channel layer, the barrier layer is formed on the insertion layer, and the cap layer is formed on the barrier layer.

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