Semiconductor device

Abstract

The invention provides a semiconductor device. The semiconductor device includes: a substrate of a first conductivity type; a gate electrode on the substrate; a first high-concentration impurity region of a first conductivity type disposed on a first side of the gate electrode; a first well of the first conductivity type disposed under the first high concentration impurity region and surrounding the first high concentration impurity region; a second well of a second conductivity type overlapping a portion of the gate electrode and adjacent to the first well; and a first deep well of a second conductivity type disposed under the first well and the second well, the first deep well and the first high concentration impurity region being responsive to the first voltage.

Description

[0001] This application is a divisional application of Chinese invention patent application 201710505735.3, filed on June 28, 2017, entitled "Semiconductor Device". Technical Field

[0002] This disclosure relates to semiconductor devices, and more particularly to semiconductor devices for use as switching devices. Background Technology

[0003] Commonly used MOSFETs offer advantages such as higher power gain compared to bipolar transistors, relatively simple gate drive circuitry, and no time delay during turn-off due to minority carrier storage or recombination. Therefore, MOSFETs are widely used as control, logic, and power switches.

[0004] In addition, double-diffused MOSFETs (DEMOS) utilizing bidirectional diffusion technology, such as lateral DEMOS transistors (LDMOS), are widely used as power MOS transistors. Summary of the Invention

[0005] A semiconductor device may be provided that can improve battery efficiency by preventing the operation of parasitic bipolar junction transistors (BJTs) in the internal regions of power switching devices.

[0006] According to one aspect of the present invention, a semiconductor device is provided, the semiconductor device comprising: a substrate of a first conductivity type; a gate electrode on the substrate; a first high-concentration impurity region of the first conductivity type disposed on a first side of the gate electrode; a first well of the first conductivity type disposed below and surrounding the first high-concentration impurity region; a second well of a second conductivity type overlapping a portion of the gate electrode and adjacent to the first well; and a first deep well of the second conductivity type disposed below the first well and the second well, the first deep well and the first high-concentration impurity region being responsive to a first voltage.

[0007] According to another aspect of the present invention, a semiconductor device is provided, the semiconductor device comprising: a substrate of a first conductivity type; a gate electrode on the substrate; a first high-concentration impurity region of the first conductivity type disposed on a first side of the gate electrode; a first well of the first conductivity type disposed below and surrounding the first high-concentration impurity region; a second high-concentration impurity region of a second conductivity type disposed on a second side of the gate electrode; a second well of the second conductivity type disposed below and surrounding the second high-concentration impurity region; a first deep well of the first conductivity type disposed below the second well; and a second deep well of the second conductivity type disposed below the first deep well across the first and second wells, the second deep well and the first high-concentration impurity region being responsive to a first voltage.

[0008] According to another aspect of the present invention, a semiconductor device is provided, the semiconductor device comprising: a substrate of a second conductivity type, including a first deep well of a first conductivity type and a second deep well of a second conductivity type on the first deep well; and a transistor formed on the substrate and including a gate electrode, a first terminal responsive to a first voltage and a second terminal responsive to a second voltage different from the first voltage, wherein the first deep well is responsive to the first voltage.

[0009] According to another aspect of the present invention, a semiconductor device is provided, comprising a substrate of a first conductivity type, a deep well on the substrate, a high-voltage well on the deep well, a pickup region on the deep well, and a drift region on the high-voltage well. The high-voltage well is located between the deep well and the drift region, but not between the deep well and the pickup region.

[0010] It should be noted that aspects of the inventive concept described with respect to one embodiment can be incorporated into different embodiments, although not specifically described herein. That is, all embodiments and / or features of any embodiment can be combined in any manner and / or combination. These and other aspects of the inventive concept are described in detail in the following description. Attached Figure Description

[0011] The above and other aspects, features, and advantages of this disclosure will become more apparent to those skilled in the art from the exemplary embodiments described in detail with reference to the accompanying drawings, in which:

[0012] Figure 1 This is a cross-sectional view of a semiconductor device according to some embodiments of the present invention;

[0013] Figure 2 It may include some embodiments based on the concept of the present invention. Figure 1 Circuit diagram of semiconductor devices;

[0014] Figure 3 These are some embodiments of the concept of the present invention. Figure 1 A cross-sectional view of the internal equivalent circuit of a semiconductor device;

[0015] Figure 4 This is a cross-sectional view of a semiconductor device according to some embodiments of the present invention;

[0016] Figure 5 This is a cross-sectional view of a semiconductor device according to some embodiments of the present invention;

[0017] Figure 6 This is a cross-sectional view of a semiconductor device according to some embodiments of the present invention;

[0018] Figure 7 This is a cross-sectional view of a semiconductor device according to some embodiments of the present invention;

[0019] Figure 8 This is a cross-sectional view of a semiconductor device according to some embodiments of the present invention;

[0020] Figure 9 This is a cross-sectional view of a semiconductor device according to some embodiments of the present invention;

[0021] Figure 10 This is a cross-sectional view of a semiconductor device according to some embodiments of the present invention;

[0022] Figure 11 This is a cross-sectional view of a semiconductor device according to some embodiments of the present invention;

[0023] Figure 12 These are cross-sectional views of semiconductor devices according to some embodiments of the present invention; and

[0024] Figures 13 to 16 This is a cross-sectional view showing an intermediate stage of manufacturing, illustrating a method for manufacturing a semiconductor device according to some embodiments of the concept of the present invention. Detailed Implementation

[0025] In the following text, reference will be made to Figures 1 to 3 Semiconductor devices according to some exemplary embodiments of the present invention are described.

[0026] Figure 1 This is a cross-sectional view of a semiconductor device according to some exemplary embodiments of the present invention. Figure 2 It may include some embodiments based on the concept of the present invention. Figure 1 Circuit diagrams of semiconductor devices, Figure 3 These are some embodiments of the concept of the present invention. Figure 1 A cross-sectional view of the internal equivalent circuit of a semiconductor device.

[0027] Reference Figure 1 Semiconductor devices according to some exemplary embodiments may include a gate electrode 130, a source region 120, a drain region 125, a body contact region 122, a body region 110, a drift region 115, a high-voltage well 155, a deep well 150, and a pickup contact region 145.

[0028] The substrate 100 may include a base substrate and an epitaxial layer grown on the base substrate, but the embodiments of the present invention are not limited thereto.

[0029] Substrate 100 may consist only of a base substrate, that is, it may not include an epitaxial layer. Substrate 100 may include one or more of the following: silicon semiconductor substrate, gallium arsenide semiconductor substrate, silicon germanium semiconductor substrate, ceramic semiconductor substrate, quartz semiconductor substrate, and glass semiconductor substrate for display.

[0030] Various embodiments are described below by way of example, wherein substrate 100 is a silicon semiconductor substrate. Furthermore, the silicon semiconductor substrate may be, for example, a first conductivity type (e.g., p-type).

[0031] Device isolation region 160 can be configured such that gate electrode 130 is spaced apart from drain region 125, as will be described below.

[0032] Device isolation region 160 can reduce or prevent reliability degradation in the semiconductor device caused by the high electric field formed between the drain region 125 and the gate electrode 130 adjacent to the edge of the drain region 125 when a high voltage is applied to the drain region 125. Device isolation region 160 can improve the breakdown voltage of the semiconductor device.

[0033] Device isolation region 160 may be formed, for example, as a shallow trench isolation (STI) region, but embodiments of the present invention are not limited thereto. For example, in other embodiments, it may also be formed as a localized silicon oxide (LOCOS) region.

[0034] The gate electrode 130 can be formed on the substrate 100. The gate electrode 130 can be formed across the drift region 115 and the body region 110.

[0035] A portion of the gate electrode 130 may overlap with the drift region 115, and another portion of the gate electrode 130 may overlap with the main body region 110.

[0036] A portion of the overlapping drift region 115 of the gate electrode 130 may overlap a portion of the device isolation region 160. The gate electrode 130 may extend along a portion of the upper surface of the device isolation region 160.

[0037] Gate electrode 130 may include, for example, polycrystalline silicon (polycrystalline Si), amorphous silicon (a-Si), titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), and titanium carbide (TiC). The following are at least one of the following: tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and combinations thereof.

[0038] When the gate electrode 130 includes silicon in its upper surface, the gate electrode 130 may include a metal silicide film formed on the upper surface of the gate electrode 130.

[0039] A gate insulating film 135 can be disposed on the gate electrode 130 and the substrate 100. The gate insulating film 135 can electrically isolate the gate electrode 130 and the substrate 100.

[0040] The gate insulating film 135 may be, for example, a silicon oxide film, a silicon nitride film, a silicon nitride oxide film, GexOyNz, GexSiyOz, a high-k dielectric film, a combination thereof, or a stack of such films sequentially stacked. For example, the high-k dielectric film may include one or more of hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, but embodiments of the invention are not limited thereto.

[0041] Gate spacer 132 may be formed on the sidewall of gate electrode 130. For example, gate spacer 132 may include at least one of silicon nitride (SiN), silicon oxide nitride (SiON), silicon oxide (SiO2), silicon oxycarbon nitride (SiOCN), silicon carbon nitride (SiCN), and combinations thereof.

[0042] although Figure 1 The gate spacer 132 is shown to be a single layer, but it is not limited to this and can be formed as multiple layers.

[0043] Reference Figure 1The semiconductor device used as the gate electrode 130 can be, for example, a first conductivity type transistor, i.e., a p-type transistor.

[0044] The source region 120 can be disposed on one side of the gate electrode 130. The source region 120 can be, for example, a high-concentration impurity region of a first conductivity type.

[0045] The source region 120 can be formed within the substrate 100. Furthermore, unlike the illustration, the source region 120 can be an elevated source region.

[0046] A metal silicide film can be formed on the upper surface of the source region 120 to reduce the resistance between the source region 120 and the contact to which the source voltage is applied.

[0047] The main body region 110 may be formed on one side of the gate electrode 130. The main body region 110 may be formed below the source region 120 to surround the source region 120.

[0048] The main body region 110 may be formed within the substrate 100. The main body region 110 may overlap a portion of the gate electrode 130.

[0049] The body region 110 can be, for example, a second conductivity type (e.g., n-type) impurity region. The body region 110 can also be a second conductivity type well, for example in... Figure 1 It is marked as NWELL.

[0050] The host region 110 may have a relatively low doping concentration compared to the source region 120, and in one example, the doping concentration may be the impurity concentration doped (or implanted) for each region.

[0051] The main contact region 122 may be adjacent to the source region 120 and formed within the main region 110. The source region 120 may be disposed between the main contact region 122 and the gate electrode 130.

[0052] The main contact region 122 can be, for example, a high-concentration impurity region of a second conductivity type. The main contact region 122 can have a relatively high doping concentration compared to the main region 110.

[0053] A metal silicide film can be formed on the upper surface of the body contact region 122 to reduce the resistance between the body contact region 122 and the contact to which a body voltage is applied to the body contact region 122.

[0054] The drain region 125 can be located on the other side of the gate electrode 130. The drain region 125 can be, for example, a high-concentration impurity region of a first conductivity type.

[0055] The drain region 125 can be formed within the substrate 100. Furthermore, unlike the illustration, the drain region 125 can be an elevated drain region.

[0056] A metal silicide film can be formed on the upper surface of the drain region 125 to reduce the resistance between the drain region 125 and the contact to which a drain voltage is applied.

[0057] The device isolation region 160 can be located between the drain region 125 and the gate electrode 130.

[0058] The drift region 115 can be disposed on the other side of the gate electrode 130. The drift region 115 can be formed adjacent to the main body region 110.

[0059] Drift region 115 can be formed below drain region 125 to surround drain region 125.

[0060] The drift region 115 may be formed within the substrate 100. The drift region 115 may overlap a portion of the gate electrode 130.

[0061] The drift region 115 can be formed around the device isolation region 160 and the drain region 125. In other words, the device isolation region 160 can be located within the drift region 115.

[0062] Drift region 115 can be, for example, a first conductivity type (e.g., p-type) impurity region, for example, in Figure 1 The middle part is marked PDRIFT. Drift region 115 can be a trap of the first conductivity type.

[0063] The drift region 115 can have a relatively low doping concentration compared to the source region 120 and the drain region 125.

[0064] like Figure 1 As shown, the drift region 115 and the main body region 110 do not contact each other, but the exemplary implementation is not limited to this.

[0065] Pick-up contact region 145 may be located on the other side of gate electrode 130. Pick-up contact region 145 may be, for example, a relatively high concentration of impurities of a second conductivity type.

[0066] The pickup contact area 145 may not be located within the drift area 115. The drain area 125 may be located between the pickup contact area 145 and the gate electrode 130.

[0067] Pickup contact area 145 may be formed within substrate 100. Furthermore, unlike the illustration, pickup contact area 145 may include an area of ​​an upper surface that is raised higher than the upper surface of substrate 100.

[0068] A metal silicide film can be formed on the upper portion of the pickup contact area 145 to reduce the resistance between the pickup contact area 145 and the contact to which a pickup voltage is applied.

[0069] The pickup area 140 can be disposed on the other side of the gate electrode 130. The pickup area 140 can be formed adjacent to the drift area 115. The drift area 115 can be disposed between the pickup area 140 and the main body area 110.

[0070] Pickup area 140 may be formed below pickup contact area 145 to surround pickup contact area 145.

[0071] Pickup area 140 may be formed within substrate 100. Pickup area 140 may not overlap with gate electrode 130.

[0072] Pickup region 140 can be, for example, a second conductivity type (e.g., n-type) impurity region. Pickup region 140 can also be a second conductivity type well, for example in... Figure 1 It is marked as NWELL.

[0073] Pickup region 140 can have a relatively low doping concentration compared to pickup contact region 145.

[0074] like Figure 1 As shown, the drift area 115 and the pickup area 140 can be in contact with each other, but the embodiments of the present invention are not limited thereto.

[0075] The deep trap 150 can be located below the main body area 110, the pickup area 140, and the drift area 115. The deep trap 150 can be located across the pickup area 140, the main body area 110, and the drift area 115.

[0076] A deep well 150 may be formed within the substrate 100. The deep well 150 may have a different conductivity type than the substrate 100. The deep well 150 may be a second conductivity type (e.g., n-type) impurity region, for example, in... Figure 1 It is marked as DEEPNW.

[0077] The deep well 150 and the drift region 115 may have the same type of conductivity and may not be in contact with each other. However, the deep well 150 and the pickup region 140 may have the same type of conductivity and may be in contact with each other.

[0078] The main area 110, drift area 115 and pickup area 140 can be respectively set on the deep trap 150.

[0079] although Figure 1 The source region 120, drain region 125, body contact region 122 and pickup contact region 145 are shown to be formed by implanting impurities into the substrate 100, but the exemplary embodiments are not limited to this.

[0080] The source region 120, drain region 125, body contact region 122 and pickup contact region 145 can be formed by removing a portion of the substrate 100 to form a recess and then forming an epitaxial pattern on the recess.

[0081] The high voltage trap 155 may be disposed below the main body region 110 and the drift region 115. However, the high voltage trap 155 may not be disposed below the pickup region 140.

[0082] A high-voltage trap 155 can be disposed between the main body region 110 and the deep trap 150. The main body region 110 and the deep trap 150 can be isolated from each other by the high-voltage trap 155.

[0083] Furthermore, a high-voltage trap 155 may be disposed between the drift region 115 and the deep trap 150. That is, a portion of the high-voltage trap 155 may extend between the drift region 115 and the deep trap 150.

[0084] exist Figure 1 In this configuration, the high-voltage trap 155 can extend completely between the regions where the drift region 115 and the deep trap 150 overlap perpendicularly with each other. That is, the width of the drift region 115 can be substantially the same as the width of the perpendicularly overlapping region of the drift region 115 and the high-voltage trap 155.

[0085] In some exemplary embodiments of the semiconductor device conceived according to the present invention, the high-voltage trap 155 may extend across the body region 110 and the drift region 115, but may not extend along the pickup region 140.

[0086] Since the high-voltage trap 155 does not need to extend between the pickup area 140 and the deep trap 150, the pickup area 140 and the deep trap 150 can contact each other.

[0087] The main body region 110 and the drift region 115 can be respectively located on the upper part of the high voltage trap 155, but the pickup region 140 can be located outside the upper part of the high voltage trap 155.

[0088] A high-voltage well 155 can be formed within the substrate 100. The high-voltage well 155 can be, for example, a well of a first conductivity type (e.g., p-type), such as in... Figure 1 It is marked as HVPW.

[0089] Since the high voltage trap 155 can be formed deeper than the pickup region 140, the drift region 115 and the main region 110, the high voltage trap 155 can be a deep trap.

[0090] The high-voltage trap 155 may be disposed within the deep trap 150. However, the high-voltage trap 155 may not be buried within the deep trap 150. That is, the deep trap 150 may not be disposed between the high-voltage trap 155 and the main body region 110, or between the high-voltage trap 155 and the drift region 115.

[0091] The high-voltage trap 155 may contact the drift region 115 and the main body region 110. The upper portion of the high-voltage trap 155 may contact the lower portion of the drift region 115 and the lower portion of the main body region 110.

[0092] In some exemplary embodiments of the semiconductor device conceived according to the present invention, the drain region 125 and the pickup contact region 145 can be connected to a first voltage (V1) (i.e., a node having the same potential). That is, the drain region 125 and the pickup contact region 145 can be connected to a node having the same potential.

[0093] The deep well 150 can be connected to the first voltage (V1) through the pickup contact area 145 and the pickup area 140. That is, the deep well 150 and the drain area 125 can be connected to the first voltage (V1).

[0094] like Figure 1 As shown, the source region 120 and the main contact region 122 can be connected to a second voltage (V2) that is different from the first voltage (V1).

[0095] The voltage connected to the source region 120 may be different from the voltage connected to the body contact region 122.

[0096] In some exemplary embodiments of the semiconductor device conceived according to the present invention, the source region 120, drain region 125, body contact region 122, body region 110, drift region 115, high voltage well 155, deep well 150, pickup contact region 145 and pickup region 140 may be impurity regions formed by implanting impurities into the substrate 100.

[0097] In other words, the substrate 100 may include a source region 120, a drain region 125, a body contact region 122, a body region 110, a drift region 115, a high-voltage well 155, a deep well 150, a pickup contact region 145, and a pickup region 140.

[0098] First conductivity type (e.g., p-type) substrate 100 (e.g., in...) Figure 1 The substrate 100 (labeled P-SUB) may include a second conductivity type (e.g., n-type) deep well 150 and a high-voltage well 155 on the deep well 150. In other words, the substrate 100, the deep well 150, and the high-voltage well 155 may have a stacked structure corresponding to a PNP transistor.

[0099] Furthermore, the transistor including the gate electrode 130 can be formed on the substrate 100, which includes a stacked structure of PNP transistors. This will be referred to... Figure 2 and 3 The details are described below.

[0100] Reference Figure 2 and 3The circuit diagrams of semiconductor devices according to some exemplary embodiments of the present invention will be described below.

[0101] Figure 2 A circuit diagram of a synchronous boost converter in which semiconductor devices according to some exemplary embodiments can be used is partially shown. Because... Figure 2 The circuit diagrams are provided for exemplary implementation purposes, so the technical nature of this disclosure may not be limited thereto.

[0102] Reference Figure 2 The inductor (L) can be placed at the input voltage terminal (V). in Between the first transistor (M1) and the first node (N1). Furthermore, the ends of the first transistor (M1) and the second transistor (M2) can contact each other at the first node (N1). The first transistor (M1) and the second transistor (M2) can, for example, be used as switching devices in a synchronous boost converter.

[0103] The other end of the second transistor (M2) can be connected to the output voltage terminal (V). out ) connection. Able to maintain the output voltage terminal (V) out A capacitor (C) with a constant voltage can be placed between the second transistor (M2) and the output voltage terminal (V). out The second node (N2) between ).

[0104] When the second transistor (M2) is formed on the semiconductor substrate, the parasitic bipolar transistor (Q1) can be included in the circuit diagram of the synchronous boost converter.

[0105] The emitter terminal of the parasitic bipolar transistor (Q1) can be connected to the first node (N1), and the base terminal of the parasitic bipolar transistor (Q1) can be connected to the second node (N2).

[0106] For example, when the second transistor (M2) is in the off state and the first transistor (M1) is in the on state, the inductor current (I) flowing through the inductor (L) is... L It can flow through the channel region of the first transistor (M1).

[0107] Subsequently, when the first transistor (M1) is turned off, both the first transistor (M1) and the second transistor (M2) can simultaneously enter a dead time section where they are off. Furthermore, when the first transistor (M1) is turned off and the second transistor (M2) is turned on, the first transistor (M1) and the second transistor (M2) can function similarly to the state during the dead time section until the second transistor (M2) is in the saturation region.

[0108] Since the first transistor (M1) and the second transistor (M2) are in the off state, the inductor current (I) L It can flow without passing through the channel region of the first transistor (M1) and the channel region of the second transistor (M2).

[0109] However, because the inductor (L) has the ability to maintain the inductor current (I) flowing through the inductor... L Due to the characteristics of inductors (L), an inductor (L) can provide inductor current (I). L It operates like a current source.

[0110] Inductor current (I) L It can be divided into those that pass through the parasitic bipolar transistor (Q1) towards the output voltage terminal (V). out ) guided output current (I out ) and substrate leakage current (I) flowing toward the semiconductor substrate psub ).

[0111] At this time, when the substrate leakage current (I) flows from the collector of the parasitic bipolar transistor (Q1) toward the semiconductor substrate... psub As the input voltage increases, the efficiency of the synchronous boost converter circuit deteriorates. For example, when the input voltage (V) increases... in When connected to the battery, the substrate leakage current (I) psub This will consume a lot of charge. Therefore, battery life will be shortened.

[0112] In other words, the efficiency of the synchronous boost converter circuit deteriorates when the parasitic bipolar transistor (Q1) is turned on and operated.

[0113] Therefore, the substrate leakage current (I psub The voltage drop across the parasitic bipolar transistor (Q1) can be reduced by keeping the parasitic bipolar transistor (Q1) inactive, thus reducing the voltage drop across the parasitic bipolar transistor (Q1) towards the output voltage terminal (V). out ) guided output current (I out The efficiency can be increased. In other words, the efficiency of the synchronous boost converter circuit can be improved.

[0114] exist Figure 2 and Figure 3 In the second transistor (M2), there may be a gate electrode 130, a drain region 125, a source region 120 and a body contact region 122.

[0115] The drain region 125 of the second transistor (M2) can be connected to the first node (N1). That is, the first voltage connected to the drain region 125 ( Figure 1 V1 can be the voltage of the first node (N1).

[0116] The source region 120 and the body contact region 122 of the second transistor (M2) can be connected to the second node (N2). That is, the second voltage (M2) connected to the source region 120 and the body contact region 122... Figure 1 V2 can be the voltage of the second node (N2).

[0117] In other words, the first terminal (e.g., drain region 125) of the second transistor (M2) can be connected to the voltage of the first node (N1) (i.e., Figure 1 The first voltage (V1) is connected, and the second terminal of the second transistor (M2) (e.g., source region 120 or body contact region 122) can be connected to the voltage of the second node (N2) (i.e., Figure 1 The second voltage (V2) is connected.

[0118] The parasitic bipolar transistor (Q1) may include a deep well 150 (n-type impurity region), a high-voltage well 155 (p-type impurity region) on the deep well 150, a drift region 115 (p-type impurity region) on the deep well 150, and a substrate 100 (p-type substrate) on the lower part of the deep well 150.

[0119] The emitter terminal of the parasitic bipolar transistor (Q1) can be a third node (N3) where a high-voltage well 155 and a drift region 115 are located. The base terminal of the parasitic bipolar transistor (Q1) can be a deep well 150. Furthermore, the collector terminal of the parasitic bipolar transistor (Q1) can be a substrate 100.

[0120] At this time, the substrate leakage current (I psub The current can flow towards the substrate 100 through the collector of the parasitic bipolar transistor (Q1). It can also flow towards the output voltage terminal (V). out ) guided output current (I out This may include the current flowing through a first diode (D1) formed between the drift region 115 and the main region 110, and the current flowing through a second diode (D2) formed between the high voltage trap 155 and the main region 110.

[0121] The deep well 150 (which is the base terminal of the parasitic bipolar transistor (Q1)) can be connected to the first node (N1) via the pick-up contact area 145 and the pick-up area 140.

[0122] Since pickup contact 145 and pickup region 140 are impurity regions of the second conductivity type, the voltage drop of pickup contact 145 and pickup region 140 can be relatively small. That is, the voltage of deep well 150 (which is the base terminal of parasitic bipolar transistor (Q1)) can be similar to the voltage of the first node (N1).

[0123] Therefore, the voltage difference between the emitter terminal (N3) and the base terminal (N4) of the parasitic bipolar transistor (Q1) can be essentially zero.

[0124] When there is no voltage difference between the emitter terminal (N3) and the base terminal (N4) of the parasitic bipolar transistor (Q1), the parasitic bipolar transistor (Q1) can be inactive.

[0125] Therefore, the substrate leakage current (I) flows towards the substrate 100 through the collector of the parasitic bipolar transistor (Q1). psub It can be essentially zero or close to zero.

[0126] Therefore, the inductor current (I) L The first diode (D1) and the second diode (D2) can be directed towards the output voltage terminal (V). out ) flows. That is, the inductor current (I) flows. L ) can be compared with the output current (I) out They are basically the same.

[0127] Additionally, a third diode (D3) can be formed between the drift region 115 and the deep well 150. In this case, the voltage difference between the drift region 115 and the deep well 150 can be essentially zero. That is, since the voltage difference applied to the third diode (D3) is approximately zero, the breakdown characteristics of the second transistor (M2) can be improved.

[0128] Furthermore, when the drift region 115 and the deep well 150 are not isolated by the high voltage well 155, the source region 120 and the drain region 125 can be electrically connected to each other through the pickup contact region 145, the pickup region 140, the deep well 150 and the body region 110.

[0129] Therefore, regardless of whether a gate voltage is applied to the gate electrode 130 of the second transistor (M2), current can flow between the source region 120 and the drain region 125 of the second transistor (M2). That is, the second transistor (M2) can be used without being a switching device.

[0130] Figure 4-7 This is a cross-sectional view of a semiconductor device according to some exemplary embodiments of the present invention. For the sake of convenience, the description will be mainly based on references. Figures 1 to 3 Differences in the described exemplary implementation methods.

[0131] Reference Figure 4 In some exemplary embodiments of the semiconductor device conceived according to the present invention, the high voltage trap 155 may vertically overlap a portion of the drift region 115.

[0132] The high-voltage trap 155 may be disposed in a portion between the drift region 115 and the deep trap 150, but may not be disposed in the other portion between them. That is, the width of the drift region 115 may be greater than the width of the vertical overlap between the drift region 115 and the high-voltage trap 155.

[0133] In other words, the lower surface of the drift region 115 may include a first portion and a second portion. In this case, the high-voltage trap 155 may be inserted between the first portion of the lower surface of the drift region 115 and the deep trap 150, but may not be disposed between the second portion of the lower surface of the drift region 115 and the deep trap 150.

[0134] Reference Figure 5 In some exemplary embodiments of the semiconductor device according to the present invention, the high voltage well 155 may be disposed between the main region 110 and the deep well 150, but may not be disposed between the drift region 115 and the deep well 150.

[0135] The main body region 110 may contact the high-voltage trap 155, but the drift region 115 may not contact the high-voltage trap 155. The lower surface of the drift region 115 may contact the deep trap 150.

[0136] Reference Figure 6 In some exemplary embodiments of semiconductor devices conceived according to the present invention, the deep well 150 and the high voltage well 155 may not be formed in the substrate 100, but may be formed in the epitaxial layer 101 formed on the substrate 100.

[0137] That is, after the epitaxial layer 101 is formed on the substrate 100, the source region 120, drain region 125, body contact region 122, body region 110, drift region 115, high voltage well 155, deep well 150, pickup contact region 145 and pickup region 140 can be formed in the epitaxial layer 101.

[0138] Epitaxial layer 101 may include, for example, elemental semiconductor materials such as silicon or germanium. Furthermore, epitaxial layer 101 may include, for example, compound semiconductors such as group IV-IV compound semiconductors or group III-V compound semiconductors.

[0139] For example, in the case of a group IV-IV compound semiconductor, the epitaxial layer 101 may be a binary or ternary compound comprising at least two or more of carbon (C), silicon (Si), germanium (Ge) and / or tin (Sn) and / or these compounds doped with group IV elements.

[0140] In the case of III-V compound semiconductors, for example, the epitaxial layer 101 may be a binary, ternary, or quaternary compound formed by combining at least one group III element selected from aluminum (Al), gallium (Ga), and indium (In) with one group V element selected from phosphorus (P), arsenic (As), and antimony (Sb).

[0141] Figure 6 The epitaxial layer 101 is shown as a single layer, but this is provided for illustrative purposes only, and the exemplary embodiments are not limited thereto.

[0142] Reference Figure 7 In some exemplary embodiments of the semiconductor device according to the present invention, the device isolation region 160 may not be formed within the drift region 115.

[0143] The gate electrode 130 may be formed on a portion of the drift region 115 and a portion of the body region 110.

[0144] The drain region 125 can be formed by spatially isolating it from the gate spacer 132, but the embodiments of the present invention are not limited thereto.

[0145] Figure 8 This is a cross-sectional view of a semiconductor device according to some exemplary embodiments of the present invention. For ease of explanation, the following description will be based on... Figure 1 and 3 The differences in descriptions are used to determine the order of things.

[0146] For reference only. Figure 8 The internal equivalent circuit of a semiconductor device is shown.

[0147] Reference Figure 8 In some exemplary embodiments of the semiconductor device according to the present invention, a pickup contact region 145 may be disposed on one side of the gate electrode 130. A source region 120 may be disposed between the pickup contact region 145 and the gate electrode 130.

[0148] The pickup area 140 can be disposed on one side of the gate electrode 130. The pickup area 140 can be formed adjacent to the main body area 110. The main body area 110 can be disposed between the pickup area 140 and the drift area 115.

[0149] exist Figure 8 In this context, the semiconductor device in which the gate electrode 130 is used as the gate can be, for example, a second conductivity type transistor, i.e., an n-type transistor.

[0150] Therefore, the source region 120 and the drain region 125 can be high-concentration impurity regions of the second conductivity type, respectively.

[0151] In addition, the main contact area 122 can be a high-concentration impurity area of ​​the first conductivity type.

[0152] In addition, the main region 110 can be a first conductivity type (e.g., p-type) impurity region, and the drift region 115 can be a second conductivity type impurity region.

[0153] The device isolation region 160 can be formed within the second conductivity type drift region 115.

[0154] A high-voltage trap 155 can be disposed between the drift region 115 and the deep trap 150. The high-voltage trap 155 can isolate the drift region 115 and the deep trap 150 from each other.

[0155] Furthermore, a high-voltage trap 155 may be disposed between the main body region 110 and the deep trap 150. That is, a portion of the high-voltage trap 155 may extend between the main body region 110 and the deep trap 150.

[0156] like Figure 8 As shown, the high-voltage trap 155 can extend completely between the vertical overlap region of the main body region 110 and the deep trap 150. That is, the width of the main body region 110 can be substantially the same as the width of the vertical overlap region of the main body region 110 and the high-voltage trap 155.

[0157] exist Figure 8 In the first conductivity type, the impurity concentration of the main region 110 can be greater than the impurity concentration of the high voltage well 155.

[0158] also, Figure 8 The upper surface of the high-voltage trap 155 is shown to be higher than the lower surface of the pickup area 140, but the embodiments of the present invention are not limited thereto.

[0159] In a semiconductor device according to some exemplary embodiments, the source region 120, the body contact region 122, and the pickup contact region 145 can be connected to a first voltage (V1) (i.e., a node having the same potential). That is, the source region 120, the body contact region 122, and the pickup contact region 145 can be connected to a node having the same potential.

[0160] exist Figure 8 In this configuration, the drain region 125 can be connected to a second voltage (V2) that is different from the first voltage (V1).

[0161] include Figure 8 The transistor with gate electrode 130 described in the text can be Figure 2 The second transistor (M2). Figure 2 The second transistor (M2) is shown to be a p-type transistor. However, the following reference... Figure 2 and 8 The second transistor (M2) described is assumed to be an n-type transistor.

[0162] Reference Figure 2 and 8 The source region 120 and the body contact region 122 of the second transistor (M2) can be connected to the first node (N1). That is, the first voltage (V1) connected to the source region 120 and the body contact region 122 can be the voltage of the first node (N1).

[0163] The drain region 125 of the second transistor (M2) can be connected to the second node (N2). That is, the second voltage (V2) connected to the drain region 125 can be the voltage of the second node (N2).

[0164] In other words, the first terminal (e.g., the body contact region 122) of the second transistor (M2) can be connected to the voltage of the first node (N1) (i.e., the first voltage (V1)), and the second terminal (e.g., the drain region 125) of the second transistor (M2) can be connected to the voltage of the second node (N2) (i.e., the second voltage (V2)).

[0165] The parasitic bipolar transistor (Q1) may include a deep well 150 (n-type impurity region), a high-voltage well 155 (p-type impurity region) on the deep well 150, a body region 110 (p-type impurity region) on the deep well 150, and a substrate 100 (p-type substrate) on the lower portion of the deep well 150.

[0166] The emitter terminal of the parasitic bipolar transistor (Q1) can be a third node (N3) where the high-voltage well 155 and the body region 110 are located. The base terminal of the parasitic bipolar transistor (Q1) can be a deep well 150. Furthermore, the collector terminal of the parasitic bipolar transistor (Q1) can be a substrate 100.

[0167] Substrate leakage current (I) psub The current can flow towards the substrate 100 through the collector of the parasitic bipolar transistor (Q1). It can also flow towards the output voltage terminal (V). out ) guided output current (I out This may include the current flowing through a first diode (D1) formed between the drift region 115 and the main region 110, and the current flowing through a second diode (D2) formed between the high voltage trap 155 and the drift region 115.

[0168] The deep well 150 (which is the base terminal of the parasitic bipolar transistor (Q1)) can be connected to the first node (N1) via the pick-up contact area 145 and the pick-up area 140.

[0169] Since pickup contact 145 and pickup region 140 are impurity regions of the second conductivity type, the voltage drop of pickup contact 145 and pickup region 140 can be relatively small. That is, the voltage of deep well 150 (which is the base terminal of parasitic bipolar transistor (Q1)) can be similar to the voltage of the first node (N1).

[0170] Therefore, the voltage difference between the emitter terminal (N3) and the base terminal (N4) of the parasitic bipolar transistor (Q1) can be essentially zero.

[0171] When there is no voltage difference between the emitter terminal (N3) and the base terminal (N4) of the parasitic bipolar transistor (Q1), the parasitic bipolar transistor (Q1) can be inactive.

[0172] Therefore, the substrate leakage current (I) flowing towards the substrate 100 through the collector of the parasitic bipolar transistor (Q1) psub It can be essentially zero or close to zero.

[0173] Figure 9-12 This is a cross-sectional view of a semiconductor device according to some exemplary embodiments of the present invention. For ease of explanation, the above-mentioned references will be mainly described below. Figure 8 There are no discrepancies described.

[0174] Reference Figure 9 In some exemplary embodiments of the semiconductor device conceived according to the present invention, the body contact region 122 and the pickup contact region 145 may be connected to a first voltage (V1), and the source region 120 may be connected to a third voltage (V3), which is different from the first voltage (V1) and the second voltage (V2).

[0175] In other words, source region 120 can be accessed through, except... Figure 2 The nodes (not shown) other than the first node (N1) are connected to the third voltage (V3).

[0176] Reference Figure 10 In some exemplary embodiments of the semiconductor device conceived according to the present invention, the high voltage trap 155 may vertically overlap a portion of the body region 110.

[0177] The high-voltage trap 155 may be located on a portion between the main body region 110 and the deep trap 150, but may not be located on the other portion between the main body region 110 and the deep trap 150.

[0178] That is, the width of the main body region 110 can be greater than the width of the vertical overlap between the main body region 110 and the high voltage trap 155.

[0179] In other words, the lower surface of the main body region 110 may include a first portion and a second portion. The high voltage trap 155 may be disposed between the first portion of the lower surface of the main body region 110 and the deep trap 150, but may not be disposed between the second portion of the lower surface of the main body region 110 and the deep trap 150.

[0180] Reference Figure 11 In some exemplary embodiments of the semiconductor device according to the present invention, the high voltage well 155 may be disposed between the drift region 115 and the deep well 150, but may not be disposed between the main region 110 and the deep well 150.

[0181] The drift region 115 may contact the high-voltage trap 155, but the main body region 110 may not contact the high-voltage trap 155. The lower surface of the main body region 110 may contact the deep trap 150.

[0182] Reference Figure 12 In some exemplary embodiments of the semiconductor device according to the present invention, the device isolation region 160 may not be formed within the drift region 115.

[0183] The gate electrode 130 may be formed on a portion of the drift region 115 of the second conductivity type and a portion of the body region 110 of the first conductivity type.

[0184] The drain region 125 of the second conductivity type can be spatially separated from the gate spacer 132, but is not limited thereto.

[0185] Reference Figures 1 to 12 The semiconductor device according to some exemplary embodiments of the present invention is described using a p-type substrate 100. However, the semiconductor device can be implemented using an n-type substrate.

[0186] When using an n-type substrate, the deep well 150 can be formed as a p-type impurity region, the high voltage well 155 can be formed as an n-type impurity region, and the pickup region 140 and the pickup contact region 145 can be formed as p-type impurity regions respectively.

[0187] Furthermore, based on the above description, it will be understood which terminal of each of the n-type and p-type transistors should be connected to the pickup contact area when using an n-type substrate.

[0188] In the following text, reference will be made to Figures 13 to 16 Methods for manufacturing semiconductor devices according to some exemplary embodiments of the present invention are described.

[0189] Figures 13 to 16 This is a view illustrating intermediate stages of manufacturing, showing a method for manufacturing a semiconductor device according to some exemplary embodiments of the concept according to the present invention. For reference, regarding... Figure 1The described semiconductor device can be based on Figures 13 to 16 It is manufactured using this method.

[0190] Reference Figure 13 The n-type deep well 150 can be formed within the p-type substrate 100.

[0191] Specifically, a mask pattern defining the region where the deep well 150 will be formed can be formed on a p-type substrate 100, and an n-type impurity can be implanted into the substrate 100. After the n-type impurity is implanted, the mask pattern can be removed.

[0192] Subsequently, a p-type high-voltage well 155 can be formed within the substrate 100. The high-voltage well 155 can be formed, for example, by implanting p-type impurities into the region forming the deep well 150, but embodiments of the present invention are not limited thereto.

[0193] After a mask pattern defining the region where the high-voltage well 155 will be formed is formed on a p-type substrate 100, p-type impurities can be implanted into the substrate 100. After the p-type impurities are implanted, the mask pattern can be removed.

[0194] Although the upper surface of the high-voltage trap 155 and the upper surface of the deep trap 150 may be in the same plane, this is provided only for illustrative purposes, and the exemplary embodiments are not limited thereto.

[0195] Since the high voltage well 155 and the deep well 150 can be formed within the substrate 100, the p-type substrate 100 can be retained on the upper surface of the high voltage well 155 and on the deep well 150.

[0196] Reference Figure 14 The p-type drift region 115 can be formed on the high voltage trap 155.

[0197] After a mask pattern defining the area where the p-type drift region 115 will be formed is formed, p-type impurities can be implanted into the substrate 100. After the p-type impurities are implanted, the mask pattern can be removed.

[0198] The n-type body region 110 can be formed on the high-voltage well 155, and the n-type pickup region 140 can be formed on the deep well 150. The body region 110 and the pickup region 140 can be formed by the same impurity implantation process.

[0199] After a mask pattern defining the areas forming the main region 110 and the pickup region 140 is formed, an n-type impurity can be implanted into the substrate 100. After the n-type impurity is implanted, the mask pattern can be removed.

[0200] Either the drift region 115 or the main region 110 can be formed first.

[0201] Reference Figure 15 The device isolation region 160 can be formed within the drift region 115.

[0202] Device isolation region 160 can be formed using STI, but the embodiments of the present invention are not limited thereto. Therefore, in other embodiments of the present invention, device isolation region 160 can be formed using LOCOS.

[0203] The gate insulating film 135 and the gate electrode 130 may be formed across a portion of the drift region 115 and a portion of the body region 110.

[0204] The gate electrode 130 of the overlapping drift region 115 may overlap a portion of the device isolation region 160.

[0205] Reference Figure 16 The drain region 125 can be formed within the drift region 115, and the source region 120 can be formed within the main region 110.

[0206] In addition, the pickup contact area 145 can be formed within the pickup area 140, and the main contact area 122 can be formed within the main area 110.

[0207] Although not in Figure 2 As shown, however, a contact connecting the drain region 125 and the pickup contact region 145 to the first voltage (V1) can be formed, and a contact connecting the source region 120 and the body contact region 122 to the second voltage (V2) can be formed.

[0208] In summary, those skilled in the art will understand that many variations and modifications can be made to the preferred embodiments without substantially departing from the principles of the inventive concept. Therefore, the preferred embodiments disclosed herein are used only in a general and descriptive sense and not for limiting purposes.

[0209] This application claims priority to Korean Patent Application No. 10-2016-0081317, filed on June 29, 2016, with the Korean Intellectual Property Office, the contents of which are incorporated herein by reference in their entirety.

Claims

1. A semiconductor device, comprising: Substrate of the first conductivity type; Gate electrode on the substrate; A first high-concentration impurity region of the first conductivity type on the first side of the gate electrode; The first well of the first conductivity type is located below and around the first high-concentration impurity region; A second well of a second conductivity type overlaps a portion of the gate electrode and is adjacent to the first well; as well as The first deep well of the second conductivity type, below the first well and the second well, the first deep well and the first high-concentration impurity region respond to the first voltage.

2. The semiconductor device of claim 1, further comprising a second deep well of a first conductivity type between the first well and the first deep well and between the second well and the first deep well.

3. The semiconductor device of claim 2, wherein the second deep well vertically overlaps a portion of the first well.

4. The semiconductor device of claim 2, further comprising a second high-concentration impurity region of the second conductivity type on the first side of the gate electrode. The second high-concentration impurity region is not located within the first trap, and The first deep well is connected to the first voltage through the second high-concentration impurity region.

5. The semiconductor device of claim 1, further comprising a second high-concentration impurity region of the first conductivity type and a third high-concentration impurity region of the first conductivity type on the second side of the gate electrode. The second high-concentration impurity region and the third high-concentration impurity region are located within the second trap.

6. The semiconductor device of claim 5, further comprising a device isolation region within the first well between the first high-concentration impurity region and the gate electrode. The gate electrode extends along a portion of the upper surface of the isolation region of the device.

7. The semiconductor device of claim 5, wherein the first high-concentration impurity region and the second high-concentration impurity region are p-type regions, and The first high-concentration impurity region is the drain region, and the second high-concentration impurity region is the source region.

8. The semiconductor device according to claim 1, further comprising: The second high-concentration impurity region of the second conductivity type is located within the first well between the gate electrode and the first high-concentration impurity region. and The third high-concentration impurity region of the second conductivity type is located on the second side of the gate electrode within the second well.

9. The semiconductor device of claim 8, further comprising a device isolation region within the second well between the third high-concentration impurity region and the gate electrode. The gate electrode extends along a portion of the upper surface of the isolation region of the device.

10. The semiconductor device of claim 8, wherein the second high-concentration impurity region and the third high-concentration impurity region are n-type regions, and The second high-concentration impurity region is the source region, and the third high-concentration impurity region is the drain region.

11. The semiconductor device of claim 8, wherein the second high-concentration impurity region responds to the first voltage.

12. A semiconductor device, comprising: Substrate of the first conductivity type; Gate electrode on the substrate; A first high-concentration impurity region of the first conductivity type on the first side of the gate electrode; The first well of the first conductivity type is located below and around the first high-concentration impurity region; A second high-concentration impurity region of a second conductivity type on the second side of the gate electrode; The second well of the second conductivity type is located below and around the second high-concentration impurity region; The first deep well of the first conductivity type is below the second well; and The second deep well of the second conductivity type is disposed below the first deep well across the first and second wells, wherein the second deep well and the first high-concentration impurity region are responsive to the first voltage.

13. The semiconductor device of claim 12, wherein a portion of the first deep well extends between the first deep well and the second deep well.

14. The semiconductor device of claim 12, further comprising a third high-concentration impurity region of the first conductivity type within the second well between the gate electrode and the second high-concentration impurity region. The first high-concentration impurity region is the drain region, and the third high-concentration impurity region is the source region.

15. The semiconductor device of claim 12, further comprising a third high-concentration impurity region of the second conductivity type within the first well between the gate electrode and the first high-concentration impurity region. The second high-concentration impurity region is the source region, and the third high-concentration impurity region is the drain region.

16. A semiconductor device, comprising: A substrate of a second conductivity type includes a first deep well of a first conductivity type and a second deep well of a second conductivity type on the first deep well; as well as A transistor, formed on the substrate, includes a gate electrode, a first terminal responsive to a first voltage, and a second terminal responsive to a second voltage different from the first voltage. The first deep well responds to the first voltage.

17. The semiconductor device of claim 16, wherein the transistor comprises: The drift region of the first conductivity type is located on the second deep well; The body region of the second conductivity type is located on the second deep well and adjacent to the drift region; The drain region of the first conductivity type is located within the drift region on the first side of the gate electrode; The source region of the first conductivity type is located within the body region on the second side of the gate electrode; as well as The second type of conductive body contact region is located within the body region and adjacent to the source region. The drain region is connected to the first voltage, and the source region is connected to the second voltage.

18. The semiconductor device of claim 17, wherein the transistor is a p-type transistor.

19. The semiconductor device of claim 16, wherein the transistor comprises: The main region of the first conductivity type is located on the second deep well; The drift region of the second conductivity type is located on the second deep well and adjacent to the main body region; The source region of the second conductivity type is located on the first side of the gate electrode and within the body region; The main contact region of the first conductivity type is adjacent to the source region and is located within the main region; as well as The drain region of the second conductivity type is located on the second side of the gate electrode and within the drift region. The main contact area is connected to the first voltage, and the drain area is connected to the second voltage.

20. The semiconductor device of claim 19, wherein the transistor is an n-type transistor.

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