Semiconductor device and manufacturing method thereof, electronic equipment and vehicle

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, electronic equipment and a vehicle. The semiconductor device comprises a base body and a first electrode arranged on the lower surface of the base body, and the base body is provided with an active area and a terminal protection area which are adjacent in the direction perpendicular to the thickness direction of the base body; the terminal protection area surrounds the active area; the substrate has a first conductive type; the base body comprises a voltage division protection structure which is located in the terminal protection region, has a second conduction type and is used for forming a first depletion region with the base body; the cut-off structure is located in the terminal protection area and surrounds the voltage division protection structure; the cut-off structure forms a second depletion region; when the first electrode receives reverse high voltage, a second depletion region formed by the cut-off structure is communicated with the first depletion region, voltage division is performed on the active region, and the first depletion region is cut off. According to the scheme, the voltage withstanding characteristic of the semiconductor device is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a semiconductor device and its manufacturing method, electronic equipment, and vehicle. Background Technology

[0002] Semiconductor devices, as core components of modern electronic systems, are widely used in power electronics, communications, computing, and other fields. Among them, high-voltage power semiconductor devices, such as insulated-gate bipolar transistors (IGBTs) and vertical double-diffused MOSFETs (VDMOS), have become key components in new energy power generation, electric vehicles, and industrial frequency conversion due to their high voltage withstand and high current characteristics. Both IGBTs and VDMOS consist of thousands of cells connected in parallel. The high voltage between the outermost cells and the substrate makes them prone to breakdown. Therefore, it is necessary to design termination protection structures to improve the voltage withstand capability of semiconductor devices and prevent breakdown.

[0003] Currently, the common terminal structures are field limiting rings and field plate structures. However, due to the influence of design size and manufacturing process, it is still impossible to significantly improve the voltage withstand characteristics of semiconductor devices. Summary of the Invention

[0004] This application provides a semiconductor device and its manufacturing method, an electronic device, and a vehicle, to improve the voltage withstand characteristics of the semiconductor device.

[0005] In a first aspect, embodiments of this application provide a semiconductor device, comprising: a substrate, and a first electrode disposed on the lower surface of the substrate, the substrate having an active region and a terminal protection region adjacent to each other along a direction perpendicular to the thickness of the substrate; the terminal protection region surrounding the active region; the substrate having a first conductivity type; the substrate comprising: a voltage divider protection structure located in the terminal protection region, having a second conductivity type, for forming a first depletion region with the substrate; a cutoff structure located in the terminal protection region, surrounding the voltage divider protection structure; the cutoff structure forming a second depletion region; when the first electrode receives a reverse high voltage, the second depletion region formed by the cutoff structure connects to the first depletion region, performs voltage division on the active region, and cuts off the first depletion region.

[0006] In one possible implementation, the cutoff structure includes a plurality of first conductivity type cutoff rings and a plurality of second conductivity type cutoff rings; the plurality of first conductivity type cutoff rings and the plurality of second conductivity type cutoff rings are alternately arranged; the plurality of first conductivity type cutoff rings and the plurality of second conductivity type cutoff rings form the second depletion region.

[0007] In one possible implementation, the doping concentration of the first conductivity type ion in the first conductivity type cutoff ring is higher than the doping concentration of the second conductivity type ion in the second conductivity type cutoff ring.

[0008] In one possible implementation, a plurality of first conductivity type cutoff rings and a plurality of second conductivity type cutoff rings are alternately arranged along the thickness direction of the substrate.

[0009] In one possible implementation, a plurality of first conductivity type cutoff rings and a plurality of second conductivity type cutoff rings are alternately arranged in a direction perpendicular to the thickness of the substrate.

[0010] In one possible implementation, the voltage divider protection structure includes multiple field limiting rings; the multiple field limiting rings have a second conductivity type and form a first depletion region between themselves and the substrate.

[0011] In one possible implementation, the field limiting ring closest to the active region among the multiple field limiting rings has a wider width than the other field limiting rings; the other field limiting rings have equal widths.

[0012] In one possible implementation, the concentrations of second conductivity type ions doped in the multiple field-limiting rings are equal.

[0013] In one possible implementation, the spacing between the multiple field limiting rings is equal.

[0014] In one possible implementation, the spacing between the multiple field limiting loops increases sequentially along the direction from the active region to the terminal protection zone.

[0015] In one possible implementation, the substrate further includes: at least one isolation structure; at least one isolation structure located in a terminal protection zone, surrounding the cut-off structure, for suppressing the diffusion of impurity ions from the outside of the edge into the interior of the semiconductor device.

[0016] In one possible implementation, the partition structure is filled with a filler material, which is one of the following: metal, silicon oxide, and a combination of silicon oxide and polycrystalline silicon.

[0017] In one possible implementation, the partition structure extends along the thickness direction of the substrate.

[0018] In one possible implementation, the width of the partition structure at the end near the upper surface of the substrate is smaller than the width at the end near the lower surface of the substrate.

[0019] In one possible implementation, the substrate further includes: a gate layer and a well region; the well region is located in the active region, extends in a direction perpendicular to the thickness of the substrate, and is connected to a terminal protection zone; the well region has a first conductivity type; the gate layer is located in the well region and extends through the well region in the thickness direction of the substrate.

[0020] In one possible implementation, when the voltage divider protection structure is located at the boundary between the terminal protection zone and the active zone, the trap region is in contact with the voltage divider protection structure.

[0021] In one possible implementation, the substrate further includes an emitter layer; the emitter layer is disposed on both sides of the gate layer, and the emitter layer has a first conductivity type.

[0022] In one possible implementation, the semiconductor device further includes: a first metal field plate, a plurality of second metal field plates, and a third metal field plate; the first metal field plate, the plurality of second metal field plates, and the third metal field plate are all disposed on the upper surface of the substrate; the first metal field plate is disposed on the active region of the substrate; the plurality of second metal field plates correspond one-to-one with the plurality of field limiting rings and are disposed on the corresponding field limiting rings; the third metal field plate corresponds one-to-one with the isolation structure and is disposed on the corresponding isolation structure.

[0023] In one possible implementation, the semiconductor device further includes: a dielectric layer and a plurality of contact holes; the dielectric layer is disposed on the upper surface of the substrate; the plurality of contact holes are formed on the dielectric layer and filled with metal; the plurality of contact holes include contact holes corresponding to a plurality of field limiting rings, contact holes corresponding to the emitter layer and contact holes corresponding to the isolation structure, and extend into the plurality of field limiting rings, the emitter layer and the isolation structure, so that the substrate is connected to the metal field plate through the contact holes.

[0024] In one possible implementation, the semiconductor device further includes: a collector layer; the collector layer is disposed on the lower surface of the substrate, and a first electrode covers the collector layer.

[0025] Secondly, embodiments of this application provide a method for fabricating a semiconductor device, comprising: providing a substrate having an active region and a terminal protection region adjacent to each other along a direction perpendicular to the thickness of the substrate; the terminal protection region surrounding the active region; the substrate having a first conductivity type; forming a voltage divider protection structure and a cutoff structure within the substrate, the voltage divider protection structure being located within the terminal protection region, having a second conductivity type, and forming a first depletion region with the substrate; the cutoff structure being located within the terminal protection region and surrounding the voltage divider protection structure; the cutoff structure forming a second depletion region; forming a first electrode located on the lower surface of the substrate; when the first electrode receives a reverse high voltage, the second depletion region formed by the cutoff structure connects to the first depletion region, performing voltage division on the active region and cutting off the first depletion region.

[0026] In one possible implementation, forming a voltage divider protection structure within a matrix includes: defining a plurality of first regions within a terminal protection zone; filling the plurality of first regions with first dopant ions to obtain a plurality of field-limiting rings; the voltage divider protection structure includes the plurality of field-limiting rings; and the first dopant ions have a second conductivity type.

[0027] In one possible implementation, forming a cutoff structure within the substrate includes: forming a plurality of alternating first conductivity type cutoff rings and a plurality of second conductivity type cutoff rings within a terminal protection zone; the cutoff structure includes a plurality of alternating first conductivity type cutoff rings and a plurality of second conductivity type cutoff rings.

[0028] In one possible implementation, within the terminal protection zone, a plurality of alternating first conductivity type cutoff rings and a plurality of second conductivity type cutoff rings are formed, including: within the terminal protection zone, a plurality of alternating first conductivity type cutoff rings and a plurality of second conductivity type cutoff rings are formed along the direction of substrate thickness; or, within the terminal protection zone, a plurality of alternating first conductivity type cutoff rings and a plurality of second conductivity type cutoff rings are formed along a direction perpendicular to the substrate thickness.

[0029] In one possible implementation, the method further includes: forming at least one isolation structure within a terminal protection zone; the at least one isolation structure surrounds a cutoff structure for suppressing the diffusion of external impurity ions into the semiconductor device.

[0030] In one possible implementation, at least one partition structure is formed on the substrate of the terminal protection zone, comprising: surrounding the voltage divider protection structure within the terminal protection zone to form at least one first groove; filling the at least one first groove with a filler to form at least one partition structure; the filler being one of the following: metal, silicon oxide, and a combination of silicon oxide and polysilicon.

[0031] In one possible implementation, the method further includes: forming a well region within an active region; the well region extending perpendicular to the thickness of the substrate and connecting to a terminal protection zone; forming a second groove penetrating the well region along the thickness direction of the substrate within the well region; and filling the second groove with an oxide layer and polysilicon to form a gate layer.

[0032] In one possible implementation, the method further includes: forming an emitter layer on both sides of the gate layer; the emitter layer having a first conductivity type.

[0033] In one possible implementation, before forming the pressure divider protection structure, the method further includes filling the upper surface of the substrate with a dielectric layer.

[0034] In one possible implementation, the method further includes: forming a plurality of through holes in the dielectric layer; the plurality of through holes correspond one-to-one with a plurality of field limiting rings, an emission layer, and a blocking structure, and extend into the interior of the plurality of field limiting rings, an emission layer, and a blocking structure; filling the through holes with metal to form contact holes.

[0035] In one possible implementation, after forming the contact hole, the process includes: depositing front metal on top of the dielectric layer to form multiple metal field plates; the multiple metal field plates correspond one-to-one with the active region, multiple field limiting rings, and isolation structures.

[0036] In one possible implementation, the method further includes: filling a lower surface of a substrate with fourth doped ions to form a collector layer; the fourth doped ions having a second conductivity type; and a first electrode covering the collector layer.

[0037] Thirdly, embodiments of this application provide an electronic device, including the semiconductor device described above.

[0038] Fourthly, embodiments of this application provide a vehicle including the semiconductor device or the electronic device described above.

[0039] In the semiconductor device, its fabrication method, electronic device, and vehicle provided in this application embodiment, the semiconductor device includes a substrate and a first electrode disposed on the lower surface of the substrate. The substrate has an active region and a terminal protection region adjacent to each other along the direction perpendicular to the thickness of the substrate; the terminal protection region surrounds the active region; the substrate has a first conductivity type; the substrate includes a voltage divider protection structure located in the terminal protection region, having a second conductivity type, used to form a first depletion region with the substrate; the voltage divider protection structure and the substrate have different conductivity types, forming the first depletion region, which can achieve voltage division of the active region, preventing the electric field strength at a certain point in the substrate from being too strong and causing overvoltage breakdown. A cutoff structure is disposed in the terminal protection region surrounding the voltage divider protection structure; the cutoff structure itself can form a second depletion region, the second depletion region has a large range and a large electric field strength; when the first electrode receives a reverse high voltage, the second depletion region formed by the cutoff structure will connect with the first depletion region, further dividing the voltage of the active region, making the electric field distribution of the semiconductor device more uniform, and cutting off the first depletion region, thereby improving the withstand voltage characteristics and reliability of the semiconductor device. Attached Figure Description

[0040] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0041] Figure 1 A cross-sectional view of an example semiconductor device;

[0042] Figure 2 This is a cross-sectional view of a semiconductor device as an example of this application;

[0043] Figure 3 This is a cross-sectional view of a semiconductor device, another example of this application;

[0044] Figure 4An interface diagram of a semiconductor device, which is yet another example of this application;

[0045] Figure 5 A cross-sectional view of a semiconductor device, which is yet another example of this application;

[0046] Figure 6 A cross-sectional view of a semiconductor device, which is yet another example of this application;

[0047] Figure 7 A cross-sectional view of a semiconductor device, which is yet another example of this application;

[0048] Figure 8 An exemplary flowchart of a method for fabricating a semiconductor device is shown.

[0049] Figure 9 This is a cross-sectional view of the substrate of an example semiconductor device according to this application;

[0050] Figure 10 This is a cross-sectional view of an example of this application after a dielectric layer and a field confinement ring have been formed on the substrate;

[0051] Figure 11 A cross-sectional view of the substrate after forming the third, fourth and fifth grooves as an example of this application;

[0052] Figure 12 This is a cross-sectional view of an example of this application after the gate layer has been generated;

[0053] Figure 13 This is a cross-sectional view of an example of the formation of the trap region and the emitter layer in this application;

[0054] Figure 14 This is a cross-sectional view of an example of this application after a dielectric layer is deposited in the active region and a via is formed;

[0055] Figure 15 This is a cross-sectional view of an example of the formed cut-off structure in this application;

[0056] Figure 16 This is a cross-sectional view of an example of the partition structure and metal field plate formed according to this application;

[0057] Figure 17 This is a cross-sectional view of a fabricated semiconductor device as an example of this application.

[0058] Explanation of reference numerals in the attached figures:

[0059] 1-Collector layer; 2-Substrate; 3-Stop ring; 4-Stop structure; 5-Field limiting ring; 6a-First conductivity type stop ring; 6b-Second conductivity type stop ring; 7-Gate layer; 8-Silicon oxide; 9-Polysilicon; 10-Trap region; 11-Emitter layer; 12-Dielectric layer; 13-Contact hole; 14-First metal field plate; 15-Second metal field plate; 16-Third metal field plate; 17-First electrode; 18-Isolation structure; 19-Third groove; 20-Fourth groove; 21-Fifth groove; 22-Through hole. Detailed Implementation

[0060] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0061] High-voltage power semiconductor devices, such as insulated-gate bipolar transistors (IGBTs) and vertically diffused metal-oxide-semiconductor field-effect transistors (VDMOS), are composed of thousands of cells connected in parallel. The surface potentials of these cells are essentially the same, so there is no breakdown problem between individual cells. However, the outermost cells of the chip have a high voltage relative to the substrate, making them the most vulnerable area for breakdown. To ensure the breakdown characteristics and reliability of power chips, termination structures are typically included in the design of power devices to reduce the electric field at the semiconductor edges and surfaces, thereby reducing leakage current and improving device stability. Currently, common termination protection technologies include: field limiting rings (FLRs), metal field plates (MFPs), semi-insulating polycrystalline silicon field plates (SIPOS FLs), metal field plates & field limiting rings (FR & FLRs), junction termination extension (JTEs), variation of lateral doping (VLDs), and bevel terminations.

[0062] The field-limiting ring (FLR), also known as a field ring or floating field ring, is a common termination structure used in high-voltage power semiconductor devices. The characteristics of a field-limiting ring termination are as follows: there is a certain distance between the ring junction (the PN junction formed between the field-limiting ring other than the one closest to the active region and the substrate) and the main junction (the PN junction formed between the field-limiting ring closest to the active region and the substrate), and the doping type and junction depth are consistent with the main junction. In the design of field-limiting ring terminations, the ring width, ring spacing, and number of rings are key areas for optimization. When the main junction voltage is low, the depletion region has not yet reached the ring junction, and the ring junction cannot bear the voltage division; when the main junction voltage is high, the depletion regions of the main junction and the ring junction are connected, and the ring junction will bear a portion of the main junction voltage, alleviating the electric field concentration at the edge of the main junction, thereby improving the breakdown voltage of the semiconductor device. Generally, with a well-designed field-limiting ring termination, both the main junction and the ring junction will simultaneously reach the critical breakdown electric field strength, thus obtaining a suitable breakdown voltage.

[0063] Traditional field-limiting ring termination structures are highly sensitive to charge density at the silicon-oxide interface. When the interface charge density is too high, the electric field distribution at the interface becomes uneven, easily accumulating a large electric field and causing surface breakdown of the semiconductor device in the termination region. To mitigate this breakdown effect, field-limiting ring terminations are rarely used alone anymore; field-ring and field-plate terminations with field plates attached to the field-limiting ring structure have become the mainstream.

[0064] Figure 1 This is a cross-sectional view of an example semiconductor device. The structure includes a substrate 2, a collector layer 1, a first electrode 17, a gate layer 7 (filled with an oxide layer 8 and deposited polysilicon 9), a first metal field plate 14, multiple second metal field plates 15, a third metal field plate 16, an emitter layer 11, a well region 10, a cutoff ring 3, a dielectric layer 12, a contact hole 13, and multiple non-contacting field-limiting rings 5 ​​arranged adjacent to each other at a specified distance. For each field-limiting ring 5, when the semiconductor device operates under voltage, the field-limiting ring 5 will be depleted sequentially along the direction from the active region of the device to the terminal protection region of the device, and the depletion regions formed will also be connected sequentially. The higher the voltage required for the semiconductor device, the more field-limiting rings and field plates are required.

[0065] If a field ring / field plate termination is used as the withstand voltage protection structure, its withstand voltage reliability is more susceptible to fluctuations in design dimensions and manufacturing processes. Furthermore, under high temperature, high humidity, and high pressure conditions, moisture diffuses into the device and decomposes into charged ions, leading to electrochemical corrosion of the termination and performance degradation. To ensure the withstand voltage characteristics of semiconductor devices, this type of termination is also very large, resulting in an increase in the overall chip area.

[0066] In the semiconductor device, its fabrication method, electronic device, and vehicle provided in this application embodiment, the semiconductor device includes a substrate and a first electrode disposed on the lower surface of the substrate. The substrate has an active region and a terminal protection region adjacent to each other along the direction perpendicular to the thickness of the substrate. The terminal protection region surrounds the active region. The substrate has a first conductivity type. The substrate includes a voltage divider protection structure located in the terminal protection region, having a second conductivity type, used to form a first depletion region with the substrate. The voltage divider protection structure and the substrate have different conductivity types, forming a depletion region, which can divide the voltage in the active region, preventing the electric field from concentrating at a certain point and causing overvoltage breakdown. Further, a cutoff structure is provided in the terminal protection region, surrounding the voltage divider protection structure. By designing the isolation structure, the isolation structure itself forms a second depletion region, which has a large range. When the first electrode receives a reverse high voltage, the second depletion region formed by the cutoff structure will connect with the first depletion region, further dividing the voltage in the active region, making the electric field distribution of the semiconductor device more uniform, and cutting off the first depletion region, thereby improving the withstand voltage characteristics and reliability of the semiconductor device.

[0067] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0068] Example 1

[0069] This application provides a semiconductor device; Figure 2 This is a cross-sectional view of an example semiconductor device of this application; as shown Figure 2 As shown, the semiconductor device includes: a substrate 2, and a first electrode 17 disposed on the lower surface of the substrate 2. The substrate 2 has an active region and a terminal protection region adjacent to each other along the direction perpendicular to the thickness of the substrate; the terminal protection region is disposed surrounding the active region; the substrate 2 has a first conductivity type.

[0070] Matrix 2 includes:

[0071] The voltage divider protection structure, located in the terminal protection zone, has a second conductivity type and is used to form a first depletion region with the substrate 2;

[0072] Cut-off structure 4 is located in the terminal protection zone and surrounds the voltage divider protection structure; the cut-off structure forms a second depletion region; when the first electrode receives reverse high voltage, the second depletion region formed by the cut-off structure connects to the first depletion region, divides the voltage in the active region, and cuts off the first depletion region.

[0073] For example, the semiconductor device can be an insulated gate bipolar transistor (IGBT) and a vertically diffused metal-oxide-semiconductor field-effect transistor (VDMOS); the semiconductor device includes a substrate 2 and a first electrode 17 disposed on the lower surface of the substrate 2; the substrate 2 has an active region and a termination protection region adjacent to each other along the direction perpendicular to the thickness of the substrate; wherein the active region is the core region of the semiconductor device; the termination protection region is a protective structure formed on the periphery of the semiconductor device; Figure 2 In the diagram, the y-direction is along the substrate thickness; the x-direction is perpendicular to the substrate thickness. The terminal protection zone surrounds the active region. In practical applications, the range of the active region and the terminal protection zone can be limited according to the specific application scenario. The substrate 2 has a first conductivity type; the voltage divider protection structure is located within the terminal protection zone and has a second conductivity type. For example, the first conductivity type is N-type and the second conductivity type is P-type; in this case, a first depletion region can be formed between the voltage divider protection structure and the substrate; based on the first depletion region, voltage division can be achieved in the active region of the semiconductor device, improving the withstand voltage characteristics of the semiconductor device. Furthermore, the substrate 2 also includes a cutoff structure, which is located in the terminal protection zone and surrounds the voltage divider protection structure; the cutoff structure 4 itself can form a second depletion region, and the electric field strength of the second depletion region is relatively large. When the first electrode 17 receives a reverse high voltage, the second depletion region formed by the cutoff structure 4 connects to the first depletion region, performing voltage division in the active region and cutting off the first depletion region. For example, the cutoff structure 4 itself can form a PN junction, thereby forming a second depletion region. When the first electrode located on the lower surface of the substrate receives a reverse high voltage, the first depletion region will expand as the external voltage increases. Subsequently, the second depletion region and the first depletion region are connected. The first depletion region is formed after the PN junction is generated when the voltage divider protection structure contacts the substrate. For example, when a P-type semiconductor contacts an N-type semiconductor, free electrons in the N-type semiconductor will move to the P-type semiconductor to recombine, generating a built-in electric field inside the PN junction. After a reverse high voltage is applied, the external voltage will accelerate the recombination of free electrons and holes to form a region with only positive charges, which is the depletion region. As the applied reverse voltage increases, the depletion region becomes larger. After the first and second depletion regions are connected, a voltage divider is achieved in the active region, making the electric field intensity distribution more uniform and improving the withstand voltage characteristics and reliability of the semiconductor device. At the same time, the cutoff structure can stop the first depletion region from continuing to expand, preventing the depletion region from reaching the edge of the semiconductor device and causing leakage current; thus improving the reliability of the semiconductor device.

[0074] Reference Figure 2 The cutoff structure 4 includes multiple first conductivity type cutoff rings 6a and multiple second conductivity type cutoff rings 6b; the multiple first conductivity type cutoff rings 6a and multiple second conductivity type cutoff rings 6b are alternately arranged; the multiple first conductivity type cutoff rings 6a and multiple second conductivity type cutoff rings 6b form a second depletion region.

[0075] Specifically, the cutoff structure 4 includes multiple first conductivity type cutoff rings 6a and multiple second conductivity type cutoff rings 6b. For example, the multiple first conductivity type cutoff rings 6a and multiple second conductivity type cutoff rings 6b are alternately arranged; for instance, the conductivity type of the first conductivity type cutoff rings 6a is N-type, and the conductivity type of the second conductivity type cutoff rings 6b is P-type. These multiple first conductivity type cutoff rings and multiple second conductivity type cutoff rings form a superjunction, which is the cutoff structure 4. The multiple first conductivity type cutoff rings 6a and multiple second conductivity type cutoff rings 6b together form the second depletion region. In this example, the multiple cutoff rings of different conductivity types are alternately arranged, and the cutoff structure itself forms the second depletion region. This achieves effective voltage division of the active region, and the cutoff structure also prevents the first depletion region from continuing to deplete towards the edge, avoiding leakage current in the semiconductor device and further improving the reliability of the semiconductor device.

[0076] Optionally, the concentration of doped ions of the first conductivity type in the first conductivity type cutoff ring 6a is higher than the concentration of doped ions of the second conductivity type in the second conductivity type cutoff ring 6b.

[0077] Specifically, the concentration of doped ions in the first conductivity type cutoff ring 6a is higher than the concentration of doped ions in the second conductivity type cutoff ring 6b. For example, the doped ions in the first conductivity type cutoff ring 6a have a first conductivity type, the same as the conductivity type of the substrate; for example, the first conductivity type is N-type. The doped ions in the second conductivity type cutoff ring 6b have a second conductivity type, for example, P-type. When the semiconductor device is subjected to an external reverse high voltage, the first depletion region formed by the voltage divider protection structure expands. The doped ions in the voltage divider protection structure have a second conductivity type, and the concentration of these second conductivity type ions is relatively high. At this time, after the ions doped in the first conductivity type cutoff ring 6a and the ions doped in the second conductivity type cutoff ring 6b within the cutoff structure are depleted, they will mutually deplete with the second conductivity type doped ions in the voltage divider protection structure. The first depletion region continues to expand within the substrate, preventing leakage current in the semiconductor device and improving its reliability.

[0078] Optionally, multiple first-conductivity type cutoff rings and multiple second-conductivity type cutoff rings are alternately arranged along the thickness direction of the substrate.

[0079] Specifically, refer to Figure 2The multiple first conductivity type stop rings 6a and second conductivity type stop rings 6b of the stop structure 4 are alternately arranged along the thickness direction of the substrate. For example, a groove can be formed in the terminal protection zone, and then dopant ions of the second conductivity type can be deposited starting from the bottom of the groove to form the first second conductivity type stop ring 6b; then, dopant ions of the second conductivity type can be deposited on the first second conductivity type stop ring 6b to form the first first conductivity type stop ring 6a. Repeatedly depositing dopant ions of different conductivity types can form multiple first conductivity type stop rings 6a and multiple second conductivity type stop rings 6b to form the stop structure 4. This application does not specifically limit the order in which the multiple first conductivity type stop rings and the second conductivity type stop rings are generated.

[0080] Optionally, a plurality of first conductivity type cutoff rings 6a and a plurality of second conductivity type cutoff rings 6b are alternately arranged in a direction perpendicular to the thickness of the substrate.

[0081] Figure 3 Here is a cross-sectional view of a semiconductor device as another example of this application; see reference. Figure 3 Multiple first-conductivity type cutoff rings 6a and multiple second-conductivity type cutoff rings 6b can also be alternately arranged along a direction perpendicular to the substrate thickness. For example, in the terminal protection zone, a groove is formed, and dopant ions of the first conductivity type are first deposited at the bottom of the groove. After deposition, the dopant ions of the first conductivity type at the corresponding positions are removed by photolithography. Then, dopant ions of the second conductivity type are deposited at the positions where the dopant ions of the first conductivity type were removed. By repeating this step multiple times, multiple first-conductivity type cutoff rings and multiple second-conductivity type cutoff rings alternately arranged along a direction perpendicular to the substrate thickness can be obtained.

[0082] Optionally, the voltage divider protection structure includes multiple field limiting rings;

[0083] Multiple field-limiting rings 5, having a second conductivity type, form a first depletion region with the substrate 2.

[0084] Specifically, refer to Figure 2 and Figure 3 The voltage divider protection structure includes multiple field-limiting rings 5. The number of field-limiting rings 5 ​​can be specifically set according to actual needs; for example, the appropriate number of cutoff rings can be selected based on the required withstand voltage of the semiconductor device. The multiple field-limiting rings 5 ​​have a second conductivity type, forming a first depletion region between themselves and the substrate 2, which has a first conductivity type. This achieves voltage divider protection for the active region. Each of the multiple field-limiting rings 5 ​​generates a depletion region between itself and the substrate, playing a voltage-dividing role and further preventing overvoltage breakdown of the semiconductor device in the terminal protection zone, thus improving the withstand voltage of the semiconductor device.

[0085] Optionally, the field limiting ring 5 closest to the active region has a wider width than the other field limiting rings; the widths of the other field limiting rings are equal.

[0086] Specifically, among the multiple field limiting rings 5, the field limiting ring closest to the active region has the largest width, exceeding the widths of the other field limiting rings; the widths of the other field limiting rings are equal. The PN junction formed between the field limiting ring closest to the active region and the substrate is the main junction; the PN junctions formed between the other field limiting rings and the substrate are loop junctions.

[0087] Optionally, the concentrations of second conductivity type ions doped in the multiple field-limiting rings 5 ​​are equal.

[0088] Specifically, the ion doping concentrations in the multiple field-limiting rings 5 ​​are equal; the field-limiting rings 5 ​​are doped with doped ions of the second conductivity type; multiple depletion regions are formed between the multiple field-limiting rings 5 ​​and the substrate 2. As the applied reverse voltage increases, the range of the multiple depletion regions will expand, and the multiple depletion regions will connect to form the first depletion region.

[0089] Optionally, the spacing between multiple field limiting rings 5 ​​is equal.

[0090] Specifically, the spacing between multiple field limiting rings 5 ​​can be designed to be equal. In practical applications, designing the spacing between multiple field limiting rings to be equal reduces the difficulty of manufacturing semiconductor devices.

[0091] Optionally, the spacing between the multiple field-limiting rings 5 ​​increases sequentially along the direction from the active region to the terminal protection zone.

[0092] Specifically, the spacing of multiple field limiting rings can be designed to increase sequentially from the active region to the terminal region. When the spacing of the field limiting rings increases sequentially from the active region to the terminal protection zone, the electric field can be more evenly distributed in the terminal region. Smaller spacing near the active region effectively suppresses high electric field peaks at the edge of the active region; as the distance from the active region increases, the electric field strength gradually decreases. Increasing the spacing of the field limiting rings at this point can reduce the number of field limiting rings while maintaining a uniform electric field distribution, thus reducing device complexity and manufacturing costs.

[0093] Optionally, the matrix further includes: at least one partition structure 18;

[0094] At least one isolation structure 18 is located in the terminal protection zone, surrounding the cut-off structure, for suppressing the diffusion of external impurity ions into the semiconductor device.

[0095] Specifically, refer to Figures 2-3The substrate 2 also includes at least one isolation structure 18; wherein, the isolation structure 18 is also located in the terminal protection zone, surrounding the stop structure 4, and the isolation structure 18 is used to suppress the diffusion of external impurity ions into the interior of the semiconductor device. In actual scenarios, when the semiconductor device operates under high temperature, high pressure, and high humidity conditions, if the passivation layer or silicon gel is not dense enough, impurities will enter the material interface from the edge of the device and begin to diffuse laterally. When they diffuse to the vicinity of the terminal, the impurities will ionize into impurity ions under a high electric field, causing electrochemical corrosion to the terminal structure, changing the distribution of the lateral electric field near the terminal, thereby degrading the device's withstand voltage capability.

[0096] Figure 4 An interface diagram of a semiconductor device, as another example of this application; such as Figure 4 As shown, multiple partition structures can also be installed between the voltage divider protection structure and the cutoff structure 4. Figure 4 Taking a barrier structure as an example, the movement path of impurity ions at the edge is blocked by the additional cut-off structure, preventing them from further diffusing into the terminal, thereby improving the reliability of the device. At the same time, the radius of curvature of the electric field gathered at the edge of the terminal increases, making the semiconductor device less prone to breakdown and greatly improving its stability. The barrier structure can effectively prevent ions from water vapor decomposition from entering the interior of the semiconductor device, thus improving the reliability of the semiconductor device.

[0097] In one example, the partition structure 18 is filled with a filler material, which is one of the following: metal, silicon oxide, and a combination of silicon oxide and polycrystalline silicon.

[0098] Reference Figure 2-4 The partition structure 18 can be filled with metal to block the flow path of edge ions at the interface. At the same time, when an external voltage is applied, the partition structure 18 will also generate a certain potential to attract impurity ions after impurity ionization under a high electric field, thereby protecting the terminal structure and maintaining the electric field near the terminal, thus improving the reliability of the device.

[0099] Figure 5 This is a cross-sectional view of another example of a semiconductor device in this application; see reference. Figure 5 The partition structure 18 can be filled with an oxide layer; this eliminates the need for an additional filling process, requiring only oxygenation in a high-temperature environment; and the oxide layer in the filling field is simpler than that in the filling metal, saving costs while preventing the lateral diffusion of impurities.

[0100] Figure 6 This is a cross-sectional view of another example of a semiconductor device in this application; see reference. Figure 6The partition structure 18 can also be filled with silicon oxide 8 and polysilicon 9; it can be co-filled with the gate layer inside the active region of the semiconductor device, saving process steps and reducing costs. In addition, the filling oxide layer and polysilicon can also attract impurity ions and prevent the lateral diffusion of impurity ions.

[0101] Optionally, the partition structure 18 extends along the thickness direction of the substrate.

[0102] Reference Figure 2-6 As shown, the partition structure 18 extends along the thickness direction of the substrate.

[0103] Optionally, the width of the partition structure 18 at the end near the upper surface of the substrate (2) is smaller than the width at the end near the lower surface of the substrate (2).

[0104] Specifically, the width of the end of the partition structure 18 near the upper surface of the substrate (2) is smaller than the width of the end near the lower surface of the substrate (2). Figure 7 This is a cross-sectional view of another example of a semiconductor device in this application; see reference. Figure 7 The cross-sectional structure has a spherical cavity near the lower surface of the substrate 2, with the width near the upper surface of the substrate being smaller than the width near the lower surface. This structure prevents the electric field from concentrating at sharp points or edges, where field concentration is likely to occur. By increasing the radius of curvature, the electric field lines diffuse at the termination, resulting in a more uniform electric field intensity near the cavity and preventing excessively high local electric field strength. The cavity also alters the heat conduction path, slowing down heat accumulation, reducing local overheating, and lowering the overall temperature of the semiconductor device.

[0105] Optionally, the substrate also includes: a gate layer 7 and a well region 10;

[0106] The well region 10 is located in the active region, and the well region 10 is provided in a direction perpendicular to the thickness of the substrate and connected to the terminal protection zone; the well region (10) has a first conductivity type;

[0107] Gate layer 7 is located in the well region and extends through the well region along the thickness direction of the substrate.

[0108] Specifically, refer to Figures 2-7 The well region 10 is located in the active region, extends along a direction perpendicular to the thickness of the substrate 2, and is connected to the terminal protection zone. The well region 10 has a second conductivity type. The gate layer 7 is located in the well region and extends through the well region along the thickness of the substrate 2; the gate layer 7 is used to control the switching of the semiconductor device; the gate layer is filled with an oxide layer 8 and polysilicon 9.

[0109] Optionally, when the voltage divider protection structure is located at the boundary between the terminal protection zone and the active zone, the trap zone 10 is in contact with the voltage divider protection structure.

[0110] Specifically, refer to Figures 2-7 When the voltage divider protection structure is located at the boundary between the terminal protection zone and the active zone, that is, when the field limiting ring 5 used to form the main junction with the substrate is located at the boundary between the active zone and the terminal protection zone, the trap region is in contact with the field limiting ring 5.

[0111] Optionally, the substrate may also include: an emission layer 11;

[0112] The emitter layer 11 is disposed on both sides of the gate layer 7, and the emitter layer 11 has a first conductivity type.

[0113] Specifically, refer to Figures 2-7 The substrate also includes an emitter layer 11; the emitter layer 11 is disposed on both sides of the gate layer 7 and has a first conductivity type; the emitter layer is the location where current flows in the semiconductor device.

[0114] Optionally, the semiconductor device may also include: a dielectric layer 12 and a plurality of contact holes 13;

[0115] Reference Figures 2-7 The dielectric layer 12 is disposed on the upper surface of the substrate 2; a plurality of contact holes 13 are formed on the dielectric layer 12, including contact holes 13 corresponding to a plurality of field limiting rings 5, contact holes 13 corresponding to the emission layer 11, and contact holes 13 corresponding to the isolation structure 18, and extending into the plurality of field limiting rings 5, the emission layer 11, and the isolation structure 18, so that the substrate 2 is connected to the metal field plate through the contact holes.

[0116] Specifically, the semiconductor device further includes a dielectric layer 12 and a plurality of contact holes 13; exemplaryly, the dielectric layer 12 is an insulating oxide layer; exemplaryly, the dielectric layer can be silicon glass, borosilicate glass, or phosphosilicate glass. The dielectric layer 12 is disposed on the upper surface of the substrate 2; a plurality of contact holes 13 are formed on the dielectric layer; the plurality of contact holes 13 include contact holes 13 corresponding one-to-one with a plurality of field limiting rings 5, contact holes 13 corresponding to the emitter layer 11, and contact holes 13 corresponding to the isolation structure 18, and the contact holes extend into the interior of the corresponding plurality of field limiting rings 5, emitter layer 11, and isolation structure 18, so that the substrate 2 is connected to the metal field plate on the dielectric layer 12 through each contact hole 13.

[0117] Optionally, the semiconductor device also includes: a first metal field plate 14, a plurality of second metal field plates 15 and a third metal field plate 16;

[0118] A first metal field plate (14), a plurality of second metal field plates (15) and a third metal field plate (16) are all disposed on the upper surface of the substrate (2);

[0119] The first metal field plate 14 is disposed on the active region of the substrate 2;

[0120] Multiple second metal field plates 15 correspond one-to-one with multiple field limiting rings and are set on the corresponding field limiting rings 5;

[0121] The third metal field plate 16 corresponds one-to-one with the partition structure 18 and is set on the corresponding partition structure 18.

[0122] Specifically, the semiconductor device also includes multiple metal field plates: a first metal field plate 14, multiple second metal field plates 15, and multiple third metal field plates 16. For example, the metal field plates are located on the upper surface of the substrate 2. The first metal field plate 14 is disposed in the active region of the substrate 2, specifically above the dielectric layer 12 corresponding to the active region. The multiple second metal field plates 15 correspond one-to-one with multiple field limiting rings 5, and are disposed above the dielectric layer 12 corresponding to each field limiting ring 5. The number of second metal field plates 15 corresponds to the number of field limiting rings 5. The third metal field plates 16 correspond one-to-one with the isolation structures 18, and are disposed above the dielectric layer 12 of the corresponding isolation structure 18. Similarly, the number of third metal field plates 16 corresponds to the number of isolation structures 18. For example, each metal field plate can be formed by depositing metal; the multiple metal field plates 15 corresponding to the multiple field limiting rings 5 ​​are typically wider than the width of the field limiting rings; when the second metal field plate 15 is connected to the interior of the multiple field limiting rings through the contact hole 13, a depletion region is also formed below the dielectric layer 12 corresponding to the second metal field plate 15, which further plays the role of uniform electric field and improves the reliability of semiconductor devices.

[0123] Optionally, the semiconductor device may further include: collector layer 1;

[0124] The collector layer 1 is disposed on the lower surface of the substrate 2, and the first electrode 17 covers the collector layer 1.

[0125] Specifically, a current collector layer 1 with a second conductivity type is also present on the lower surface of the substrate 2. A first electrode 17 formed by depositing back metal covers the current collector layer 1.

[0126] The semiconductor device provided in this application includes a substrate and a first electrode disposed on the lower surface of the substrate. The substrate has an active region and a termination protection region adjacent to each other along a direction perpendicular to the thickness of the substrate. The termination protection region surrounds the active region. The substrate has a first conductivity type. The substrate includes a voltage divider protection structure located in the termination protection region, having a second conductivity type, used to form a first depletion region with the substrate. The voltage divider protection structure and the substrate have different conductivity types, forming the first depletion region, which can achieve voltage division in the active region and prevent excessive electric field strength at a certain point in the substrate, thus preventing overvoltage breakdown. A cutoff structure is disposed in the termination protection region, surrounding the voltage divider protection structure. The cutoff structure itself can form a second depletion region, which has a large range and a large electric field strength. When the first electrode receives a reverse high voltage, the second depletion region formed by the cutoff structure will connect with the first depletion region, further dividing the voltage in the active region, making the electric field distribution of the semiconductor device more uniform, and cutting off the first depletion region, thereby improving the withstand voltage characteristics and reliability of the semiconductor device.

[0127] Example 2

[0128] Figure 8 An exemplary flowchart of a method for fabricating a semiconductor device is shown; including:

[0129] Step 101: Provide a substrate having an active region and a terminal protection region adjacent to each other along a direction perpendicular to the thickness of the substrate; the terminal protection region is disposed surrounding the active region; the substrate has a first conductivity type;

[0130] Step 102: A voltage divider protection structure and a cutoff structure are formed in the substrate. The voltage divider protection structure is located in the terminal protection zone, has a second conductivity type, and forms a first depletion region with the substrate. The cutoff structure is located in the terminal protection zone and surrounds the voltage divider protection structure. The cutoff structure forms a second depletion region.

[0131] Step 103: Form a first electrode located on the lower surface of the substrate; when the first electrode receives a reverse high voltage, the second depletion region formed by the cutoff structure connects to the first depletion region, performs voltage division on the active region, and cuts off the first depletion region.

[0132] Specifically, provide substrate 2; refer to Figures 2-7The substrate 2 has an active region and a termination protection region adjacent to each other along the direction perpendicular to the substrate thickness. The active region is located at the center of the semiconductor device, and the termination protection region surrounds and protects the active region. The substrate has a first conductivity type. A voltage divider protection structure and a cutoff structure 4 are formed within the substrate. The voltage divider protection structure is located in the termination protection region, has a second conductivity type, and forms a first depletion region between itself and the substrate. The cutoff structure 4 is also located in the termination protection region and surrounds the voltage divider protection structure. The cutoff structure 4 itself can generate a second depletion region. A first electrode 17 is formed on the lower surface of the substrate 2. The first electrode 17 is obtained by depositing back metal on the lower surface of the substrate. When the first electrode in the semiconductor device receives a reverse high voltage, the second depletion region formed by the cutoff structure 4 connects to the first depletion region, realizing voltage division of the active region and cutting off the first depletion region. The range of the first depletion region is affected by the external voltage and expands as the external voltage increases. The electric field strength in the second depletion region formed by the cutoff structure 4 itself is strong, which plays a role in uniform electric field and improves the withstand voltage characteristics and reliability of the semiconductor device.

[0133] Optionally, a pressure-partial protection structure is formed within the matrix, including:

[0134] Define multiple first zones within the terminal protection zone;

[0135] Multiple field-limiting rings are obtained by filling multiple first regions with first doped ions; the voltage divider protection structure includes multiple field-limiting rings; the first doped ions have a second conductivity type.

[0136] Specifically, refer to Figures 2-7 Multiple first regions are defined within the terminal protection zone, and the dielectric layer 12 corresponding to the defined first regions is removed. For example, the dielectric layer 12 corresponding to the multiple first regions can be etched away using photolithography. Then, first doped ions are filled into the multiple first regions to obtain multiple field-limiting rings 5. The voltage divider protection structure consists of multiple field-limiting rings 5. The first doped ions have a second conductivity type. For example, the filling method of the first doped ions is ion implantation. Subsequently, by heating, the first doped ions in the multiple regions can diffuse into the substrate within the multiple first regions, thereby obtaining multiple field-limiting rings 5 ​​and forming a voltage divider protection structure.

[0137] Optionally, a stop structure may be formed within the matrix, including:

[0138] Within the terminal protection zone, multiple first-conductivity type cutoff rings and multiple second-conductivity type cutoff rings are formed in alternating configurations; the cutoff structure includes multiple first-conductivity type cutoff rings and multiple second-conductivity type cutoff rings in alternating configurations.

[0139] Specifically, within the terminal protection zone, multiple alternating first conductivity type cutoff rings 6a and multiple second conductivity type cutoff rings 6b are formed; these alternating first conductivity type cutoff rings 6a and multiple second conductivity type cutoff rings 6b form a cutoff structure 4. By alternating multiple cutoff rings of different conductivity types, the cutoff structure itself can form a second depletion region; the radius of curvature of the electric field edge is increased to achieve a uniform electric field for the semiconductor device, preventing overvoltage breakdown caused by uneven electric field distribution; simultaneously, the depletion region formed by the cutoff structure has a large electric field strength, which can better achieve voltage division and cutoff effect for the first depletion region. Even if the voltage division effect of the voltage divider protection structure is poor due to process errors during actual manufacturing, a uniform electric field can still be achieved. This improves the breakdown voltage of the semiconductor device and also improves the reliability of the semiconductor device. Furthermore, it increases the size and process tolerance between the field limiting rings of the voltage divider protection structure, increases the fluctuation window of the device structure design, and improves the tolerance of subsequent packaging processes. The distance between the cutoff structure and the voltage divider protection structure can be set closer, which can effectively reduce the size of the terminal protection zone of the semiconductor device while ensuring the breakdown voltage performance of the semiconductor device, thereby saving chip area and reducing chip manufacturing costs.

[0140] Optionally, within the terminal protection zone, multiple alternating first conductivity type cutoff rings and multiple second conductivity type cutoff rings are formed, including:

[0141] Within the terminal protection zone, multiple first-conductivity type cutoff rings and multiple second-conductivity type cutoff rings are alternately arranged along the thickness of the substrate; or,

[0142] Within the terminal protection zone, multiple first-conductivity type cutoff rings and multiple second-conductivity type cutoff rings are alternately arranged along a direction perpendicular to the thickness of the substrate.

[0143] Specifically, refer to Figures 2-3 Within the terminal protection zone, a plurality of first conductivity type cutoff rings 6a and a plurality of second conductivity type cutoff rings 6b may be formed alternately along the direction of substrate thickness; or, within the terminal protection zone, a plurality of first conductivity type cutoff rings 6a and second conductivity type cutoff rings 6b may be formed alternately along a direction perpendicular to the substrate thickness. For example, refer to... Figure 2 First, a groove can be etched within the terminal protection zone of the substrate. Dopant ions of a second conductivity type are deposited from the bottom of the groove upwards to form the first second conductivity type cutoff ring 6b. Then, dopant ions of a first conductivity type are deposited above the first second conductivity type cutoff ring 6b to form the first first conductivity type cutoff ring 6a. By alternating the deposition of dopant ions of different conductivity types, multiple first conductivity type cutoff rings 6a and multiple second conductivity type cutoff rings 6b can be obtained. Figure 2 Taking the formation of a stop ring 6b with a second conductivity type at the bottom of the groove as an example, in practical scenarios, a stop ring 6a with a first conductivity type can also be formed at the bottom of the groove first. This application does not specifically limit this. For example, refer to Figure 3 Within the terminal protection zone, multiple first-conductivity type cutoff rings 6a and second-conductivity type cutoff rings 6b are alternately arranged along a direction perpendicular to the substrate thickness. First, a groove can also be formed; a layer of silicon with the first conductivity type is deposited at the bottom of the groove; then, the silicon with the first conductivity type at the corresponding positions is etched away using photolithography, and the etched positions are filled with dopant ions with the second conductivity type; at this point, the bottom layer of the groove, consisting of multiple first-conductivity type cutoff rings and multiple second-conductivity type cutoff rings along a direction perpendicular to the substrate thickness, is formed. By repeating the deposition, photolithography, and ion filling steps, the desired result can be obtained. Figure 3 The diagram shows multiple first-conductivity type cutoff rings 6a and multiple second-conductivity type cutoff rings 6b alternately arranged along a direction perpendicular to the substrate thickness. By alternately arranging multiple first-conductivity type cutoff rings and multiple second-conductivity type cutoff rings along the substrate thickness direction, or along a direction perpendicular to the substrate thickness, the cutoff structure can form a superjunction structure based on multiple cutoff rings of different conductivity types. This results in a stronger electric field in the generated second depletion region. When the semiconductor device receives an external reverse high voltage, the cutoff structure can make the electric field more uniform, improving the voltage withstand characteristics and reliability of the semiconductor device.

[0144] Optionally, the method also includes:

[0145] Within the terminal protection zone, at least one isolation structure is formed; at least one isolation structure surrounds the cut-off structure to suppress the diffusion of external impurity ions into the semiconductor device.

[0146] Specifically, within the terminal protection zone, at least one isolation structure 18 is formed, wherein the isolation structure 18 surrounds the stop structure 4 to suppress the diffusion of external impurity ions into the semiconductor device. Exemplarily, there is at least one isolation structure 18 located at the outermost periphery of the terminal protection zone, used to suppress the diffusion of external edge ions into the semiconductor device, further improving the reliability of the semiconductor device. When there are multiple isolation structures, the isolation structure 18 can be positioned between the voltage divider protection structure and the stop structure, such as... Figure 4 As shown, adding a partition structure between the voltage divider protection structure and the cutoff structure can further suppress the diffusion of edge ions into the active region of the semiconductor device. The partition structure diverts some of the electric field near the cutoff structure, making the electric field distribution inside the semiconductor device substrate more uniform and reducing the possibility of internal breakdown of the semiconductor device.

[0147] Optionally, in the terminal protection zone, at least one partition structure is formed, including:

[0148] Within the terminal protection zone, at least one first groove is formed around the cut-off structure.

[0149] In at least one first groove, a filler is filled to form at least one partition structure; the filler is one of the following: a metal, an oxide layer, and a combination of an oxide layer and polysilicon.

[0150] Specifically, firstly, a first groove is formed within the terminal protection zone, surrounding the cutoff structure. For example, a first groove can be formed by etching at the location surrounding the cutoff structure. There is at least one first groove, and the number of first grooves depends on the number of isolation structures to be formed. Then, a filler is filled into the first groove to form the isolation structure. For example, the filler can be metal, an oxide layer, or an oxide layer can be formed on the inner wall of the first groove before filling it with polysilicon. For example, metal can be formed by deposition; when filling with metal, in addition to effectively blocking the diffusion path of ions at the external edges, the metal can also generate a certain potential when the semiconductor device receives voltage, thereby adsorbing ions. If the filler is an oxide layer, it can be formed by high-temperature oxygen permeation, which is simpler and reduces process costs. When using a combination of oxide and polysilicon as the filler, the groove of the isolation structure can be an inverted trapezoidal groove with a certain angle, which facilitates the effective implementation of the oxide layer filling process; and it can be filled together with the gate layer of the active region, reducing process steps and costs. In this example, the formed isolation structure improves the reliability of the semiconductor device by isolating it from external ions. Simultaneously, the presence of the isolation structure also enhances the process tolerance of the semiconductor device. For example, even when the surface silicone gel has slightly poor sealing properties, the isolation structure can still improve the reliability of the semiconductor device.

[0151] Optionally, the method also includes:

[0152] Within the active region, a trap region is formed; the trap region extends in a direction perpendicular to the thickness of the substrate and connects to the terminal protection zone;

[0153] Within the well region, a second groove is formed that penetrates the well region along the thickness direction of the substrate;

[0154] The second groove is filled with silicon oxide and polysilicon to form a gate layer.

[0155] Specifically, a well region 10 is formed within the active region of the semiconductor device; wherein the well region 10 extends in a direction perpendicular to the thickness of the substrate and connects to a terminal protection zone; the well region 10 has a second conductivity type. Further, a second groove is formed within the well region, extending along the thickness direction of the substrate 2 and penetrating the well region; exemplaryly, the second groove can also be formed by etching. Silicon oxide 8 is filled into the inner wall of the second groove; the silicon oxide is formed by passing oxygen under high temperature conditions. After forming an oxide layer on the inner wall of the second groove, polysilicon 9 is then filled to form a gate layer 7; the gate layer is used to control the switching of the semiconductor device. In this example, by forming a well region inside the active region to form a conductive channel for the semiconductor device; simultaneously, a gate layer is formed within the well region, working together with the well region to control the switching of the semiconductor device, thereby improving the reliability of the semiconductor device.

[0156] Optionally, the method also includes:

[0157] Emitter layers are formed on both sides of the gate layer; the emitter layers have a first conductivity type.

[0158] Specifically, an emitter layer 11 is formed on both sides of the gate layer 7, which is an active region; as a location for current to pass through the semiconductor device, the emitter layer 11 has a first conductivity type.

[0159] Optionally, before forming the voltage divider protection structure, it also includes:

[0160] A dielectric layer is filled on the upper surface of the substrate.

[0161] Furthermore, after providing the substrate 2, a dielectric layer 12 is first filled on the upper surface of the substrate 2; exemplaryly, the dielectric layer can be silicon glass, borosilicate glass, or phosphosilicate glass.

[0162] Optionally, the method also includes:

[0163] Multiple vias are formed in the dielectric layer; each via corresponds to a field limiting ring, an emission layer, and a blocking structure, and extends into the interior of the field limiting ring, the emission layer, and the blocking structure.

[0164] Metal is filled into the through hole to form a contact hole.

[0165] Furthermore, after forming a dielectric layer 12 on the upper surface of the substrate 2, a plurality of through-holes are formed on the dielectric layer 12; the plurality of through-holes correspond one-to-one with a plurality of field limiting rings 5, an emission layer 11, and a blocking structure 18. For example, the plurality of through-holes can be formed by etching. The plurality of through-holes extend into the interior of the plurality of field limiting rings 5, the emission layer 11, and the blocking structure 18; then, metal is filled into the through-holes to form contact holes 13.

[0166] Optionally, after forming the contact hole 13, the following is included:

[0167] Above the dielectric layer, front metal is deposited to form multiple metal field plates; each of the multiple metal field plates corresponds to an active region, multiple field confinement rings, and a partition structure.

[0168] Furthermore, after forming multiple vias, a front-side metal is deposited above the dielectric layer 12 to form a metal field plate on the upper surface of the semiconductor device. Each metal field plate corresponds to an active region, multiple field-limiting rings 5, and a blocking structure; that is, the metal field plate covers the active region of the substrate 2, as well as the multiple field-limiting rings 5 ​​and the blocking structure 18. In this example, by creating vias in the dielectric layer and further filling the vias with metal, the contact holes contact the metal plate on the upper surface of the substrate, enabling the semiconductor device to conduct electricity and improving its reliability.

[0169] Optionally, the method also includes:

[0170] A fourth doped ion is filled on the lower surface of the substrate to form a collector layer; the fourth doped ion has a second conductivity type; a first electrode covers the collector layer.

[0171] Specifically, a fourth doped ion is filled on the lower surface of the substrate 2 to form the collector layer 1 of the semiconductor device; wherein the fourth doped ion has a second conductivity type, and the aforementioned first electrode 17 covers the collector layer. In this example, a collector layer is formed to collect charge carriers and generate output current, thereby improving the breakdown voltage characteristics of the semiconductor device.

[0172] Example 3

[0173] See Figures 9-17 ; Figures 9-17 This is a schematic diagram of the process steps of the semiconductor device fabrication method of this application; taking a semiconductor device including three field-limiting rings, one cutoff structure and one isolation structure as an example. Figure 9 This is a cross-sectional view of the substrate of an example semiconductor device of this application; firstly, a substrate 2 is provided, the substrate having a first conductivity type; exemplary, the substrate 2 is N-type silicon.

[0174] Figure 10 This is a cross-sectional view of an example of this application after a dielectric layer and a field confinement ring have been formed on the substrate; see reference. Figure 10A dielectric layer 12 is formed on the upper surface of the substrate 2. When the dielectric is silicon dioxide, the silicon dioxide layer is grown using a dry oxygen + wet oxygen + dry oxygen method, which facilitates the rapid formation of a high-quality dielectric layer 12. Optionally, after forming the dielectric layer 12, a chemical mechanical polishing process can be introduced to make the surface of the dielectric layer 12 smoother, which helps to increase the stability of the process steps. At the location of the field confinement ring corresponding to the defined terminal protection zone, the dielectric layer at the corresponding location is etched away to form the corresponding groove. Then, in the corresponding region, dopant ions with a second conductivity type, i.e., P-type dopant ions, are implanted to form multiple field confinement rings 5. For example, the implantation mask is the dielectric layer 12. First, the implantation region location is determined by exposure and development. Then, the implantation region is exposed by etching the dielectric layer 12. Finally, dopant ions of the second conductivity type are implanted using the dielectric layer 12 as a mask.

[0175] Figure 11 This is a cross-sectional view of an example of this application after forming the third, fourth, and fifth grooves on the substrate; see reference to Figure 11 The third groove 19, the fourth groove 20, and the fifth groove 21 are formed by etching at the corresponding positions of the active region and the terminal protection region. The third groove 19 corresponds to the active region and is used to form the gate layer later. The fourth groove 20 is located in the terminal protection region and is used to form the cutoff structure 4 later. The fifth groove 21 is located outside the fourth groove 20 in the direction perpendicular to the substrate thickness. The fifth groove is used to form the isolation structure 18 later. The groove depths of the third groove 19, the fourth groove 20, and the fifth groove 21 are equal. In this way, as long as the width of each groove is defined in advance, the third groove 19, the fourth groove 20, and the fifth groove 21 can be generated simultaneously in one etching, saving process steps.

[0176] Figure 12 This is a cross-sectional view of an example of this application after the gate layer has been generated; see reference. Figure 12 By introducing oxygen at high temperature, silicon oxide 8 is generated inside the third groove 19, and then polysilicon 9 is deposited to form the gate layer 7.

[0177] Figure 13 This is a cross-sectional view of an example of the formation of the well region and the emitter layer in this application; see reference. Figure 13 Then, within the active region, ion implantation is performed to implant dopants of the second conductivity type (P-type) to form the active region well region 10; the gate layer 7 is located inside the well region 10, and ion implantation is performed at corresponding positions on both sides of the gate layer 7 to implant dopants of the first conductivity type (N-type) to form the emitter layer 11; wherein, the concentration of dopants of the second conductivity type implanted in the well region 10 is 1-2 orders of magnitude smaller than the doping concentration of dopants of the second conductivity type implanted in the field confinement ring 5.

[0178] Figure 14This is a cross-sectional view of an example of this application after a dielectric layer has been deposited in the active region and a via has been formed; see reference. Figure 14 Then, the etched dielectric layer, except for the dielectric layer on the fourth groove 20, is re-deposited; and at the positions corresponding to the multiple field limiting rings 5 ​​and the emission layer 11, multiple through holes 22 are generated on the dielectric layer 12 by etching.

[0179] Figure 15 Here is a cross-sectional view of an example of the formed cut-off structure in this application; see reference. Figure 15 In the fourth groove 20, ions of the first conductivity type and ions of the second conductivity type are alternately and repeatedly deposited to form a plurality of alternately arranged first conductivity type cutoff rings 6a and second conductivity type cutoff rings 6b, generating a cutoff structure 4.

[0180] Figure 16 This is a cross-sectional view of an example of the partition structure formed and the metal field plate formed according to this application; see reference. Figure 16 Metal is deposited inside the fifth groove 21 to form a cutoff structure 4, and a dielectric layer 12 is regenerated above the partition structure 4; and front metal is deposited at the corresponding positions above the multiple field limiting rings 5 ​​and above the partition structure 18 in the active region to form a first metal field plate 14, multiple second metal field plates 15 and a third metal field plate 16; at the same time, metal is filled inside the multiple through holes 12 to form multiple contact holes.

[0181] Figure 17 This is a cross-sectional view of a fabricated semiconductor device as an example of this application; see reference. Figure 17 On the lower surface of the substrate 2, doped ions with a second conductivity type (Px type) are implanted to generate the collector layer 1; and back metal is deposited on the lower surface to form the first electrode 17 (collector) of the semiconductor device. Thus, the process steps for fabricating the semiconductor device are completed, and the fabricated semiconductor device is generated.

[0182] The method for fabricating a semiconductor device provided in this embodiment includes: providing a substrate having an active region and a termination protection region adjacent to each other along a direction perpendicular to the thickness of the substrate; the termination protection region surrounding the active region; the substrate having a first conductivity type; forming a voltage divider protection structure and a cutoff structure within the substrate, the voltage divider protection structure being located in the termination protection region, having a second conductivity type, and forming a first depletion region with the substrate; the cutoff structure being located in the termination protection region and surrounding the voltage divider protection structure; the cutoff structure forming a second depletion region; forming a first electrode located on the lower surface of the substrate; when the first electrode receives a reverse high voltage, the second depletion region formed by the cutoff structure connects to the first depletion region, performing voltage division on the active region and cutting off the first depletion region. The semiconductor device fabrication method provided in this embodiment forms a cutoff structure in the terminal protection zone, which itself can form a second depletion region. When an external reverse voltage is received, the first depletion region formed between the voltage divider protection structure and the substrate will connect with the second depletion region, thereby achieving voltage division of the active region, optimizing the electric field distribution, and improving the withstand voltage characteristics of the semiconductor device. At the same time, the second depletion region will stop the first depletion region from continuing to diffuse, preventing edge leakage of the semiconductor device and improving the accuracy of the semiconductor device.

[0183] Example 4

[0184] This application also provides an electronic device, which includes the aforementioned semiconductor device. The electronic device can be a mobile phone, a portable Android device (PAD), a personal digital assistant (PDA), a computing device, a wearable device, a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, etc. The electronic device can also be a main drive inverter, a converter, an on-board charger (OBC), and an on-board charging pile, etc.

[0185] This application also provides a vehicle that includes the aforementioned semiconductor device or electronic device. The vehicle can be an electric vehicle, a hybrid vehicle, or other new energy vehicle.

[0186] The embodiments or implementation methods described in this specification are presented in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The terms "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with an embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described can be combined in any suitable manner in one or more embodiments or examples.

[0187] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A semiconductor device, characterized in that, include: The substrate (2) and a first electrode (17) disposed on the lower surface of the substrate (2), the substrate (2) having an active region and a terminal protection region adjacent to each other along the thickness direction perpendicular to the substrate (2); The terminal protection zone surrounds the active area; the substrate (2) has a first conductivity type; The matrix (2) includes: The voltage divider protection structure, located in the terminal protection zone, has a second conductivity type and is used to form a first depletion region with the substrate (2); The cutoff structure (4) is located in the terminal protection zone and surrounds the voltage divider protection structure; the cutoff structure (4) forms a second depletion region; when the first electrode (17) receives a reverse high voltage, the second depletion region formed by the cutoff structure (4) connects to the first depletion region, divides the voltage of the active region, and cuts off the first depletion region.

2. The semiconductor device according to claim 1, characterized in that, The cutoff structure (4) includes a plurality of first conductivity type cutoff rings (6a) and a plurality of second conductivity type cutoff rings (6b); the plurality of first conductivity type cutoff rings (6a) and the plurality of second conductivity type cutoff rings (6b) are alternately arranged; the plurality of first conductivity type cutoff rings (6a) and the plurality of second conductivity type cutoff rings (6b) form the second depletion region.

3. The semiconductor device according to claim 2, characterized in that, The first conductivity type ion doping concentration of the first conductivity type cutoff ring (6a) is higher than the second conductivity type ion doping concentration of the second conductivity type cutoff ring (6b).

4. The semiconductor device according to claim 2, characterized in that, The plurality of first conductivity type cutoff rings (6a) and the plurality of second conductivity type cutoff rings (6b) are alternately arranged along the thickness direction of the substrate (2).

5. The semiconductor device according to claim 2, characterized in that, The plurality of first conductivity type cutoff rings (6a) and the plurality of second conductivity type cutoff rings (6b) are alternately arranged in a direction perpendicular to the thickness of the substrate.

6. The semiconductor device according to claim 1, characterized in that, The voltage divider protection structure includes multiple field limiting rings (5); The plurality of field limiting rings (5) have a second conductivity type and form the first depletion region between them and the substrate (2).

7. The semiconductor device according to claim 6, characterized in that, The width of the field limiting ring (5) closest to the active region among the plurality of field limiting rings is greater than the width of the other field limiting rings (5).

8. The semiconductor device according to claim 6, characterized in that, The widths of the other field limiting rings (5) are equal.

9. The semiconductor device according to claim 6, characterized in that, The concentrations of second conductivity type ions doped in the plurality of field-limiting rings (5) are equal.

10. The semiconductor device according to claim 6, characterized in that, The spacing (5) of the multiple field limiting rings is equal.

11. The semiconductor device according to claim 6, characterized in that, The spacing of the plurality of field limiting rings (5) increases sequentially along the direction from the active region to the terminal protection zone.

12. The semiconductor device according to claim 1, characterized in that, The substrate further includes: at least one partition structure (18); The at least one isolation structure (18) is located in the terminal protection zone and surrounds the cut-off structure to suppress the diffusion of external impurity ions into the semiconductor device.

13. The semiconductor device according to claim 11, characterized in that, The partition structure (18) is filled with a filler material, which is one of the following: metal, silicon oxide, and a combination of silicon oxide and polycrystalline silicon.

14. The semiconductor device according to claim 13, characterized in that, The partition structure extends along the thickness direction of the substrate.

15. The semiconductor device according to claim 14, characterized in that, The width of the partition structure (18) at the end near the upper surface of the substrate (2) is smaller than the width at the end near the lower surface of the substrate (2).

16. The semiconductor device according to claim 1, characterized in that, The substrate (2) further includes: a gate layer (7) and a well region (10); The well region (10) is located in the active region, the well region (10) extends along the thickness direction perpendicular to the substrate (2) and is connected to the terminal protection zone; the well region (10) has a first conductivity type; The gate layer (7) is located in the well region (10) and extends through the well region (10) along the thickness direction of the substrate (2).

17. The semiconductor device according to claim 16, characterized in that, When the voltage divider protection structure is located at the boundary between the terminal protection zone and the active zone, the sink region (10) is in contact with the voltage divider protection structure.

18. The semiconductor device according to claim 17, characterized in that, The substrate further includes: an emission layer; The emitter layer (11) is disposed on both sides of the gate layer (7), and the emitter layer (11) has a first conductivity type.

19. The semiconductor device according to claim 12, characterized in that, The semiconductor device further includes: a first metal field plate (14), a plurality of second metal field plates (15) and a third metal field plate (16); The first metal field plate (14), a plurality of second metal field plates (15) and a third metal field plate (16) are all disposed on the upper surface of the substrate (2); The first metal field plate (14) is disposed on the active region of the substrate (2); The plurality of second metal field plates (15) correspond one-to-one with the plurality of field limiting rings (5) and are disposed on the corresponding field limiting rings (5); The third metal field plate (16) corresponds one-to-one with the partition structure (18) and is disposed on the corresponding partition structure (18).

20. The semiconductor device according to claim 18, characterized in that, The semiconductor device further includes: a dielectric layer (12) and a plurality of contact holes (13); The dielectric layer (12) is disposed on the upper surface of the substrate (2); the plurality of contact holes (13) are formed on the dielectric layer (12), and the plurality of contact holes (13) are filled with metal; the plurality of contact holes (13) include contact holes (13) corresponding to the plurality of field limiting rings (5), contact holes (13) corresponding to the emission layer (11) and contact holes (13) corresponding to the partition structure (18), and extend into the plurality of field limiting rings (5), the emission layer (11) and the partition structure (18), so that the substrate is connected to the metal field plate through the contact holes.

21. The semiconductor device according to any one of claims 1-20, characterized in that, The semiconductor device further includes: a collector layer (1); The current collector layer (1) is disposed on the lower surface of the substrate (2), and the first electrode (17) covers the current collector layer (1).

22. A method for fabricating a semiconductor device, characterized in that, include: A substrate (2) is provided, the substrate (2) having an active region and a terminal protection region adjacent to each other along a thickness direction perpendicular to the substrate (2); the terminal protection region is disposed surrounding the active region; the substrate (2) has a first conductivity type; A voltage divider protection structure and a cutoff structure are formed within the substrate (2). The voltage divider protection structure is located in the terminal protection zone, has a second conductivity type, and forms a first depletion region with the substrate. The cutoff structure (4) is located in the terminal protection zone and surrounds the voltage divider protection structure. The cutoff structure (4) forms a second depletion region. A first electrode (17) is formed on the lower surface of the substrate; when the first electrode (17) receives a reverse high voltage, the second depletion region formed by the cut-off structure (4) connects to the first depletion region, divides the voltage of the active region, and cuts off the first depletion region.

23. The method according to claim 22, characterized in that, A pressure-distributing protection structure is formed within the matrix, comprising: Multiple first zones are defined within the terminal protection zone; In the plurality of first regions, first doped ions are filled to obtain a plurality of field limiting rings (5); the voltage divider protection structure includes the plurality of field limiting rings (5); the first doped ions have a second conductivity type.

24. The method according to claim 22, characterized in that, A stop structure (4) is formed within the matrix, comprising: Within the terminal protection zone, a plurality of first conductivity type cutoff rings (6a) and a plurality of second conductivity type cutoff rings are formed in alternating arrangement; the cutoff structure includes the plurality of first conductivity type cutoff rings and the plurality of second conductivity type cutoff rings (6b) in alternating arrangement.

25. The method according to claim 24, characterized in that, Within the terminal protection zone, a plurality of alternating first conductivity type cutoff rings (6a) and a plurality of second conductivity type cutoff rings (6b) are formed, including: Within the terminal protection zone, a plurality of first conductivity type cutoff rings (6a) and a plurality of second conductivity type cutoff rings (6b) are formed alternately along the thickness direction of the substrate (2); or, Within the terminal protection zone, a plurality of first conductivity type cutoff rings (6a) and a plurality of second conductivity type cutoff rings (6b) are formed alternately arranged along the thickness direction perpendicular to the substrate (2).

26. The method according to claim 25, characterized in that, The method further includes: Within the terminal protection zone, at least one isolation structure (18) is formed; the at least one isolation structure (18) surrounds the voltage divider protection structure and is used to suppress the diffusion of external impurity ions into the semiconductor device.

27. The method according to claim 26, characterized in that, The terminal protection zone includes at least one partition structure (18), comprising: Within the terminal protection zone, at least one first groove is formed around the stop structure (4); The at least one first groove is filled with a filler to form the at least one partition structure; the filler is one of the following: metal, silicon oxide, and a combination of silicon oxide and polycrystalline silicon.

28. The method according to claim 27, characterized in that, The method further includes: Within the active region, a trap region (10) is formed; the trap region extends perpendicularly to the thickness direction of the substrate (2) and is connected to the terminal protection zone; Within the well region (10), a second groove is formed that penetrates the well region (10) along the thickness direction of the substrate (2); The second groove is filled with silicon oxide and polysilicon to form a gate layer (7).

29. The method according to claim 28, characterized in that, The method further includes: On both sides of the gate layer (7), an emitter layer (11) is formed; the emitter layer (11) has a first conductivity type.

30. The method according to claim 29, characterized in that, Before forming the voltage divider protection structure, the method further includes: A medium layer (12) is filled on the upper surface of the substrate (2).

31. The method according to claim 30, characterized in that, The method further includes: In the dielectric layer (12), a plurality of through holes (22) are formed; the plurality of through holes (22) correspond one-to-one with a plurality of field limiting rings (5), the emission layer (11), and the isolation structure (18), and extend into the interior of the plurality of field limiting rings (5), the emission layer (11), and the isolation structure (18); The through hole is filled with metal to form a contact hole (13).

32. The method according to claim 31, characterized in that, After forming the contact hole 9(3), the following is included: Above the dielectric layer (12), front metal is deposited to form multiple metal field plates; the multiple metal field plates correspond one-to-one with the active region, the multiple field limiting rings and the isolation structure.

33. The method according to any one of claims 22-32, characterized in that, The method further includes: A fourth doped ion is filled on the lower surface of the substrate (2) to form a collector layer (1); the fourth doped ion has a second conductivity type; the first electrode (17) covers the collector layer (1).

34. An electronic device, characterized in that, Includes the semiconductor device according to any one of claims 1-21.

35. A vehicle, characterized in that, This includes the semiconductor device according to any one of claims 1-21 or the electronic device according to claim 34.

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