Semiconductor device

Abstract

A semiconductor device may include: a substrate including an active pattern; first channel layers spaced apart in a vertical direction on the active pattern; a first gate structure surrounding the first channel layer; first source / drain patterns on both sides of the first gate structure and connected to the first channel layer; a first internal spacer between the first gate structure and the first source / drain pattern; second channel layers spaced apart in a vertical direction on the first channel layer; a second gate structure on the first gate structure and surrounding the second channel layer; a second source / drain pattern on both sides of the second gate structure and connected to the second channel layer; and a second internal spacer between the second gate structure and the second source / drain pattern. The first inner spacer and the second inner spacer may be in different shapes. The vertical direction may be perpendicular to the upper surface of the substrate.

Description

Technical Field

[0001] The inventive concept relates to semiconductor devices and methods for manufacturing semiconductor devices. Background Technology

[0002] As the demand for high performance, speed, and / or multifunctionality in semiconductor devices increases, the integration density of semiconductor devices is also increasing. In order to reduce the limitations in operating characteristics caused by the shrinking size of planar metal-oxide-semiconductor field-effect transistors (MOSFETs), efforts are being made to develop semiconductor devices including FinFETs with fin channels and all-to-the-loop field-effect transistors with nanosheets surrounded by a gate. Summary of the Invention

[0003] The example embodiment provides a semiconductor device with improved electrical characteristics and reliability.

[0004] According to an example embodiment, a semiconductor device may include: a substrate including an active pattern; a first channel layer spaced apart from each other in a vertical direction on the active pattern, the vertical direction being perpendicular to the upper surface of the substrate; a first gate structure surrounding the first channel layer; a first source / drain pattern located on both sides of the first gate structure and connected to the first channel layer; a first internal spacer located between the first gate structure and the first source / drain pattern; a second channel layer spaced apart from each other in a vertical direction on the first channel layer; a second gate structure located on the first gate structure and surrounding the second channel layer; a second source / drain pattern located on both sides of the second gate structure and connected to the second channel layer; and a second internal spacer located between the second gate structure and the second source / drain pattern, the shape of the second internal spacer being different from the shape of the first internal spacer.

[0005] According to an example embodiment, a semiconductor device may include: a substrate including an active pattern; a first channel layer spaced apart from each other in a vertical direction on the active pattern, the vertical direction being perpendicular to an upper surface of the substrate; a first gate structure surrounding the first channel layer; a first source / drain pattern located on both sides of the first gate structure and connected to the first channel layer; a first internal spacer located between the first gate structure and the first source / drain pattern, the recessed side surface of the first internal spacer contacting the first gate structure; a second channel layer spaced apart from each other in a vertical direction on the first channel layer; a second gate structure surrounding the second channel layer on the first gate structure; a second source / drain pattern located on both sides of the second gate structure and connected to the second channel layer; and a second internal spacer located between the second gate structure and the second source / drain pattern, each second internal spacer including a first spacer portion contacting the second source / drain pattern and a second spacer portion contacting the second gate structure.

[0006] According to an example embodiment, a semiconductor device may include: a substrate including an active pattern; a first channel layer spaced apart from each other in a vertical direction on the active pattern, the vertical direction being perpendicular to an upper surface of the substrate; a first gate structure surrounding the first channel layer; a first source / drain pattern located on both sides of the first gate structure and connected to the first channel layer, the first source / drain pattern including a recessed portion, and the recessed portion of the first source / drain pattern being partially recessed toward the first gate structure; a second channel layer spaced apart from each other in a vertical direction on the first channel layer; a second gate structure surrounding the second channel layer on the first gate structure; a second source / drain pattern located on both sides of the second gate structure and connected to the second channel layer; and an internal spacer located between the second gate structure and the second source / drain pattern. Attached Figure Description

[0007] The above and other aspects, features, and advantages of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 This is a top view illustrating a semiconductor device according to an example embodiment; Figure 2 yes Figure 1 A cross-sectional view of a semiconductor device taken along line I1-I1'; Figure 3A and Figure 3B They are Figure 1A cross-sectional view of a semiconductor device taken along lines II1-II1' and II2-II2'; Figure 4A and Figure 4B The diagrams are shown below. Figure 2 Enlarged views of parts “A1” and “B1” of the semiconductor device; Figure 5 This is a cross-sectional view of a semiconductor device according to an example embodiment; Figure 6A and Figure 6B The diagrams are shown below. Figure 5 Enlarged views of parts “A2” and “B2” of the semiconductor device; Figure 7 This is a cross-sectional view of a semiconductor device according to an example embodiment; Figure 8 This is a top view illustrating a semiconductor device according to an example embodiment; Figure 9 yes Figure 8 A cross-sectional view of a semiconductor device taken along line I2-I2'; Figure 10A and Figure 10B The diagrams are shown below. Figure 9 Enlarged views of parts "A3" and "B3" of the semiconductor device; Figures 11A to 11H It is a cross-sectional view used to illustrate each major process of a portion of a semiconductor device manufacturing method according to an example embodiment (formation of a first source / drain pattern and a second source / drain pattern); Figure 12A It is illustrated in Figure 11E A schematic diagram of the process for growing the first source / drain pattern in the process, and Figure 12B It is illustrated in Figure 11H A schematic diagram of the process for growing the second source / drain pattern in the process; and Figures 13A to 13D It is a cross-sectional view used to describe the various main processes of another part of the semiconductor device manufacturing method according to the example embodiment (the formation of the first gate structure and the second gate structure). Detailed Implementation

[0008] In the following description, exemplary embodiments will be illustrated with reference to the accompanying drawings.

[0009] Figure 1 This is a top view illustrating a semiconductor device according to an example embodiment. Figure 2 yes Figure 1 A cross-sectional view of a semiconductor device taken along line I1-I1', and Figure 3A and Figure 3B They are Figure 1A cross-sectional view of a semiconductor device taken along lines II1-II1' and II2-II2'.

[0010] refer to Figure 1 , Figure 2 , Figure 3A and Figure 3B The semiconductor device 100 includes an active pattern 105 extending on a substrate 101 in a first direction (e.g., the X direction), a first channel layer 131 (also referred to as a "lower channel layer") spaced apart from each other in a direction perpendicular to the upper surface of the substrate 101 (e.g., the Z direction) on each region of the active pattern 105, a second channel layer 132 (also referred to as an "upper channel layer") spaced apart from each other in a vertical direction (e.g., the Z direction) on the first channel layer 131, and a gate structure (GS) extending across each region of the active pattern 105 and surrounding the first channel layer 131 and the second channel layer 132 in a second direction (e.g., the Z direction) intersecting the first direction (e.g., the X direction).

[0011] refer to Figure 1 , Figure 1 The active pattern 105 is shown to include two active patterns, and the gate structure GS includes three gate structures spanning each region of the two active patterns 105, but the inventive concept is not limited thereto.

[0012] Substrate 101 may include semiconductor materials, such as group IV semiconductors, group III-V compound semiconductors, or group II-VI compound semiconductors. For example, group IV semiconductors may include silicon (Si), germanium (Ge), or silicon-germanium (SiGe). Substrate 101 may include a bulk wafer, an epitaxial layer, or a silicon-on-insulator (SOI) layer.

[0013] like Figure 1 As illustrated, the active pattern 105 may have a fin-shaped structure extending from the substrate 101 in a first direction (e.g., the X direction). Figure 3A and Figure 3B As illustrated, a device isolation layer 110 may define an active pattern 105 in a substrate 101. The device isolation layer 110 is disposed on the substrate 101, and a portion of the active pattern 105 may protrude from the upper surface of the device isolation layer 110. For example, the device isolation layer 110 may be formed using a shallow trench isolation (STI) process. The device isolation layer 110 may include an insulating material. The device isolation layer 110 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof.

[0014] like Figure 2As illustrated, the semiconductor device 100 according to this embodiment may include a first transistor TR1 and a second transistor TR2 stacked on each region of the active pattern 105. Each of the first transistor TR1 and the second transistor TR2 used in this embodiment may be a multi-bridge channel FET (MBCFET) including a gate structure (GS) surrounding a first channel layer 131 and a second channel layer 132 disposed on the active pattern 105. TM In this embodiment, the gate structure GS includes the first gate structure GS1 of the first transistor TR1 and the second gate structure GS2 of the second transistor TR2.

[0015] For details, please refer to Figure 2 , Figure 3A and Figure 3B The first transistor structure TR1 may include a first channel layer 131 stacked on an active pattern 105, a first gate electrode 145A surrounding the first channel layer 131, a first source / drain pattern 150A (also referred to as a "lower source / drain pattern") connected to a side surface of the first gate electrode 145A to the first channel layer 131, and a first gate insulating layer 142A located between the first channel layer 131 and the first gate electrode 145A.

[0016] Similarly, the second transistor structure TR2 may include a second channel layer 132 (also referred to as the "upper channel layer"), a second gate electrode 145B surrounding the second channel layer 132, a second source / drain pattern 150B (also referred to as the "upper source / drain pattern") connected to both sides of the second gate electrode 145B to the second channel layer 132, and a second gate insulating layer 142B located between the second channel layer 132 and the second gate electrode 145B.

[0017] The semiconductor device 100 according to this embodiment may include an insulating layer 170 disposed on a first source / drain pattern 150A to electrically separate the first source / drain pattern 150A and the second source / drain pattern 150B from each other. The insulating layer 170 used in this embodiment can provide a separation structure that stably covers a region from the upper surface of the first source / drain pattern 150A to two edge regions along a first direction (e.g., the X direction).

[0018] As described above, first channel layers 131 are stacked on a region of active pattern 105 and spaced apart from each other in a vertical direction (e.g., the Z direction). The first channel layers 131 may be provided in multiple quantities (e.g., two or three), and each may include a semiconductor pattern. For example, the first channel layer 131 may include at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge). Similarly, second channel layers 132 may be provided in multiple quantities (e.g., two or three), and each may include a semiconductor pattern. For example, the second channel layer 132 may include at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge).

[0019] An intermediate insulating pattern 160 is disposed on the uppermost first channel layer of the first channel layer 131, and a second channel layer 132 is stacked on the intermediate insulating pattern 160, while being spaced apart from each other in a vertical direction (e.g., the Z direction). The intermediate insulating pattern 160 may be arranged to overlap the first channel layer 131 and the second channel layer 132 in a direction perpendicular to (e.g., the Z direction) to the first channel layer 131 and the second channel layer 132. In this way, the stacked first channel layer 131 and the stacked second channel layer 132 may be separated by the intermediate insulating pattern 160.

[0020] The intermediate insulating pattern 160 includes an insulating material and may include at least one of, for example, silicon nitride, silicon oxynitride, or silicon carbide nitride. The intermediate insulating pattern 160 may be a single insulating material layer, but in some embodiments, it may include multiple insulating material layers.

[0021] refer to Figure 2 and Figure 3B The first gate insulating layer 142A may be disposed not only between the first channel layer 131 and the first gate electrode 145A, but also on the lower surface and some side surfaces of the intermediate insulating pattern 160. Additionally, the first gate insulating layer 142A may extend on the device isolation layer 110. The second gate insulating layer 142B may be disposed between the second channel layer 132 and the second gate electrode 145A, as well as on the upper surface and some side surfaces of the intermediate insulating pattern 160.

[0022] The gate structure GS may further include gate spacers 141. Gate spacers 141 may be disposed on two sidewalls of an electrode portion extending in a second direction (e.g., the Y direction) on the uppermost second channel layer 132 of the second gate electrode 145B. A gate capping layer 147 may be formed on the portion of the second gate electrode 145B between the gate spacers 141.

[0023] The first gate electrode 145A and the second gate electrode 145B used in this embodiment may comprise conductive materials with different work functions. For example, the first gate electrode 145A and the second gate electrode 145B may comprise at least one of W, Ti, Ta, Mo, TiN, TaN, WN, TiON, TiAlC, TiAlN, and TaAlC. The first gate electrode 145A and the second gate electrode 145B may comprise semiconductor materials such as doped polycrystalline silicon. The first gate electrode 145A and the second gate electrode 145B may each consist of two or more layers.

[0024] The first gate insulating layer 142A and the second gate insulating layer 142B may each comprise an oxide, a nitride, and / or a high-k material. The first gate insulating layer 142A and the second gate insulating layer 142B may be composed of different dielectric layers. A high-k material refers to a dielectric material having a higher dielectric constant than a silicon oxide film (SiO2), and the high-k material may include at least one of the following: for example, alumina (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), and zirconium silicon oxide (ZrSi). x O y Hafnium oxide (HfO2) and hafnium silicon oxide (HfSi) x O y ), Lanthanum oxide (La₂O₃), Lanthanum aluminum oxide (LaAl) x O y ), lanthanum hafnium oxide (LaHf) x O y Hafnium aluminum oxide (HfAl) x O y ) and praseodymium oxide (Pr2O3). In some embodiments, each of the first gate insulating layer 142A and the second gate insulating layer 142B may include an interface insulating film and a high-k dielectric film (see Figure 6A and Figure 6B as well as Figure 10A and Figure 10B ).

[0025] For example, gate spacer 141 may include at least one of silicon nitride and silicon oxynitride. In some embodiments, gate spacer 141 may include a multilayer structure. Gate capping layer 147 may include, for example, silicon nitride, silicon oxynitride, silicon carbide, or silicon carbide.

[0026] In some embodiments, the first transistor TR1 and the second transistor TR2 may share a single gate structure GS. For example, the single gate structure may be provided as a common gate electrode surrounding the first channel layer 131 and the second channel layer 132.

[0027] The first source / drain pattern 150A can be disposed in the recessed portions on both sides of the active pattern 105 in the first channel layer 131. The first source / drain pattern 150A can be disposed as the source region or drain region of the first transistor TR1. The first source / drain pattern 150A can include epitaxial growth portions extending from the surface of the recessed portions of the active pattern 105 and from both sides of the first channel layer 131. Similarly, the second source / drain pattern 150B is disposed on both sides of the second channel layer 132 and can be used as the source region or drain region of the second transistor TR2. The second source / drain pattern 150B can include epitaxial growth portions using both sides of the second channel layer 132 as seed layers.

[0028] The first source / drain pattern 150A and the second source / drain pattern 150B may comprise a semiconductor epitaxial material such as silicon (Si). The first source / drain pattern 150A and the second source / drain pattern 150B may comprise impurities of different types and / or concentrations. For example, when the first transistor TR1 is a P-type MOSFET, the first source / drain pattern 150A may comprise silicon germanium (SiGe) doped with p-type impurities, while when the second transistor TR2 is an N-type MOSFET, the second source / drain pattern 150B may comprise silicon (Si) doped with n-type impurities. Specifically, in the first transistor TR1, the first source / drain pattern 150A formed of silicon germanium (SiGe) acts as a stressor, applying compressive force to the first channel layer 131, thereby increasing the charge mobility within the first channel layer 131.

[0029] In some embodiments, the cross-sections of the first source / drain pattern 150A and the second source / drain pattern 150B along a second direction (e.g., the Y direction) may have different shapes. For example, the cross-section of the first source / drain pattern 150A may be pentagonal, while the cross-section of the second source / drain pattern 150B may be a polygon with gentle angles (see [link to documentation]). Figure 3A ).

[0030] refer to Figure 2 The first transistor TR1 and the second transistor TR2 may each include a first internal spacer 190A and a second internal spacer 190B. The first internal spacer 190A may be disposed between the first gate structure GS1 (specifically, the portion adjacent to the first channel layer 131) and the first source / drain pattern 150A, and the second internal spacer 190B may be disposed between the second gate structure GS2 (specifically, the portion adjacent to the second channel layer 131) and the second source / drain pattern 150B. However, the first internal spacer 190A and the second internal spacer 190B are formed by different methods and have different shapes.

[0031] Figure 4A and Figure 4B The diagrams are shown below. Figure 2 Enlarged views of "A1" and "B1" of the semiconductor device.

[0032] refer to Figure 2 and Figure 4A Each first internal spacer 190A may have a side surface CA1 that is partially recessed toward the first gate structure GS1 adjacent to the first channel layer 131. In some embodiments, the side surface CA1 may have different shapes depending on the forming process of the first internal spacer 190A. For example, the side surface CA1 may have a slightly convex side surface. The first source / drain pattern 150A includes a recessed portion 155A that is partially recessed toward the first gate structure GS1 adjacent to the first channel layer 131, and the recessed portion 155A may overlap the first channel layer 131 in the vertical direction (e.g., the Z direction). The side surface CA2 of each first internal spacer 190A facing the recessed portion 155A may also have a recessed side surface. When the sacrificial layer 122 is removed in the process of forming the gate structure GS (see...), Figure 13B When these recessed portions 155A are used, they can be set as buffer areas to limit and / or prevent attacks on the pre-formed first source / drain pattern 150A.

[0033] refer to Figure 2 and Figure 4B Unlike the shape of the first internal spacer 190A, each of the second internal spacers 190B may have a side surface CB that protrudes towards a portion of the second gate structure GS2 adjacent to the second channel layer 132.

[0034] In this embodiment, it can be understood that this structural difference arises from differences in the manufacturing processes of the first internal spacer 190A and the second internal spacer 190B. Specifically, although the second internal spacer 190B is formed after the recess process and before the formation of the second source / drain pattern 150B (see...),... Figure 11E However, the first internal spacer 190A is formed in the process of forming the first gate structure GS1 after the formation of the first source / drain pattern 150A (see [link]). Figure 13C ).

[0035] Therefore, in this embodiment, the first source / drain pattern 150A may include a SiGe epitaxial portion for applying compressive force to the first channel layer 131 as described above. However, if crystal defects such as dislocations occur in the first source / drain pattern 150A, sufficient compressive force cannot be applied. Unlike typical second internal spacers, the first internal spacer 190A is formed after the formation of the first source / drain pattern 150A, thereby significantly reducing crystal defects in the first source / drain pattern 150A.

[0036] Therefore, due to the aforementioned differences in manufacturing processes, the first internal spacer 190A and the second internal spacer 190B can have different shapes and structures. (Refer to...) Figures 11A to 11H and Figures 13A to 13D This will be described in detail.

[0037] The second internal spacer 190B can extend to the adjacent corner portion of the adjacent second channel layer 132, such as Figure 4B As illustrated. In this embodiment, the other side surface of the second internal spacer 190B (the side surface facing the second source / drain pattern 150B) is illustrated as a relatively flat side surface. However, in some embodiments, even if the indentation depth or shape differs, similar to the first source / drain pattern 150A, the second source / drain pattern 150B may also have an indentation portion facing the second internal spacer 190B (see Figure 150B). Figure 7 (155B in the text).

[0038] The semiconductor device 100 according to this embodiment may include an interlayer insulating layer 180 disposed on an isolation insulating layer 170 and covering a second source / drain pattern 150B. The interlayer insulating layer 180 may be silicon oxide. For example, the interlayer insulating layer 180 may be a spin-coated hard mask (SOH), a flowable oxide (FOX), a Tonen silazane (TOSZ), undoped silicon glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), plasma-enhanced tetraethyl orthosilicate (PETEOS), fluorosilicate glass (FSG), high-density plasma (HDP) oxide, plasma-enhanced oxide (PEOX), flowable CVD (FCVD) oxide, or a combination thereof. The interlayer insulating layer 180 may be formed using chemical vapor deposition (CVD), a flowable CVD process, or a spin-coating process.

[0039] The semiconductor device 100 according to this embodiment may further include a first lower contact 210A connected to a first source / drain pattern 150A, a first upper contact 210B connected to a second source / drain pattern 150B, and a second contact 220 connected to a second gate electrode 145B. The first upper contacts 210B are connected to the second source / drain patterns 150B through an interlayer insulating layer 180, and the second contacts 220 can penetrate the gate capping layer 147 and are connected to the second gate electrode 145B. The first lower contact 210A may include a horizontal contact portion 210L and a vertical contact portion 210V. The horizontal contact portion 210L is connected to the first source / drain pattern 150A and extends in a horizontal direction (e.g., the Y direction) along the upper surface of the substrate 101. The vertical contact portion 210V is connected to the horizontal contact portion 210L and extends in a direction perpendicular to the upper surface of the substrate 101 (e.g., the Z direction). For example, the contacts 210A, 210B and 220 described above may include at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), tungsten carbide (WCN), titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), aluminum (Al), cobalt (Co), ruthenium (Ru) and molybdenum (Mo).

[0040] Figure 5 This illustration shows a cross-sectional view of a semiconductor device according to an example embodiment, and Figure 6A and Figure 6B The diagrams are shown below. Figure 5 Enlarged views of parts “A2” and “B2” of the semiconductor device.

[0041] refer to Figure 5 , Figure 6A and Figure 6B The semiconductor device 100A according to this embodiment can be understood as being related to Figures 1 to 4B The illustrated semiconductor device 100 is identical or similar, except that the second internal spacer 190B is similar to the first internal spacer 190A, also having a recessed side surface CB1 that contacts the second gate structure GS2. The second source / drain pattern 150B is similar to the first source / drain pattern 150A, having a recessed portion 155B. Furthermore, the first gate insulating layer 142A and the second gate insulating layer 142B include interface insulating films 142A1 and 142B1 and high-k dielectric films 142A2 and 142B2. Additionally, unless otherwise stated, reference may be made to... Figures 1 to 4B The components of this embodiment are understood by describing the same or similar components of the illustrated semiconductor device 100.

[0042] refer to Figure 5 and Figure 6ASimilar to the previous embodiments, each first internal spacer 190A may have a side surface CA1 that is recessed toward a portion of the first gate structure GS1 adjacent to the first channel layer 131. The first source / drain pattern 150A includes a recessed portion 155A that is recessed toward a portion of the first gate structure GS1 adjacent to the first channel layer 131, and the recessed portion 155A may overlap with the first channel layer 131 in a vertical direction (e.g., the Z direction). The side surface CA2 of each first internal spacer 190A facing the recessed portion 155A may also have a recessed side surface.

[0043] refer to Figure 5 and Figure 6B Similar to the first internal spacer 190A, each second internal spacer 190B used in this embodiment may have a side surface CB1 that is recessed toward the portion of the second gate structure GS2 adjacent to the second channel layer 132. The second source / drain pattern 150B includes a recessed portion 155B that is recessed toward the portion of the second gate structure GS2 adjacent to the second channel layer 132, and the recessed portion 155B may overlap with the second channel layer 132 in the vertical direction (e.g., the Z direction). The side surface CB2 of each second internal spacer 190B facing the recessed portion 155B may also have a recessed side surface.

[0044] Therefore, the first internal spacer 190A and the second internal spacer 190B are manufactured using a similar manufacturing process and are provided after the formation of the first source / drain pattern 150A and the second source / drain pattern 150B. Thus, in the epitaxial layers of the first source / drain pattern 150A and the second source / drain pattern 150B, the recessed side surfaces can be stably grown from all epitaxial crystal planes (e.g., the first channel layer 131, the second channel layer 132, and the sacrificial layer 122) (see [link]). Figure 11G and Figure 12A ).

[0045] Additionally, when the sacrificial layer 122 is removed during the process of forming the first gate structure GS1 and the second gate structure GS2 (see...), Figure 13B When the first source / drain pattern 150A is recessed 155A and the second source / drain pattern 150B is recessed 155B, the recessed portion 155A of the first source / drain pattern 150A and the second source / drain pattern 150B can be set as a buffer area to limit and / or prevent attacks on the pre-formed first source / drain pattern 150A and the second source / drain pattern 150B.

[0046] However, since the first internal spacer 190A and the second internal spacer 190B are formed by different processes, the detailed structure can have different shapes (e.g., widths Wa and Wb and indentation depths da and db).

[0047] First, the first internal spacer 190A and the second internal spacer 190B can have different widths (Wa ≠ Wb). For example, the width (Wa) of the first internal spacer 190A can be greater than the width (Wb) of the second internal spacer 190B.

[0048] Similarly, the recessed portion 155A of the first source / drain pattern 150A and the recessed portion 155B of the second source / drain pattern 150B can have different depths (da≠db). For example, the depth da of the recessed portion 155A of the first source / drain pattern 150A can be less than the depth db of the recessed portion 155B of the second source / drain pattern 150B.

[0049] In this embodiment, the first gate insulating layer 142A and the second gate insulating layer 142B may respectively include a first interface insulating film 142A1 and a second interface insulating film 142B1, and a first high-k dielectric film 142A2 and a second high-k dielectric film 142B2. In some embodiments, the first internal spacer 190A and the second internal spacer 190B may be formed after the formation of the first interface insulating film 142A1 and the second interface insulating film 142B1 and before the formation of the first high-k dielectric film 142A2 and the second high-k dielectric film 142B2.

[0050] As a result, Figure 6A As illustrated, each first internal spacer 190A can be disposed between the first interface insulating film 142A1 and the first high-k dielectric film 142A2. Similarly, refer to Figure 6B Each second internal spacer 190B can be disposed between the second interface insulating film 142B1 and the second high-k dielectric film 142B2.

[0051] In some embodiments, the first interface insulating film 142A1 and the second interface insulating film 142B1, as well as the first internal spacer 190A and the second internal spacer 190B, may be formed of different materials. For example, the first interface insulating film 142A1 and the second interface insulating film 142B1 may comprise silicon oxide, while the first internal spacer 190A and the second internal spacer 190B may comprise silicon nitride. In this case, the first interface insulating film 142A1 and the second interface insulating film 142B1 may comprise a first portion that contacts the first channel layer and the second channel layer, respectively, and a second portion that contacts the first internal spacer 190A and the second internal spacer 190B, and the first portion and the second portion may comprise different materials. For example, the first portion may still be silicon oxide, while the second portion may be silicon oxynitride diffused by nitrogen.

[0052] In contrast, similar to the previous embodiments, when the second internal spacer is introduced before the formation of the second source / drain pattern, the second internal spacer can be disposed between the second source / drain pattern and the second interface insulating film (see [reference]). Figure 10B ).

[0053] Figure 7 The illustration shows a cross-sectional view of a semiconductor device according to an example embodiment, and can be understood as... Figure 2 The corresponding cross-section.

[0054] refer to Figure 7 The semiconductor device 100B according to this embodiment can be understood as being related to Figures 1 to 4B The illustrated semiconductor device 100 is the same as or similar to the first transistor TR1, except that an internal spacer 190B is provided only in the second transistor TR2, and no internal spacer is provided in the first transistor TR1. Furthermore, the second source / drain pattern 150B also has a recessed portion 155B similar to the first source / drain pattern 150A. Additionally, unless otherwise stated, reference may be made to… Figures 1 to 4B The components of this embodiment are understood by describing the same or similar components of the illustrated semiconductor device 100.

[0055] In this embodiment, compared with the previous embodiment (see...), Figure 2 Similar to the second internal spacer of the second transistor TR2, the second transistor TR2 includes an internal spacer 190B having a protruding side surface facing a portion of the second gate structure GS2 adjacent to the second channel layer 132. The internal spacer 190B may be formed prior to the formation of the second source / drain pattern 150B. However, as with the previous embodiment (see...), Figure 2 Unlike the second source / drain pattern 150B, the second source / drain pattern 150B includes recessed portions 155B that are partially recessed toward the second gate structure GS2 adjacent to the second channel layer 132. These recessed portions 155B may overlap with the second channel layer 132 in the vertical direction. The recessed portions 155B can be formed by over-etching in a process that partially removes the insulating film to form the internal spacers 190B (see [link to documentation]). Figure 11C and Figure 11D ).

[0056] In this embodiment, the first transistor TR1 may include a first source / drain pattern 150A with a recessed portion, and the first transistor TR1 does not include internal spacers. The recessed portion 155A of the first source / drain pattern 150A may be formed toward a portion of the first gate structure GS1 adjacent to the first channel layer 131. In this embodiment, the first source / drain pattern 150A may include silicon germanium (SiGe), and the second source / drain pattern 150B may include silicon (Si). Specifically, when the sacrificial layer 122 is removed during the process of forming the first gate structure GS1 (see...), Figure 13B When the first transistor TR1 is in the first channel layer 131, the recessed portion 155A can protect the pre-formed first source / drain pattern 150A. Therefore, the first source / drain pattern 150A can stably apply compressive force to the first channel layer 131, thereby improving the mobility of the first channel layer 131.

[0057] In this embodiment, each first source / drain pattern 150A may include a first epitaxial layer connected to each side surface of the first channel layer 131 and a second epitaxial layer located on the first epitaxial layer, and the Ge concentration of the first epitaxial layer may be configured to be lower than the Ge concentration of the second epitaxial layer (see [link to documentation]). Figure 12A Therefore, during the removal process of the sacrificial layer 122, the recessed portion 155A can have sufficient selectivity to serve as a adequate buffer area.

[0058] Figure 8 This is a top view illustrating a semiconductor device according to an example embodiment. Figure 9 yes Figure 8 A cross-sectional view of a semiconductor device taken along line I2-I2', and Figure 10A and Figure 10B The diagrams are shown below. Figure 9 Enlarged views of parts “A3” and “B3” of the semiconductor device.

[0059] refer to Figure 8 , Figure 9 , Figure 10A and Figure 10B The semiconductor device 100C according to this embodiment can be understood as being similar to... Figures 1 to 4BThe illustrated semiconductor device 100 is identical or similar, except that the second internal spacer 190B has a first spacer portion 190B1 and a second spacer portion 190B2 with different structures. The second internal spacer 190B has a recessed side surface that contacts the second gate structure GS2. The first gate insulating layer 142A and the second gate insulating layer 142B respectively include a first interface insulating film 142A1 and a second interface insulating film 142B1, as well as a first high-k dielectric film 142A2 and a second high-k dielectric film 142B2. Other types of contact structures 220 and 230 are included, and the associated first interconnect structure 280 and second interconnect structure 290 are also illustrated. Additionally, unless otherwise stated, reference may be made to... Figures 1 to 4B The components of this embodiment are understood by describing the same or similar components of the illustrated semiconductor device 100.

[0060] In this embodiment, the first internal spacer has the same characteristics as in the previous embodiment (see...). Figure 4A and Figure 6A The same or similar structure. On the other hand, unlike the previous embodiment, the second internal spacer 190B has a first spacer portion 190B1 that contacts the second source / drain pattern 150B and a second spacer portion 190B2 that contacts the second gate structure GS2. The first spacer portion 190B1 has a protruding side surface CB2 facing the second spacer portion 190B2, while the second spacer portion 190B2 has a recessed side surface CB1 that contacts the second gate structure GS2.

[0061] In this embodiment, the first gate insulating layer 142A and the second gate insulating layer 142B may respectively include a first interface insulating film 142A1 and a second interface insulating film 142B1, and a first high-k dielectric film 142A2 and a second high-k dielectric film 142B2. (Reference) Figure 10A ,and Figure 6A The shapes shown in the illustrations are similar, and each first internal spacer 190A can be disposed between the first interface insulating film 142A1 and the first high-k dielectric film 142A2. On the other hand, reference... Figure 10B The first spacer portion 190B1 is disposed between the second source / drain pattern 150B and the second interface insulating film 142B1, and the second spacer portion 190B2 can be disposed between the second interface insulating film 142B1 and the second high-k dielectric film 142B2.

[0062] The first source / drain pattern 150A includes a recessed portion 155A that is recessed toward the first internal spacer 190A, and the side surface CA2 of each first internal spacer 190A facing the recessed portion 155A may also have a recessed side surface. The second source / drain pattern 150B includes a recessed portion 155B toward the second internal spacer 190B, and the side surface CB2 of each first spacer portion 190B1 facing the recessed portion 155B may also have a recessed side surface.

[0063] The semiconductor device 100C according to this embodiment may include a first interconnect structure 280 (also referred to as a "front interconnect structure") disposed on an interlayer insulating layer 180 and a second interconnect structure 290 (also referred to as a "back interconnect structure") disposed on the lower surface of a substrate 101. The first interconnect structure 280 includes a first interconnect insulating layer 281 disposed on the interlayer insulating layer 180 and a first interconnect line M1 disposed in the first interconnect insulating layer 281. The first interconnect line M1 can be connected to a first upper contact 210B or a second contact 220 via a metal passage.

[0064] Similarly, the second interconnect structure 290 includes a second interconnect insulating layer 291 disposed on the lower surface of the substrate 101 and a second interconnect line M2 disposed in the second interconnect insulating layer 291. The second interconnect line M2 may be a power line. In this embodiment, an etch stop layer 270 may be disposed between the substrate 101 and the second interconnect insulating layer 291. The etch stop layer 270 may be used in the process of forming the second interconnect line M2.

[0065] The lower contact structure 240 used in this embodiment can penetrate the substrate 101 and connect the first source / drain pattern 150A to the second interconnect M2. The lower contact structure 240 may include a conductive path 230 penetrating the substrate 101 and a conductive connection portion 220 obtained by selectively removing the buried insulating portion 220P. The buried insulating portion 220P may remain below the first source / drain pattern 150A where the lower contact structure 240 is not formed. The buried insulating portion 220P for forming the lower contact structure may be an obstacle to growing the epitaxial portion for the first source / drain pattern 150A, and in this structure, the method for improving crystallinity according to this embodiment (introducing the indentation portion 155A and / or the first internal spacer 190A) can be used more advantageously.

[0066] Hereinafter, a method for manufacturing a semiconductor device according to an example embodiment will be described.

[0067] Figures 11A to 11H and Figures 13A to 13D This is a cross-sectional view illustrating each major process of a method for manufacturing a semiconductor device according to an exemplary embodiment. The manufacturing method according to this embodiment... Figures 1 to 4B The illustrated method of manufacturing semiconductor device 100, and each cross-section can be understood as Figure 2 The corresponding drawing in the diagram.

[0068] In detail, Figures 11A to 11H This is a cross-sectional view of each major process used to describe the formation processes of the first source / drain pattern and the second source / drain pattern as part of a semiconductor device manufacturing method according to an example embodiment, and Figures 13A to 13D This is a cross-sectional view of the main process used to describe the formation process of the first gate structure and the second gate structure as another part of the semiconductor device manufacturing method according to the example embodiment.

[0069] First, refer to Figure 11A A fin stack structure is disposed on an active pattern 105 extending on a substrate 101 along a first direction (e.g., the X direction), and may include a dummy gate structure (DS) intersecting the fin stack structure in a second direction (e.g., the Y direction).

[0070] Each fin stack structure may include a first stack structure in which a first sacrificial layer 121 and a first channel layer 131 are alternately stacked, a second stack structure in which a second sacrificial layer 122 and a second channel layer 132 are alternately stacked on the first stack structure, and an intermediate sacrificial layer 165 located between the first stack structure and the second stack structure. The first channel layer 131 and the second channel layer 132 may include a semiconductor material to form channels for the first transistor and the second transistor. Each of the first channel layer 131 and the second channel layer 132 may include a semiconductor material having at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge). The first channel layer 131 and the second channel layer 132 may include impurities, but are not limited thereto. The intermediate sacrificial layer 165 may include at least one of SiO, SiN, SiCN, SiOC, SiON, SiOCN, SiBN, and SiBCN.

[0071] The first sacrificial layer 121 and the second sacrificial layer 122 may comprise different materials to have etch selectivity relative to the first channel layer 131 and the second channel layer 132. In some embodiments (e.g., when the first gate electrode and the second gate electrode are formed of different gate electrode materials), the first sacrificial layer 121 may comprise a different material than the second sacrificial layer 122 to have etch selectivity. For example, the first sacrificial layer 121 and the second sacrificial layer 122 may comprise silicon germanium (SiGe), while the first channel layer 131 and the second channel layer 132 may comprise silicon (Si). In some embodiments, the number of alternately stacked first sacrificial layer 121 and the first channel layer, and the second sacrificial layer 122 and the second channel layer 132 may vary.

[0072] Dummy gate structures DS and gate spacers 141 can be formed on a fin stack structure. Each dummy gate structure DS can be a sacrificial structure that provides space for forming a gate structure GS to be formed in a subsequent process. The dummy gate structures DS are in the shape of a line that intersects the fin stack structure and extends in a second direction (e.g., the Y direction), and can be arranged to be spaced apart from each other in a first direction (e.g., the X direction).

[0073] The dummy gate structure DS may include a first dummy material layer 242 and a second dummy material layer 245 sequentially stacked, and a mask patterning layer 247. The first dummy material layer 242 and the second dummy material layer 245 may be patterned using the mask patterning layer 247. The first dummy material layer 242 and the second dummy material layer 245 may be an insulating layer and a conductive layer, respectively, but are not limited thereto, and the first dummy material layer 242 and the second dummy material layer 245 may be formed as a single layer. In some embodiments, the first dummy material layer 242 may include silicon oxide, while the second dummy material layer 245 may include polysilicon. The mask patterning layer 247 may include silicon oxide and / or silicon nitride.

[0074] Gate spacers 141 can be formed on the two sidewalls of the dummy gate structure DS. Gate spacers 141 can be formed by forming a film of uniform thickness along the upper and side surfaces of the substrate on which the dummy gate structure DS is formed, followed by anisotropic etching of the film. Gate spacers 141 can be formed of a low-dielectric-constant material and can include at least one of, for example, SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0075] Next, refer to Figure 11B The first recess RS1 can be formed by partially removing the portion of the fin stack structure between the dummy gate structure DS up to the active pattern 105.

[0076] In this process, the first recess RS1 can be formed using a dummy gate structure DS and gate spacer 141 as a mask such that the intermediate sacrificial layer 165 is exposed in the exposed region of the fin stack structure. Through this process, the second channel layer 132 is etched together with the second sacrificial layer 122 and can have the desired length along a first direction (e.g., the X direction). The first recess RS1 is provided as a region for forming the first source / drain pattern, and the side surfaces of the second channel layer 132 and the second sacrificial layer 122 can be exposed by the first recess RS1. The recessed region D1 can be formed by additionally etching both ends of the second sacrificial layer 122 during the process of forming the first recess RS1 or by a separate additional process. The recessed region D1 can define the region for forming the second internal spacer. Since the surface of the recessed portion has a protruding surface during the etching process, the second internal spacer 190B formed in this region can also have a protruding side surface.

[0077] Next, refer to Figure 11C A spacer insulating layer 191 is formed on the surface exposed by the first recess RS1 to fill the recessed region D1 of the second sacrificial layer 122.

[0078] The spacer insulating layer 191 may be conformally formed on the exposed surface. Specifically, the spacer insulating layer 191 may fill the recessed region. The spacer insulating layer 191 may include silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), or silicon carbide nitride (SiCN).

[0079] Next, refer to Figure 11D The second internal spacer 190B is formed by using an etching process, and the first channel layer 131 and the first sacrificial layer 121 are selectively removed to form the second recess (RS2).

[0080] The second internal spacer 190B can be formed by removing the sidewalls of the second channel layer 132 and the portion of the spacer insulating layer 191 located on the bottom surface of the first recess RS1. In this process, the exposed portion of the second internal spacer 190B can be further etched to have a recessed structure (see...). Figure 7 This etching process can be performed using anisotropic etching processes such as dry etching.

[0081] Additionally, a dummy gate structure DS and gate spacer 141 are used as masks to partially etch the first channel layer 131, the first sacrificial layer 121, and the intermediate sacrificial layer 165, thereby forming a second recess RS2. Through the second recess RS2, the side surfaces of the first channel layer 131 and the first sacrificial layer 121 can be exposed together with the bottom surface of the active pattern 105.

[0082] The recessed region D2 can be formed either by additionally etching both ends of the first sacrificial layer 121 during the process of forming the second recess RS2, or by a separate additional process. The recessed region D2 can be... Figure 2 and Figure 3A The recessed portion 155A of the first source / drain pattern 150A shown in the figure provides space.

[0083] Next, refer to Figure 11E The second recess RS2 is filled with a gap-filling insulating material, which is then etched back. A gap-filling insulating pattern 250 corresponding to the first source / drain pattern can be formed in each second recess RS2.

[0084] Gap-filling insulating material can be deposited to fill the spaces between the dummy gate structures DS. For example, the gap-filling insulating material can be silicon oxide, such as a spin-on hard mask (SOH). The gap-filling insulating pattern 250 with the desired height can be formed by depositing the gap-filling insulating material through an etch-back process. The gap-filling insulating pattern 250 can be formed to have an upper surface height that at least covers the side surfaces of the first channel layer 131. In this embodiment, the upper surface height of the gap-filling insulating pattern 250 can be formed to overlap with the intermediate sacrificial layer 165 in the horizontal direction.

[0085] Next, refer to Figure 11F A barrier insulating layer 260 is formed on the exposed sidewall portion of the dummy gate structure DS, and the gap-filling insulating pattern 250 can be removed to open the region where the first source / drain pattern will be formed.

[0086] A barrier insulating layer 260 is conformally formed over the entire region as a barrier insulating material. Specifically, the barrier insulating material film is formed not only on the sidewalls of the dummy gate structure DS, but also on the upper surface of the dummy gate structure DS and the bottom surface therebetween (e.g., the upper surface of the gap-filling insulating pattern 250). The barrier insulating material layer may include a dielectric material that inhibits epitaxial growth. For example, it may include silicon nitride (SiN), silicon oxynitride (SiON), or silicon carbide nitride (SiCN). Then, an anisotropic etching process, such as dry etching, is applied to remove portions of the barrier insulating material film located on the upper surface of the dummy gate structure DS and the gap-filling insulating pattern 250, and as... Figure 11F As illustrated, the barrier insulating layer 260 may remain on the exposed sidewall portion of the dummy gate structure DS. The barrier insulating layer 260 may be configured to cover the sidewall portion of the dummy gate structure DS and the side surface of the second channel layer 132.

[0087] Next, the gap-filling insulating pattern 250 can be removed to open up the area where the first source / drain pattern will be formed. For example, the bottom of the active pattern 105 and the side surfaces of the first channel layer 131 can be exposed.

[0088] Next, refer to Figure 11G It can perform the process of forming the first source / drain pattern 150A.

[0089] The first source / drain pattern 150A can be formed epitaxially from the side surface of the first channel layer 131 in the second recess RS2. On the other hand, epitaxial layer growth can be suppressed in the region where the barrier insulating layer 260 is formed. In this embodiment, the lower end of the barrier insulating layer 260 can be slightly spaced from the first source / drain pattern 150A. A portion of the isolation insulating layer 170 can be located in the spaced-out region in a subsequent process.

[0090] In this embodiment, each first source / drain pattern 150A may include a first epitaxial layer 150A1 connected to each side surface of the first channel layer 131 and a second epitaxial layer 150A2 located on the first epitaxial layer 150A1, and the Ge concentration of the first epitaxial layer 150A1 may be configured to be lower than the Ge concentration of the second epitaxial layer 150A2.

[0091] refer to Figure 12A In this process, the side surface of the first sacrificial layer 121, together with the side surface of the first channel layer 131, serves as the epitaxial growth surface of the first source / drain pattern 150A. Therefore, the first epitaxial layer 150A1 can grow relatively high-quality crystals from the side surfaces of the first sacrificial layer 121 and the first channel layer 131.

[0092] Additionally, the first epitaxial layer 150A1 can be grown in the recessed region D2 of the first sacrificial layer 121 to form a recessed portion 155A of the first source / drain pattern 150A. When the first sacrificial layer 121 is later removed (see...), Figure 13B When this indentation 155A is used, it can serve as a buffer area.

[0093] Next, refer to Figure 11H After removing the blocking insulation layer 260, an isolation insulation layer 170 is formed to cover the surface of the first source / drain pattern 150A, and subsequently, a second source / drain pattern 150B is formed.

[0094] The second source / drain pattern 150B can be formed by epitaxial growth from the side surface of the second channel layer 132 in the first recess RS1. In this process, unlike the epitaxial growth of the first source / drain pattern 150A, the second internal spacer 190B is formed on the side surface of the second sacrificial layer 122, and as... Figure 12B As illustrated, the epitaxial growth of the second source / drain pattern 150B is only grown on the side surface of the second channel layer 132, and the portion grown on the side surface of the second channel layer 132 is merged onto the second internal spacer 190B to form the desired second source / drain pattern 150B. During this merging process, defects such as dislocations may occur significantly.

[0095] In contrast, since the first source / drain pattern 150A is grown from the side surfaces of the first sacrificial layer 121 and the first channel layer 131 before the formation of internal spacers, as Figure 12A As described, a relatively high-quality crystal can be obtained without many crystal defects. Therefore, the first source / drain pattern 150A can be configured to apply sufficient compressive force to improve the mobility of the first channel layer.

[0096] Figures 13A to 13D It is a cross-sectional view used to describe each major process of another part of the semiconductor device manufacturing method according to the example embodiment (the formation of the first gate structure and the second gate structure).

[0097] refer to Figure 13A An interlayer insulating layer 180 is formed, and a polishing process is performed at a constant height PL to expose the second dummy material layer 245. Next, refer to... Figure 13B The first dummy material layer 242 and the second dummy material layer 245, as well as the first sacrificial layer 121 and the second sacrificial layer 122, are removed to form the upper gap region UR and can form the first lower gap region LR1 and the second lower gap region LR2.

[0098] In some embodiments, after removing the first dummy material layer 242 and the second dummy material layer 245, the intermediate sacrificial layer 165 may be removed first, and an intermediate insulating pattern 160 may be formed. Selective removal of the intermediate sacrificial layer 165 may be achieved by configuring the Ge concentration to be higher than that of the first sacrificial layer 121 and the second sacrificial layer 122.

[0099] Next, the first sacrificial layer 121 and the second sacrificial layer 122 can be removed to form the first lower gap region LR1 and the second lower gap region LR2. In this process, the second source / drain pattern 150B is protected by the second internal spacer 190B, and in the first lower gap region LR1, essentially the entire region can be protected by the recessed portion 155A of the first source / drain pattern 150A. Specifically, since the recessed portion 155A is composed of a first epitaxial layer with a relatively low Ge concentration ( Figure 12AThe first source / drain pattern 150A is composed of 150A1, so substantial damage to the first source / drain pattern 150A can be limited and / or prevented during the process of removing the first sacrificial layer 121. In the final structure, the recessed portion 155A of the first source / drain pattern 150A is partially etched away, but some portions may be retained. In some embodiments, the recessed portion 155A of the first source / drain pattern 150A may be substantially removed.

[0100] Next, refer to Figure 13C A first internal spacer 190A can be formed in the first lower gap region LR1, and then a first gate structure GS1 can be formed.

[0101] The first internal spacer can be achieved by repeatedly performing deposition and etching processes. Specifically, an insulating film is formed on the inner surface of the first lower gap region LR1 using a deposition process such as atomic layer deposition. In the first lower gap region LR1, the first film portions located at both ends in a first direction (e.g., the X direction) can be deposited to a thickness relatively greater than the thickness of the second film portions on the upper and lower surfaces of the first channel layer, and the first film portions can be retained even if the relatively thin second film portions are removed during the etching process. By repeating these deposition and etching processes, the desired first internal spacer 190A can be formed. Through this process, each first internal spacer 190A can have a side surface CA1 recessed toward the center of the first lower gap region LR1.

[0102] A first gate structure GS1 can be formed to fill the first lower gap region LR1 by forming a first gate insulating layer 142A around the first channel layer 131 and forming a first gate electrode 145A on the first gate insulating layer 142A.

[0103] Next, refer to Figure 13D A second gate structure GS2 can be formed in the second lower gap region LR2 and the upper gap region UR.

[0104] A second gate structure GS2 can be formed to fill the second lower gap region LR2 by forming a second gate insulating layer 142B surrounding the second channel layer 132 and forming a second gate electrode 145B on the second gate insulating layer 142B. In the second gate structure GS2, after filling the second gate insulating layer 142B and the second gate electrode 145B between the gate spacers 141 and partially etching back the second gate electrode 145B, a gate capping layer 147 can be formed. Next, it can be manufactured by forming contact structures 210A, 210B, and 220. Figure 2 The semiconductor device 100 shown in the figure.

[0105] As explained above, at least the first transistor, unlike the second transistor located above it, has a first internal spacer introduced during the gate structure formation process following the formation of the first source / drain pattern. Therefore, the crystallinity of the first source / drain pattern (e.g., SiGe) can be improved, and as a result, the forces induced by the first source / drain pattern can be preserved by reducing defects.

[0106] On the other hand, in the process of manufacturing the first internal spacer, a structure (recess) can be provided that is recessed toward the gate structure of the first source / drain pattern to reduce unnecessary loss of the first source / drain pattern when the sacrificial layer (e.g., SiGe) is removed.

[0107] Although exemplary embodiments have been described and illustrated above, it will be clear to those skilled in the art that modifications and variations can be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor device, the semiconductor device comprising: Substrate, the substrate comprising an active pattern; First channel layers, the first channel layers being spaced apart from each other in a vertical direction on the active pattern, the vertical direction being perpendicular to the upper surface of the substrate; A first gate structure, the first gate structure surrounding the first channel layer; The first source / drain pattern is located on both sides of the first gate structure and connected to the first channel layer; A first internal spacer is located between the first gate structure and the first source / drain pattern; The second channel layer is spaced apart from each other on the first channel layer along the vertical direction; A second gate structure is located on the first gate structure and surrounds the second channel layer; The second source / drain pattern is located on both sides of the second gate structure and connected to the second channel layer; as well as The second internal spacer is located between the second gate structure and the second source / drain pattern, and the shape of the second internal spacer is different from that of the first internal spacer.

2. The semiconductor device according to claim 1, wherein, The first source / drain pattern comprises silicon-germanium, and The second source / drain pattern comprises silicon.

3. The semiconductor device according to claim 1, wherein, The side surface of the first internal spacer is recessed and faces the portion of the first gate structure.

4. The semiconductor device according to claim 1, wherein, The first source / drain pattern includes an indentation. The recessed portion of the first source / drain pattern is recessed toward a portion of the first gate structure, and The recessed portion of the first source / drain pattern overlaps with the first channel layer in the vertical direction.

5. The semiconductor device according to claim 4, wherein, The first internal spacer has a recessed side surface, and the side surface of the first internal spacer faces the recessed portion of the first source / drain pattern.

6. The semiconductor device according to claim 1, wherein, The side surface of the second internal spacer protrudes towards a portion of the second gate structure.

7. The semiconductor device according to claim 1, wherein, The second source / drain pattern includes an indentation. The recessed portion of the second source / drain pattern is recessed toward a portion of the second gate structure, and The recessed portion of the second source / drain pattern overlaps with the second channel layer in the vertical direction.

8. The semiconductor device according to claim 7, wherein, The second internal spacer has a recessed side surface, and the side surface of the second internal spacer faces the recessed portion of the second source / drain pattern.

9. The semiconductor device according to claim 1, wherein, The first gate structure includes a first gate electrode and a first gate insulating layer. The first gate electrode surrounds the first channel layer. The first gate insulating layer is located between the first gate electrode and the first channel layer. The first gate insulating layer includes a first interface insulating film and a first high-k dielectric film located on the first interface insulating film, and The first internal spacer is located between the first interface insulating film and the first high-k dielectric film.

10. The semiconductor device according to claim 1, wherein, The second gate structure includes a second gate electrode and a second gate insulating layer. The second gate electrode surrounds the second channel layer. The second gate insulating layer is located between the second gate electrode and the second channel layer. The second gate insulating layer includes a second interface insulating film and a second high-k dielectric film located on the second interface insulating film. The second internal spacer is located between the second source / drain pattern and the second interface insulating film. The first portion of the second interface insulating film is located on the second channel layer. The second portion of the second interface insulating film is located on the second internal spacer. The first portion of the second interface insulating film and the second portion of the second interface insulating film comprise different materials.

11. The semiconductor device according to claim 1, wherein, The portion of the recessed side surface of the first internal spacer facing the first gate structure. The recessed side surface of the second internal spacer faces the portion of the second gate structure, and The width of the first internal spacer is different from the width of the second internal spacer.

12. The semiconductor device according to claim 11, wherein, The first source / drain pattern includes an indentation. The recessed portion of the first source / drain pattern is recessed toward a portion of the first gate structure, and The recessed portion of the first source / drain pattern overlaps with the first channel layer in the vertical direction.

13. The semiconductor device according to claim 12, wherein, The second source / drain pattern includes an indentation. The recessed portion of the second source / drain pattern is recessed towards a portion of the second gate structure. The recessed portion of the second source / drain pattern overlaps with the second channel layer in the vertical direction, and The length of the recessed portion of the first source / drain pattern is different from the length of the recessed portion of the second source / drain pattern.

14. A semiconductor device, the semiconductor device comprising: Substrate, the substrate comprising an active pattern; First channel layers, the first channel layers being spaced apart from each other in a vertical direction on the active pattern, the vertical direction being perpendicular to the upper surface of the substrate; A first gate structure, the first gate structure surrounding the first channel layer; The first source / drain pattern is located on both sides of the first gate structure and connected to the first channel layer; A first internal spacer is located between the first gate structure and the first source / drain pattern, and the recessed side surface of the first internal spacer is in contact with the first gate structure. The second channel layer is spaced apart from each other on the first channel layer along the vertical direction; A second gate structure, wherein the second gate structure surrounds the second channel layer on the first gate structure; The second source / drain pattern is located on both sides of the second gate structure and connected to the second channel layer; as well as The second internal spacer is located between the second gate structure and the second source / drain pattern, and each of the second internal spacers includes a first spacer portion that contacts the second source / drain pattern and a second spacer portion that contacts the second gate structure.

15. The semiconductor device according to claim 14, wherein, The side surface of the first spacer portion is convex and contacts the second spacer portion.

16. The semiconductor device according to claim 14, wherein, The first gate structure includes a first gate insulating layer and a first high-k dielectric film. The first gate insulating layer includes a first interface insulating film surrounding the first channel layer. The first high-k dielectric film is located on the first interfacial insulating film, and The first internal spacer is located between the first interface insulating film and the first high-k dielectric film.

17. The semiconductor device according to claim 14, wherein, The second gate structure includes a second gate insulating layer and a second high-k dielectric film. The second gate insulating layer includes a second interface insulating film surrounding the second channel layer. The second high-k dielectric film is located on the second interfacial insulating film, and The second spacer portion is located between the second interface insulating film and the second high-k dielectric film.

18. A semiconductor device, the semiconductor device comprising: Substrate, the substrate comprising an active pattern; First channel layers, the first channel layers being spaced apart from each other in a vertical direction on the active pattern, the vertical direction being perpendicular to the upper surface of the substrate; A first gate structure, the first gate structure surrounding the first channel layer; A first source / drain pattern is located on both sides of the first gate structure. The first source / drain pattern is connected to the first channel layer. The first source / drain pattern includes a recessed portion, and the recessed portion of the first source / drain pattern is partially recessed toward the first gate structure. The second channel layer is spaced apart from each other on the first channel layer along the vertical direction; A second gate structure, wherein the second gate structure surrounds the second channel layer on the first gate structure; The second source / drain pattern is located on both sides of the second gate structure and connected to the second channel layer; as well as An internal spacer is located between the second gate structure and the second source / drain pattern.

19. The semiconductor device of claim 18, wherein, The first source / drain pattern comprises silicon-germanium, and The second source / drain pattern comprises silicon.

20. The semiconductor device of claim 19, wherein, Each of the first source / drain patterns includes a first epitaxial layer and a second epitaxial layer located on the first epitaxial layer. The first epitaxial layer is connected to a corresponding side surface of a first channel layer in the first channel layer. The germanium concentration of the second epitaxial layer is higher than that of the first epitaxial layer.

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