Composite wafer and preparation method thereof

Abstract

The invention discloses a composite wafer and a preparation method thereof, and the preparation method comprises the steps: S1, cutting a non-silicon optoelectronic material into crystal grains, and enabling the crystal grains to be pasted on a slide through temporary bonding glue, and obtaining a slide wafer; s2, carrying out wafer bonding on the slide wafer and a target wafer A, and then carrying out heat treatment to obtain a bonded wafer A; s3, carrying out de-bonding on the bonded wafer A to obtain a composite wafer A; s4, ions are injected into the crystal grains on the composite wafer A, then the composite wafer A and the target wafer B are bonded, and a wafer complex is obtained; and S5, carrying out heating treatment on the wafer composite body to expand the injected ions to obtain a composite wafer A'and a composite wafer B. According to the preparation method of the composite wafer, the problem of wafer size mismatch during heterogeneous integration of the non-silicon optoelectronic material and the large-size target wafer is solved, the purpose of preparing a plurality of composite wafers by repeatedly utilizing the same non-silicon optoelectronic material is achieved, and the cost is effectively reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a composite wafer and a method for preparing the same. Background Technology

[0002] Integrated optoelectronic chip technology, represented by silicon-based optoelectronics, has made remarkable progress over the past 20 years. With the rapid development of artificial intelligence (AI) chips, data centers, 5G / 6G, and LiDAR in recent years, leading to higher demands for communication bandwidth and optoelectronic integration, integrated optoelectronic chips are widely recognized as one of the most promising technological development directions. Against this backdrop, non-silicon optoelectronic materials such as indium phosphide (InP), lithium niobate (LiNbO3), and lithium tantalate (LiTaO3), as well as integrated photonic circuit (PIC) chip technology, have all made significant progress. For example, PIC chips, based on the non-silicon optoelectronic material indium phosphide (InP) as an integration platform, can simultaneously integrate high-performance semiconductor lasers, optical modulators, photodetectors, passive optical waveguide circuits, and other active and passive optoelectronic devices necessary for photonic integration, exhibiting high integration and relatively mature related technologies. Compared to PIC chips that use non-silicon optoelectronic materials as an integration platform, silicon photonic chips have passive optical waveguides with moderate loss levels, optical modulators with moderate modulation bandwidth, and photodetectors with basically equivalent performance (photodetectors using germanium epitaxial layers), but they lack directly integrateable semiconductor lasers. Therefore, silicon photonic chips that integrate non-silicon optoelectronic materials onto silicon wafers have become one of the important development directions in the current optoelectronic integration field. Meanwhile, composite wafers obtained by integrating non-silicon optoelectronic materials onto silicon wafers through wafer bonding technology have even broader application prospects due to the achievement of heterogeneous integration.

[0003] Currently, non-silicon optoelectronic materials such as indium phosphide (InP), lithium niobate (LiNbO3), and lithium tantalate (LiTaO3) are difficult to fabricate into large-size wafers, especially those with a diameter ≥150mm. This leads to wafer size mismatch issues when heterogeneously integrating them with large-size target wafers, making it difficult to fabricate composite wafers with a diameter ≥150mm. Furthermore, due to the high cost of non-silicon optoelectronic materials, reusing the same non-silicon optoelectronic material to fabricate multiple large-size wafers can effectively reduce costs.

[0004] Therefore, it is of great significance to develop a composite wafer fabrication method that can prepare multiple composite wafers with a diameter ≥150mm by solving the wafer mismatch problem and reusing the same non-silicon optoelectronic material. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a composite wafer and its preparation method.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] In a first aspect, the present invention provides a method for preparing a composite wafer, the method comprising the following steps:

[0008] S1. Cut the non-silicon optoelectronic material into granules and attach the granules to the carrier wafer with temporary bonding adhesive to obtain the carrier wafer;

[0009] S2. Perform wafer bonding between the carrier wafer and the target wafer A, so that the grain is located between the carrier wafer and the target wafer A, and then perform heat treatment to obtain the bonded wafer A;

[0010] S3. Debond the bonded wafer A, separate the grains from the carrier, and leave the grains on the target wafer A to obtain the composite wafer A;

[0011] S4. Ions are implanted into the grains on the composite wafer A, and then composite wafer A and target wafer B are bonded together so that the grains are located between target wafer A and target wafer B, thus obtaining a wafer composite.

[0012] S5. The wafer composite is heated to cause the implanted ions to expand, and the grains break apart into two layers located on target wafer A and target wafer B respectively, to obtain composite wafer A' with grains located on target wafer A and composite wafer B with grains located on target wafer B;

[0013] The diameter of target wafer A is ≥150mm, and the diameter of target wafer B is ≥150mm.

[0014] The present invention provides a method for fabricating composite wafers by cutting non-silicon optoelectronic materials into grains and then dispersing them onto a target wafer with a diameter ≥150mm. This solves the wafer size mismatch problem that occurs when non-silicon optoelectronic materials are heterogeneously integrated with large-size target wafers. Furthermore, steps S4-S5 of the present invention enable the reuse of the same non-silicon optoelectronic material to fabricate multiple composite wafers, effectively reducing costs.

[0015] The reason why this invention first bonds the grains to the target wafer to obtain a composite wafer, and then prepares multiple composite wafers, is that compared with the method of first preparing multiple grains (achieving the preparation of multiple grains by ion implantation to disconnect the grains) and then bonding them to the target wafer to prepare multiple composite wafers, the method of this invention makes it easier to fully recycle the grain material. In particular, the operation of first composite the grains with the wafer and then breaking and dividing them can maximize the utilization of each grain and is less likely to cause the grains to break due to being first divided into thin, difficult-to-handle sheets and then transferred and composited to the wafer. Moreover, the method of this invention is not limited by the source of the grains, the size of the substrate, and the size of the target wafer. At the same time, the composite wafer made by bonding the grains to the target wafer has high strength, can withstand multiple subsequent process steps, and is not prone to grain detachment.

[0016] The reason why ions are implanted into the die in step S4 instead of directly implanting ions into the die in step S1 is that temporary bonding adhesive is used to attach the die to the carrier in step S1. However, temporary bonding adhesive may not be able to withstand the ion implantation process. Ion implantation may affect the adhesion of the temporary bonding adhesive, causing the bonded die to fall off, which is not conducive to withstanding subsequent multiple process steps.

[0017] Preferably, the diameters of the target wafers A and B are one or any two of the following values: 150mm, 160mm, 170mm, 180mm, 190mm, 200mm, 210mm, 220mm, 230mm, 240mm, 250mm, 260mm, 270mm, 280mm, 290mm, 300mm, 310mm, 320mm, 330mm, 340mm, and 350mm.

[0018] In step S1 of this invention, any non-silicon optoelectronic material commonly used in the art can be used in this invention. For example, the non-silicon optoelectronic material is at least one of indium phosphide (InP), lithium niobate (LiNbO3), lithium tantalate (LiTaO3), gallium arsenide (GaAs), and gallium nitride (GaN).

[0019] Preferably, in step S1, the non-silicon optoelectronic material is double-sided polished before cutting to make the surface roughness ≤1nm.

[0020] More preferably, the surface roughness is ≤0.5nm.

[0021] In step S1 of this invention, the shape and size of the grain depend on actual needs. For example, the grain shape can be square or rectangular, and the grain area can be 1-800 mm². 2 The thickness of the grains is ≤1mm.

[0022] In step S1 of the present invention, the mounting spacing and density of the grains on the substrate depend on actual requirements.

[0023] Preferably, in step S1, the substrate is made of at least one of silicon, quartz, and glass.

[0024] Preferably, in step S1, the shape of the carrier is a circle with a diameter ≥ 150 mm.

[0025] Preferably, in step S1, the thickness of the carrier is 0.5-1.5 mm.

[0026] In step S1 of this invention, the surface roughness of the substrate is ≤1 nm and the total thickness variation (TTV) is ≤15 μm. Specifically, the surface roughness of the substrate is ≤0.5 nm.

[0027] In step S1 of this invention, any temporary bonding adhesive commonly used in the art can be used in this invention. For example, the temporary bonding adhesive includes at least one of thermoplastic temporary bonding adhesive and laser temporary bonding adhesive.

[0028] In step S2 of the present invention, the carrier wafer and the target wafer A are cleaned before use.

[0029] Preferably, in step S2, the target wafer A contains at least one of elemental silicon and silicon dioxide.

[0030] Preferably, in step S2, the surface roughness of the target wafer A is ≤1nm.

[0031] More preferably, the surface roughness of the target wafer A is ≤0.5nm.

[0032] Preferably, in step S2, the thickness of the target wafer A is 0.5-1.5 mm.

[0033] Preferably, in step S2, the wafer bonding process includes activating the carrier wafer and the target wafer A with plasma, and then cleaning the carrier wafer and the target wafer A respectively.

[0034] In step S2 of this invention, activating the carrier wafer and the target wafer A with plasma can enhance the bonding energy of the initial bonding, which is beneficial to improving the bonding yield.

[0035] More preferably, the gas used for plasma activation is at least one of nitrogen and oxygen.

[0036] More preferably, the plasma power of the plasma-activated plasma is 20-100W.

[0037] More preferably, the plasma activation time is 0.5-10 min.

[0038] More preferably, the cleaning method is mega-sound cleaning.

[0039] More preferably, the cleaning agent used for the cleaning is water.

[0040] Preferably, in step S2, the temperature of the heat treatment is 100-250℃.

[0041] Preferably, in step S2, the heat treatment time is 2-6 hours.

[0042] In step S2 of this invention, heat treatment after wafer bonding can enhance the bonding strength between the grain and the target wafer A, so that the grain is stably attached to the target wafer A, which is beneficial to subsequent operations and can improve the processing performance of the composite wafer.

[0043] In step S3 of this invention, any debonding method commonly used in the art can be used in this invention. For example, the debonding method includes at least one of thermal separation debonding, thermal slip debonding, and laser debonding.

[0044] Preferably, in step S3, the debonding temperature is 150-280℃.

[0045] Preferably, in step S3, after debonding, the process further includes cleaning the grains.

[0046] More preferably, the cleaning refers to cleaning the temporary bonding adhesive remaining on the grains with an organic solvent.

[0047] More preferably, the organic solvent includes at least one of acetone, isopropanol, dimethyl sulfoxide, and N-methylpyrrolidone.

[0048] More preferably, after cleaning the grains, heat treatment is also included.

[0049] More preferably, the temperature of the heat treatment is 200-450°C.

[0050] More preferably, the heat treatment time is 1-6 hours.

[0051] In step S3 of this invention, since debonding and cleaning the grains can easily damage the bonding strength between the grains and the target wafer A, heat treatment after debonding and cleaning the grains can repair and further strengthen the bonding strength between the grains and the target wafer A, making the grains more stably attached to the target wafer A, which is more conducive to subsequent operations and can further improve the processing performance of the composite wafer.

[0052] Preferably, in step S4, the ion is at least one of H ions and He ions.

[0053] In step S4 of this invention, the implantation energy and dosage of the ions depend on the actual requirements for the grain thickness in the product. For example, if it is necessary to transfer a non-silicon optoelectronic material with a thickness of 500 nm onto the target wafer B, the required H and / or He ion implantation energy can be calculated based on the constituent elements of the non-silicon optoelectronic material, typically 100-300 keV.

[0054] Preferably, in step S4, the target wafer B contains at least one of elemental silicon and silicon dioxide.

[0055] Preferably, in step S4, the surface roughness of the target wafer B is ≤1nm.

[0056] More preferably, the surface roughness of the target wafer B is ≤0.5nm.

[0057] Preferably, in step S4, the thickness of the target wafer B is 0.5-1.5 mm.

[0058] Preferably, in step S4, the bonding process includes cleaning the composite wafer A and the target wafer B, activating the composite wafer A and the target wafer B with plasma, and then cleaning the composite wafer A and the target wafer B.

[0059] In step S4 of this invention, activating the composite wafer A and the target wafer B with plasma can enhance the bonding energy of the initial bonding, which is beneficial to improving the bonding yield.

[0060] More preferably, the gas used for plasma activation is at least one of nitrogen and oxygen.

[0061] More preferably, the plasma power of the plasma-activated plasma is 20-100W.

[0062] More preferably, the plasma activation time is 0.5-5 min.

[0063] More preferably, the cleaning method is mega-sound cleaning.

[0064] More preferably, the cleaning agent used for the cleaning is water.

[0065] Preferably, in step S5, the temperature of the heat treatment is 150-250°C.

[0066] In step S5 of this invention, the wafer composite is heated, and the implanted ions expand to cause debonding.

[0067] Preferably, in step S5, the obtained composite wafer B is cleaned and then annealed.

[0068] More preferably, the annealing temperature is 200-450℃.

[0069] In step S5 of this invention, annealing the composite wafer B can enhance the bonding strength between the grains and the target wafer B, making the grains stably attached to the target wafer B, which is beneficial for subsequent operations and can improve the processing performance of the composite wafer.

[0070] In step S5 of the present invention, the obtained composite wafer A' and composite wafer B are subjected to chemical mechanical polishing to remove surface defects caused by ion implantation.

[0071] Preferably, the method for preparing the composite wafer further includes step S6. Repeating steps S4-S5 multiple times for composite wafers A' and / or B.

[0072] In the method for preparing composite wafers of the present invention, multiple composite wafers with a diameter ≥150mm can be prepared by repeating steps S4-S5 multiple times on composite wafers A' and / or B. The preparation method is simple to operate, can improve production efficiency, and is conducive to reducing production costs.

[0073] In a second aspect, the present invention provides a composite wafer prepared by the preparation method described in the first aspect. The composite wafer includes a target wafer and a grain, wherein the grain is disposed on the surface of the target wafer and the diameter of the target wafer is ≥150mm.

[0074] Preferably, the diameter of the target wafer is one or any two of the following: 150mm, 160mm, 170mm, 180mm, 190mm, 200mm, 210mm, 220mm, 230mm, 240mm, 250mm, 260mm, 270mm, 280mm, 290mm, 300mm, 310mm, 320mm, 330mm, 340mm, and 350mm.

[0075] Preferably, the target wafer contains at least one of elemental silicon and silicon dioxide.

[0076] More preferably, the elemental silicon and / or silicon dioxide is located on the surface of the target wafer.

[0077] Preferably, the surface roughness of the target wafer is ≤1nm.

[0078] More preferably, the surface roughness of the target wafer is ≤0.5nm.

[0079] Preferably, the thickness of the target wafer is 0.5-1.5 mm.

[0080] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0081] The present invention provides a method for fabricating composite wafers by cutting non-silicon optoelectronic materials into grains and then dispersing them onto a target wafer with a diameter ≥150mm. This solves the wafer size mismatch problem that occurs when non-silicon optoelectronic materials are heterogeneously integrated with large-size target wafers. Furthermore, steps S4-S5 of the present invention enable the reuse of the same non-silicon optoelectronic material to fabricate multiple composite wafers, effectively reducing costs. Attached Figure Description

[0082] Figure 1 This is a schematic diagram of the non-silicon optoelectronic material after cutting according to the present invention;

[0083] Figure 2 This is a schematic diagram of a substrate coated with temporary bonding adhesive according to the present invention;

[0084] Figure 3 This is a schematic diagram of the process for mounting dies on a substrate according to the present invention;

[0085] Figure 4 This is a schematic diagram of the process for wafer bonding between the carrier wafer and the target wafer A in this invention;

[0086] Figure 5 This is a schematic diagram of the process for debonding bonded wafer A according to the present invention;

[0087] Figure 6 This is a schematic diagram of H-ion implantation into the grains on composite wafer A according to the present invention;

[0088] Figure 7 This is a schematic diagram of the bonding process between composite wafer A and target wafer B according to the present invention.

[0089] Figure 8 This is a schematic diagram of the process for preparing composite wafer A' and composite wafer B from wafer composites according to the present invention;

[0090] In the figure, 1-grain, 2-carrier, 3-temporary bonding adhesive, 4-target wafer A, 5-target wafer B, 6-composite wafer A', 7-composite wafer B. Detailed Implementation

[0091] To better illustrate the purpose, technical solution, and advantages of the present invention, the present invention will be further described below in conjunction with specific embodiments.

[0092] The experimental methods in the following examples, unless otherwise specified, are generally performed under conventional conditions in the art or as recommended by the manufacturer; the raw materials and reagents used, unless otherwise specified, are all commercially available from the conventional market.

[0093] Example 1

[0094] This embodiment provides a method for preparing a composite wafer, the method comprising the following steps:

[0095] S1. The non-silicon optoelectronic material indium phosphide (InP) (circular with a diameter of 100 mm and a thickness of 0.5 mm) is polished on both sides to achieve a surface roughness of ≤0.5 nm, and then cut into grains (square with an area of ​​25 mm²). 2 (thickness = 0.5mm), such as Figure 1 As shown; temporary bonding adhesive (thermoplastic temporary bonding adhesive) is coated onto a cleaned substrate (material: silicon, circular with a diameter of 300 mm, thickness = 0.725 mm, surface roughness ≤ 0.5 nm, total thickness variation ≤ 15 μm), as shown. Figure 2 As shown, then the die is mounted, as follows. Figure 3 As shown, a carrier wafer is obtained;

[0096] S2. Clean the carrier wafer and target wafer A (diameter 300mm, thickness = 0.725mm, surface roughness ≤ 0.5nm) separately. Activate the carrier wafer and target wafer A with O2 plasma at 60W for 1min. Then, clean the carrier wafer and target wafer A separately with mega-acoustic cleaning agent using water. Next, transfer the carrier wafer and target wafer A into the wafer bonding equipment, align them, and perform wafer bonding in the bonding cavity, positioning the die between the carrier wafer and target wafer A. Finally, place them in a 200℃ oven for heat treatment for 4 hours. Figure 4 As shown, bonded wafer A is obtained;

[0097] S3. Perform thermal debonding on bonded wafer A at 200℃, as follows: Figure 5 As shown, the grain and the carrier are separated, so that the grain remains on the target wafer A. The residual temporary bonding adhesive (thermoplastic temporary bonding adhesive) on the grain is cleaned with acetone, and then heat-treated at 300°C for 4 hours to obtain composite wafer A.

[0098] S4. Implant H ions (implantation energy = 200 keV, implantation dose = 2 × 10⁻⁶) 12 / cm 2 In the grains on composite wafer A, such as Figure 6 As shown, composite wafer A and target wafer B (diameter 300mm, thickness 0.725mm, surface roughness ≤0.5nm) were cleaned separately. Composite wafer A and target wafer B were activated with O2 plasma at 60W for 1min. Then, composite wafer A and target wafer B were cleaned separately with mega-sonic cleaning using water as the cleaning agent. Next, composite wafer A and target wafer B were transferred into a wafer bonding apparatus, aligned, and bonded in the bonding cavity, so that the die is located between target wafer A and target wafer B, resulting in a wafer composite. Figure 7 As shown;

[0099] S5. The wafer composite is heated at 190℃ for 1 hour to cause the implanted ions to expand, and the grains break apart into two layers located on target wafer A and target wafer B, respectively, resulting in composite wafer A' with grains located on target wafer A and composite wafer B with grains located on target wafer B. Figure 8 As shown, composite wafer B was cleaned and annealed at 300°C for 4 hours. Then, composite wafers A' and B were chemically and mechanically polished to remove surface defects caused by ion implantation.

[0100] S6. Repeat steps S4-S5 multiple times for composite wafers A' and B;

[0101] The target wafer A is a silicon wafer (elemental silicon);

[0102] The target wafer B is a silicon wafer (elemental silicon);

[0103] A composite wafer is prepared by the above-described preparation method; the composite wafer includes a target wafer and a grain, the grain being disposed on the surface of the target wafer; the diameter of the target wafer is 300 mm; the target wafer is a silicon wafer (elemental silicon), the surface roughness of the target wafer is ≤0.5 nm, and the thickness is 0.725 mm.

[0104] Example 2

[0105] This embodiment provides a method for preparing a composite wafer, the method comprising the following steps:

[0106] S1. The non-silicon optoelectronic material lithium niobate (LiNbO3) (circular with a diameter of 120 mm and a thickness of 0.5 mm) is polished on both sides to achieve a surface roughness of ≤0.5 nm, and then cut into grains (square with an area of ​​25 mm²). 2 (thickness = 0.5mm), such as Figure 1 As shown; temporary bonding adhesive (thermoplastic temporary bonding adhesive) is coated onto a cleaned substrate (material: silicon, circular with a diameter of 200 mm, thickness = 0.725 mm, surface roughness ≤ 0.5 nm, total thickness variation ≤ 15 μm), as shown. Figure 2 As shown, then the die is mounted, as follows. Figure 3 As shown, a carrier wafer is obtained;

[0107] S2. Clean the carrier wafer and target wafer A (diameter 200mm, thickness = 0.725mm, surface roughness ≤ 0.5nm) separately. Activate the carrier wafer and target wafer A with O2 plasma at 60W for 1min. Then, clean the carrier wafer and target wafer A separately with mega-sound cleaning agent using water as the cleaning agent. Next, transfer the carrier wafer and target wafer A into the wafer bonding equipment, align them, and perform wafer bonding in the bonding cavity, so that the die is located between the carrier wafer and target wafer A. Then, place them in a 200℃ oven for heat treatment for 4 hours. Figure 4 As shown, bonded wafer A is obtained;

[0108] S3. Perform thermal debonding on bonded wafer A at 200℃, as follows: Figure 5 As shown, the grain and the carrier are separated, so that the grain remains on the target wafer A. The residual temporary bonding adhesive (thermoplastic temporary bonding adhesive) on the grain is cleaned with acetone, and then heat-treated at 300°C for 4 hours to obtain composite wafer A.

[0109] S4. Implant H ions (implantation energy = 200 keV, implantation dose = 1 × 10⁻⁶) 12 / cm 2 In the grains on composite wafer A, such as Figure 6 As shown, composite wafer A and target wafer B (diameter 200mm, thickness 0.725mm, surface roughness ≤0.5nm) were cleaned separately. Composite wafer A and target wafer B were activated with O2 plasma at 65W for 1min. Then, composite wafer A and target wafer B were cleaned separately with mega-sonic cleaning using water as the cleaning agent. Next, composite wafer A and target wafer B were transferred into a wafer bonding apparatus, aligned, and bonded in the bonding cavity, so that the die is located between target wafer A and target wafer B, resulting in a wafer composite. Figure 7 As shown;

[0110] S5. The wafer composite is heated at 190℃ for 1 hour to cause the implanted ions to expand, and the grains break apart into two layers located on target wafer A and target wafer B, respectively, resulting in composite wafer A' with grains located on target wafer A and composite wafer B with grains located on target wafer B. Figure 8 As shown, composite wafer B was cleaned and annealed at 300°C for 3 hours. Then, composite wafers A' and B were chemically and mechanically polished to remove surface defects caused by ion implantation.

[0111] S6. Repeat steps S4-S5 multiple times for composite wafers A' and B;

[0112] The target wafer A is a silicon wafer (elemental silicon);

[0113] The target wafer B is a silicon wafer (elemental silicon);

[0114] A composite wafer is prepared by the above-described preparation method; the composite wafer includes a target wafer and a grain, the grain being disposed on the surface of the target wafer; the diameter of the target wafer is 200 mm; the target wafer is a silicon wafer (elemental silicon), the surface roughness of the target wafer is ≤0.5 nm, and the thickness is 0.725 mm.

[0115] Example 3

[0116] This embodiment provides a method for preparing a composite wafer, the method comprising the following steps:

[0117] S1. The non-silicon optoelectronic material lithium tantalate (LiTaO3) (circular with a diameter of 120 mm and a thickness of 0.5 mm) is polished on both sides to achieve a surface roughness of ≤0.5 nm, and then cut into grains (square with an area of ​​16 mm²). 2 (thickness = 0.5mm), such as Figure 1 As shown; temporary bonding adhesive (thermoplastic temporary bonding adhesive) is coated onto a cleaned substrate (material: silicon, circular with a diameter of 200 mm, thickness = 0.725 mm, surface roughness ≤ 0.5 nm, total thickness variation ≤ 15 μm), as shown. Figure 2 As shown, then the die is mounted, as follows. Figure 3 As shown, a carrier wafer is obtained;

[0118] S2. Clean the carrier wafer and target wafer A (diameter 200mm, thickness 0.5mm, surface roughness ≤0.5nm) separately. Activate the carrier wafer and target wafer A with O2 plasma at 60W for 1min. Then, clean the carrier wafer and target wafer A separately with mega-acoustic cleaning using water as the cleaning agent. Next, transfer the carrier wafer and target wafer A into the wafer bonding equipment, align them, and perform wafer bonding in the bonding cavity, so that the die is located between the carrier wafer and target wafer A. Then, place them in a 200℃ oven for heat treatment for 4 hours. Figure 4 As shown, bonded wafer A is obtained;

[0119] S3. Perform thermal debonding on bonded wafer A at 200℃, as follows: Figure 5 As shown, the grain and the carrier are separated, so that the grain remains on the target wafer A. The residual temporary bonding adhesive (thermoplastic temporary bonding adhesive) on the grain is cleaned with acetone, and then heat-treated at 300°C for 4 hours to obtain composite wafer A.

[0120] S4. Implant H ions (implantation energy = 200 keV, implantation dose = 1 × 10⁻⁶) 12 / cm 2 In the grains on composite wafer A, such as Figure 6As shown, composite wafer A and target wafer B (diameter 200mm, thickness 0.5mm, surface roughness ≤0.5nm) were cleaned separately. Composite wafer A and target wafer B were activated with O2 plasma at 60W for 1min. Then, composite wafer A and target wafer B were cleaned with megaphonic cleaning agent using water as the cleaning agent. Next, composite wafer A and target wafer B were transferred into a wafer bonding apparatus, aligned, and bonded in the bonding cavity, so that the die is located between target wafer A and target wafer B, resulting in a wafer composite. Figure 7 As shown;

[0121] S5. The wafer composite is heated at 190℃ for 1 hour to cause the implanted ions to expand, and the grains break apart into two layers located on target wafer A and target wafer B, respectively, resulting in composite wafer A' with grains located on target wafer A and composite wafer B with grains located on target wafer B. Figure 8 As shown, composite wafer B was cleaned and annealed at 300°C for 4 hours. Then, composite wafers A' and B were chemically and mechanically polished to remove surface defects caused by ion implantation.

[0122] S6. Repeat steps S4-S5 multiple times for composite wafers A' and B;

[0123] The target wafer A is a silicon wafer (elemental silicon);

[0124] The target wafer B is a silicon wafer (elemental silicon);

[0125] A composite wafer is prepared by the above-described preparation method; the composite wafer includes a target wafer and a grain, the grain being disposed on the surface of the target wafer; the target wafer has a diameter of 200 mm; the target wafer is a silicon wafer (elemental silicon), the surface roughness of the target wafer is ≤0.5 nm, and the thickness is 0.5 mm.

[0126] Example 4

[0127] This embodiment provides a method for preparing a composite wafer, the method comprising the following steps:

[0128] S1. The non-silicon optoelectronic material gallium arsenide (GaAs) (circular in diameter of 120 mm and thickness of 0.5 mm) is polished on both sides to achieve a surface roughness of ≤0.5 nm, and then cut into grains (square, area = 25 mm²). 2 (thickness = 0.5mm), such as Figure 1 As shown; temporary bonding adhesive (thermoplastic temporary bonding adhesive) is coated onto a cleaned substrate (material: silicon, circular with a diameter of 300 mm, thickness = 0.725 mm, surface roughness ≤ 0.5 nm, total thickness variation ≤ 15 μm), as shown. Figure 2As shown, then the die is mounted, as follows. Figure 3 As shown, a carrier wafer is obtained;

[0129] S2. Clean the carrier wafer and target wafer A (diameter 300mm, thickness = 0.725mm, surface roughness ≤ 0.5nm) separately. Activate the carrier wafer and target wafer A with O2 plasma at 60W for 1min. Then, clean the carrier wafer and target wafer A separately with mega-acoustic cleaning agent using water. Next, transfer the carrier wafer and target wafer A into the wafer bonding equipment, align them, and perform wafer bonding in the bonding cavity, positioning the die between the carrier wafer and target wafer A. Finally, place them in a 200℃ oven for heat treatment for 4 hours. Figure 4 As shown, bonded wafer A is obtained;

[0130] S3. Perform thermal debonding on bonded wafer A at 200℃, as follows: Figure 5 As shown, the grain and the carrier are separated, so that the grain remains on the target wafer A. The residual temporary bonding adhesive (thermoplastic temporary bonding adhesive) on the grain is cleaned with acetone, and then heat-treated at 300°C for 4 hours to obtain composite wafer A.

[0131] S4. Implant H ions (implantation energy = 200 keV, implantation dose = 2 × 10⁻⁶) 12 / cm 2 In the grains on composite wafer A, such as Figure 6 As shown, composite wafer A and target wafer B (diameter 300mm, thickness 0.725mm, surface roughness ≤0.5nm) were cleaned separately. Composite wafer A and target wafer B were activated with O2 plasma at 60W for 1min. Then, composite wafer A and target wafer B were cleaned separately with mega-sonic cleaning using water as the cleaning agent. Next, composite wafer A and target wafer B were transferred into a wafer bonding apparatus, aligned, and bonded in the bonding cavity, so that the die is located between target wafer A and target wafer B, resulting in a wafer composite. Figure 7 As shown;

[0132] S5. The wafer composite is heated at 190℃ for 1 hour to cause the implanted ions to expand, and the grains break apart into two layers located on target wafer A and target wafer B, respectively, resulting in composite wafer A' with grains located on target wafer A and composite wafer B with grains located on target wafer B. Figure 8 As shown, composite wafer B was cleaned and annealed at 300°C for 4 hours. Then, composite wafers A' and B were chemically and mechanically polished to remove surface defects caused by ion implantation.

[0133] S6. Repeat steps S4-S5 multiple times for the composite wafer A';

[0134] The target wafer A is a silicon wafer (elemental silicon);

[0135] The target wafer B is a silicon wafer (elemental silicon);

[0136] A composite wafer is prepared by the above-described preparation method; the composite wafer includes a target wafer and a grain, the grain being disposed on the surface of the target wafer; the diameter of the target wafer is 300 mm; the target wafer is a silicon wafer (elemental silicon), the surface roughness of the target wafer is ≤0.5 nm, and the thickness is 0.725 mm.

[0137] Example 5

[0138] This embodiment provides a method for preparing a composite wafer, the method comprising the following steps:

[0139] S1. The non-silicon optoelectronic material gallium nitride (GaN) (circular with a diameter of 120 mm and a thickness of 0.5 mm) is polished on both sides to achieve a surface roughness of ≤1 nm, and then cut into grains (square with an area of ​​16 mm²). 2 (thickness = 0.5mm), such as Figure 1 As shown; temporary bonding adhesive (thermoplastic temporary bonding adhesive) is coated onto a cleaned substrate (material: silicon, circular with a diameter of 300 mm, thickness = 0.775 mm, surface roughness ≤ 1 nm, total thickness variation ≤ 15 μm), as shown. Figure 2 As shown, then the die is mounted, as follows. Figure 3 As shown, a carrier wafer is obtained;

[0140] S2. Clean the carrier wafer and target wafer A (diameter 300mm, thickness = 0.775mm, surface roughness ≤ 1nm) separately. Activate the carrier wafer and target wafer A with O2 plasma at 60W for 1min. Then, clean the carrier wafer and target wafer A separately with mega-sound cleaning agent using water. Next, transfer the carrier wafer and target wafer A into the wafer bonding equipment, align them, and perform wafer bonding in the bonding cavity, positioning the die between the carrier wafer and target wafer A. Finally, place them in a 200℃ oven for heat treatment for 4 hours. Figure 4 As shown, bonded wafer A is obtained;

[0141] S3. Perform thermal debonding on bonded wafer A at 200℃, as follows: Figure 5 As shown, the grain and the carrier are separated, so that the grain remains on the target wafer A. The residual temporary bonding adhesive (thermoplastic temporary bonding adhesive) on the grain is cleaned with acetone, and then heat-treated at 300°C for 5 hours to obtain composite wafer A.

[0142] S4. Implant H ions (implantation energy = 200 keV, implantation dose = 4 × 10⁻⁶) 12 / cm2 In the grains on composite wafer A, such as Figure 6 As shown, composite wafer A and target wafer B (diameter 300mm, thickness 0.775mm, surface roughness ≤1nm) were cleaned separately. Composite wafer A and target wafer B were activated with O2 plasma at 50W for 1.5min. Then, composite wafer A and target wafer B were cleaned separately in water using mega-sonic cleaning. Next, composite wafer A and target wafer B were transferred into a wafer bonding apparatus, aligned, and bonded in the bonding cavity, so that the die was located between target wafer A and target wafer B, resulting in a wafer composite. Figure 7 As shown;

[0143] S5. The wafer composite is heated at 190℃ for 1.5 hours to cause the implanted ions to expand, and the grains break apart into two layers located on target wafer A and target wafer B, respectively, resulting in composite wafer A' with the grains located on target wafer A and composite wafer B with the grains located on target wafer B, as shown. Figure 8 As shown, composite wafer B was cleaned and annealed at 300°C for 4 hours. Then, composite wafers A' and B were chemically and mechanically polished to remove surface defects caused by ion implantation.

[0144] S6. Repeat steps S4-S5 multiple times for composite wafer B;

[0145] The target wafer A is a silicon wafer (elemental silicon);

[0146] The target wafer B is a silicon wafer (elemental silicon);

[0147] A composite wafer is prepared by the above-described preparation method; the composite wafer includes a target wafer and a grain, the grain being disposed on the surface of the target wafer; the diameter of the target wafer is 300 mm; the target wafer is a silicon wafer (elemental silicon), the surface roughness of the target wafer is ≤0.5 nm, and the thickness is 0.775 mm.

[0148] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the scope of protection of the present invention. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the essence and scope of the technical solutions of the present invention.

Claims

1. A method for preparing a composite wafer, characterized in that, The preparation method includes the following steps: S1. Cut the non-silicon optoelectronic material into granules and attach the granules to the carrier wafer with temporary bonding adhesive to obtain the carrier wafer; S2. Perform wafer bonding between the carrier wafer and the target wafer A, so that the grain is located between the carrier wafer and the target wafer A, and then perform heat treatment to obtain the bonded wafer A; S3. Debond the bonded wafer A, separate the grains from the carrier, and leave the grains on the target wafer A to obtain the composite wafer A; S4. Ions are implanted into the grains on the composite wafer A, and then composite wafer A and target wafer B are bonded together so that the grains are located between target wafer A and target wafer B, thus obtaining a wafer composite. S5. The wafer composite is heated to cause the implanted ions to expand, and the grains break apart into two layers located on target wafer A and target wafer B respectively, to obtain composite wafer A' with grains located on target wafer A and composite wafer B with grains located on target wafer B; The diameter of target wafer A is ≥150mm, and the diameter of target wafer B is ≥150mm.

2. The method for preparing the composite wafer as described in claim 1, characterized in that, The non-silicon optoelectronic material is at least one of indium phosphide, lithium niobate, lithium tantalate, gallium arsenide, and gallium nitride.

3. The method for preparing a composite wafer as described in claim 1, characterized in that, Includes at least one of the following (1)-(3): (1) In step S1, the material of the carrier is at least one of silicon, quartz, and glass; (2) In step S2, the target wafer A contains at least one of elemental silicon and silicon dioxide; (3) In step S4, the target wafer B contains at least one of elemental silicon and silicon dioxide.

4. The method for preparing a composite wafer as described in claim 1, characterized in that, Includes at least one of the following (1)-(4): (1) In step S2, the wafer bonding process includes activating the carrier wafer and the target wafer A with plasma, and then cleaning the carrier wafer and the target wafer A respectively. (2) In step S2, the temperature of the heat treatment is 100-250℃; (3) In step S2, the heat treatment time is 2-6 hours; (4) In step S3, after debonding, the process also includes cleaning the grains.

5. The method for preparing a composite wafer as described in claim 4, characterized in that, (4) After cleaning the grains, heat treatment is also included.

6. The method for preparing the composite wafer as described in claim 5, characterized in that, Includes at least one of the following (1)-(2): (1) The temperature of the heat treatment is 200-450℃; (2) The heat treatment time is 1-6 hours.

7. The method for preparing a composite wafer as described in claim 1, characterized in that, In step S4, the bonding process includes cleaning the composite wafer A and the target wafer B, activating the composite wafer A and the target wafer B with plasma, and then cleaning the composite wafer A and the target wafer B.

8. The method for preparing a composite wafer as described in claim 1, characterized in that, Includes at least one of the following (1)-(3): (1) In step S5, the temperature of the heat treatment is 150-250℃; (2) In step S5, the obtained composite wafer B is cleaned and annealed. (3) The method for preparing the composite wafer further includes step S6. Repeating steps S4-S5 multiple times for composite wafers A' and / or B.

9. A composite wafer, characterized in that, The composite wafer is prepared by any one of the preparation methods described in claims 1-8, and includes a target wafer and a grain, wherein the grain is disposed on the surface of the target wafer and the diameter of the target wafer is ≥150mm.

10. The composite wafer as described in claim 9, characterized in that, Includes at least one of the following (1)-(2): (1) The target wafer contains at least one of elemental silicon and silicon dioxide; (2) The surface roughness of the target wafer is ≤1nm.

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