IBC solar cell and preparation method thereof

Abstract

The invention discloses an IBC solar cell and a preparation method thereof, and the IBC solar cell comprises a silicon wafer which comprises a first surface and a second surface which are oppositely arranged, the second surface comprises a first region, a second region and an isolation region, and the isolation region is located between the first region and the second region; the diffusion layer is formed below the second surface of the silicon wafer, and the silicon wafer and the diffusion layer form a PN junction; a passivation contact structure on the first region of the second surface; the hole selective contact structure is positioned on the second region of the second surface and is electrically isolated from the passivation contact structure; and an electrode structure including a first electrode on the passivation contact structure and a second electrode on the hole selective contact structure. According to the invention, hole contact with lower resistivity can be realized, and the electrical property and the conversion efficiency of the cell are improved; and meanwhile, the technological process is remarkably simplified, the product yield is improved, and the battery reliability is improved.

Description

Technical Field

[0001] This invention belongs to the field of solar cell technology, specifically relating to an IBC solar cell and its preparation method. Background Technology

[0002] Interdigitated Back Contact (IBC) cells fabricate the PN junction and both positive and negative electrodes on the back side, maximizing the light-receiving area of ​​the cell and minimizing optical energy loss, thereby significantly improving the photoelectric conversion efficiency. In recent years, IBC cells have attracted increasing attention, not only because of their potential for the highest conversion efficiency, but also because they can continuously absorb the process advantages and passivation techniques of other crystalline silicon technologies to further improve conversion efficiency. IBC cells have evolved into POLO-IBC, TBC cells, and others by adopting TOPCon passivation contact technology.

[0003] However, IBC batteries still have the following problems: First, the SiO2 on the back... X First, the back hole contact resistivity formed by P-Poly polycrystalline silicon contacts is high, resulting in low battery efficiency. Second, the IBC battery manufacturing process is complex, requiring multiple masking and laser etching processes, and the resulting battery has high leakage current, affecting battery efficiency.

[0004] Therefore, in order to address the above-mentioned technical problems, it is necessary to provide an IBC solar cell and its preparation method. Summary of the Invention

[0005] The purpose of this invention is to provide an IBC solar cell and its preparation method, which achieves hole contact with lower resistivity and reduces the risk of leakage current in the cell.

[0006] To achieve the above objectives, an embodiment of the present invention provides the following technical solution:

[0007] An IBC solar cell, the IBC solar cell comprising:

[0008] A silicon wafer includes a first surface and a second surface disposed opposite to each other, the second surface including a first region, a second region and an isolation region, the isolation region being located between the first region and the second region;

[0009] A diffusion layer is formed beneath the second surface of a silicon wafer, and the silicon wafer and the diffusion layer form a PN junction;

[0010] A passivated contact structure is located on the first region of the second surface;

[0011] A hole-selective contact structure is located on a second region of the second surface and is electrically isolated from the passivation contact structure;

[0012] The electrode structure includes a first electrode located on a passivated contact structure and a second electrode located on a hole-selective contact structure.

[0013] In one embodiment, the hole-selective contact structure includes AlO₂ sequentially stacked on the second region. X Nanolayer, SiN X The nanolayer and the second doped layer, wherein the doping type of the second doped layer is the same as that of the diffusion layer.

[0014] In one embodiment, the AlO X The thickness of the nanolayer is 1 nm to 2 nm; and / or,

[0015] The SiN X The thickness of the nanolayer is 2 nm to 3 nm; and / or,

[0016] The thickness of the second doped layer is 80 nm to 120 nm; and / or,

[0017] The second doped layer is p-type doped with a doping concentration of 1E20cm⁻¹. -3 ~1E21cm -3 .

[0018] In one embodiment, the passivated contact structure includes a tunneling layer and a first doped layer sequentially stacked on a first region, wherein the doping type of the first doped layer is opposite to that of the diffusion layer.

[0019] In one embodiment, the tunneling layer is any one or more combinations of a silicon oxide layer and a silicon oxynitride layer; and / or,

[0020] The thickness of the tunneling layer is 1.5 nm to 2 nm;

[0021] The thickness of the first doped layer is 100 nm to 150 nm; and / or,

[0022] The first doped layer is N-type doped with a doping concentration of 1E20cm⁻¹. -3 ~1E21cm -3 .

[0023] In one embodiment, a first antireflection layer is provided on the first surface of the silicon wafer; and / or,

[0024] The second surface of the silicon wafer is provided with a second antireflection layer covering a passivation contact structure, a hole-selective contact structure and an isolation region. The first electrode penetrates the second antireflection layer and is electrically connected to the passivation contact structure, and the second electrode penetrates the second antireflection layer and is electrically connected to the hole-selective contact structure.

[0025] The technical solution provided by one embodiment of the present invention is as follows:

[0026] A method for fabricating an IBC solar cell, the method comprising the following steps:

[0027] A silicon wafer is provided, the silicon wafer including a first surface and a second surface disposed opposite to each other;

[0028] A diffusion process is performed on a silicon wafer to form a diffusion layer under the second surface of the silicon wafer, and the silicon wafer and the diffusion layer form a PN junction;

[0029] Passivation contact structures and hole-selective contact structures are fabricated on the second surface of a silicon wafer, and the passivation contact structures and hole-selective contact structures are isolated.

[0030] The first electrode and the second electrode are fabricated on the passivated contact structure and the hole-selective contact structure, respectively.

[0031] In one embodiment, the fabrication and isolation of the passivated contact structure and the hole-selective contact structure include the following steps:

[0032] A tunneling layer and a first doped layer are sequentially deposited on the second surface, and a first mask is formed on the surface of the first doped layer;

[0033] The first mask on a local area of ​​the second surface is etched by laser process, and the tunneling layer and the first doped layer underneath, as well as the first mask on other areas, are removed.

[0034] AlO is deposited sequentially on the second surface X Nanolayer, SiN X Nanolayer, second doped layer and second mask;

[0035] The AlO on the first doped layer was treated using laser technology. X Nanolayer, SiN X The nanolayer, the second doped layer, and the second mask are etched, and the second mask on other areas is removed by a wet etching process.

[0036] The region at the junction of the passivated contact structure and the hole-selective contact structure is isolated by laser technology, so as to form an isolation trench extending to the second surface of the silicon wafer between the passivated contact structure and the hole-selective contact structure.

[0037] In one embodiment, the fabrication of the tunneling layer, the first doped layer, and the first mask includes:

[0038] A tunneling layer of 1.5 nm to 2 nm thickness and an amorphous silicon layer of 100 nm to 150 nm thickness are sequentially deposited on the second surface using LPCVD process.

[0039] Gas is introduced into a diffusion furnace to transform the amorphous silicon layer into a doped polycrystalline silicon layer, while a first mask is formed on the surface of the doped polycrystalline silicon layer. The first mask is a PSG mask.

[0040] In one embodiment, the AlO X Nanolayer, SiN X The fabrication of the nanolayer, the second doped layer, and the second mask includes:

[0041] A 1nm to 2nm thick AlO layer was deposited on the second surface using the ALD process. X The nanolayers are deposited at temperatures of 100℃ to 200℃ in the ALD process, and the reaction gases are trimethylaluminum and H2O.

[0042] Using PECVD process on AlO X A 2nm-3nm thick SiN layer is deposited on the nanolayer. X The nanolayers were deposited at a temperature of 300℃~400℃, a deposition power of 20W~50W, a chamber pressure of 500mTorr~700mTorr, and reacted with silane and ammonia.

[0043] In-situ doping process in SiN X A second doped layer with a thickness of 80 nm to 120 nm is fabricated on the nanolayer, and a second mask is formed on the surface of the second doped layer. The second mask is SiO2. X Mask.

[0044] In one embodiment, in the laser process for etching the tunneling layer, the first doped layer, and the first mask in a local area of ​​the second surface, the laser wavelength is 400 nm to 500 nm, and the pulse width is 1 ns to 100 ns; and / or,

[0045] AlO on the first doped layer X Nanolayer, SiN X In the laser process for etching the nanolayer, the second doped layer, and the second mask, the laser wavelength is 300nm to 400nm and the pulse width is 1ns to 10ns.

[0046] In one embodiment, the AlO on the first doped layer is treated with a laser process. X Nanolayer, SiN X Before etching the nanolayer, the second doped layer, and the second mask, the following steps are also included:

[0047] A pyramidal texturing structure is formed on the first surface of a silicon wafer using an alkaline texturing process; and / or,

[0048] A first antireflection layer is prepared on the first surface of a silicon wafer.

[0049] In one embodiment, after isolating the area at the junction of the passivated contact structure and the hole-selective contact structure using laser technology, the method further includes:

[0050] A second antireflection layer is prepared on the second surface of the silicon wafer; and,

[0051] A first electrode electrically connected to the first doped layer is fabricated on a passivated contact structure, and a second electrode electrically connected to the second doped layer is fabricated on a hole-selective contact structure.

[0052] Compared with the prior art, the present invention has the following beneficial effects:

[0053] In this invention, by forming a hole-selective contact structure in a local area on the back of the IBC solar cell, hole contact with lower resistivity can be achieved, thereby improving the electrical performance and conversion efficiency of the cell.

[0054] The preparation method of the present invention significantly simplifies the process flow, improves product yield, and enhances battery reliability. Attached Figure Description

[0055] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0056] Figure 1a This is a schematic diagram of the structure of an IBC solar cell in a specific embodiment of the present invention;

[0057] Figure 1b for Figure 1a A magnified view of a portion of point A in the middle;

[0058] Figures 2a-2k This is a process flow diagram of the IBC solar cell fabrication method in a specific embodiment of the present invention. Detailed Implementation

[0059] To enable those skilled in the art to better understand the technical solutions of this invention, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this invention.

[0060] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0061] This invention discloses an IBC solar cell, comprising:

[0062] A silicon wafer includes a first surface and a second surface disposed opposite to each other, the second surface including a first region, a second region and an isolation region, the isolation region being located between the first region and the second region;

[0063] A diffusion layer is formed beneath the second surface of the silicon wafer, and the silicon wafer and the diffusion layer form a PN junction.

[0064] A passivated contact structure is located on the first region of the second surface;

[0065] A hole-selective contact structure is located on a second region of the second surface and is electrically isolated from the passivation contact structure;

[0066] The electrode structure includes a first electrode located on a passivated contact structure and a second electrode located on a hole-selective contact structure.

[0067] This invention also discloses a method for preparing an IBC solar cell, comprising the following steps:

[0068] A silicon wafer is provided, the silicon wafer including a first surface and a second surface disposed opposite to each other;

[0069] A diffusion process is performed on the silicon wafer to form a diffusion layer under the second surface of the silicon wafer, and a PN junction is formed between the silicon wafer and the diffusion layer;

[0070] Passivation contact structures and hole-selective contact structures are fabricated on the second surface of a silicon wafer, and the passivation contact structures and hole-selective contact structures are isolated.

[0071] The first electrode and the second electrode are fabricated on the passivated contact structure and the hole-selective contact structure, respectively.

[0072] In this invention, by forming a hole-selective contact structure in a localized area on the back of the IBC solar cell, hole contact with lower resistivity can be achieved, thereby improving the electrical performance and conversion efficiency of the cell.

[0073] The present invention will be further described below with reference to specific embodiments.

[0074] Reference Figure 1a 、 Figure 1b As shown, the IBC solar cell in a specific embodiment of the present invention includes:

[0075] A silicon wafer 10, the silicon wafer is a doped silicon wafer, including a first surface S1 (i.e., the front or light-receiving surface) and a second surface S2 (i.e., the back or light-blocking surface) arranged oppositely. The second surface S2 includes a first region S21, a second region S22 and an isolation region S23, and the isolation region S23 is located between the first region S21 and the second region S22;

[0076] A diffusion layer 11, formed under the second surface of the silicon wafer 10, and the doping type of the diffusion layer is opposite to that of the silicon wafer 10. A PN junction is formed between the silicon wafer 10 and the diffusion layer 11.

[0077] A passivation contact structure 20, located on the first region S21 of the second surface S2;

[0078] A hole selective contact structure 30, located on the second region S22 of the second surface S2, and is electrically isolated from the passivation contact structure through an isolation groove 40;

[0079] An electrode structure, including a first electrode 51 located on the passivation contact structure 20 and a second electrode 52 located on the hole selective contact structure 30.

[0080] Exemplarily, the silicon wafer 10 in this embodiment is taken as an example of an N-type silicon wafer (i.e., N-type doping) for illustration, and the diffusion layer 11 is a P-type diffusion layer (such as boron diffusion, etc.).

[0081] The passivation contact structure 20 in this embodiment includes a tunneling layer 21 and a first doping layer 22 stacked in sequence on the first region S21. The doping type of the first doping layer 22 is opposite to that of the diffusion layer 11. In this embodiment, it is N-type doping (such as phosphorus doping, etc.).

[0082] Specifically, the tunneling layer 21 is any one or a combination of silicon oxide layer and silicon oxynitride layer, with a thickness of 1.5 nm to 2 nm; the first doping layer 22 is a polysilicon layer doped with N-type, with a thickness of 100 nm to 150 nm, and a doping concentration of 1E20 cm -3 ~1E21 cm -3 .

[0083] The hole selective contact structure 30 in this embodiment includes an AlO X nanolayer 31, a SiN X nanolayer 32 and a second doping layer 33 stacked in sequence on the second region. The doping type of the second doping layer is the same as that of the diffusion layer 11. In this embodiment, it is P-type doping (such as boron doping, etc.).

[0084] Specifically, AlO X The thickness of the nanolayer is 1nm to 2nm; SiN X The thickness of the nanolayer is 2nm to 3nm; the second doped layer is a p-type doped polycrystalline silicon layer with a thickness of 80nm to 120nm and a doping concentration of 1E20cm⁻¹. -3 ~1E21cm -3 .

[0085] Furthermore, in this embodiment, the first surface S1 of the silicon wafer is formed with a pyramid textured structure by an alkaline texturing process, and a first antireflection layer 61 is provided on the first surface S1.

[0086] In addition, a second antireflection layer 62 covering the passivation contact structure 20, the hole selective contact structure 30 and the isolation region 40 is provided on the second surface S2 of the silicon wafer 10. The first electrode 51 penetrates the second antireflection layer 62 and is electrically connected to the first doped layer 22 in the passivation contact structure. The second electrode 52 penetrates the second antireflection layer 62 and is electrically connected to the second doped layer 33 in the hole selective contact structure.

[0087] The first anti-reflection layer 61 and the second anti-reflection layer 62 can be SiN. X Layer, SiN X O Y Layers, preferably SiN X The layer has a thickness of 80nm to 95nm and a refractive index of 1.9 to 2.1.

[0088] In this embodiment, an isolation trench 40 is formed on the third region S23. The isolation trench 40 extends at least to the second surface S2 of the silicon wafer. The isolation trench can isolate the passivation contact structure 20 and the hole selective contact structure 30, thus avoiding short circuits between the two structures.

[0089] Furthermore, in this embodiment, the isolation trench 40 is filled with a second antireflection layer (SiN). X The material of the second antireflection layer 62 (SiN) is 62. X The insulating material is a second anti-reflective layer 62, which can further improve the isolation effect and greatly reduce the risk of leakage on the back of the battery.

[0090] In existing technology, the SiO2 back side of IBC solar cells X There are several reasons why P-Poly contacts are less efficient at hole selectivity:

[0091] First, the valence band offset is very high, resulting in a high hole tunneling barrier and consequently a low tunneling current. (Compared to SiO2) XDifferent from the electron selective contact of Poly, in order to achieve a low resistivity of holes, the main conduction mechanism must be provided by the pinholes in the thin oxide. The pinholes are local damages of the oxide layer, which lead to poor passivation quality at the silicon interface;

[0092] Secondly, the high-temperature annealing provides a driving force for the doped atoms to diffuse from the heavily doped polysilicon to the base wafer. The diffusion of boron in SiO X is not hindered like the diffusion of phosphorus, resulting in an increase in the boron concentration and a deeper boron diffusion at the Si / SiO X interface, thereby increasing the Auger recombination.

[0093] The hole selective contact structure in the present invention is a composite structure of an AlO X nano-layer, a SiN X nano-layer and a doped polysilicon layer. The valence band offset values of the AlO X and SiN X layers are significantly lower than that of the SiOx layer. For a given thickness, SiN X has the maximum tunneling probability. When realizing hole selectivity, the resistance of SiN X tunneling is the smallest. Therefore, a thinner AlO X , SiN X nano-composite layer and the hole selective contact structure of P-Poly can achieve a hole contact with a lower resistivity.

[0094] Refer Figures 2a-2k As shown, the preparation method of the IBC solar cell in a specific embodiment of the present invention includes the following steps:

[0095] 1. Refer Figure 2a As shown, provide a silicon wafer 10 and perform double-sided polishing and cleaning.

[0096] Among them, the silicon wafer is a doped silicon wafer, including a first surface S1 and a second surface S2 arranged oppositely. The second surface S2 includes a first region S21, a second region S22 and an isolation region S23. The isolation region S23 is located between the first region S21 and the second region S22.

[0097] Exemplarily, an N-type silicon wafer is selected in this embodiment, and the resistivity is 1 Ω / cm 2 ~5 Ω / cm 2 .

[0098] 2. Refer Figure 2b As shown, perform a diffusion process on the silicon wafer 10 to form a diffusion layer 11 below the second surface S2 of the silicon wafer, and a PN junction is formed between the silicon wafer and the diffusion layer.

[0099] For example, in this embodiment, boron diffusion is performed on the back side of the silicon wafer using LPCVD process at a diffusion temperature of 1000°C. BCl3 gas is introduced to form a PN junction, and the doping concentration of the diffusion layer 11 is 1E19cm⁻¹. -3 ~1E21cm -3 Then, a chain acid washing process using HF solution was used to remove all BSG (borosilicate glass) from the back surface and edges.

[0100] 3. A passivation contact structure 20 and a hole-selective contact structure 30 are prepared on the second surface S2 of the silicon wafer, and the passivation contact structure and the hole-selective contact structure are isolated. The following is a detailed description.

[0101] 3.1, Reference Figure 2c As shown, a tunneling layer 21 and a first doped layer 22 are sequentially deposited on the second surface S2, and a first mask 71 is formed on the surface of the first doped layer 22.

[0102] First, a tunneling layer of 1.5 nm to 2 nm thickness and an amorphous silicon layer of 100 nm to 150 nm thickness are sequentially deposited on the second surface S2 using LPCVD process;

[0103] Then, a gas (such as PClO3) is introduced into a tube diffusion furnace, and the amorphous silicon layer is transformed into a doped polycrystalline silicon layer at a temperature of 1050°C. At the same time, a first mask 71 is formed on the surface of the doped polycrystalline silicon layer. In this embodiment, the first mask 71 is a PSG (phosphosilicate glass) mask.

[0104] 3.2, Reference Figure 2d As shown, the first mask 71 on a local area of ​​the second surface S2 is etched by laser process, and the tunneling layer 21 and the first doped layer 22 underneath it, as well as the first mask 71 on other areas, are removed.

[0105] For example, in this embodiment, the first mask 71 on the second region S22 and the isolation region S23 is etched, while the first mask 71 on the first region S21 is retained. The laser wavelength in the laser process is 400nm to 500nm, and the pulse width is 1ns to 100ns.

[0106] After laser etching, RCA cleaning is performed. The tunneling layer 21 and the first doped layer 22 on the second region S22 and the isolation region S23 are removed by chain alkaline etching. The first region S21 is not damaged by alkaline etching due to the protection of the PSG mask. The PSG mask on the first region S21 is then removed by acid washing.

[0107] 3.3, Reference Figure 2e As shown, AlO is sequentially deposited on the second surface S2. X Nanolayer 31, SiN XNanolayer 32, second doped layer 33 and second mask 72.

[0108] First, a 1nm-2nm thick AlO layer is deposited on the second surface S2 using the ALD process. X Nanolayer 31, the deposition temperature in the ALD process is 100℃~200℃, preferably 150℃, and the reaction gas is trimethylaluminum (TMA) and H2O alternately introduced;

[0109] Secondly, the PECVD process was used to process AlO X A 2nm-3nm thick SiN layer is deposited on nanolayer 31. X The nanolayer 32, the deposition temperature in the PECVD process is 300℃~400℃, preferably 350℃, the deposition power is 20W~50W, the chamber pressure is 500mTorr~700mTorr, the reaction gases are silane and ammonia, and the flow rate of each is 20sccm;

[0110] Finally, in-situ doping of SiN was achieved using PECVD. X A second doped layer 33 with a thickness of 80 nm to 120 nm is fabricated on the nanolayer 32, and a second mask 72 is formed on the surface of the second doped layer. In this embodiment, the second doped layer 33 is a p-type doped polysilicon layer, and the second mask is SiO2. X Mask.

[0111] 3.4, Reference Figure 2f As shown, a pyramidal textured structure is formed on the first surface S1 of the silicon wafer by an alkaline (NaOH solution) texturing process, and the pyramid size is preferably 0.5μm to 5μm.

[0112] 3.5, Reference Figure 2g As shown, a first antireflection layer 61 is prepared on the first surface S1 of a silicon wafer.

[0113] The first anti-reflection layer 61 is SiN X The first antireflective layer is deposited using PECVD technology, with a thickness of 70nm–85nm and a refractive index of 1.9–2.1. The preferred structure for the first antireflective layer is a gradient structure with decreasing refractive index from the inside out, which minimizes light reflection.

[0114] 3.6, Reference Figure 2h As shown, the AlO on the first doped layer 22 is processed by laser technology. X Nanolayer 31, SiN X The nanolayer 32, the second doped layer 33 and the second mask 72 are etched, and the second mask 72 on other areas is removed by a wet etching process.

[0115] For example, in this embodiment, AlO on the first region S21 XNanolayer 31, SiN X The nanolayer 32, the second doped layer 33, and the second mask 72 are etched, retaining the second mask 72 on the second region S22 and the isolation region S23. The laser process must ensure that it does not damage the underlying passivated contact structure. Specifically, in this embodiment, the laser wavelength in the laser process is 300nm to 400nm, and the pulse width is 1ns to 10ns.

[0116] After laser etching, RCA cleaning is performed. Due to the presence of SiO2 in the second region S22 and the isolation region S23... X The mask's protection was not destroyed by alkaline etching, and then acid washing removed the SiO on the second region S22 and the isolation region S23. X Mask.

[0117] 3.7, Reference Figure 2i As shown, the region at the junction of the passivation contact structure 20 and the hole-selective contact structure 30 is isolated by laser technology to form an isolation groove 40 extending to the second surface S2 of the silicon wafer between the passivation contact structure and the hole-selective contact structure.

[0118] For example, in this embodiment, a laser process is performed on the isolation region S23 to remove all AlO2 on the isolation region S23. X Nanolayer 31, SiN X Nanolayer 32 and second doped layer 33 are formed to form isolation trench 40 extending to the second surface S2 of the silicon wafer.

[0119] 3.8, Reference Figure 2j As shown, a second antireflection layer 62 is prepared on the second surface S2 of a silicon wafer.

[0120] The second antireflection layer 62 is SiN. X The layer is deposited using PECVD technology, with a thickness of 80nm to 95nm and a refractive index of 1.9 to 2.1.

[0121] In this embodiment, the second antireflection layer 62 is deposited not only on the first doped layer 22 and the second doped layer 33, but also in the isolation trench 40. The second antireflection layer in the isolation trench 40 can further improve the isolation effect and reduce the risk of leakage.

[0122] 4. Participate Figure 2k As shown, a first electrode 51 and a second electrode 52 are fabricated on the passivated contact structure 20 and the hole-selective contact structure 30, respectively.

[0123] Specifically, in this embodiment, the first electrode 51 and the second electrode 52 are metallized using silver paste through screen printing. The first electrode 51 is sintered to the first doped layer 22 below it and is electrically connected to the first doped layer 22. The second electrode 52 is sintered to the second doped layer 33 below it and is electrically connected to the second doped layer 33.

[0124] In other embodiments, the laser process in step 3.2 can etch the first mask on the second region S22 and part of the isolation region S23, while retaining the first mask on the first region S21 and part of the isolation region S23; the laser process in step S6 then etches the AlO on the first region S21 and part of the isolation region S23. X Nanolayer 31, SiN X The nanolayer 32, the second doped layer 33, and the second mask 72 are etched, retaining the second mask on the second region S22 and part of the isolation region S23; the laser process in step 3.7 removes all the tunneling layer 21, the first doped layer 22, and AlO on the isolation region S23. X Nanolayer 31, SiN X Nanolayer 32 and second doped layer 33.

[0125] In the fabrication method of the IBC solar cell of the present invention, a second doped layer (P-Poly) is formed by in-situ doping using PECVD, and a SiO layer is formed on the outer layer. X Layer, SiO X The layer can control the poly doping concentration and also serve as a back mask for front texturing, eliminating the need for separate mask deposition equipment, which significantly simplifies the process and improves product yield.

[0126] In addition, by using laser isolation, the isolation area is also coated with an anti-reflective film when the anti-reflective film is deposited on the back side, which greatly reduces the risk of leakage on the back side of the battery and improves the reliability of the battery.

[0127] As can be seen from the above technical solution, the present invention has the following beneficial effects:

[0128] In this invention, by forming a hole-selective contact structure in a local area on the back of the IBC solar cell, hole contact with lower resistivity can be achieved, thereby improving the electrical performance and conversion efficiency of the cell.

[0129] The preparation method of the present invention significantly simplifies the process flow, improves product yield, and enhances battery reliability.

[0130] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0131] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. An IBC solar cell, characterized in that, The IBC solar cell includes: A silicon wafer includes a first surface and a second surface disposed opposite to each other, the second surface including a first region, a second region and an isolation region, the isolation region being located between the first region and the second region; A diffusion layer is formed beneath the second surface of a silicon wafer, and the silicon wafer and the diffusion layer form a PN junction; A passivated contact structure is located on the first region of the second surface; A hole-selective contact structure is located on a second region of the second surface and is electrically isolated from the passivation contact structure; The electrode structure includes a first electrode located on a passivated contact structure and a second electrode located on a hole-selective contact structure.

2. The IBC solar cell according to claim 1, characterized in that, The hole-selective contact structure includes AlO₂ sequentially stacked on the second region. X Nanolayer, SiN X The nanolayer and the second doped layer, wherein the doping type of the second doped layer is the same as that of the diffusion layer.

3. The IBC solar cell according to claim 2, characterized in that, The AlO X The thickness of the nanolayer is 1 nm to 2 nm; and / or, The SiN X The thickness of the nanolayer is 2 nm to 3 nm; and / or, The thickness of the second doped layer is 80 nm to 120 nm; and / or, The second doped layer is p-type doped with a doping concentration of 1E20cm⁻¹. -3 ~1E21cm -3 .

4. The IBC solar cell according to claim 1, characterized in that, The passivated contact structure includes a tunneling layer and a first doped layer stacked sequentially on a first region, wherein the doping type of the first doped layer is opposite to that of the diffusion layer.

5. The IBC solar cell according to claim 4, characterized in that, The tunneling layer is any one or more combinations of silicon oxide layer and silicon oxynitride layer; and / or, The thickness of the tunneling layer is 1.5 nm to 2 nm; The thickness of the first doped layer is 100 nm to 150 nm; and / or, The first doped layer is N-type doped with a doping concentration of 1E20cm⁻¹. -3 ~1E21cm -3 .

6. The IBC solar cell according to claim 1, characterized in that, A first antireflection layer is provided on the first surface of the silicon wafer; and / or, The second surface of the silicon wafer is provided with a second antireflection layer covering a passivation contact structure, a hole-selective contact structure and an isolation region. The first electrode penetrates the second antireflection layer and is electrically connected to the passivation contact structure, and the second electrode penetrates the second antireflection layer and is electrically connected to the hole-selective contact structure.

7. A method for preparing an IBC solar cell, characterized in that, The preparation method includes the following steps: A silicon wafer is provided, the silicon wafer including a first surface and a second surface disposed opposite to each other; A diffusion process is performed on a silicon wafer to form a diffusion layer under the second surface of the silicon wafer, and the silicon wafer and the diffusion layer form a PN junction; Passivation contact structures and hole-selective contact structures are fabricated on the second surface of a silicon wafer, and the passivation contact structures and hole-selective contact structures are isolated. The first electrode and the second electrode are fabricated on the passivated contact structure and the hole-selective contact structure, respectively.

8. The IBC solar cell according to claim 7, characterized in that, The preparation and isolation of the passivated contact structure and the hole-selective contact structure include the following steps: A tunneling layer and a first doped layer are sequentially deposited on the second surface, and a first mask is formed on the surface of the first doped layer; The first mask on a local area of ​​the second surface is etched by laser process, and the tunneling layer and the first doped layer underneath, as well as the first mask on other areas, are removed. AlO is deposited sequentially on the second surface X Nanolayer, SiN X Nanolayer, second doped layer and second mask; The AlO on the first doped layer was treated using laser technology. X Nanolayer, SiN X The nanolayer, the second doped layer, and the second mask are etched, and the second mask on other areas is removed by a wet etching process. The region at the junction of the passivated contact structure and the hole-selective contact structure is isolated by laser technology, so as to form an isolation trench extending to the second surface of the silicon wafer between the passivated contact structure and the hole-selective contact structure.

9. The IBC solar cell according to claim 8, characterized in that, The fabrication of the tunneling layer, the first doped layer, and the first mask includes: A tunneling layer of 1.5 nm to 2 nm thickness and an amorphous silicon layer of 100 nm to 150 nm thickness are sequentially deposited on the second surface using LPCVD process. Gas is introduced into a diffusion furnace to transform an amorphous silicon layer into a doped polycrystalline silicon layer, while a first mask is formed on the surface of the doped polycrystalline silicon layer. The first mask is a PSG mask.

10. The IBC solar cell according to claim 8, characterized in that, The AlO X Nanolayer, SiN X The fabrication of the nanolayer, the second doped layer, and the second mask includes: A 1nm to 2nm thick AlO layer was deposited on the second surface using the ALD process. X The nanolayers are deposited at temperatures of 100℃ to 200℃ in the ALD process, and the reaction gases are trimethylaluminum and H2O. Using PECVD process on AlO X A 2nm-3nm thick SiN layer is deposited on the nanolayer. X The nanolayers were deposited at a temperature of 300℃~400℃, a deposition power of 20W~50W, a chamber pressure of 500mTorr~700mTorr, and reacted with silane and ammonia. In-situ doping process in SiN X A second doped layer with a thickness of 80 nm to 120 nm is fabricated on the nanolayer, and a second mask is formed on the surface of the second doped layer. The second mask is SiO2. X Mask.

11. The IBC solar cell according to claim 8, characterized in that, In the laser process for etching the tunneling layer, the first doped layer, and the first mask in a local area of ​​the second surface, the laser wavelength is 400 nm to 500 nm, and the pulse width is 1 ns to 100 ns; and / or, AlO on the first doped layer X Nanolayer, SiN X In the laser process for etching the nanolayer, the second doped layer, and the second mask, the laser wavelength is 300nm to 400nm and the pulse width is 1ns to 10ns.

12. The IBC solar cell according to claim 8, characterized in that, The AlO on the first doped layer was treated using laser technology. X Nanolayer, SiN X Before etching the nanolayer, the second doped layer, and the second mask, the following steps are also included: A pyramidal texturing structure is formed on the first surface of a silicon wafer using an alkaline texturing process; and / or, A first antireflection layer is prepared on the first surface of a silicon wafer.

13. The IBC solar cell according to claim 8, characterized in that, After isolating the area at the interface between the passivated contact structure and the hole-selective contact structure using laser technology, the process also includes: A second antireflection layer is prepared on the second surface of the silicon wafer; and, A first electrode electrically connected to the first doped layer is fabricated on a passivated contact structure, and a second electrode electrically connected to the second doped layer is fabricated on a hole-selective contact structure.

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