Selective via fill with conformal sidewall coverage

Abstract

A method of selectively filling a via with simultaneous liner deposition in a semiconductor structure includes selectively forming a passivation layer on an exposed surface of a conductive layer within a via formed in a dielectric layer formed over the conductive layer, selectively forming a barrier layer on the via and an inner sidewall of a trench formed in the dielectric layer, selectively filling the through hole at least partially with a first conductive material, and simultaneously depositing the first conductive material on the barrier layer on the inner sidewalls of the through hole and the trench to form a liner on the inner sidewalls of the through hole and the trench, and filling the via and a remaining portion of the trench with a second conductive material.

Description

Background Technology

[0001] field

[0002] The embodiments described herein generally relate to the fabrication of semiconductor devices, and more particularly, to methods for selectively filling vias and forming conformal pads on the inner sidewalls of via and trench structures.

[0003] Related technical descriptions

[0004] In copper (Cu) interconnects used in silicon integrated circuits (ICs), barrier metal layers are typically used to surround the copper interconnects to prevent diffusion and other undesirable interactions with the surrounding material. At small device sizes, such as the critical dimension (CD) of vias smaller than 12 nm, the typical thickness of the barrier metal layer and padding layer on the via sidewalls can exceed 3 nm, leaving a small volume within the via to fill the copper, resulting in high via resistance. Scaling the barrier metal layer to below 1 nm and the padding layer to below 2 nm presents challenges in terms of continuity of the barrier metal layer and padding layer, metal barrier properties, adhesion of the padding layer to copper, and copper filling of the via.

[0005] Therefore, it is necessary to selectively fill vias with conductive materials to reduce via resistance and decrease the via aspect ratio in a method of copper filling in the dual damascene process for forming interconnect structures. Summary of the Invention

[0006] Embodiments of this disclosure provide a method for selectively filling vias in a semiconductor structure using simultaneous pad deposition. The method includes selectively forming a passivation layer on an exposed surface of the conductive layer within a via formed in a dielectric layer formed on a conductive layer; selectively forming a barrier layer on the inner sidewalls of the via and a trench formed in the dielectric layer; selectively filling the via at least partially with a first conductive material; simultaneously depositing the first conductive material on the barrier layer on the inner sidewalls of the via and the trench to form a pad on the inner sidewalls of the via and the trench; and filling the remaining portion of the via and the trench with a second conductive material.

[0007] Embodiments of this disclosure also provide a method for selectively filling vias in a semiconductor structure with a pad deposit. The method includes selectively forming a passivation layer on an exposed surface of the conductive layer within a via formed in a dielectric layer formed on a conductive layer; selectively forming a barrier layer on the inner sidewalls of the via; selectively filling the via at least partially with a first conductive material without depositing the first conductive material on the barrier layer on the inner sidewalls of the via; selectively depositing a second conductive material on the barrier layer on the inner sidewalls of the via and a trench formed in the dielectric layer to form a pad on the inner sidewalls of the via and the trench; and filling the remaining portion of the via and the trench with a third conductive material.

[0008] Embodiments of this disclosure also provide a method for selectively filling vias in a semiconductor structure using simultaneous pad deposition. The method includes selectively filling vias in a dielectric layer formed on a conductive layer at least partially with a first conductive material, simultaneously forming pad layers on the inner sidewalls of the vias and trenches formed in the dielectric layer, and filling the remaining portion of the vias with a second conductive material. Attached Figure Description

[0009] To gain a detailed understanding of the features described above regarding the embodiments of this disclosure, a more specific description of the disclosure, which has been briefly summarized above, can be obtained with reference to the embodiments illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only typical embodiments of this disclosure and should therefore not be considered as limiting the scope of this disclosure, as other equally effective embodiments are permissible.

[0010] Figure 1 A processing system according to one embodiment is described.

[0011] Figure 2 This is a process flow diagram of a method for selectively filling vias with pads in a semiconductor structure according to a first embodiment of the present disclosure.

[0012] Figure 3A , 3B 3C, 3D, 3E, 3F and Figure 3G It corresponds to Figure 2 A cross-sectional view of a portion of the interconnect structure for various states of the method.

[0013] Figure 4 This is a process flow diagram of a method for selectively filling vias with pads in a semiconductor structure according to a second embodiment of the present disclosure.

[0014] Figure 5A and Figure 5B It corresponds to Figure 4 A cross-sectional view of a portion of the interconnect structure for various states of the method.

[0015] For ease of understanding, the same element symbols are used where possible to denote elements common to the figures. It is conceivable that elements disclosed in one embodiment may be advantageously used in other embodiments without further elaboration. Detailed Implementation

[0016] A method is provided for at least partially and selectively filling vias while conformally depositing pads on the sidewalls of both vias and trenches. The proposed method enables selective or partial via filling during conformal pad deposition. In the method provided herein, a conductive material, such as ruthenium (Ru), cobalt (Co), molybdenum (Mo), or tungsten (W), is selectively deposited at a faster deposition rate on the bottom of the via, while simultaneously deposited at a slower deposition rate on the sidewalls of the via (e.g., low-dielectric-constant (SiCOH), silicon dioxide (SiO2), or silicon nitride (Si3N4)). Because the bottom of the via is filled with a conductive material, the overall via resistance is reduced, and it is easier to fill the remaining via with copper.

[0017] Figure 1 This is a schematic top view of a multi-chamber processing system 100 according to one or more embodiments of the present disclosure. The processing system 100 generally includes a factory interface 102, loading and locking chambers 104, 106, transfer chambers 108, 110 with corresponding transfer robots 112, 114, holding chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130. As detailed herein, substrates in the processing system 100 can be processed in and transferred between the respective chambers without exposing the substrates to the surrounding environment outside the processing system 100 (e.g., the ambient atmosphere that may exist in a wafer fab). For example, in the various processes performed on the substrates in the processing system 100, the substrates can be processed and transferred between them in various chambers maintained in a low-pressure (e.g., less than or equal to about 300 Torr) or vacuum environment without disrupting the low-pressure or vacuum environment. Therefore, the processing system 100 can provide an integrated solution for some processing of substrates.

[0018] Examples of processing systems that can be appropriately modified based on the teachings provided in this article include: or Integrated processing systems or other suitable processing systems commercially available from Applied Materials, Inc., located in Santa Clara, California. It is conceivable that other processing systems (including those from other manufacturers) may be suitable to benefit from the aspects described herein.

[0019] exist Figure 1In the illustrated example, the factory interface 102 includes a docking station 132 and a factory interface robot 134 to facilitate substrate transfer. The docking station 132 is adapted to receive one or more front-opening unified pods (FOUPs) 136. In some examples, each factory interface robot 134 generally includes a blade 138 disposed at one end of the respective factory interface robot 134, the blade 138 being adapted to transfer the substrate from the factory interface 102 to the loading locking chambers 104, 106.

[0020] Loading and locking chambers 104 and 106 have corresponding ports 140 and 142 coupled to factory interface 102 and corresponding ports 144 and 146 coupled to transfer chamber 108. Transfer chamber 108 also has corresponding ports 148 and 150 coupled to holding chambers 116 and 118 and corresponding ports 152 and 154 coupled to processing chambers 120 and 122. Similarly, transfer chamber 110 has corresponding ports 156 and 158 coupled to holding chambers 116 and 118 and corresponding ports 160, 162, 164, and 166 coupled to processing chambers 124, 126, 128, and 130. Ports 144, 146, 148, 150, 152, 154, 156, 158, 160, 162, 164, and 166 can be, for example, slit valve openings with slit valves for allowing the substrate to pass through via transfer robots 112 and 114, and for providing a seal between the respective chambers to prevent gas from passing between them. Generally, any port is open to allow the substrate to be transferred through. Otherwise, the port is closed.

[0021] Loading and locking chambers 104, 106, transfer chambers 108, 110, holding chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130 can be fluidly coupled to a gas and pressure control system (not specifically shown). The gas and pressure control system may include one or more gas pumps (e.g., turbopumps, cryogenic pumps, roughing pumps), gas sources, various valves, and conduits fluidly coupled to the various chambers. In operation, a factory interface robot 134 transfers a substrate from the FOUP 136 to the loading and locking chamber 104 or 106 via port 140 or 142. The gas and pressure control system then evacuates the loading and locking chamber 104 or 106. The gas and pressure control system also maintains the transfer chambers 108, 110, and holding chambers 116, 118 in an internal low-pressure or vacuum environment (which may include an inert gas). Therefore, the evacuation of the locking chamber 104 or 106 facilitates the transfer of the substrate between the atmospheric environment of the factory interface 102 and the low-pressure or vacuum environment of the transfer chamber 108.

[0022] With the substrate in the de-evacuated loading and locking chamber 104 or 106, the transfer robot 112 transfers the substrate from the loading and locking chamber 104 or 106 to the transfer chamber 108 via port 144 or 146. The transfer robot 112 is then able to transfer the substrate to any processing chamber 120, 122 and / or between any processing chambers 120, 122 for processing via corresponding ports 152, 154, and to holding chambers 116, 118 via corresponding ports 148, 150 for holding pending further transfer. Similarly, the transfer robot 114 can pick up substrates from holding chambers 116 or 118 via ports 156 or 158, and can transfer substrates to any processing chambers 124, 126, 128, 130 and / or between any processing chambers 124, 126, 128, 130 for processing via corresponding ports 160, 162, 164, 166, and transfer substrates to holding chambers 116, 118 via corresponding ports 156, 158 for holding pending further transfer. The transfer and holding of substrates within and between different chambers can be performed in a low-pressure or vacuum environment provided by a gas and pressure control system.

[0023] Processing chambers 120, 122, 124, 126, 128, and 130 can be any suitable chamber for processing a substrate. In some examples, processing chamber 120 is capable of performing an etching process, processing chamber 122 is capable of performing a cleaning process, and processing chambers 126, 128, and 130 are capable of performing corresponding epitaxial growth processes. Processing chamber 120 can be a Selectra type available from Applied Materials Inc. in Santa Clara, California. TM Etching chamber. Processing chamber 122 can be SiCoNi available from Applied Materials, Santa Clara, California. TM Pre-cleaning chambers. Processing chambers 126, 128, or 130 can be Centura, available from Applied Materials, Santa Clara, California. TM Extensional chamber, Volta TM CVD / ALD chamber or Encore TM PVD chamber.

[0024] System controller 168 is coupled to processing system 100 for controlling processing system 100 or its components. For example, system controller 168 may control the operation of processing system 100 by directly controlling chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, and 130, or by controlling controllers associated with chambers 104, 106, 108, 110, 116, 118, 120, 122, 126, 128, and 130. During operation, system controller 168 can collect data and feedback from individual chambers to coordinate the execution of processing system 100.

[0025] The system controller 168 generally includes a central processing unit (CPU) 170, memory 172, and support circuitry 174. The CPU 170 can be one of any type of general-purpose processor that can be used in an industrial environment. Memory 172, or a non-transitory computer-readable medium, can be accessed by the CPU 170 and can be one or more memories, such as random access memory (RAM), read-only memory (ROM), floppy disk, hard disk, or any other form of local or remote digital memory. Support circuitry 174 is coupled to the CPU 170 and may include cache, clock circuitry, input / output subsystems, power supply, etc. The various methods disclosed herein can generally be implemented by the CPU 170 executing computer instruction code, stored as, for example, software routines, in memory 172 (or memory of a specific processing chamber), under the control of the CPU 170. When the computer instruction code is executed by the CPU 170, the CPU 170 controls the chamber to perform processes according to various methods.

[0026] Other processing systems may employ different configurations. For example, more or fewer processing chambers may be coupled to a transport device. In the illustrated example, the transport device includes transport chambers 108, 110 and holding chambers 116, 118. In other examples, more or fewer transport chambers (e.g., one transport chamber) and / or more or fewer holding chambers (e.g., no holding chambers) may be implemented as the transport device in the processing system.

[0027] Figure 2 A process flow diagram is depicted for a method 200 of selectively filling vias with pads in a semiconductor structure such as an interconnect structure 300 formed on a substrate, according to a first embodiment of the present disclosure. Figure 3A , 3B 3C, 3D, 3E, 3F and Figure 3GThis is a cross-sectional view of a portion of the interconnect structure 300 corresponding to various states of method 200. It should be understood that... Figure 3A , 3B 3C, 3D, 3E, 3F and Figure 3G Only a partial schematic of the interconnect structure 300 is shown, and the interconnect structure 300 can contain any number of transistor portions and additional materials with the aspects shown. It should also be noted that, although... Figure 2 The methods shown are described sequentially, but other procedural sequences including one or more operations that have been omitted and / or added and / or rearranged in another desired order are within the scope of embodiments of the present disclosure provided herein.

[0028] As used herein, the term "substrate" refers to a layer of material that forms the basis for subsequent processing operations and includes the surface to be cleaned. Depending on the requirements, the substrate can be a silicon-based material or any suitable insulating or conductive material. The substrate may include, for example, crystalline silicon (e.g., Si). <100> or Si <111> Materials including silicon oxide, strained silicon, silicon germanium, doped or undoped polycrystalline silicon, doped or undoped silicon wafers and patterned or unpatterned wafers, silicon on insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass or sapphire.

[0029] like Figure 3AAs shown, the interconnect structure 300 includes a first dielectric layer 302 formed on a substrate (not shown). The first dielectric layer 302 may be formed of a dielectric material, such as a low dielectric constant dielectric (SiCOH), silicon dioxide (SiO2), silicon nitride (Si3N4), silicon carbide (SiC), aluminum oxide (Al2O3), or aluminum nitride (AlN). A first etch stop layer 304 may be disposed between the first dielectric layer 302 and the substrate. The interconnect structure 300 also includes a conductive layer 306 embedded within the first dielectric layer 302 and separated from it by a pad layer 308 and a barrier layer 310. The conductive layer 306 may be formed of copper (Cu), cobalt (Co), molybdenum (Mo), tungsten (W), or ruthenium (Ru). The pad layer 308 may be formed of ruthenium (Ru) and cobalt (Co) or RuCo. The barrier layer 310 may be formed of tantalum nitride (TaN) or doped tantalum nitride (TaN). The interconnect structure 300 also includes a second dielectric layer 312 having one or more features 314 on the first dielectric layer 302 and the conductive layer 306, such as vias 314V and trenches 314T formed in the conductive layer. The second dielectric layer 312 may be formed of the same material as the first dielectric layer 302, such as a low-dielectric-constant dielectric (SiCOH), silicon dioxide (SiO2), silicon nitride (Si3N4), silicon carbide (SiC), aluminum oxide (Al2O3), or aluminum nitride (AlN). In another embodiment, the second dielectric layer 312 may be formed of a different material than the first dielectric layer 302 while maintaining the same low-dielectric-constant properties. A second etch stop layer 316 may be disposed between the second dielectric layer 312 and the first dielectric layer 302. Within the via 314V, the surface of the conductive layer 306 is exposed.

[0030] Method 200 begins at frame 210, wherein an immersion process is performed to selectively form a passivation layer 318 on the exposed surface of the conductive layer 306 within the via 314V, such as Figure 3B As shown. The soaking process can be carried out in a treatment chamber, such as... Figure 1 The processing chambers shown are 124, 126, 128, or 130.

[0031] The passivation layer 318 can be formed from a self-assembled monolayer (SAM) of organic molecules. In the immersion process, the interconnect structure 300 is immersed in a gaseous precursor comprising unsaturated hydrocarbons at a temperature less than about 450°C and a pressure less than about 80 Torr for a duration greater than about 10 seconds, with the precursor flow rate between 50 sccm and about 600 sccm. In some embodiments, a liquid precursor is used in the immersion process. In the immersion process, the organic molecules in the precursor are absorbed only on metal surfaces, such as the exposed surface of the conductive layer 306. The passivation layer 318 can act as a barrier layer to inhibit the nucleation or growth of subsequent materials deposited thereon.

[0032] In frame 220, a first selective deposition process is performed to form a barrier layer 320 on the inner sidewalls of vias 314V and trenches 314T, rather than on the passivation layer 318, as follows: Figure 3C As shown. The first selective deposition process may include an ALD process in the treatment chamber, for example... Figure 1 The processing chambers shown are 124, 126, 128, or 130.

[0033] The barrier layer 320 may be formed of tantalum nitride (TaN) or doped tantalum nitride (TaN), metal-doped TaN, titanium nitride (TiN), tungsten nitride (WN), or tungsten carbonitride (WCN). The selectivity in the first selective deposition process may be caused by the difference in nucleation of the barrier layer 320 on the exposed surface of the second dielectric layer 312 (e.g., silicon dioxide (SiO2) or silicon nitride (Si3N4)) and on the passivation layer 318. In some embodiments, the barrier layer 320 is deposited by sequentially exposing the interconnect structure 300 to a metal precursor and a reactant.

[0034] In block 230, a removal process is performed to remove the passivation layer 318 from the surface of the conductive layer 306, such as Figure 3D As shown. The removal process can include a dry etching process in an etching chamber, such as... Figure 1 The processing chamber 122 shown.

[0035] The removal process may include anisotropic remote plasma-assisted dry etching processes, such as reactive ion etching (RIE), using a plasma formed from a gas including argon (Ar), helium (He), nitrogen (N2), hydrogen (H2), ammonia (NH3), or combinations thereof. The plasma effluent directionally bombards and removes the passivation layer 318.

[0036] In frame 240, a second selective deposition process is performed to selectively fill via 314V at least partially with conductive via filling material 322, and simultaneously form a liner layer 324 on the barrier layer 320 on the inner sidewalls of via 314V and trench 314T, with or without the aid of a passivation layer (SAM). Figure 3E As shown. The second selective deposition process may be included in the processing chamber (e.g., Figure 1 Any suitable deposition process in the processing chambers 124, 126, 128, or 130 shown, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), or a wet process including electroplating.

[0037] In the second selective deposition process, the interconnect structure 300 is exposed to a precursor comprising a conductive via-filling material 322, which grows from the exposed surface of the conductive layer 306 (e.g., copper (Cu), cobalt (Co), molybdenum (Mo), tungsten (W), or ruthenium (Ru)) at a faster rate, for example, about ten times faster, than from the exposed surface of the barrier layer 320 (e.g., tantalum nitride (TaN)). Thus, the via 314V is at least partially filled with the conductive filler material 322, while a thin conformal liner layer 324 of the same conductive filler material 322 is formed on the barrier layer 320 on the sidewalls of the via 314V and the trench 314T. The conductive via-filling material 322 may be ruthenium (Ru), cobalt (Co), molybdenum (Mo), or tungsten (W).

[0038] As an alternative to a second deposition process that simultaneously fills vias 314V and forms a barrier layer 320 in frame 240, a selective via-hole filling process that at least partially and selectively fills vias 314V in frame 250 and a selective deposition process that forms a liner layer 324 in frame 260 can be performed sequentially with or without the assistance of a passivation layer similar to passivation layer 318. The selective via-hole filling process and the selective deposition process can be included in a processing chamber (e.g., Figure 1 Any suitable deposition process in the processing chambers 124, 126, 128, or 130 shown, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), or a wet process including electroplating.

[0039] In box 250, as Figure 3FAs shown, via 314V is selectively filled at least partially with conductive via filler material 322, without depositing conductive via filler material 322 on the barrier layer 320 on the sidewalls of via 314V and trench 314T. The selectivity in the selective via filling process in frame 250 is caused by the difference in nucleation or growth of conductive filler material 322 on the exposed surface of conductive layer 306 (e.g., copper (Cu), cobalt (Co), molybdenum (Mo), tungsten (W), or ruthenium (Ru)) and the exposed surface of barrier layer 320 (e.g., tantalum nitride (TaN)). In some embodiments, a passivation layer (not shown) similar to passivation layer 318 is formed on barrier layer 320 to prevent conductive filler material 322 from growing on the sidewalls of via 314V and trench 314T during the via filling process in frame 250, and is removed from barrier layer 320 after the via filling process. The conductive via filling material 322 can be ruthenium (Ru), cobalt (Co), molybdenum (Mo), or tungsten (W).

[0040] In box 260, as Figure 3E As shown, the liner layer 324 is selectively deposited on the barrier layer 320 on the inner sidewalls of the via 314V and the trench 314T. The liner layer 324 may be formed of the same conductive material as the conductive via filler material 322, or of a different conductive material, such as ruthenium (Ru), cobalt (Co), molybdenum (Mo), or tungsten (W).

[0041] In box 270, an optional liner treatment process is performed to densify the liner layer 324. The optional liner treatment process may include plasma treatment or gas immersion. Plasma treatment can be performed in, for example... Figure 1 The processing chamber 122 shown uses either capacitively coupled plasma (CCP) or inductively coupled plasma (ICP) processes. In gas immersion, the interconnect structure 300 is immersed in a gas such as hydrogen (H2) or ammonia (NH3).

[0042] In frame 280, a metal-filling process is performed to fill the remaining portions of via 314V and trench 314T with metal-filled conductive material 326, such as Figure 3F As shown. The metal-filled conductive material 326 can be copper (Cu), cobalt (Co), ruthenium (Ru), or molybdenum (Mo). In, for example... Figure 1 In the processing chambers 124, 126, 128 or 130 shown, the metal filling process may include chemical vapor deposition (CVD), physical vapor deposition (PVD) and electroplating.

[0043] Figure 4A process flow diagram of a method 400 for selectively filling vias with pads in a semiconductor structure, such as an interconnect structure 500 formed on a substrate, according to a second embodiment of this disclosure is shown. In the second embodiment, a passivation layer or barrier layer 320, such as a passivation layer 318, is not used, which enhances the selectivity of depositing various layers. The selectivity of filling vias and depositing pads on the inner sidewalls of vias depends on the difference in nucleation or growth of conductive materials on metal and dielectric surfaces. Figure 5A and Figure 5B This is a cross-sectional view of a portion of the interconnect structure 500 corresponding to various states of method 400. It should be understood that... Figure 5A and Figure 5B Only a partial schematic of the interconnect structure 500 is shown, and the interconnect structure 500 can contain any number of transistor portions and additional materials with the aspects shown. It should also be noted that, although... Figure 4 The methods shown are described sequentially, but other procedural sequences including one or more operations that have been omitted and / or added and / or rearranged in another desired order fall within the scope of embodiments of this disclosure provided herein. In the following description, the same element symbols are used for components substantially the same as those in the first embodiment, and descriptions of repeated components may be omitted.

[0044] Method 400 begins at frame 410, wherein a selective deposition process is performed to selectively fill via 314V with conductive via filling material 322, and simultaneously form a liner layer 324 on the barrier layer 320 on the inner sidewalls of via 314V and trench 314T, as shown. Figure 5A As shown. Selective deposition processes can be included in a processing chamber (e.g., Figure 1 Any suitable deposition process in the processing chambers 124, 126, 128, or 130 shown, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), or a wet process including electroplating.

[0045] In a selective deposition process, interconnect structure 300 is exposed to a precursor comprising conductive via filling material 322, which grows from the exposed surface of conductive layer 306 (e.g., copper (Cu), cobalt (Co), molybdenum (Mo), tungsten (W), or ruthenium (Ru)) at a rate, for example, approximately ten times faster, than from the inner sidewalls of vias 314V and trenches 314T (e.g., silicon dioxide (SiO2) or silicon nitride (Si3N4)). Thus, vias 314V are at least partially filled with conductive filling material 322, while thin conformal pad layers 324 of the same conductive filling material 322 are formed on the inner sidewalls of vias 314V and trenches 314T. The conductive via filling material 322 may be ruthenium (Ru), cobalt (Co), molybdenum (Mo), or tungsten (W).

[0046] In box 420, an optional gasket treatment process is performed to densify gasket layer 324. The optional gasket treatment process in box 420 is substantially the same as the optional gasket treatment process in box 270.

[0047] In frame 430, a metal-filling process is performed to fill the remaining portions of via 314V and trench 314T with metal-filled conductive material 326, such as Figure 5B As shown. The metal filling process in box 430 is largely the same as the metal filling process in box 280.

[0048] The embodiments described herein provide a method for at least partially and selectively filling vias while conformally depositing pads on the sidewalls of the vias. In the method described herein, conformal deposition of pads and selective filling of vias can be achieved simultaneously. The selective filling of vias can be complete or partial. Due to the via filling, the overall via resistance is reduced, and because the aspect ratio of the remaining vias is reduced, subsequent copper filling to form interconnects is less difficult.

[0049] While the foregoing embodiments relating to this disclosure are available, other and further embodiments of this disclosure may be devised without departing from its essential scope, and the scope of this disclosure is defined by the appended claims.

Claims

1. A method for selectively filling vias in a semiconductor structure using simultaneous pad deposition, comprising: A passivation layer is selectively formed on the exposed surface of the conductive layer within a via formed in a dielectric layer formed above the conductive layer; A barrier layer is selectively formed on the inner sidewalls of the vias and the trenches formed in the dielectric layer; The via is selectively filled at least partially with a first conductive material, and the first conductive material is deposited on the barrier layer on the inner sidewalls of the via and the trench to form a liner on the inner sidewalls of the via and the trench. as well as The remaining portion of the through-hole and the trench is filled with a second conductive material.

2. The method of claim 1, further comprising: After the formation of the barrier layer and before the selective filling of the via with the first conductive material, the passivation layer is removed from the surface of the conductive layer.

3. The method of claim 1, further comprising: A liner treatment process is performed to densify the liner, the liner treatment process including plasma treatment or gas immersion.

4. The method of claim 1, wherein the passivation layer comprises a self-assembled monolayer (SAM) of organic molecules.

5. The method of claim 1, wherein the dielectric layer comprises a low dielectric constant dielectric (SiOCH), silicon dioxide (SiO2), silicon nitride (Si3N4), silicon carbide (SiC), aluminum oxide (Al2O3), or aluminum nitride (AlN).

6. The method of claim 1, wherein the barrier layer comprises tantalum nitride (TaN), metal-doped TaN, titanium nitride (TiN), tungsten nitride (WN), or tungsten carbonitride (WCN).

7. The method of claim 1, wherein the first conductive material comprises copper (Cu), cobalt (Co), molybdenum (Mo), tungsten (W), or ruthenium (Ru).

8. The method of claim 1, wherein the second conductive material comprises copper (Cu), cobalt (Co), ruthenium (Ru), or molybdenum (Mo).

9. A method for selectively filling vias in a semiconductor structure using pad deposition, comprising: A passivation layer is selectively formed on the exposed surface of the conductive layer within a via formed in a dielectric layer formed above the conductive layer; A barrier layer is selectively formed on the inner wall of the through hole; The via is selectively filled at least partially with a first conductive material, without depositing the first conductive material on the barrier layer on the inner sidewall of the via; A second conductive material is selectively deposited on the barrier layer on the inner sidewalls of the via and the trench formed in the dielectric layer to form a liner on the inner sidewalls of the via and the trench. as well as The remaining portion of the through-hole and the trench is filled with a third conductive material.

10. The method of claim 9, further comprising: After the formation of the barrier layer and before the selective filling of the via with the first conductive material, the passivation layer is removed from the surface of the conductive layer.

11. The method of claim 9, further comprising: A liner treatment process is performed to densify the liner, the liner treatment process including plasma treatment or gas immersion.

12. The method of claim 9, wherein the passivation layer comprises a self-assembled monolayer (SAM) of organic molecules.

13. The method of claim 9, wherein the dielectric layer comprises a low dielectric constant dielectric (SiCOH), silicon dioxide (SiO2), silicon nitride (Si3N4), silicon carbide (SiC), aluminum oxide (Al2O3), or aluminum nitride (AlN).

14. The method of claim 9, wherein the barrier layer comprises tantalum nitride (TaN), metal-doped TaN, titanium nitride (TiN), tungsten nitride (WN), or tungsten carbonitride (WCN).

15. The method of claim 9, wherein The first conductive material includes copper (Cu), cobalt (Co), molybdenum (Mo), tungsten (W), or ruthenium (Ru), and The second conductive material includes copper (Cu), cobalt (Co), molybdenum (Mo), tungsten (W), or ruthenium (Ru).

16. The method of claim 9, wherein The third conductive material includes copper (Cu), cobalt (Co), ruthenium (Ru), and molybdenum (Mo).

17. A method for selectively filling vias in a semiconductor structure using simultaneous pad deposition, comprising: The vias in the dielectric layer formed on the conductive layer are selectively filled at least partially with a first conductive material, and a liner layer is simultaneously formed on the vias and the inner sidewalls of the trenches formed in the dielectric layer; and The remaining portion of the through-hole is filled with a second conductive material.

18. The method of claim 17, further comprising: A liner treatment process is performed to densify the liner, the liner treatment process including plasma treatment or gas immersion.

19. The method of claim 17, wherein the dielectric layer comprises a low dielectric constant dielectric (SiCOH), silicon dioxide (SiO2), silicon nitride (Si3N4), silicon carbide (SiC), aluminum oxide (Al2O3), or aluminum nitride (AlN).

20. The method of claim 17, wherein The first conductive material includes copper (Cu), cobalt (Co), molybdenum (Mo), tungsten (W), or ruthenium (Ru), and The second conductive material includes copper (Cu), cobalt (Co), ruthenium (Ru), or molybdenum (Mo).

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