Semiconductor device

Abstract

A semiconductor device (A10) is provided with a first die pad (21), a first semiconductor element (11), a second die pad (22), a second semiconductor element (12), a sealing resin (50), a first lead (23), a second lead (24), a third lead (25), and a fourth lead (26). The first lead, the second lead, the third lead, and the fourth lead are separated from a third side surface (55) and a fourth side surface (56) of the sealing resin, respectively, and are exposed to the outside from any one of a first side surface (53) and a second side surface (54) of the sealing resin. An area of the first die pad is larger than an area of the second die pad when viewed in a third direction (z) orthogonal to the first direction (x) and the second direction (y). When viewed in the third direction, the first lead and the third lead are each farther from a first imaginary line (VL1) in the first direction toward a side on which the first side surface of the sealing resin is located.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device. Background Technology

[0002] The semiconductor device disclosed in Patent Document 1 includes: two chip pads; a control element (controller) and a drive element (gate driver), respectively mounted on the two chip pads; and a sealing resin covering the two chip pads, the control element, and the drive element. This semiconductor device drives switching elements such as IGBTs and MOSFETs. This semiconductor device is used in inverter circuits, etc.

[0003] In this semiconductor device, the power supply voltage supplied to the driving element is higher than the voltage applied to the switching element, therefore the power supply voltage supplied to the control element is different from the power supply voltage supplied to the driving element. Consequently, the voltage applied to the control element and its conductive path differs from the voltage applied to the driving element and its conductive path. Therefore, in this semiconductor device, by using an insulating element in the electrical signal transmission path between the control element and the driving element, the control element and its conductive path are mutually insulated from the driving element and its conductive path. This prevents the insulation of the control element and the driving element from breaking down.

[0004] In this semiconductor device, two chip pads include: a first chip pad mounting a control element and an insulating element; and a second chip pad mounting a driving element. The semiconductor device also includes: a first lead connected to one side of the first chip pad in a first direction (the X direction shown in Patent Document 1); and a second lead opposite to the first lead in a second direction (the Y direction shown in Patent Document 1). The second lead is located closer to the second chip pad than the first lead. Viewed in the thickness direction of the semiconductor device, the area of ​​the first chip pad is larger than the area of ​​the second chip pad. In this case, the dimension in the second direction of the portion of the first lead covered by the sealing resin is sometimes larger than the dimension in the second direction of the portion of the second lead covered by the sealing resin. Therefore, when forming the sealing resin, the molten resin flows more easily to the second chip pad than to the first chip pad, and thus the sealing resin filling may be insufficient. If the sealing resin filling is insufficient, the proportion of voids in the sealing resin becomes higher, thus raising concerns about a decrease in the insulation withstand voltage of the semiconductor device.

[0005] Existing technical documents

[0006] Patent documents

[0007] Patent Document 1: Japanese Patent Application Publication No. 2016-207714 Summary of the Invention

[0008] The problem that the invention aims to solve

[0009] One object of this disclosure is to provide a semiconductor device that is an improvement over the conventional one. In particular, in view of the above, one object of this disclosure is to provide a semiconductor device that can improve the filling state of the sealing resin.

[0010] Solution for solving the problem

[0011] A semiconductor device provided by one aspect of this disclosure includes: a first chip pad; a first semiconductor element mounted on the first chip pad; a second chip pad located away from the first chip pad along a first direction; a second semiconductor element mounted on the second chip pad; a sealing resin having a first side and a second side facing opposite sides in the first direction, and a third side and a fourth side facing opposite sides in a second direction orthogonal to the first direction, and covering the first chip pad, the first semiconductor element, the second chip pad, and the second semiconductor element; a first lead including a portion extending toward the first chip pad and located closest to the third side; a second lead including a portion extending toward the second chip pad and located closest to the third side; a third lead including a portion extending toward the first chip pad and located closest to the fourth side; and a fourth lead including a portion extending toward the second chip pad and located closest to the fourth side. The first lead and the third lead exit from the third side and the fourth side, respectively, and are exposed externally from the first side. The second lead and the fourth lead exit from the third side and the fourth side, respectively, and are exposed outward from the second side. When viewed from a third direction orthogonal to the first and second directions, the area of ​​the first chip pad is larger than the area of ​​the second chip pad. When viewed from this third direction, the first lead and the third lead are respectively farther away from the side containing the first side in the first direction than a first imaginary line passing through the center of the first chip pad and extending along the second direction.

[0012] Invention Effects

[0013] Based on the above structure, the filling state of the sealing resin can be improved.

[0014] Other features and advantages of this disclosure will become more apparent from the following detailed description based on the accompanying drawings. Attached Figure Description

[0015] Figure 1 This is a top view of a semiconductor device according to a first embodiment of the present disclosure.

[0016] Figure 2 Is with Figure 1 The corresponding top view is shown through the sealing resin.

[0017] Figure 3 Is with Figure 2 The corresponding top view shows each of the first semiconductor element, the second semiconductor element, and the insulating element, and omits the illustration of each of the plurality of first metal wires to the plurality of fourth metal wires.

[0018] Figure 4 yes Figure 1 Rear view of the semiconductor device shown.

[0019] Figure 5 yes Figure 1 The front view of the semiconductor device shown.

[0020] Figure 6 yes Figure 1 Left side view of the semiconductor device shown.

[0021] Figure 7 yes Figure 1 The right-side view of the semiconductor device shown.

[0022] Figure 8 It is along Figure 2 A cross-sectional view of line VIII-VIII.

[0023] Figure 9 It is along Figure 2 A cross-sectional view of the IX-IX line.

[0024] Figure 10 It is along Figure 2 A cross-sectional view along the XX line.

[0025] Figure 11 This is a top view of a semiconductor device according to a second embodiment of the present disclosure.

[0026] Figure 12 Is with Figure 11 The corresponding top view is shown through the sealing resin.

[0027] Figure 13 Is with Figure 12 The corresponding top view shows each of the first semiconductor element, the second semiconductor element, and the insulating element, and omits the illustration of each of the plurality of first metal wires to the plurality of fourth metal wires.

[0028] Figure 14 yes Figure 11 Rear view of the semiconductor device shown.

[0029] Figure 15 yes Figure 11 The front view of the semiconductor device shown.

[0030] Figure 16 It is along Figure 12 A cross-sectional view along the XVI-XVI line.

[0031] Figure 17 It is along Figure 12 A cross-sectional view along line XVII-XVII.

[0032] Figure 18 This is a top view of a semiconductor device according to a third embodiment of the present disclosure.

[0033] Figure 19 yes Figure 18 Rear view of the semiconductor device shown.

[0034] Figure 20 yes Figure 18 The front view of the semiconductor device shown.

[0035] Figure 21 This is a top view of a semiconductor device according to the fourth embodiment of the present disclosure.

[0036] Figure 22 yes Figure 21 Rear view of the semiconductor device shown.

[0037] Figure 23 yes Figure 21 The front view of the semiconductor device shown. Detailed Implementation

[0038] The manner in which this disclosure is carried out is described with reference to the accompanying drawings.

[0039] First implementation method:

[0040] based on Figures 1-10The semiconductor device A10 according to the first embodiment of this disclosure will be described below. The semiconductor device A10 includes a first semiconductor element 11, a second semiconductor element 12, an insulating element 13, a first chip pad 21, a second chip pad 22, a first lead 23, a second lead 24, a third lead 25, a fourth lead 26, a plurality of first intermediate leads 31, a plurality of second intermediate leads 32, and a sealing resin 50. The semiconductor device A10 also includes two support leads 28, a plurality of first metal wires 41, a plurality of second metal wires 42, a plurality of third metal wires 43, and a plurality of fourth metal wires 44. The semiconductor device A10 is surface-mounted on a wiring substrate of an inverter device, such as an electric vehicle or a hybrid vehicle. The package form of the semiconductor device A10 is SOP (Small Outline Package). However, the package form of the semiconductor device A10 is not limited to SOP. Here, for ease of understanding, Figure 2 Shown through sealing resin 50. Figure 2 In the diagram, the outline of the sealing resin 50 is represented by an imaginary line (double-dotted line). Figure 3 For ease of understanding, relative to Figure 2 The diagram is shown through each of the first semiconductor element 11, the second semiconductor element 12, and the insulating element 13, and the illustrations of each of the plurality of first metal wires 41 to the plurality of fourth metal wires 44 are omitted. Figure 3 In the diagram, the outlines of the first semiconductor element 11, the second semiconductor element 12, the insulating element 13, and the sealing resin 50 are represented by imaginary lines.

[0041] In the description of semiconductor device A10, for convenience, for example, a direction orthogonal to the normal direction of the first mounting surface 21A of the first chip pad 21 (described later) is referred to as "first direction x". A direction orthogonal to the first direction x is referred to as "second direction y". The second direction y is orthogonal to the normal direction of the first mounting surface 21A. A direction orthogonal to both the first direction x and the second direction y is referred to as "third direction z". The third direction z corresponds to the normal direction of the first mounting surface 21A.

[0042] In semiconductor device A10, a first semiconductor element 11, a second semiconductor element 12, and an insulating element 13 are each composed of individual elements. The second semiconductor element 12 is located on the opposite side of the first semiconductor element 11 in the first direction x, with the insulating element 13 as a reference. The insulating element 13 is located next to the first semiconductor element 11 in the second direction y. Viewed in the third direction z, the first semiconductor element 11, the second semiconductor element 12, and the insulating element 13 are all rectangular in shape with the second direction y as their longer side.

[0043] The first semiconductor element 11 controls the second semiconductor element 12. The first semiconductor element 11 includes: a circuit for converting an electrical signal input from another semiconductor device into a PWM control signal; a transmitting circuit for transmitting the PWM control signal to the second semiconductor element 12; and a receiving circuit for receiving an electrical signal from the second semiconductor element 12.

[0044] The second semiconductor element 12 drives a switching element located outside the semiconductor device A10. The switching element is, for example, an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The second semiconductor element 12 includes a receiving circuit for receiving a PWM control signal, circuitry for driving the switching element based on the PWM control signal, and a transmitting circuitry for transmitting an electrical signal to the first semiconductor element 11. This electrical signal may, for example, be an output signal from a temperature sensor located near the motor.

[0045] The insulating element 13 transmits electrical signals such as PWM (Pulse Width Modulation) control signals in an isolated state. The insulating element 13 is of the inductively coupled type. An example of an inductively coupled insulating element 13 is an insulated transformer. An insulated transformer transmits electrical signals based on an isolated state by inductively coupling two inductors (coils). These two inductors include a transmitting-side inductor and a receiving-side inductor. These two inductors are stacked on a third direction z. A dielectric layer made of silicon dioxide (SiO2) or the like is located between the transmitting-side inductor and the receiving-side inductor. Through this dielectric layer, the transmitting-side inductor and the receiving-side inductor are electrically insulated. Alternatively, the insulating element 13 can also be of the capacitive type. An example of a capacitive insulating element 13 is a capacitor.

[0046] The voltages applied to the first semiconductor element 11 and the second semiconductor element 12 are different. Therefore, a potential difference is generated between the first semiconductor element 11 and the second semiconductor element 12. In semiconductor device A10, the voltage applied to the second semiconductor element 12 is higher than the voltage applied to the first semiconductor element 11. Furthermore, in semiconductor device A10, the power supply voltage supplied to the second semiconductor element 12 is higher than the power supply voltage supplied to the first semiconductor element 11.

[0047] Therefore, in semiconductor device A10, a first circuit having a first semiconductor element 11 and a second circuit having a second semiconductor element 12 are insulated from each other by an insulating element 13. The insulating element 13 is conductive to both the first and second circuits. In addition to the first semiconductor element 11, the first circuit includes a first lead 23, a third lead 25, and a plurality of first intermediate leads 31. In addition to the second chip pad 22, the second circuit includes a second lead 24, a fourth lead 26, and a plurality of second intermediate leads 32. The potentials of the first and second circuits are relatively different. In semiconductor device A10, the potential of the first circuit is higher than that of the second circuit. Based on this, the insulating element 13 relays the mutual signals between the first and second circuits. For example, in the inverter device of an electric vehicle or hybrid vehicle, the voltage applied to the ground (GND) of the first semiconductor element 11 is approximately 0V, while the voltage applied to the ground of the second semiconductor element 12 sometimes transitionally becomes 600V or higher.

[0048] like Figure 2 as well as Figure 8 As shown, the first semiconductor element 11 has a plurality of first electrodes 111. The plurality of first electrodes 111 are disposed on the upper surface of the first semiconductor element 11 (the surface facing the same side as the first mounting surface 21A of the first chip pad 21 described later). The plurality of first electrodes 111 include, for example, aluminum (Al). The plurality of first electrodes 111 are connected to a circuit formed in the first semiconductor element 11.

[0049] like Figure 2 as well as Figure 8 As shown, the second semiconductor element 12 has a plurality of second electrodes 121. The plurality of second electrodes 121 are disposed on the upper surface of the second semiconductor element 12 (the surface facing the same side as the second mounting surface 22A of the second chip pad 22 described later). The plurality of second electrodes 121 include, for example, aluminum. The plurality of second electrodes 121 are connected to a circuit formed in the second semiconductor element 12.

[0050] like Figure 2 as well as Figure 8As shown, the insulating element 13 is located between the second semiconductor element 12 and the first semiconductor element 11 in the third direction z. Therefore, the first semiconductor element 11 is located on the side opposite to the second semiconductor element 12 in the first direction x, with reference to the insulating element 13. A plurality of third electrodes 131 and a plurality of fourth electrodes 132 are provided on the upper surface of the insulating element 13 (the surface facing the same side as the first mounting surface 21A of the first chip pad 21 described later). The plurality of third electrodes 131 and the plurality of fourth electrodes 132 are respectively connected to either the transmitting-side inductor or the receiving-side inductor. The plurality of third electrodes 131 are arranged along the second direction y and are located between the first semiconductor element 11 and the second semiconductor element 12 in the first direction x. The plurality of fourth electrodes 132 are arranged along the second direction y and are located on the side opposite to the first semiconductor element 11 in the first direction x, with reference to the plurality of third electrodes 131. The plurality of third electrodes 131 and the plurality of fourth electrodes 132 may include, for example, aluminum.

[0051] like Figure 1 As shown, sealing resin 50 covers the first semiconductor element 11, the second semiconductor element 12, the insulating element 13, the first chip pad 21, and the second chip pad 22. Figure 8 As shown, the sealing resin 50 also covers a plurality of first metal wires 41, a plurality of second metal wires 42, a plurality of third metal wires 43, and a plurality of fourth metal wires 44. The sealing resin 50 is an insulator. The sealing resin 50 is, for example, made of a material including epoxy resin. Viewed in the third direction z, the sealing resin 50 is rectangular.

[0052] like Figures 4-7 As shown, the sealing resin 50 has a top surface 51, a bottom surface 52, a first side surface 53, a second side surface 54, a third side surface 55, and a fourth side surface 56.

[0053] like Figures 4-7 As shown, the top surface 51 and the bottom surface 52 face opposite sides of each other in the third direction z. The top surface 51 and the bottom surface 52 are both generally flat.

[0054] like Figures 4-6As shown, the first side surface 53 is connected to the top surface 51 and the bottom surface 52, and faces the first direction x. The first side surface 53 is located closer to the first chip pad 21 than the second side surface 54. The first side surface 53 includes a first upper portion 531, a first lower portion 532, and a first middle portion 533. The first upper portion 531 is connected to the top surface 51 on one side of the third direction z, and the other side of the third direction z is connected to the first middle portion 533. The first upper portion 531 is inclined relative to the top surface 51. The first lower portion 532 is connected to the bottom surface 52 on one side of the third direction z, and the other side of the third direction z is connected to the first middle portion 533. The first lower portion 532 is inclined relative to the bottom surface 52. The first middle portion 533 is located between the first upper portion 531 and the first lower portion 532 in the third direction z. The in-plane direction of the first middle portion 533 includes the third direction z. Viewed in the third direction z, the first middle portion 533 is located on the outer side of the top surface 51 and the bottom surface 52.

[0055] like Figure 4 , Figure 5 as well as Figure 7 As shown, the second side surface 54 is connected to the top surface 51 and the bottom surface 52, and faces the opposite side to the first side surface 53 in the first direction x. The second side surface 54 is located closer to the second chip pad 22 than the first side surface 53. The second side surface 54 includes a second upper portion 541, a second lower portion 542, and a second middle portion 543. The second upper portion 541 is connected to the top surface 51 on one side in the third direction z, and to the second middle portion 543 on the other side in the third direction z. The second upper portion 541 is inclined relative to the top surface 51. The second lower portion 542 is connected to the bottom surface 52 on one side in the third direction z, and to the second middle portion 543 on the other side in the third direction z. The second lower portion 542 is inclined relative to the bottom surface 52. The second middle portion 543 is located between the second upper portion 541 and the second lower portion 542 in the third direction z. The in-plane direction of the second middle portion 543 includes the third direction z. Viewed in the third direction z, the second middle portion 543 is located on the outer side of the top surface 51 and the bottom surface 52.

[0056] like Figure 4 , Figure 6 as well as Figure 7As shown, the third side surface 55 is connected to the top surface 51 and the bottom surface 52, and faces towards the side in the second direction y. The third side surface 55 includes a third upper part 551, a third lower part 552, and a third middle part 553. The third upper part 551 is connected to the top surface 51 on the third direction z side, and the other side of the third direction z side is connected to the third middle part 553. The third upper part 551 is inclined relative to the top surface 51. The third lower part 552 is connected to the bottom surface 52 on the third direction z side, and the other side of the third direction z side is connected to the third middle part 553. The third lower part 552 is inclined relative to the bottom surface 52. The third middle part 553 is located between the third upper part 551 and the third lower part 552 in the third direction z. The in-plane direction of the third middle part 553 includes the third direction z. When viewed in the third direction z, the third middle part 553 is located on the outer side of the top surface 51 and the bottom surface 52.

[0057] like Figures 5-7 As shown, the fourth side surface 56 is connected to the top surface 51 and the bottom surface 52, and faces the side opposite to the third side surface 56 in the second direction y. The fourth side surface 56 includes a fourth upper part 561, a fourth lower part 562, and a fourth middle part 563. The fourth upper part 561 is connected to the top surface 51 on one side in the third direction z, and the other side in the third direction z is connected to the fourth upper part 561. The fourth upper part 561 is inclined relative to the top surface 51. The fourth lower part 562 is connected to the bottom surface 52 on one side in the third direction z, and the other side in the third direction z is connected to the fourth middle part 563. The fourth lower part 562 is inclined relative to the bottom surface 52. The fourth middle part 563 is located between the fourth upper part 561 and the fourth lower part 562 in the third direction z. The in-plane direction of the fourth middle part 563 includes the third direction z. Viewed in the third direction z, the third middle part 563 is located outside the top surface 51 and the bottom surface 52.

[0058] The first chip pad 21, the second chip pad 22, the first lead 23, the second lead 24, the third lead 25, the fourth lead 26, the plurality of first intermediate leads 31, and the plurality of second intermediate leads 32 all comprise copper (Cu). The first chip pad 21, the second chip pad 22, and these leads are formed by the same lead frame.

[0059] like Figure 1 as well as Figure 2As shown, the first chip pad 21 and the second chip pad 22 are separated from each other in the first direction x. In the semiconductor device A10, a first semiconductor element 11 and an insulating element 13 are mounted on the first chip pad 21, and a second semiconductor element 12 is mounted on the second chip pad 22. In this case, when viewed in the third direction z, the area of ​​the first chip pad 21 is larger than the area of ​​the second chip pad 22. Alternatively, the first semiconductor element 11 may be mounted on the first chip pad 21, and the second semiconductor element 12 and the insulating element 13 may be mounted on the second chip pad 22.

[0060] like Figure 8 as well as Figure 9 As shown, the first chip pad 21 has a first mounting surface 21A facing a third direction z. A first semiconductor element 11 and an insulating element 13 are respectively bonded to the first mounting surface 21A via a bonding layer 29. The bonding layer 29 is composed of a paste including metal particles. These metal particles are, for example, silver (Ag). Therefore, the bonding layer 29 is conductive. Alternatively, the bonding layer 29 can also be solder. The first chip pad 21 is covered by a sealing resin 50.

[0061] like Figure 2 , Figure 8 as well as Figure 9 As shown, the first chip pad 21 is provided with two first holes 211, multiple second holes 212, and two third holes 213. The two first holes 211, multiple second holes 212, and two third holes 213 respectively penetrate the first chip pad 21 in a third direction z. The two first holes 211 are located on both sides of the first semiconductor element 11 in a second direction y. The two first holes 211 extend along a first direction x. The multiple second holes 212 are located between the first semiconductor element 11 and the insulating element 13 in the first direction x. The multiple second holes 212 extend along the second direction y. The multiple second holes 212 are arranged along the second direction y. The two third holes 213 are located on both sides of the insulating element 13 in the second direction y. The two third holes 213 extend along the first direction x.

[0062] like Figure 1 as well as Figure 2As shown, the first lead 23 includes a portion extending toward the first chip pad 21 and is located closest to the third side 55 of the sealing resin 50. The first lead 23 is connected to one side of the first chip pad 21 in the second direction y. The first lead 23 is separated from the third side 55 and the fourth side 56 of the sealing resin 50. The first lead 23 is exposed externally from the first side 53 of the sealing resin 50. The first lead 23 has a first interior 231 and a first exterior 232. The first interior 231 is connected to the first chip pad 21 and is covered by the sealing resin 50. The first exterior 232 is connected to the first interior 231 and is exposed externally. When viewed in the third direction z, the first exterior 232 extends in the first direction x. Figure 4 As shown, the first outer surface 232 is curved in a gull-wing shape when viewed in the second direction y. The surface of the first outer surface 232 is, for example, tin-plated.

[0063] like Figure 1 as well as Figure 2 As shown, the third lead 25 includes a portion extending toward the first chip pad 21 and is located closest to the fourth side 56 of the sealing resin 50. The third lead 25 is connected to the side opposite to the side where the first lead 23 is located in the second direction y of the first chip pad 21. The third lead 25 is separate from the third side 55 and the fourth side 56 of the sealing resin 50. The third lead 25 is exposed externally from the first side 53 of the sealing resin 50. The third lead 25 has a third interior 251 and a third exterior 252. The third interior 251 is connected to the first chip pad 21 and is covered by the sealing resin 50. The third exterior 252 is connected to the third interior 251 and is exposed externally. When viewed in the third direction z, the third exterior 252 extends in the first direction x. Figure 5 As shown, the third outer portion 252 is curved into a gull-wing shape when viewed in the second direction y. For example, tin plating is applied to the surface of the third outer portion 252.

[0064] like Figure 9 As shown, when viewed in the second direction y, the first interior 231 of the first lead 23 and the third interior 251 of the third lead 25 overlap with the first chip pad 21, respectively.

[0065] like Figure 8 as well as Figure 10 As shown, the second chip pad 22 has a second mounting surface 22A facing the same side as the first mounting surface 21A of the first chip pad 21 in the third direction z. The second semiconductor element 12 is bonded to the second mounting surface 22A via a bonding layer 29. The second chip pad 22 is covered by a sealing resin 50.

[0066] like Figure 1 as well as Figure 2As shown, the second lead 24 includes a portion extending toward the second chip pad 22 and is located closest to the third side 55 of the sealing resin 50. The second lead 24 is connected to one side of the second chip pad 22 in the second direction y. The second lead 24 is separated from the third side 55 and the fourth side 56 of the sealing resin 50. The second lead 24 is exposed externally from the second side 54 of the sealing resin 50. The second lead 24 has a second interior 241 and a second exterior 242. The second interior 241 is connected to the second chip pad 22 and is covered by the sealing resin 50. The second exterior 242 is connected to the second interior 241 and is exposed externally. When viewed in the third direction z, the second exterior 242 extends in the first direction x. Figure 4 As shown, the second outer portion 242 is curved in a gull-wing shape when viewed in the second direction y. The surface of the second outer portion 242 is, for example, tin-plated.

[0067] like Figure 1 as well as Figure 2 As shown, the fourth lead 26 includes a portion extending toward the second chip pad 22 and is located closest to the fourth side surface 56 of the sealing resin 50. The fourth lead 26 is connected in the second direction y of the second chip pad 22 to the opposite side of the side where the second lead 24 is located. The fourth lead 26 is separated from the third side surface 55 and the fourth side surface 56 of the sealing resin 50. The fourth lead 26 is exposed externally from the second side surface 54 of the sealing resin 50. The fourth lead 26 has a fourth interior 261 and a fourth exterior 262. The fourth interior 261 is connected to the second chip pad 22 and is covered by the sealing resin 50. The fourth exterior 262 is connected to the fourth interior 261 and is exposed externally. When viewed in the third direction z, the fourth exterior 262 extends in the first direction x. Figure 5 As shown, the fourth outer portion 262 is curved into a gull-wing shape when viewed in the second direction y. For example, tin plating is applied to the surface of the fourth outer portion 262.

[0068] like Figure 10 As shown, when viewed in the second direction y, the second interior 241 of the second lead 24 and the fourth interior 261 of the fourth lead 26 overlap with the second chip pad 22, respectively.

[0069] like Figure 3 As shown, when viewed in the third direction z, the first lead 23 and the third lead 25 are respectively further away from the first imaginary line VL1 in the first direction x towards the side where the first side surface 53 of the sealing resin 50 is located. When viewed in the third direction z, the first imaginary line VL1 passes through the center C1 of the first chip pad 21 and extends along the second direction y.

[0070] like Figure 3As shown, when viewed in the third direction z, the second lead 24 and the fourth lead 26 overlap with the second imaginary line VL2. When viewed in the third direction z, the second imaginary line VL2 passes through the center C2 of the second chip pad 22 and extends along the second direction y.

[0071] like Figure 3 As shown, when viewed in the third direction z, the first interior 231 of the first lead 23, the third interior 251 of the third lead 25, and the plurality of second holes 212 of the first chip pad 21 overlap with the third imaginary line VL3 extending along the second direction y.

[0072] like Figure 3 As shown, the dimension L2 of the second interior 241 of the second lead 24 in the first direction x is equal to the dimension L1 of the first interior 231 of the first lead 23 in the first direction x. Viewed in the third direction z, the minimum distance d2 between the second interior 241 and the third side surface 55 of the sealing resin 50 in the second direction y is equal to the minimum distance d1 between the first interior 231 and the third side surface 55 in the second direction y.

[0073] like Figure 3 As shown, the dimension L4 of the fourth interior 261 of the fourth lead 26 in the first direction x is equal to the dimension L3 of the third interior 251 of the third lead 25 in the first direction x. Viewed in the third direction z, the minimum distance d4 between the fourth interior 261 and the fourth side surface 56 of the sealing resin 50 in the second direction y is equal to the minimum distance d3 between the third interior 251 and the fourth side surface 56 in the second direction y.

[0074] like Figure 4 As shown, a first gate trace 55A is formed on the third side surface 55 of the sealing resin 50. The first gate trace 55A includes a portion of the third lower portion 552 of the third side surface 55 and a portion of the third middle portion 553 of the third side surface 55. The surface roughness of the first gate trace 55A is greater than the surface roughness of other areas of the third side surface 55 besides the first gate trace 55A. Figure 5 As shown, a second gate trace 56A is formed on the fourth side surface 56 of the sealing resin 50. The second gate trace 56A includes a portion of the fourth lower portion 562 of the fourth side surface 56 and a portion of the fourth middle portion 563 of the fourth side surface 56. The surface roughness of the second gate trace 56A is greater than the surface roughness of other areas of the fourth side surface 56 other than the second gate trace 56A.

[0075] The first gate mark 55A and the second gate mark 56A are formed during the transfer molding process of forming the sealing resin 50, as the resin in the mold filling the flow channel separates from the sealing resin 50. The first gate mark 55A is formed at the resin inlet of the mold cavity. The second gate mark 56A is formed at the resin outlet of the mold cavity.

[0076] like Figure 3 As shown, the first gate trace 55A is located between the first interior 231 of the first lead 23 and the second interior 241 of the second lead 24. The second gate trace 56A is located between the third interior 251 of the third lead 25 and the fourth interior 261 of the fourth lead 26.

[0077] like Figure 1 as well as Figure 2 As shown, the two support leads 28 are separated from each other in the first direction x. The two support leads 28 extend respectively in the first direction x. The two support leads 28 are respectively connected to the first chip pad 21 and the second chip pad 22. Figure 6 as well as Figure 7 As shown, each of the two support leads 28 has an end face 28A facing the first direction x. The end face 28A of the support lead 28 connected to the first chip pad 21 is exposed from the first side surface 53 of the sealing resin 50. The end face 28A of the support lead 28 connected to the second chip pad 22 is exposed from the second side surface 54 of the sealing resin 50.

[0078] like Figure 1 as well as Figure 2 As shown, a plurality of first intermediate leads 31 are located between the first lead 23 and the third lead 25 in the second direction y. The plurality of first intermediate leads 31 are located on the opposite side of the second chip pad 22 in the first direction x, with the first chip pad 21 as a reference. The plurality of first intermediate leads 31 are arranged along the second direction y. At least one of the plurality of first intermediate leads 31 is connected to the first semiconductor element 11 via any one of the plurality of second metal wires 42.

[0079] like Figure 2 as well as Figure 8 As shown, the plurality of first intermediate leads 31 each have an inner 311 and an outer 312. The inner 311 is covered by a sealing resin 50. The outer 312 is connected to the inner 311 and protrudes outward from the first side 53 of the sealing resin 50. Viewed from a third direction z, the outer 312 extends along a first direction x. Viewed from a second direction y, the outer 312 is curved into a gull-wing shape. The shape of the outer 312 is similar to... Figure 4 The first outer portion 232 of the first lead 23 shown has the same shape. For example, the surface of the outer portion 312 is tin-plated.

[0080] like Figure 1 as well as Figure 2 As shown, a plurality of second intermediate leads 32 are located between the second lead 24 and the fourth lead 26 in the second direction y. The plurality of second intermediate leads 32 are located on the opposite side of the first chip pad 21 in the first direction x, with the second chip pad 22 as a reference. The plurality of second intermediate leads 32 are arranged along the second direction y. At least one of the plurality of second intermediate leads 32 is connected to the second semiconductor element 12 via any one of the plurality of fourth metal wires 44.

[0081] like Figure 2 as well as Figure 8 As shown, the plurality of second intermediate leads 32 each have an inner 321 and an outer 322. The inner 321 is covered by a sealing resin 50. The outer 322 is connected to the inner 321 and protrudes outward from the second side 54 of the sealing resin 50. Viewed from a third direction z, the outer 322 extends along a first direction x. Viewed from a second direction y, the outer 322 is curved into a gull-wing shape. The shape of the outer 322 is similar to... Figure 4 The second outer portion 242 of the second lead 24 shown has the same shape. For example, the surface of the outer portion 322 is tin-plated.

[0082] like Figure 2 and Figure 8 As shown, a plurality of first metal wires 41 are electrically bonded to any one of the plurality of third electrodes 131 of the insulating element 13 and any one of the plurality of first electrodes 111 of the first semiconductor element 11. Thus, the first semiconductor element 11 is connected to the insulating element 13. The plurality of first metal wires 41 are arranged along a second direction y. Any one of the plurality of first metal wires 41 crosses any one of the plurality of second holes 212 disposed on the first chip pad 21. The plurality of first metal wires 41 may include, for example, gold.

[0083] like Figure 2 as well as Figure 8As shown, a plurality of second metal wires 42 are electrically bonded to the interior 311 of any one of the plurality of first electrodes 111 and any one of the plurality of first intermediate leads 31 of the first semiconductor element 11. Thus, at least one of the plurality of first intermediate leads 31 is connected to the first semiconductor element 11. At least one of the plurality of second metal wires 42 is electrically bonded to the first interior 231 of any one of the plurality of first electrodes 111 and the first lead 23. Thus, the first lead 23 is connected to the first semiconductor element 11. Furthermore, at least one of the plurality of second metal wires 42 is electrically bonded to the third interior 251 of any one of the plurality of first electrodes 111 and the third lead 25. Thus, the third lead 25 is connected to the first semiconductor element 11. At least one of the first leads 23 and the third leads 25 serves as the ground wire of the first semiconductor element 11. The plurality of second metal wires 42 may, for example, comprise gold. Alternatively, the plurality of second metal wires 42 may each have a core material comprising copper and a covering comprising palladium covering the core material.

[0084] like Figure 2 and Figure 8 As shown, a plurality of third metal wires 43 are electrically bonded to any one of the plurality of fourth electrodes 132 of the insulating element 13 and any one of the plurality of second electrodes 121 of the second semiconductor element 12. Thus, the second semiconductor element 12 is connected to the insulating element 13. The plurality of third metal wires 43 are arranged along a second direction y. The plurality of third metal wires 43 span between the first chip pad 21 and the second chip pad 22. The plurality of third metal wires 43 may include, for example, gold.

[0085] like Figure 2 and Figure 8 As shown, a plurality of fourth metal wires 44 are electrically bonded to the interior 321 of any one of the plurality of second electrodes 121 and any one of the plurality of second intermediate leads 32 of the second semiconductor element 12. Thus, at least one of the plurality of second intermediate leads 32 is connected to the second semiconductor element 12. At least one of the plurality of fourth metal wires 44 is electrically bonded to the second interior 241 of any one of the plurality of second electrodes 121 and the second lead 24. Thus, the second lead 24 is connected to the second semiconductor element 12. At least one of the plurality of fourth metal wires 44 is electrically bonded to the fourth interior 261 of any one of the plurality of second electrodes 121 and the fourth lead 26. Thus, the fourth lead 26 is connected to the second semiconductor element 12. The second lead 24 and at least one of the fourth leads 26 serve as the ground wire of the second semiconductor element 12. The plurality of fourth metal wires 44 may, for example, comprise gold. Furthermore, the plurality of fourth metal wires 44 may each have a core material comprising copper and a cladding comprising palladium and covering the core material.

[0086] In the motor drive circuit of an inverter device, a half-bridge circuit is generally configured, comprising a low-side (low-potential side) switching element and a high-side (high-potential side) switching element. In the following description, the case where these switching elements are MOSFETs is taken as the example. Here, in the low-side switching element, both the source of the switching element and the reference potential of the gate driver driving the switching element are grounded. On the other hand, in the high-side switching element, both the source of the switching element and the reference potential of the gate driver driving the switching element are equivalent to the potential at the output node of the half-bridge circuit. The potential at the output node changes depending on the driving of the high-side and low-side switching elements, thus changing the reference potential of the gate driver driving the high-side switching element. When the high-side switching element is turned on, this reference potential is equivalent to the voltage applied to the drain of the high-side switching element (e.g., 600V or more). In the semiconductor device A10, the grounding of the first semiconductor element 11 and the grounding of the second semiconductor element 12 are separate structures. Therefore, when using semiconductor device A10 as a gate driver for driving high-side switching elements, a voltage equivalent to the voltage applied to the drain of the high-side switching element is applied to the ground transition of the second semiconductor element 12.

[0087] Next, the function and effect of semiconductor device A10 will be explained.

[0088] Semiconductor device A10 includes a first chip pad 21, a first semiconductor element 11, a second chip pad 22, a second semiconductor element 12, a sealing resin 50, a first lead 23, a second lead 24, a third lead 25, and a fourth lead 26. The first lead 23, the second lead 24, the third lead 25, and the fourth lead 26 are separated from the third side 55 and the fourth side 56 of the sealing resin 50, respectively, and are exposed to the outside from either the first side 53 or the second side 54 of the sealing resin 50. Viewed in a third direction z, the area of ​​the first chip pad 21 is larger than the area of ​​the second chip pad 22. Viewed in a third direction z, the first lead 23 and the third lead 25 are respectively separated from the third side 55 and the fourth side 56 of the sealing resin 50. Figure 3The first imaginary line VL1 shown is further away from the side where the first side 53 of the sealing resin 50 is located in the first direction x. By adopting this structure, the dimension of the second interior 241 of the second lead 24 covered by the sealing resin 50 in the first direction x can be set to a value closer to the dimension of the first interior 231 of the first lead 23 covered by the sealing resin 50 in the first direction x. Furthermore, the dimension of the fourth interior 261 of the fourth lead 26 covered by the sealing resin 50 in the first direction x can be set to a value closer to the dimension of the third interior 251 of the third lead 25 covered by the sealing resin 50 in the first direction x. Here, when forming the sealing resin 50, the first lead 23, the second lead 24, the third lead 25, and the fourth lead 26 restrict the flow of molten resin in the cavity of the molding die. Therefore, by adopting this structure, the molten resin whose flow is restricted by the first lead 23, the second lead 24, the third lead 25, and the fourth lead 26 can easily spread throughout the entire first chip pad 21 and the second chip pad 22. As a result, the sealing resin 50 becomes denser. Therefore, according to this structure, the sealing resin 50 can be made to have a better filling state in the semiconductor device A10.

[0089] When viewed from the third direction z, the second lead 24 and the fourth lead 26 overlap with the second imaginary line VL2, which passes through the center C2 of the second chip pad 22 and extends along the second direction y. By employing this structure, the dimension of the second interior 241 of the second lead 24 in the first direction x is approximately the same as the dimension of the first interior 231 of the first lead 23 in the first direction x. Furthermore, the dimension of the fourth interior 261 of the fourth lead 26 in the first direction x is approximately the same as the dimension of the third interior 251 of the third lead 25 in the first direction x. Therefore, the molten resin, whose flow is restricted by the first lead 23, the second lead 24, the third lead 25, and the fourth lead 26 in the mold cavity, more easily spreads throughout the first chip pad 21 and the second chip pad 22.

[0090] When viewed in the second direction y, the first lead 23 and the third lead 25 overlap with the first chip pad 21. By employing this structure, the flow rate of molten resin flowing in the mold cavity towards both sides in the third direction z, with the first chip pad 21 as a reference, becomes more uniform. Consequently, when viewed in the third direction z, the filling of the portion of the sealing resin 50 that completely overlaps with the first chip pad 21 becomes denser.

[0091] When viewed in the second direction y, the second lead 24 and the fourth lead 26 overlap with the second chip pad 22. By employing this structure, the flow rate of molten resin flowing in the mold cavity in the third direction z, with the second chip pad 22 as a reference, becomes more uniform. Consequently, when viewed in the third direction z, the filling of the portion of the sealing resin 50 that completely overlaps with the second chip pad 22 becomes denser.

[0092] A first gate mark 55A is formed on the third side 55 of the sealing resin 50. The first gate mark 55A is located between the first lead 23 and the second lead 24. By adopting this structure, the flow of molten resin flowing into the cavity from the flow channel of the molding die can be prevented from being obstructed by the first lead 23 and the second lead 24.

[0093] A second gate mark 56A is formed on the fourth side 56 of the sealing resin 50. The second gate mark 56A is located between the third lead 25 and the fourth lead 26. By adopting this structure, the flow of molten resin flowing from the cavity of the molding die to the runner can be prevented from being obstructed by the third lead 25 and the fourth lead 26.

[0094] When viewed in the third direction z, the minimum distance d2 between the second interior 241 of the second lead 24 and the third side surface 55 of the sealing resin 50 in the second direction y is equal to the minimum distance d1 between the first interior 231 and the first side surface 53 of the first lead 23 in the second direction y. By adopting this structure, the timing of the flow towards the first chip pad 21 and the timing of the flow towards the second chip pad 22 in the molten resin flowing into the cavity of the molding die can be the same (or approximately the same). As a result, the distribution of molten resin in the cavity becomes more uniform.

[0095] The semiconductor device A10 also includes an insulating element 13 mounted on the first chip pad 21. The first chip pad 21 has two first holes 211 and a second hole 212 respectively extending in the third direction z. The two first holes 211 are located on either side of the first semiconductor element 11 in the second direction y. The second hole 212 is located between the first semiconductor element 11 and the insulating element 13 in the first direction x. By employing this structure, in the cavity of the molding die, molten resin passes through the two first holes 211 and the second hole 212, thus further densifying the filling state of the sealing resin 50.

[0096] The first lead 23 and the third lead 25 are respectively connected to the first chip pad 21. Viewed in the third direction z, the first lead 23, the third lead 25, and the second hole 212 of the first chip pad 21 overlap with a third imaginary line VL3 extending along the second direction y. By employing this structure, rotation of the first chip pad 21 around the second direction y caused by contact between the molten resin and the first chip pad 21 in the cavity of the molding die can be suppressed. This allows for a more uniform coverage thickness of the sealing resin 50 on the first chip pad 21. In this case, by making the second hole 212 extend along the second direction y, rotation of the first chip pad 21 around the second direction y can be suppressed more effectively.

[0097] The semiconductor device A10 also includes a support lead 28. The support lead 28 is connected to the first chip pad 21 and protrudes outward from the first side 53 of the sealing resin 50. By adopting this structure, when a third-direction z-load is applied to the first chip pad 21, the support lead 28, together with the first lead 23 and the third lead 25, resists bending in the third-direction z-. As a result, the posture of the first chip pad 21 can be made more stable.

[0098] Second implementation method:

[0099] based on Figures 11-17 The semiconductor device A20 according to the second embodiment of this disclosure will be described. In these figures, elements that are the same or similar to those in the semiconductor device A10 described above are labeled with the same reference numerals, and repeated descriptions are omitted. Here, for ease of understanding, Figure 12 Shown through sealing resin 50. Figure 2 In the diagram, the shape of the sealing resin 50 is represented by an imaginary line. Figure 13 For ease of understanding, relative to Figure 12 The diagram is shown through each of the first semiconductor element 11, the second semiconductor element 12, and the insulating element 13, and the illustrations of each of the plurality of first metal wires 41 to the plurality of fourth metal wires 44 are omitted. Figure 13 In the diagram, the outlines of the first semiconductor element 11, the second semiconductor element 12, the insulating element 13, and the sealing resin 50 are represented by imaginary lines.

[0100] In semiconductor device A20, the structure of the second lead 24 and the fourth lead 26, as well as the presence of two suspension leads 27 instead of two support leads 28, differ from that in semiconductor device A10.

[0101] like Figure 11 as well as Figure 12 As shown, the second lead 24 and the fourth lead 26 are separated from the second chip pad 22.

[0102] like Figure 11as well as Figure 12 As shown, two suspension leads 27 are respectively connected to both sides of the second chip pad 22 in the second direction y. The two suspension leads 27 are separated from the third side 55 and the fourth side 56 of the sealing resin 50, respectively. The two suspension leads 27 are exposed externally from the second side 54 of the sealing resin 50. The two suspension leads 27 are located between the second lead 24 and the fourth lead 26. The two suspension leads 27 are respectively connected to any one of the plurality of second electrodes 121 of the second semiconductor element 12 via any one of the plurality of fourth metal wires 44.

[0103] like Figure 11 as well as Figure 12 As shown, the two suspension leads 27 each have an inner 271 and an outer 272. The inner 271 is connected to the second chip pad 22 and is covered by sealing resin 50. Figure 13 As shown, the dimension of the inner part 271 in the first direction x is smaller than the dimension of the second inner part 241 of the second lead 24 and the fourth inner part 261 of the fourth lead 26 in the first direction x. The outer part 272 is connected to the inner part 271 and protrudes outward. Viewed from the second direction y, the outer part 272 is curved into a gull-wing shape. The shape of the outer part 272 is similar to... Figure 14 The second outer portion 242 shown has the same shape. For example, the surface of the outer portion 272 is tin-plated.

[0104] like Figure 17 As shown, when viewed in the second direction y, the second interior 241 of the second lead 24 and the fourth interior 261 of the fourth lead 26, as well as the interior 271 of each of the two suspension leads 27, overlap with the second chip pad 22.

[0105] like Figure 13 As shown, in the semiconductor device A20, when viewed in the third direction z, the first lead 23 and the third lead 25 also move away from the first imaginary line VL1 in the first direction x towards the side where the first side surface 53 of the sealing resin 50 is located. When viewed in the third direction z, the second lead 24 and the fourth lead 26 overlap with the second imaginary line VL2.

[0106] like Figure 14 As shown, in the semiconductor device A20, a first gate trace 55A is also formed on the third side 55 of the sealing resin 50. Meanwhile, as... Figure 15 As shown, a second gate trace 56A is formed on the fourth side 56 of the sealing resin 50. Figure 13 As shown, the first gate trace 55A is located between the first interior 231 of the first lead 23 and the second interior 241 of the second lead 24. The second gate trace 56A is located between the third interior 251 of the third lead 25 and the fourth interior 261 of the fourth lead 26.

[0107] Next, the function and effect of the semiconductor device A20 will be explained.

[0108] Semiconductor device A20 includes a first chip pad 21, a first semiconductor element 11, a second chip pad 22, a second semiconductor element 12, a sealing resin 50, a first lead 23, a second lead 24, a third lead 25, and a fourth lead 26. The first lead 23, the second lead 24, the third lead 25, and the fourth lead 26 are separated from the third side 55 and the fourth side 56 of the sealing resin 50, respectively, and are exposed to the outside from either the first side 53 or the second side 54 of the sealing resin 50. Viewed in a third direction z, the area of ​​the first chip pad 21 is larger than the area of ​​the second chip pad 22. Viewed in a third direction z, the first lead 23 and the third lead 25 are respectively... Figure 3 The first imaginary line VL1 shown is further away from the side where the first side surface 53 of the sealing resin 50 is located in the first direction x. Therefore, according to this structure, the filling state of the sealing resin 50 can also be better in the semiconductor device A20. Furthermore, the semiconductor device A20 has a structure common to the semiconductor device A10, and therefore achieves the same effect as the semiconductor device A10.

[0109] Third implementation method:

[0110] based on Figures 18-20 The semiconductor device A30 according to the third embodiment of this disclosure will be described. In these figures, the same reference numerals are used for elements that are the same as or similar to those of the semiconductor device A10 described above, and repeated descriptions are omitted.

[0111] In semiconductor device A30, the structure of sealing resin 50 is different from that in semiconductor device A10.

[0112] like Figure 18 as well as Figure 19 As shown, the first gate trace 55A formed on the third side 55 of the sealing resin 50 is located closer to the second lead 24 than the first lead 23. Figure 18 as well as Figure 20 As shown, the second gate trace 56A formed on the fourth side surface 56 of the sealing resin 50 is located closer to the third lead 25 than the fourth lead 26. Thus, the first gate trace 55A and the second gate trace 56A are separated from each other in the first direction x.

[0113] Next, the function and effect of the semiconductor device A30 will be explained.

[0114] Semiconductor device A30 includes a first chip pad 21, a first semiconductor element 11, a second chip pad 22, a second semiconductor element 12, a sealing resin 50, a first lead 23, a second lead 24, a third lead 25, and a fourth lead 26. The first lead 23, the second lead 24, the third lead 25, and the fourth lead 26 are separated from the third side 55 and the fourth side 56 of the sealing resin 50, respectively, and are exposed to the outside from either the first side 53 or the second side 54 of the sealing resin 50. Viewed from a third direction z, the area of ​​the first chip pad 21 is larger than the area of ​​the second chip pad 22. In semiconductor device A30, viewed from a third direction z, the first lead 23 and the third lead 25 are also separated from the third side 55 and the fourth lead 26, respectively. Figure 3 The first imaginary line VL1 shown is further away from the side where the first side surface 53 of the sealing resin 50 is located in the first direction x. Therefore, according to this structure, the filling state of the sealing resin 50 can also be better in the semiconductor device A30. Furthermore, the semiconductor device A30 has a structure common to the semiconductor device A10, and therefore achieves the same effect as the semiconductor device A10.

[0115] In the semiconductor device A30, the first gate trace 55A formed on the third side 55 of the sealing resin 50 is located closer to the second lead 24 than the first lead 23. The second gate trace 56A formed on the fourth side 56 of the sealing resin 50 is located closer to the third lead 25 than the fourth lead 26. By adopting this structure, when forming the sealing resin 50, the molten resin can be more easily and uniformly distributed in the cavity of the molding die. As a result, the filling state of the sealing resin 50 is improved.

[0116] Fourth implementation method:

[0117] based on Figures 21-23 The semiconductor device A40 according to the fourth embodiment of this disclosure will be described. In these figures, the same reference numerals are used for elements that are the same as or similar to those of the semiconductor device A10 described above, and repeated descriptions are omitted.

[0118] In semiconductor device A40, the structure of sealing resin 50 is different from that in semiconductor device A10.

[0119] like Figure 21 as well as Figure 22 As shown, the first gate trace 55A formed on the third side 55 of the sealing resin 50 is located closer to the first lead 23 than the second lead 24. Figure 21 as well as Figure 23As shown, the second gate trace 56A formed on the fourth side surface 56 of the sealing resin 50 is located closer to the fourth lead 26 than the third lead 25. Thus, the first gate trace 55A and the second gate trace 56A are separated from each other in the first direction x.

[0120] Next, the function and effect of the semiconductor device A40 will be explained.

[0121] Semiconductor device A40 includes a first chip pad 21, a first semiconductor element 11, a second chip pad 22, a second semiconductor element 12, a sealing resin 50, a first lead 23, a second lead 24, a third lead 25, and a fourth lead 26. The first lead 23, the second lead 24, the third lead 25, and the fourth lead 26 are separated from the third side 55 and the fourth side 56 of the sealing resin 50, respectively, and are exposed to the outside from either the first side 53 or the second side 54 of the sealing resin 50. Viewed from a third direction z, the area of ​​the first chip pad 21 is larger than the area of ​​the second chip pad 22. In semiconductor device A40, viewed from a third direction z, the first lead 23 and the third lead 24 are also separated from the third side 55 and the fourth lead 26, respectively. Figure 3 The first imaginary line VL1 shown is further away from the side where the first side surface 53 of the sealing resin 50 is located in the first direction x. Therefore, according to this structure, the filling state of the sealing resin 50 can also be better in the semiconductor device A40. Furthermore, the semiconductor device A40 has a structure common to the semiconductor device A10, and therefore achieves the same effect as the semiconductor device A10.

[0122] In the semiconductor device A40, the first gate trace 55A formed on the third side 55 of the sealing resin 50 is located closer to the first lead 23 than the second lead 24. The second gate trace 56A formed on the fourth side 56 of the sealing resin 50 is located closer to the fourth lead 26 than the third lead 25. By adopting this structure, when forming the sealing resin 50, the molten resin can be more easily and uniformly distributed in the cavity of the molding die. As a result, the filling state of the sealing resin 50 is improved.

[0123] This disclosure is not limited to the embodiments described above. The specific structure of each part of this disclosure can be freely modified in various ways.

[0124] This disclosure includes the embodiments described in the following notes.

[0125] Appendix 1. A semiconductor device comprising:

[0126] First chip pad;

[0127] A first semiconductor element is mounted on the first chip pad;

[0128] The second chip pad is located away from the first chip pad along a first direction;

[0129] A second semiconductor element is mounted on the second chip pad;

[0130] A sealing resin having a first side and a second side facing opposite sides to each other in the first direction, and a third side and a fourth side facing opposite sides to each other in a second direction orthogonal to the first direction, and covering the first chip pad, the first semiconductor element, the second chip pad and the second semiconductor element;

[0131] The first lead includes a portion extending toward the first chip pad and is located closest to the third side.

[0132] The second lead includes a portion extending toward the second chip pad and is located closest to the third side.

[0133] The third lead includes a portion extending toward the first chip pad and located closest to the fourth side surface; and

[0134] The fourth lead includes a portion extending toward the second chip pad and is located closest to the fourth side surface.

[0135] The first lead and the third lead are respectively located away from the third side and the fourth side, and are exposed outward from the first side.

[0136] The second lead and the fourth lead are respectively located away from the third side and the fourth side, and are exposed outward from the second side.

[0137] Viewed from a third direction orthogonal to both the first and second directions, the area of ​​the first chip pad is larger than the area of ​​the second chip pad.

[0138] When viewed from above by a third party, the first lead and the third lead are respectively farther away from the side containing the first side in the first direction than the first imaginary line that passes through the center of the first chip pad and extends along the second direction.

[0139] Note 2. The semiconductor device according to Note 1, wherein,

[0140] When viewed from above by a third party, the second lead and the fourth lead respectively overlap with a second imaginary line that passes through the center of the second chip pad and extends along the second direction.

[0141] Note 3. The semiconductor device according to Note 2, wherein,

[0142] When viewed in the second direction, the first lead and the third lead overlap with the first chip pad, respectively.

[0143] Note 4. The semiconductor device according to Note 3, wherein,

[0144] The first lead and the third lead are respectively connected to the first chip pad.

[0145] Note 5. The semiconductor device according to Note 4, wherein,

[0146] When viewed in the second direction, the second lead and the fourth lead overlap with the second chip pad, respectively.

[0147] Note 6. The semiconductor device according to Note 5, wherein,

[0148] The second lead and the third lead are respectively connected to the second chip pad.

[0149] Note 7. The semiconductor device according to Note 5,

[0150] It also has two suspension leads that are respectively connected to both sides of the second chip pad in the second direction.

[0151] The two suspension leads exit from the third and fourth sides respectively, and protrude outward from the second side.

[0152] The two suspension leads are located between the second lead and the fourth lead.

[0153] The second lead and the fourth lead are respectively separated from the second chip pad.

[0154] Note 8. The semiconductor device according to Note 5, wherein,

[0155] A first gate trace is formed on the third side.

[0156] The surface roughness of the first gate trace is greater than the surface roughness of the other regions of the third side surface, excluding the first gate trace.

[0157] A second gate mark is formed on the fourth side.

[0158] The surface roughness of the second gate trace is greater than the surface roughness of the other areas of the fourth side surface, excluding the second gate trace.

[0159] Note 9. The semiconductor device according to Note 8, wherein,

[0160] The first gate trace is located between the first lead and the second lead.

[0161] The second gate trace is located between the third lead and the fourth lead.

[0162] Note 10. The semiconductor device according to Note 8, wherein,

[0163] The first gate trace is located closer to the second lead than the first lead.

[0164] The second gate trace is located closer to the third lead than the fourth lead.

[0165] Note 11. The semiconductor device according to Note 8, wherein,

[0166] The first gate trace is located closer to the first lead than the second lead.

[0167] The second gate trace is located closer to the fourth lead than the third lead.

[0168] Note 12. The semiconductor device according to Note 8, wherein,

[0169] The first lead has a first interior covered by the sealing resin.

[0170] The second lead has a second interior covered by the sealing resin.

[0171] The dimension of the second interior in the first direction is equal to the dimension of the first interior in the first direction.

[0172] Note 13. The semiconductor device according to Note 12, wherein,

[0173] The third lead has a third interior covered by the sealing resin.

[0174] The fourth lead has a fourth interior covered by the sealing resin.

[0175] The dimension of the first direction of the fourth interior is equal to the dimension of the first direction of the third interior.

[0176] Note 14. The semiconductor device according to Note 13, wherein,

[0177] When viewed from the third side upwards, the minimum distance between the second interior and the second direction of the third side is equal to the minimum distance between the first interior and the second direction of the third side.

[0178] Note 15. The semiconductor device according to any one of Notes 5 to 14,

[0179] It also includes insulating components mounted on the pads of the first chip.

[0180] The insulating element is of the inductive coupling type.

[0181] The insulating element is connected to both the first semiconductor element and the second semiconductor element.

[0182] Note 16. The semiconductor device according to Note 15, wherein,

[0183] The insulating element is located next to the first semiconductor element in the first direction.

[0184] The first chip pad has two first holes and a second hole that respectively penetrate the first chip pad along the third direction.

[0185] The two first holes are located on both sides of the first semiconductor element in the second direction.

[0186] The second hole is located between the first semiconductor element and the insulating element in the first direction.

[0187] Note 17. The semiconductor device according to Note 16, wherein,

[0188] Viewed along the third direction, the first lead, the third lead, and the second hole respectively overlap with a third imaginary line extending along the second direction.

[0189] Note 18. The semiconductor device according to Note 17,

[0190] It also includes a plurality of first intermediate leads located between the first lead and the third lead.

[0191] At least one of the plurality of first intermediate leads is connected to the first semiconductor element.

[0192] Note 19. The semiconductor device according to Note 18,

[0193] It also includes a plurality of second intermediate leads located between the second lead and the fourth lead.

[0194] At least one of the plurality of second intermediate leads is connected to the second semiconductor element.

[0195] Symbol Explanation

[0196] A10, A20, A30, A40—Semiconductor devices; 11—First semiconductor element; 111—First electrode; 12—Second semiconductor element; 121—Second electrode; 13—Insulating element; 131—Third electrode; 132—Fourth electrode; 21—First chip pad; 21A—First mounting surface; 21B—First edge; 211—First hole; 212—Second hole; 213—Third hole; 22—Second chip pad; 22A—Second mounting surface. Cross-section, 23—First suspension lead, 231—First interior, 231A—First section, 231B—Second section, 232—First exterior, 232A—Cut-off mark, 232B—Third section, 232C—Fourth section, 24—Second suspension lead, 241—Second interior, 242—Second exterior, 25—Third suspension lead, 251—Third interior, 252—Third exterior, 26—Fourth suspension lead, 261—Fourth interior, 262— Fourth outer layer, 27—Suspension lead, 271—Inner layer, 272—Outer layer, 28—Support lead, 28A—End face, 29—Joint layer, 31—First intermediate lead, 311—Inner layer, 312—Outer layer, 32—Second intermediate lead, 321—Inner layer, 322—Outer layer, 41—First metal wire, 42—Second metal wire, 43—Third metal wire, 44—Fourth metal wire, 50—Sealing resin, 51—Top surface, 52—Bottom surface, 53—First side layer Face, 531—First upper part, 532—First lower part, 533—First middle part, 54—Second side, 541—Second upper part, 542—Second lower part, 543—Second middle part, 55—Third side, 551—Third upper part, 552—Third lower part, 553—Third middle part, 56—Fourth side, 561—Fourth upper part, 562—Fourth lower part, 563—Fourth middle part, x—First direction, y—Second direction, z—Third direction.

Claims

1. A semiconductor device, characterized in that, have: First chip pad; A first semiconductor element is mounted on the first chip pad; The second chip pad is located away from the first chip pad along a first direction; A second semiconductor element is mounted on the second chip pad; A sealing resin having a first side and a second side facing opposite sides to each other in the first direction, and a third side and a fourth side facing opposite sides to each other in a second direction orthogonal to the first direction, and covering the first chip pad, the first semiconductor element, the second chip pad and the second semiconductor element; The first lead includes a portion extending toward the first chip pad and is located closest to the third side. The second lead includes a portion extending toward the second chip pad and is located closest to the third side. The third lead includes a portion extending toward the first chip pad and is located closest to the fourth side surface; as well as The fourth lead includes a portion extending toward the second chip pad and is located closest to the fourth side surface. The first lead and the third lead are respectively located away from the third side and the fourth side, and are exposed outward from the first side. The second lead and the fourth lead are respectively located away from the third side and the fourth side, and are exposed outward from the second side. Viewed from a third direction orthogonal to both the first and second directions, the area of ​​the first chip pad is larger than the area of ​​the second chip pad. When viewed from above by a third party, the first lead and the third lead are respectively farther away from the side containing the first side in the first direction than the first imaginary line that passes through the center of the first chip pad and extends along the second direction.

2. The semiconductor device according to claim 1, characterized in that, When viewed from above by a third party, the second lead and the fourth lead respectively overlap with a second imaginary line that passes through the center of the second chip pad and extends along the second direction.

3. The semiconductor device according to claim 2, characterized in that, When viewed in the second direction, the first lead and the third lead overlap with the first chip pad, respectively.

4. The semiconductor device according to claim 3, characterized in that, The first lead and the third lead are respectively connected to the first chip pad.

5. The semiconductor device according to claim 4, characterized in that, When viewed in the second direction, the second lead and the fourth lead overlap with the second chip pad, respectively.

6. The semiconductor device according to claim 5, characterized in that, The second lead and the third lead are respectively connected to the second chip pad.

7. The semiconductor device according to claim 5, characterized in that, It also has two suspension leads that are respectively connected to both sides of the second chip pad in the second direction. The two suspension leads exit from the third and fourth sides respectively, and protrude outward from the second side. The two suspension leads are located between the second lead and the fourth lead. The second lead and the fourth lead are respectively separated from the second chip pad.

8. The semiconductor device according to claim 5, characterized in that, A first gate mark is formed on the third side surface. The surface roughness of the first gate trace is greater than the surface roughness of the other regions of the third side surface, excluding the first gate trace. A second gate mark is formed on the fourth side surface. The surface roughness of the second gate trace is greater than that of the other regions of the fourth side surface, excluding the second gate trace.

9. The semiconductor device according to claim 8, characterized in that, The first gate trace is located between the first lead and the second lead. The second gate trace is located between the third lead and the fourth lead.

10. The semiconductor device according to claim 8, characterized in that, The first gate trace is located closer to the second lead than the first lead. The second gate trace is located closer to the third lead than the fourth lead.

11. The semiconductor device according to claim 8, characterized in that, The first gate trace is located closer to the first lead than the second lead. The second gate trace is located closer to the fourth lead than the third lead.

12. The semiconductor device according to claim 8, characterized in that, The first lead has a first interior covered by the sealing resin. The second lead has a second interior covered by the sealing resin. The dimension of the second interior in the first direction is equal to the dimension of the first interior in the first direction.

13. The semiconductor device according to claim 12, characterized in that, The third lead has a third interior covered by the sealing resin. The fourth lead has a fourth interior covered by the sealing resin. The dimension of the first direction of the fourth interior is equal to the dimension of the first direction of the third interior.

14. The semiconductor device according to claim 13, characterized in that, When viewed from above by a third party, the minimum distance between the second interior and the second direction of the third side is equal to the minimum distance between the first interior and the second direction of the third side.

15. The semiconductor device according to any one of claims 5 to 14, characterized in that, It also includes insulating components mounted on the pads of the first chip. The insulating element is of the inductive coupling type. The insulating element is connected to both the first semiconductor element and the second semiconductor element.

16. The semiconductor device according to claim 15, characterized in that, The insulating element is located next to the first semiconductor element in the first direction. The first chip pad has two first holes and a second hole that extend through the first chip pad along the third direction. The two first holes are located on both sides of the first semiconductor element in the second direction. The second hole is located between the first semiconductor element and the insulating element in the first direction.

17. The semiconductor device according to claim 16, characterized in that, When viewed from above by a third party, the first lead, the third lead, and the second hole respectively overlap with a third imaginary line extending along the second direction.

18. The semiconductor device according to claim 17, characterized in that, It also includes a plurality of first intermediate leads located between the first lead and the third lead. At least one of the plurality of first intermediate leads is connected to the first semiconductor element.

19. The semiconductor device according to claim 18, characterized in that, It also includes a plurality of second intermediate leads located between the second lead and the fourth lead. At least one of the plurality of second intermediate leads is connected to the second semiconductor element.

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