Bimetal silicide-containing semiconductor device with reduced contact resistivity

Abstract

The present techniques include semiconductor devices and methods having improved contact resistivity. The semiconductor device includes: a substrate base; a silicon oxide disposed on the substrate, thereby defining one or more features; a bi-metal silicide layer disposed on the substrate in the one or more features, and at least one metal silicide layer disposed on the substrate in the one or more features; and at least a first metal layer. The bimetallic silicide layer includes a first metal, a second metal different from the first metal, and a silicon-containing compound, and includes a second metal atom greater than or about 0.8 E + 14 / cm-2. The first metal layer includes the first metal and covers the bimetallic silicide layer.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit and priority of U.S. Patent Application No. 18 / 185,242, filed March 16, 2023, entitled “SEMICONDUCTOR DEVICESCONTAINING BI-METALLIC SILICIDE WITH REDUCED CONTACT RESISTIVITY”, which is incorporated herein by reference in its entirety. Technical Field

[0003] This technology relates to methods for processing semiconductors and devices formed therefrom. More specifically, this technology relates to methods for reducing the contact resistivity of semiconductor devices and devices incorporating such contacts. Background Technology

[0004] Integrated circuits have evolved into complex devices that can include millions of transistors, capacitors, and resistors on a single chip. In the evolution of integrated circuits, functional density (i.e., the number of interconnects per chip area) has generally increased while geometric size has decreased. Transistors are circuit components or elements that are frequently formed on semiconductor devices. Depending on the circuit design, many transistors can be formed on a semiconductor device, in addition to capacitors, inductors, resistors, diodes, conductive lines, or other components. Integrated circuits incorporate field-effect transistors (FETs), in which current flows through a semiconductor channel between the source and drain in response to a voltage applied to the control gate.

[0005] Integrated circuits are realized through processes that create complex patterned material layers on a substrate surface. Creating patterned materials on a substrate requires controlled methods for material formation and removal. As device sizes continue to shrink, film properties can significantly impact device performance. Thin film deposition becomes challenging as devices shrink and more complex patterning schemes are used in industry. Furthermore, as material thickness continues to decrease, the properties of the deposited film can have a significant impact on device performance.

[0006] Therefore, there is a need for high-quality devices and structures with improved resistance, as well as methods for fabricating such devices. These and other issues need to be addressed by this technology. Summary of the Invention

[0007] Embodiments of this technology include semiconductor devices and methods with improved contact resistivity. The semiconductor device includes: a substrate; silicon oxide disposed on the substrate to define one or more features; a bimetallic silicide layer disposed on the substrate in the one or more features; and at least a first metal layer. The bimetallic silicide layer includes a first metal, a second metal different from the first metal, and a silicon-containing compound, and comprises a resistivity greater than or about 0.8E+14 / cm. -2 The second metal atom. The first metal layer includes the first metal and is covered by a bimetallic silicide layer.

[0008] In embodiments, the semiconductor device exhibits a Schottky barrier height that is at least about 5% smaller than that in a semiconductor device without a bimetallic silicide. In some embodiments, the semiconductor device exhibits a Schottky barrier height of less than 0.39 eV. In further embodiments, the bimetallic silicide layer comprises a value greater than or about 3E+14 / cm². -2 The second metallic atom.

[0009] In a further embodiment, the semiconductor device further includes a second metal layer comprising a second metal covering the first metal layer. Additionally or alternatively, the second metal is titanium, zirconium, nickel, molybdenum, gold, tungsten, palladium, platinum, chromium, or a combination thereof. In embodiments, the first metal is titanium, zirconium, nickel, molybdenum, gold, tungsten, palladium, platinum, chromium, or a combination thereof. In still other embodiments, the first metal is molybdenum, the second metal is titanium, and the bimetallic silicide is a molybdenum (titanium) silicide. In embodiments, the bimetallic silicide layer is disposed in the p-MOS region. Additionally or alternatively, in embodiments, the bimetallic silicide layer is disposed in the n-MOS region.

[0010] Embodiments of this technology include a semiconductor device processing system. The system includes a first processing chamber, a second processing chamber, and a third processing chamber. The system includes a system controller configured to etch at least a first feature in an oxide layer on a silicon-containing substrate in the first processing chamber. The system includes a system controller configured to deposit a first metal layer containing a first metal onto the silicon-containing substrate in the first feature in the second processing chamber. The system includes a system controller configured to deposit a second metal layer containing a second metal onto the first metal layer in either the second or third processing chamber. The system includes a system controller configured to anneal the semiconductor device to form a bimetallic silicide layer between the silicon-containing substrate and the first metal layer.

[0011] In one embodiment, the first metal is molybdenum, titanium, zirconium, nickel, or a combination thereof, and the substrate is exposed to the first metal precursor and the first metal reactant in a second processing chamber. In further embodiments, the second metal is molybdenum, titanium, zirconium, nickel, or a combination thereof, and the substrate is exposed to the second metal precursor and the second metal reactant in a third processing chamber.

[0012] Embodiments of this technology include a method of forming a semiconductor device. The method includes etching at least a first feature into an oxide disposed on a silicon-containing substrate. The method includes depositing a first metal layer containing a first metal over the silicon-containing substrate containing at least the first feature. The method includes depositing a second metal layer containing a second metal different from the first metal over the first metal layer. The method includes annealing the semiconductor device to form a bimetallic silicide layer between the silicon-containing substrate and the first metal layer.

[0013] In embodiments, the method includes depositing a first metal layer by exposing a substrate in at least a first feature to a first metal precursor and a first metal reactant. In further embodiments, the method includes depositing a second metal layer by exposing the first metal layer to a second metal precursor and a second metal reactant. Additionally or alternatively, embodiments include wherein the first metal and the second metal are individually selected from molybdenum, titanium, zirconium, nickel, or combinations thereof. In embodiments, the semiconductor device exhibits a Schottky barrier height that is at least about 5% smaller than that in a semiconductor device without a bimetallic silicide. In further embodiments, the second metal is sufficiently used to produce a value greater than or about 0.8E+14 / cm in the bimetallic silicide layer. -2 The amount of the second metal atoms is applied to the second metal layer. In some other embodiments, the bimetallic silicide layer exhibits a binding energy to the substrate that is at least about 3% greater than that of the monometallic silicide layer to the same substrate.

[0014] This technology offers numerous advantages over conventional technologies. For example, embodiments of this technology provide improved contact strength and reduced contact resistivity, even with small contact sizes. Additionally, this technology allows for control over the degree and strength of the contact. Thus, this technology provides improved contacts without the need for annealing methods that could damage the substrate. These and other embodiments, along with their many advantages and features, are described in more detail below in conjunction with the accompanying drawings. Attached Figure Description

[0015] The nature and advantages of the disclosed technology can be further understood by referring to the remainder of the specification and the accompanying drawings.

[0016] Figure 1 A top plan view of an exemplary processing chamber according to some embodiments of the present technology is shown.

[0017] Figure 2Selected operations in a formation method according to some embodiments of the present technology are shown.

[0018] Figures 3A to 3E A cross-sectional view of an exemplary semiconductor structure according to some embodiments of the present technology is shown.

[0019] Several figures in the figures are included as schematic diagrams. It should be understood that these figures are for illustrative purposes only and should not be considered to be to scale unless specifically stated otherwise. Additionally, as schematic diagrams, these figures are provided to aid understanding and may not include all aspects or information compared to a realistic representation, and may include material exaggerated for illustrative purposes.

[0020] In the accompanying drawings, similar parts and / or features may have the same element symbol. Additionally, various parts of the same type can be distinguished by following the element symbol with letters that differentiate them. If only the first element symbol is used in the specification, the description applies to any of the similar parts having the same first element symbol, regardless of the letter. Detailed Implementation

[0021] Microelectronic devices are fabricated as integrated circuits on semiconductor substrates, where conductive layers are interconnected to allow electronic signals to propagate within the device. Such devices can include transistors, such as complementary metal-oxide-semiconductor (CMOS), field-effect transistors (FETs), MOSFETs including planar and three-dimensional structures such as finFETs, gate-enclosed FETs, and nanosheet FETs, as well as other types of transistors. The drive current of a transistor, and thus its speed, is proportional to the gate width of the transistor. Faster transistors generally require larger gate widths. There is a trade-off between transistor size and speed, and finFETs and gate-enclosed FETs have been developed as examples of resolving the conflicting goals of having the largest drive current and the smallest size transistors.

[0022] An exemplary finFET or MOSFET includes a gate electrode on a gate dielectric layer on the surface of a semiconductor substrate. Source and drain regions are provided along opposite sides of the gate electrode. The source and drain regions are generally heavily doped (p-doped or n-doped) regions of the semiconductor substrate. Contacts are typically coupled to the source and drain regions using a capped silicide layer (e.g., molybdenum silicide). However, this capping, and the reduced contact size, results in undesirably high contact resistivity, hindering continuous improvement of electrical properties, particularly in smaller technologies. That is, the high contact resistance, at least in part, is problematic for improved semiconductor devices due to the limited contact surface area between the source and drain regions and the corresponding metal contacts.

[0023] Furthermore, during middle-of-line (MOL) processes, the goal is to minimize the via resistance of the MOL structure. However, MOL contact dimensions are also affected by technology scaling. Consequently, appropriately reducing the contact size can lead to a significant increase in contact resistance. For example, it is estimated that the contact between the epitaxial substrate and the silicide can contribute more than 80% of the correspondingly determined total resistance. Attempts have been made to modify the silicide process to improve deposition, reduce oxidation, and utilize different materials. Additionally, conventional processes have suggested using high-temperature thermal annealing to attempt to improve contact adhesion and / or interface crystallinity. However, this approach has proven insufficient to improve contact resistivity to the levels desired in the art and also reduces the amount of material that could be utilized elsewhere on the device due to the high temperatures (e.g., films, pads, etc. that cannot withstand high annealing temperatures).

[0024] This technology overcomes these and other challenges by providing strong and robust contacts, thereby promoting a reduction in barrier height and contact resistivity. Specifically, this technology surprisingly discovers that contact strength and resistivity are significantly improved by utilizing a second metal layer deposited above the first metal layer prior to silicide. In embodiments of this technology, the first metal layer is applied over the silicon-containing layer, and a second metal, different from the first metal, is applied over the first metal layer. By utilizing this method and device, this technology surprisingly discovers that the adhesion between contact layers is improved when a hybrid metal bonding layer (e.g., a bimetallic or bimetallic silicide) is formed at the interface between the substrate and the first metal. Surprisingly, this technology also finds that this approach improves contact resistivity in both p-MOS and n-MOS regions.

[0025] While the remainder of this disclosure will conventionally refer to specific metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, and their components, it will be readily understood that the devices and methods are equally applicable to other field-effect transistors, their orientations, and the processes used to form such devices. Therefore, the technology should not be considered limited to use only with these specific devices or methods. Before describing additional variations and modifications to this device according to embodiments of the present technology, this disclosure will discuss a possible semiconductor device according to embodiments of the present technology that may include one or more components utilizing one or more self-aligned single diffusion breakpoints.

[0026] Figure 1 A top plan view of a multi-chamber processing system 100, which may be specifically configured to be implemented or operated according to some embodiments of the present technology, is shown. The multi-chamber processing system 100 may be configured to perform one or more fabrication processes on separate substrates, such as any number of semiconductor substrates, for forming semiconductor devices. The multi-chamber processing system 100 may include some or all of the following: a transfer chamber 106, a buffer chamber 108, single-wafer loading latches 110 and 112 (although dual loading latches may also be included), processing chambers 114, 116, 118, 120, 122, and 124, preheating chambers 123 and 125, and robots 126 and 128. Single-wafer loading latches 110 and 112 may include a heating element 113 and may be attached to the buffer chamber 108. Processing chambers 114, 116, 118, and 120 may be attached to the transfer chamber 106. Processing chambers 122 and 124 may be attached to the buffer chamber 108. Two substrate transfer platforms 102 and 104 are located between transfer chamber 106 and buffer chamber 108, and facilitate transfer between robots 126 and 128. Platforms 102 and 104 may have access to the transfer chamber and buffer chamber, or the platforms may be selectively isolated from or sealed to allow different operating pressures to be maintained between transfer chamber 106 and buffer chamber 108. Transfer platforms 102 and 104 may each include one or more tools 105, such as those for orientation or measurement operations.

[0027] The operation of the multi-chamber processing system 100 can be controlled by a computer system 130. The computer system 130 may include any device or combination of devices configured to perform the operations described below. Thus, the computer system 130 may be a controller or array of controllers and / or a general-purpose computer configured with software stored on a non-transitory computer-readable medium, which, when executed, can perform the operations described with respect to the method according to embodiments of the present technology. Each of the processing chambers 114, 116, 118, 120, 122, and 124 may be configured to perform one or more processing steps during the fabrication of a semiconductor structure. More specifically, the processing chambers 114, 116, 118, 120, 122, and 124 may be equipped to perform a variety of substrate processing operations, including dry etching processes, cyclic layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etching, pre-cleaning, degassing, orientation, and any number of other substrate processes.

[0028] Figure 2 Exemplary operations in method 200 according to some embodiments of the present technology are illustrated. The method can be performed in various processing chambers, including the processing chamber 100 described above. Method 200 may include numerous optional operations that may or may not be specifically associated with some embodiments of the method according to the present technology. For example, numerous operations are described to provide a broader range of structure formations, but these operations are not critical to the technology or may be performed by alternative methods that would be readily understood.

[0029] Method 200 may include additional operations prior to the operations listed above. For example, additional processing operations may include forming a structure on a semiconductor substrate, which may include forming and removing material. The prior processing operations may be performed in a chamber in which method 200 is performed, or processing prior to delivering the substrate to a semiconductor processing chamber in which method 200 is performed may be performed in one or more other processing chambers. Nevertheless, method 200 may, as appropriate, include delivering the semiconductor substrate to a processing region of the semiconductor processing system 100 (such as processing chambers 114, 116, 118, 120, 122 and / or 124 described above) or other chambers that may include components as described above. The substrate may be deposited on a substrate support, which may be a base, such as substrate platform 104, and may be placed in a processing region of the chamber, such as processing region 120 described above. Method 200 describes in Figures 3A to 3E The operations illustrated herein will be described in conjunction with the operations of method 200. It will be understood that... Figures 3A to 3E Only partial schematic diagrams are shown, and the semiconductor substrate may include additional components and alternative components of any size or configuration as shown in the figures, as well as any other components that may still benefit from aspects of this technology.

[0030] Method 200 may or may not involve optional operations for developing semiconductor structures to specific polishing operations, such as one or more semiconductor processing operations to generate one or more layers of material on a substrate, clamping the substrate to a carrier head of a polishing system, or depositing one or more metal layers in one or more features 302. It will be understood that method 200 can be performed on any number of semiconductor structures or substrates 305, such as... Figure 3A The diagram illustrates an exemplary structure 300 on which silicon oxide 310 may be formed over a substrate 305. For example, in an embodiment, operation 205 may include transferring the substrate 305 to a deposition chamber (such as a processing chamber 114) to etch one or more features 302 in the silicon oxide 310.

[0031] Structure 300 may show a partial view of a substrate, which in embodiments can be used for n-channel and p-channel MOSFETs, FinFETs, gate-enclosed FETs, complementary metal-oxide-semiconductor (CMOS) and nanosheet FETs, as well as other types of semiconductor transistor structures. Material layers can be produced by any number of methods, including chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermally enhanced chemical vapor deposition (TECVD), plasma-enhanced chemical vapor deposition (PECVD), plasma-enhanced atomic layer deposition (PEALD), or any other formation technique. In embodiments, any one or more deposition methods or operations can be performed in a processing chamber, such as the previously described processing chambers 118 and / or 120. The substrate layer may include silicon oxide and silicon nitride, silicon oxide and silicon, silicon nitride and silicon, silicon and doped silicon, or any number of other materials.

[0032] However, in embodiments, substrate 305 may be a host semiconductor substrate. As used herein, the term "host semiconductor substrate" refers to a substrate wherein the entire substrate is made of a semiconductor material. The host semiconductor substrate may include any suitable semiconductor material and / or combination of semiconductor materials for forming the semiconductor structure. For example, the semiconductor layer may include one or more materials, such as crystalline silicon (e.g., Si). <100> or Si <111> The semiconductor substrate 305 comprises silicon oxide, strained silicon, germanium silicon, doped or undoped polycrystalline silicon, doped or undoped silicon wafers, patterned or unpatterned wafers, doped silicon, germanium, germanium silicon, epitaxial substrates, gallium arsenide, or other suitable semiconductor materials. In one embodiment, the semiconductor material is silicon (Si). In one or more embodiments, the semiconductor substrate 305 comprises a semiconductor material, such as silicon (Si), carbon (C), germanium (Ge), germanium silicon (SiGe), germanium tin (GeSn), other semiconductor materials, or any combination thereof. In one or more embodiments, the substrate 305 comprises one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), or phosphorus (P). Although several examples of materials from which substrates can be formed are described herein, any material that can be used as a substrate falls within the spirit and scope of this disclosure on which passive and active electronic devices (e.g., transistors, memories, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic devices) can be constructed.

[0033] In embodiments, the semiconductor material may be a doped material, such as n-doped silicon (n-Si) or p-doped silicon (p-Si). In embodiments, the substrate may be doped using any suitable process, such as ion implantation. As used herein, the term "n-type" refers to a semiconductor produced during manufacturing by doping an intrinsic semiconductor with an electron donor element. The term n-type derives from the negative charge of electrons. In an n-type semiconductor, electrons are the majority carriers and holes are the minority carriers. As used herein, the term "p-type" refers to the positive charge of the well (or hole). In contrast to an n-type semiconductor, a p-type semiconductor has a larger hole concentration compared to the electron concentration. In a p-type semiconductor, holes are the majority carriers and electrons are the minority carriers. As discussed above, in embodiments, this technique can provide improved mobility in both p-type and n-type semiconductors (also referred to herein as p-MOS and n-MOS regions).

[0034] Although the following description will conventionally discuss silicon oxide deposited as a dielectric material on substrate 305, it will be understood that any number of dielectric materials can be used in embodiments of this technology, and this technology should not be limited to any particular dielectric material in which features can be formed. Figure 3AAs shown, silicon oxide 310 can be processed to form one or more recesses or features 302, such as trenches, holes, or through-holes, or any other structure that can be used for semiconductor processing. The substrate 305 can be any number of materials, such as a substrate wafer or substrate 305 made of silicon or a silicon-containing material, or other substrate materials as discussed above. In embodiments, the method may include the optional step of etching 205 one or more features 302 in an etching chamber (such as processing chamber 114). Although two features 302 are illustrated in the figures, it will be understood that the exemplary structure may have any number of features defined along the structure of embodiments according to the present technology. Thus, in embodiments, only one feature may be formed, or more than two features may be formed, such as more than three, more than four, more than five, more than six, more than seven, more than eight, more than nine, more than ten features, or any range or value between these.

[0035] Nevertheless, in embodiments, depending on the preceding processing steps, optional etching operation 205 may be the first operation in processing system 100. If so, substrate 305 may be loaded into loading locks 110, 112 and transferred via robots 126, 128 to an etching chamber (such as processing chamber 114). Thus, the etching process can be considered an in-situ etching process within processing system 100. However, in embodiments, if the preceding operation is performed according to the method embodiment, the transfer may be from the first processing chamber (such as processing chamber 114) to the second processing chamber 116, rather than being loaded through loading locks 110, 112. That is, as will be discussed in more detail below, in embodiments, for proper annealing of the two or more metal layers used to form the bimetallic silicide of this technology, prevention and removal of oxides may be necessary. Therefore, in this aspect, processing system 100 may provide an end-to-end platform such that each operation (including transfers therebetween) can be performed under vacuum.

[0036] However, in embodiments, it may be desirable to perform an optional pre-cleaning operation 210 to remove any existing oxides, or, if a full vacuum process is not feasible, to perform it before or after the etching operation 205. In embodiments, the cleaning operation (also referred to as the pre-cleaning operation) is any cleaning process suitable for removing the oxide layer from the substrate 305. For example, in embodiments, plasma-assisted etching processes, reactive etching or cleaning processes, or similar combinations thereof may be performed to remove any byproducts formed on the substrate, such as surface oxidation. In embodiments, the pre-cleaning operation 210 may be performed via Siconi... TMThe pre-cleaning process can be performed using an etching process or any reactive etching or cleaning process known in the art. For example, by way of example only, this pre-cleaning may be selected to remove silicon oxide formed on the upper surface 312 of the substrate 305 within feature 302. Nevertheless, in embodiments, the substrate 305 may be transferred from the etching chamber 114 to the pre-cleaning chamber (such as the processing chamber 116) via robots 126, 128. Thus, the pre-cleaning process can be considered an in-situ cleaning process within the processing system 100.

[0037] Furthermore, as discussed above, in this embodiment, after the pre-cleaning process, the substrate 305 is transferred to a deposition chamber, such as the processing chamber 118, under vacuum. That is, forming oxides on the silicon-containing substrate 305 can prevent two or more metals from diffusing into the silicon-containing substrate 305. Therefore, in this embodiment, in order to prevent the formation of additional oxides after the pre-cleaning operation 210, it may be necessary to transfer the substrate to the deposition chamber 118 under vacuum.

[0038] Nevertheless, in the embodiment, during operation 215, a first metal layer 314 containing the first metal 315 is deposited over the substrate 305 in feature 302, such as Figure 3B As shown. In embodiments, deposition may be performed according to any suitable method in the art and may be carried out in a processing chamber configured as a chemical vapor deposition chamber, a physical vapor deposition chamber, an atomic layer deposition chamber, a thermally enhanced chemical vapor deposition chamber, a plasma-enhanced chemical vapor deposition chamber, an electroless deposition chamber, or a plasma-enhanced atomic layer deposition chamber.

[0039] In embodiments, the first metal is tungsten, molybdenum, titanium, zirconium, nickel, hafnium, cobalt, tin, tantalum, platinum, iron, niobium, palladium, its metallic components, alloys thereof, or combinations thereof. However, it should be understood that in embodiments, the first metal may be a low-resistivity conductive metal known in the art. Nevertheless, in embodiments, the first metal is molybdenum, titanium, zirconium, nickel, its metallic components, alloys thereof, or combinations thereof. In embodiments, the first metal is molybdenum, its metallic components, or alloys thereof.

[0040] The deposition of the first metal 215 may include masking operations known in the art to mask areas of structure 300 where the deposition of the first metal layer 314 is not desired (e.g., all areas except feature 302). Nevertheless, the deposition of the first metal layer 314 may include exposing feature 302 to a metal precursor, which may be a precursor of any one or more of the first metals discussed above, thereby forming the first metal layer 314 in one or more features 302. As used in this specification and the appended claims, the terms “reactive compound,” “reactive gas,” “reactive substance,” “precursor,” “processing gas,” and the like are used interchangeably to mean a substance having species capable of reacting with the substrate 305 (or substrate surface 312) or materials on the substrate 305 (or substrate surface) in a surface reaction (e.g., chemisorption, oxidation, reduction). In embodiments, the precursor may be a metal vapor or metal (e.g., when using a PVD process), or may be a precursor and reactant, as well as other precursor forms known in the art.

[0041] After forming the first metal layer 314, a conventional process anneals the structure 300 to form a first metal silicide via a silicide process. However, as discussed above, this process results in poor adhesion of the silicide to the substrate and unacceptably high contact resistivity (as measured by Schottky barrier height). This technique surprisingly discovers that by subsequently depositing a second metal layer over the first metal layer, the silicide layer formed at the interface between the substrate and the first metal layer contains doping with second metal atoms. By driving the second metal atoms to the interface, this technique surprisingly discovers that not only is the barrier height in the p-MOS region reduced due to the decreased contact resistivity, but the contact strength is also significantly improved, resulting in a surprising improvement in barrier height in both the p-MOS and n-MOS regions.

[0042] Therefore, in an embodiment, the substrate 305 is transferred to a deposition chamber, such as processing chamber 120, under vacuum. That is, the formation of oxides on the first metal layer 314 prevents two or more metals from diffusing into the silicon-containing substrate 305. Therefore, in an embodiment, it may be necessary to transfer the substrate to a deposition chamber to prevent the formation of additional oxides, which may be the same deposition chamber 118 or a second deposition chamber 120 under vacuum. Additionally or alternatively, optional further cleaning processes according to any one or more of the cleaning operations 210 described above may be performed prior to deposition at operation 220.

[0043] Nevertheless, in the embodiment, during operation 220, a second metal layer 316 containing the second metal 317 is deposited over the first metal layer 314 in feature 302, as... Figure 3CAs shown. In embodiments, deposition may be performed according to any suitable method in the art and may be carried out in a processing chamber configured as a chemical vapor deposition chamber, a physical vapor deposition chamber, an atomic layer deposition chamber, a thermally enhanced chemical vapor deposition chamber, a plasma-enhanced chemical vapor deposition chamber, an electroless deposition chamber, or a plasma-enhanced atomic layer deposition chamber.

[0044] In embodiments, the second metal is tungsten, molybdenum, titanium, zirconium, nickel, hafnium, cobalt, tin, tantalum, platinum, iron, niobium, palladium, its metal-containing substances, their alloys, or combinations thereof, but it should be noted that the second metal is different from the first metal. Therefore, although each of the first and second metals may be selected from metals or substances of the same or similar group, it should be understood that the second metal contains at least one metal substance different from the metal or metal substance of the first metal. For example, if the first metal is molybdenum or a molybdenum-containing substance, by way of example only, the second metal may be a metal or metal-containing substance of tungsten, titanium, zirconium, nickel, hafnium, cobalt, tin, tantalum, platinum, iron, niobium, palladium, its metal-containing substances, their alloys, or combinations thereof. Nevertheless, it should be understood that in embodiments, the second metal may also be a low-resistivity conductive metal known in the art. In embodiments, the second metal is molybdenum, titanium, zirconium, nickel, its metal-containing substances, their alloys, or combinations thereof. In embodiments, the second metal is titanium, its metal-containing substances, or their alloys.

[0045] The deposition of the second metal layer 316 may include masking operations known in the art to mask areas of the structure 300 where the deposition of the second metal layer 316 is not desired (e.g., all areas except feature 302). The masking layer may be maintained from the first metal deposition operation described above or may be a new masking operation. Nevertheless, the deposition of the second metal layer 316 may include exposing feature 302 to a second metal precursor, which may be any one or more of the second metals described above, thereby forming the second metal layer 316 over the first metal layer 314 in one or more features 302.

[0046] However, both the first metal layer 314 and the second metal layer 316 can be formed using any one or more of the deposition methods discussed above. In an embodiment, the second metal layer 316 can be deposited via a physical vapor deposition (PVD) method or system. That is, in an embodiment, the second metal layer 316 can be applied as a thin film because it is present to dope the first metal / major metal and is thus a minor component of the bimetallic silicide.

[0047] For example, such as Figure 3CAs shown, in an embodiment, the first metal layer 314 may have a first height or thickness T1, and the second metal layer may have a second height or thickness T2. In an embodiment, the thickness T1 of the first metal layer may be greater than or about 1.1 times the thickness T2 of the second metal layer, such as greater than or about 1.2 times, greater than or about 1.3 times, greater than or about 1.4 times, greater than or about 1.5 times, greater than or about 1.6 times, greater than or about 1.7 times, greater than or about 1.8 times, greater than or about 1.9 times, greater than or about 2 times, or any range or value between these values. Of course, in an embodiment, the thicknesses T1 of the first metal layer and T2 of the second metal layer may be substantially equal (e.g., about 1:1), or the second metal layer 316 may be applied as a thicker layer than the first metal layer 314, depending on the desired concentration of the first metal particles 315 and the second metal particles 317 in the bimetallic silicide layer 318.

[0048] Regardless of the method used to form the first metal layer 314 and / or the second metal layer 316, after the formation of the second metal layer 316, the substrate 305 is exposed to a thermal annealing process in operation 225 to form a silicide layer 318. Figure 3D As shown, during the diffusion process, the second metal particle 317 diffuses through the first metal layer 314 toward the upper surface 312, and the first metal particle 315 diffuses through the first metal layer 314 to the upper surface 312, so as to form a bimetallic silicide layer 318 containing both the first metal particle 315 and the second metal particle 317 at the interface between the substrate 305 and the first metal layer 314.

[0049] This technology surprisingly found that even a low concentration of the second metal 317 significantly improved the adhesion between the bimetallic silicide layer 318 and the substrate 305 compared to the same structure 300 utilizing a single metal silicide layer. Without being bound by theory, it is believed that the second metal particles 317 provide improved bonding orientation between the highly ordered silicon-containing substrate 305 and the silicide. Furthermore, in the embodiments, and without being bound by theory, the second metal particles 317 are observed only at the interface between the substrate 305 and the bimetallic silicide layer 318. Therefore, in the embodiments, the second metal particles 317 can form a bonding interface between the silicide layer 318 and the substrate 305, such as... Figure 3E As shown, and typically not present at the interface between the silicide layer 318 and the first metal layer 314. Nevertheless, it should be understood that the second metal particle 317 is integrated into the lattice of the bimetallic silicide layer 318 and can thus be considered part of the bimetallic silicide layer 318. In embodiments, the second metal particle 317 may be found alone or throughout the bimetallic silicide layer 318, except at the interface between the substrate 305 and the bimetallic silicide layer 318.

[0050] Therefore, in this embodiment, substrate 305 is a silicon-containing substrate, such as a germanium-silicon substrate. In more embodiments, the substrate may be an epitaxially formed silicon-containing substrate, such as an epitaxially formed germanium-silicon substrate. Therefore, in this embodiment, the bimetallic silicide may be molybdenum silicide (titanium).

[0051] Nevertheless, in embodiments, the thickness and / or annealing time and temperature of the second metal layer 316 may be selected to provide a bimetallic silicide layer 318 comprising a thickness greater than or about 0.8E+14 / cm at the interface between the bimetallic silicide layer 318 and the substrate 305, throughout the bimetallic silicide layer 318, or in combinations thereof. -2 The second metal atom, such as greater than or about 1E+14 / cm -2 The second metal atom, such as greater than or about 1.5E+14 / cm -2 The second metal atom, such as greater than or about 2E+14 / cm -2 The second metal atom, such as greater than or about 2.5E+14 / cm -2 The second metal atom, such as greater than or about 3E+14 / cm -2 The second metal atom, such as greater than or about 3.5E+14 / cm -2 The second metal atom, such as greater than or about 4E+14 / cm -2 The second metal atom, such as greater than or about 4.5E+14 / cm -2 The second metal atom, such as greater than or about 5E+14 / cm -2 The second metal atom, such as greater than or about 6E+14 / cm -2 The second metal atom, such as greater than or about 7E+14 / cm -2 The second metal atom, such as greater than or about 8E+14 / cm -2 The second metal atom, such as greater than or about 9E+14 / cm -2 The second metal atom, such as greater than or about 10E+14 / cm -2 The second metal atom or any range or value between them.

[0052] That is, this technology has discovered that by utilizing a bimetallic silicide having a second metal, the resulting semiconductor device can exhibit a Schottky barrier height that is at least about 5% smaller than that in a semiconductor device of the same formation (the difference being that the device does not contain the bimetallic silicide according to this technology), such as less than or greater than about 6%, such as less than or greater than about 7%, such as less than or greater than about 8%, such as less than or greater than about 9%, such as less than or greater than about 10%, such as less than or greater than about 12.5%, such as less than or greater than about 15%, such as less than or greater than about 17.5%, such as less than or greater than about 20%, such as less than or greater than about 22.5%, such as less than or greater than about 25%, such as less than or greater than about 30%, or any range or value between these values.

[0053] In other words, in embodiments, the resulting semiconductor device formed using bimetallic silicides according to the present technology may have a Schottky barrier height of less than or about 0.55 eV, such as less than or about 0.5 eV, such as less than or about 0.45 eV, such as less than or about 0.4 eV, such as less than or about 0.35 eV, such as less than or about 0.325 eV, such as less than or about 0.3 eV, such as less than or about 0.275 eV, or any range or value between these values.

[0054] In embodiments, the interfacial bonding between the bimetallic silicide layer and the substrate can be significantly improved. For example, in embodiments, the bonding energy (cohesion) exhibited by the bimetallic silicide to the substrate is at least about 3% greater than the bonding energy between a single metal silicide layer and the same substrate, such as greater than or about 4%, such as greater than or about 5%, such as greater than or about 6%, such as greater than or about 7%, such as greater than or about 8%, such as greater than or about 9%, such as greater than or about 10%, such as greater than or about 11%, or any range or value between these values. In other words, this interfacial bonding can also be expressed as the cohesion / bonding energy between the bimetallic silicide and the substrate.

[0055] Nevertheless, as shown, it should be understood that in the embodiments, the annealing process does not completely eliminate the first metal layer 314, the second metal layer 316, or both the first metal layer 314 and the second metal layer 316. However, in the embodiments, it may be desirable to select the annealing time and temperature (although not illustrated) to completely diffuse one or more of the first metal layer 314 and the second metal layer 316 into the bimetallic silicide layer 318. If one or more of the first metal layer 314 and the second metal layer 316 are retained after the formation of the bimetallic silicide layer 318, the thickness T1p of the first metal layer after annealing may be less than the thickness T1 of the first metal layer, such as being less than or greater than 1.1 times, less than or greater than 1.2 times, less than or greater than 1.3 times, less than or greater than 1.4 times, less than or greater than 1.5 times, less than or greater than 1.6 times, less than or greater than 1.7 times, less than or greater than 1.8 times, less than or greater than 1.9 times, less than or greater than 2 times, or any range or value between these values. The thickness T2p of the second metal layer after annealing may also be less than the thickness T2 of the second metal layer, but may exhibit a smaller change compared to the thickness of the first metal layer, at least in part attributable to a lower amount of second metal particles 317 available for diffusion. Therefore, in the embodiments, the thickness of the second metal after annealing, T2p, may be less than or about 0.95 times the thickness of the second metal layer before annealing, such as less than or about 0.925 times, less than or about 0.9 times, less than or about 0.875 times, less than or about 0.875 times, less than or about 0.85 times, less than or about 0.825 times, less than or about 0.8 times, or any range or value between these values.

[0056] After the bimetallic silicide layer 318 is formed, the structure 300 may undergo the deposition or formation of additional layers or features. Additionally or alternatively, the structure 300 may be transferred to a polishing operation, an interconnect deposition operation, or any other operation known in the art.

[0057] In the foregoing description, numerous details have been set forth for illustrative purposes in order to provide an understanding of various embodiments of the present technology. However, it will be apparent to those skilled in the art that certain embodiments may be practiced without some of these details or with the addition of the additional details.

[0058] Having disclosed several embodiments, those skilled in the art will recognize that various modifications, alternative constructions, and equivalents can be used without departing from the spirit of the embodiments. Additionally, to avoid unnecessarily obscuring the present technology, many well-known processes and elements have not been described. Therefore, the foregoing description should not be considered as limiting the scope of the present technology. Additionally, methods or processes may be described sequentially or in steps, but it should be understood that operations may be performed concurrently or in a different order than listed.

[0059] Where a range of values ​​is provided, it should be understood that, unless the context clearly specifies otherwise, each intermediate value (the smallest fraction to the lower limit unit) between the upper and lower limits of that range is also specifically disclosed. Any narrower range between any stated or unstated intermediate value within the stated range and any other stated or intermediate value within the stated range is included. The upper and lower limits of those smaller ranges may be independently included or excluded from that range, and any one limit, no limit, or both limits included in each of the smaller ranges are also covered in this technique, but are limited by any specifically excluded limit in the stated range. When a stated range includes one or both limits, the range excluding any one or both of those included limits is also included.

[0060] As used herein and in the appended claims, the singular forms “a,” “an,” and “the” include plural references unless the context clearly specifies otherwise. Thus, for example, reference to “metal” includes a plurality of such metals, and reference to “layer” includes one or more layers known to those skilled in the art and their equivalents, and so on.

[0061] Furthermore, the terms “comprise(s)”, “comprising”, “contain(s)”, “containing”, “include(s)”, and “including” are intended, when used in this specification and the appended claims, to indicate the presence of the stated features, integers, components, or operations, but do not exclude the presence or addition of one or more other features, integers, components, operations, actions, or groups.

Claims

1. A semiconductor device, the semiconductor device comprising: substrate, Silicon oxide, disposed on the substrate, thereby defining one or more features; A bimetallic silicide layer disposed on the substrate of one or more of the features, the bimetallic silicide comprising a first metal, a second metal different from the first metal, and a silicon-containing compound, wherein the bimetallic silicide layer comprises a concentration greater than or about 0.8E+14 / cm². -2 The second metal atom; and At least a first metal layer, the first metal layer comprising the first metal covering the bimetallic silicide layer.

2. The semiconductor device of claim 1, wherein the semiconductor device exhibits a Schottky barrier height that is at least about 5% smaller than that of a semiconductor device without bimetallic silicides.

3. The semiconductor device of claim 1, wherein the semiconductor device exhibits a Schottky barrier height of less than 0.55 eV.

4. The semiconductor device of claim 1, wherein the bimetallic silicide layer comprises a value greater than or about 3E+14 / cm -2 The second metallic atom.

5. The semiconductor device of claim 1, further comprising a second metal layer, the second metal layer comprising a second metal covering the first metal layer.

6. The semiconductor device of claim 4, wherein the second metal is titanium, zirconium, nickel, molybdenum, or a combination thereof.

7. The semiconductor device of claim 6, wherein the first metal is titanium, zirconium, nickel, molybdenum, or a combination thereof.

8. The semiconductor device of claim 7, wherein the first metal is molybdenum, the second metal is titanium, and the bimetallic silicide is molybdenum silicide (titanium).

9. The semiconductor device of claim 1, wherein the bimetallic silicide layer is disposed in the p-MOS region.

10. The semiconductor device of claim 1, wherein the bimetallic silicide layer is disposed in the n-MOS region.

11. A semiconductor device processing system, the semiconductor device processing system comprising: First processing chamber; Second processing chamber; The third processing chamber; as well as System controller, the system controller being configured to: In the first processing chamber, at least a first feature is etched into an oxide on a silicon-containing substrate; In the second processing chamber, a first metal layer containing the first metal is deposited over the silicon-containing substrate, which contains at least the first feature; In the second processing chamber or the third processing chamber, a second metal layer containing a second metal is deposited on top of the first metal layer; as well as The semiconductor device is annealed to form a bimetallic silicide layer between the silicon-containing substrate and the first metal layer.

12. The semiconductor processing system of claim 11, wherein the first metal is molybdenum, titanium, zirconium, nickel, or a combination thereof, and wherein the substrate is exposed to the first metal precursor and the first metal reactant in the second processing chamber.

13. The semiconductor processing system of claim 12, wherein the second metal is molybdenum, titanium, zirconium, nickel, or a combination thereof, and wherein the substrate is exposed to the second metal precursor and the second metal reactant in the third processing chamber.

14. A method of forming a semiconductor device, the method comprising: At least the first feature is etched into an oxide disposed on a silicon-containing substrate; A first metal layer containing a first metal is deposited over the silicon-containing substrate, at least in the first feature; A second metal layer containing a second metal different from the first metal is deposited on top of the first metal layer; as well as The semiconductor device is annealed to form a bimetallic silicide layer between the silicon-containing substrate and the first metal layer.

15. The method of claim 14, wherein depositing the first metal layer comprises exposing the substrate, at least in the first feature, to the first metal precursor.

16. The method of claim 15, wherein depositing the second metal layer includes exposing the first metal layer to the second metal precursor.

17. The method of claim 16, wherein the first metal and the second metal are individually selected from molybdenum, titanium, zirconium, nickel, or combinations thereof.

18. The method of claim 14, wherein the semiconductor device exhibits a Schottky barrier height that is at least about 5% smaller than that in a semiconductor device without bimetallic silicides.

19. The method of claim 14, wherein the second metal is sufficient to produce a value greater than or about 0.8E+14 / cm in the bimetallic silicide layer. -2 The amount of the second metal atoms is applied to the second metal layer.

20. The method of claim 14, wherein the bimetallic silicide layer exhibits a binding energy to the same substrate that is at least about 3% greater than that of the monometallic silicide layer to the substrate.

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