A method and system for detecting insertion of a semiconductor device

Abstract

The application discloses a kind of plug-in detection method and system of semiconductor device, it is related to semiconductor device detection technical field.The method comprises: obtaining device application record set;Constitute temperature and humidity heterostructure scene group, mechanical impact heterostructure scene group and thermal shock heterostructure scene group;Semiconductor device is carried out plug-in temperature and humidity heterochange detection, obtains plug-in detection first atlas;Semiconductor device is carried out plug-in mechanical heterochange detection, obtains plug-in detection second atlas;Semiconductor device is carried out plug-in thermal shock heterochange detection, obtains plug-in detection third atlas;According to plug-in detection first atlas, plug-in detection second atlas and plug-in detection third atlas, establish plug-in detection fourth atlas.The technical problem that single semiconductor device plug-in detection scene in prior art leads to difficult to comprehensively and accurately evaluate device plug-in performance is solved, reaches the technical effect that through introduction multiple heterostructure detection scene, realizes to the comprehensive and accurate evaluation of semiconductor device plug-in performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device testing technology, and specifically to a method and system for testing the connection of semiconductor devices. Background Technology

[0002] In practical applications, semiconductor devices often undergo multiple mating operations, and the reliability of mating performance directly affects the quality of electrical connections and the long-term lifespan of the devices. Existing mating testing methods mostly focus on single scenarios, such as testing under constant temperature and humidity conditions or specific mechanical shock conditions. While these methods can provide a certain degree of evaluation of device performance, they struggle to cover the complex and ever-changing environmental factors encountered in real-world applications. Under the influence of multiple environmental factors, the mating performance of semiconductor devices may exhibit complex abnormal patterns, and traditional testing methods often fail to effectively identify and comprehensively evaluate these potential anomalies, resulting in limitations in the mating performance evaluation results. Summary of the Invention

[0003] This application provides a method and system for testing the insertion of semiconductor devices, which solves the technical problem that the existing semiconductor device insertion testing scenarios are limited, making it difficult to comprehensively and accurately evaluate the device insertion performance.

[0004] The first aspect of this application provides a method for detecting the insertion of a semiconductor device, the method comprising:

[0005] Application record retrieval is performed on semiconductor devices to obtain a device application record set; based on the device application record set, multi-dimensional detection scenario optimization is performed to construct temperature and humidity heterogeneous scenario groups, mechanical shock heterogeneous scenario groups, and thermal shock heterogeneous scenario groups; a connection performance variation tracing channel is established, and connection temperature and humidity variation detection is performed on the semiconductor devices based on the connection performance variation tracing channel and the temperature and humidity heterogeneous scenario groups to obtain a first connection detection spectrum; based on the connection performance variation tracing channel, connection mechanical variation detection is performed on the semiconductor devices according to the mechanical shock heterogeneous scenario groups to obtain a second connection detection spectrum; based on the connection performance variation tracing channel, connection thermal shock variation detection is performed on the semiconductor devices according to the thermal shock heterogeneous scenario groups to obtain a third connection detection spectrum; based on the first connection detection spectrum, the second connection detection spectrum, and the third connection detection spectrum, a fourth connection detection spectrum is established.

[0006] A second aspect of this application provides a semiconductor device insertion detection system, the system comprising:

[0007] The system comprises the following modules: a retrieval module for application records of semiconductor devices to obtain a set of device application records; a scenario optimization module for multi-dimensional detection scenario optimization based on the device application record set to construct temperature and humidity heterogeneous scenario groups, mechanical shock heterogeneous scenario groups, and thermal shock heterogeneous scenario groups; a first detection module for establishing a connection performance variation tracing channel and performing connection temperature and humidity variation detection on the semiconductor devices based on the connection performance variation tracing channel and the temperature and humidity heterogeneous scenario groups to obtain a first connection detection spectrum; a second detection module for performing connection mechanical variation detection on the semiconductor devices based on the connection performance variation tracing channel and the mechanical shock heterogeneous scenario groups to obtain a second connection detection spectrum; a third detection module for performing connection thermal shock variation detection on the semiconductor devices based on the connection performance variation tracing channel and the thermal shock heterogeneous scenario groups to obtain a third connection detection spectrum; and a spectrum establishment module for establishing a fourth connection detection spectrum based on the first, second, and third connection detection spectra.

[0008] One or more technical solutions provided in this application have at least the following technical effects or advantages:

[0009] First, application records are retrieved for semiconductor devices to obtain a device application record set. Next, based on the device application record set, multi-dimensional detection scenario optimization is performed to construct temperature and humidity heterogeneous scenario groups, mechanical shock heterogeneous scenario groups, and thermal shock heterogeneous scenario groups. Then, a connection performance variation traceability channel is established, and connection temperature and humidity variation detection is performed on semiconductor devices based on the connection performance variation traceability channel and the temperature and humidity heterogeneous scenario groups to obtain the first connection detection spectrum. Based on the connection performance variation traceability channel, connection mechanical variation detection is performed on semiconductor devices according to the mechanical shock heterogeneous scenario group to obtain the second connection detection spectrum. Based on the connection performance variation traceability channel, connection thermal shock variation detection is performed on semiconductor devices according to the thermal shock heterogeneous scenario group to obtain the third connection detection spectrum. Finally, a fourth connection detection spectrum is established based on the first, second, and third connection detection spectra. This invention solves the technical problem that the single testing scenario for semiconductor device insertion in existing technologies makes it difficult to comprehensively and accurately evaluate the device insertion performance. It achieves the technical effect of comprehensively and accurately evaluating the insertion performance of semiconductor devices by introducing diverse and heterogeneous testing scenarios. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 A schematic flowchart of a semiconductor device insertion detection method provided in an embodiment of this application;

[0012] Figure 2 This is a schematic diagram of a semiconductor device insertion detection system provided in an embodiment of this application.

[0013] Explanation of reference numerals in the attached diagram: retrieval module 11, scene optimization module 12, first detection module 13, second detection module 14, third detection module 15, map building module 16. Detailed Implementation

[0014] This application provides a semiconductor device insertion detection method and system, which solves the technical problem in the prior art where the semiconductor device insertion detection scenario is limited, making it difficult to comprehensively and accurately evaluate the device insertion performance.

[0015] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0016] It should be noted that the terms "comprising" and "having" are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or server that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or modules that are not explicitly listed or that are inherent to these processes, methods, products, or devices.

[0017] Example 1, as Figure 1 As shown, this application provides a method for detecting the insertion of a semiconductor device, wherein the method includes:

[0018] Application records of semiconductor devices are retrieved to obtain a set of device application records.

[0019] Furthermore, application record retrieval of semiconductor devices yields a device application record set, including:

[0020] Obtain the application record library of the semiconductor device; clean the application record library to obtain the application record set of the device.

[0021] In this embodiment, application record retrieval is performed on the target semiconductor device. Specifically, an application record library of the semiconductor device during actual operation is obtained. The application record library includes the device's usage environment parameters, number of insertion operations, operating time information, and historical fault information. Data cleaning is performed on the data in the application record library, including removing redundant records, completing missing data, and standardizing the data format, thereby forming a standardized record dataset for analysis. After preprocessing, index matching is performed on the target semiconductor device to retrieve all record data related to the device model, batch, and application environment. The retrieved valid datasets are merged, deduplicated, and structured for storage, forming a device application record set.

[0022] Based on the device application record set, multi-dimensional detection scenario optimization is performed to construct temperature and humidity heterogeneous scenario group, mechanical shock heterogeneous scenario group and thermal shock heterogeneous scenario group.

[0023] In this embodiment, based on the device application record set, multi-dimensional detection scenario optimization is performed to construct a heterogeneous scenario group covering actual application environments. Specifically, multi-dimensional feature analysis is performed on the device application record set to extract temperature and humidity features, mechanical shock features, and thermal shock features related to mating performance. For temperature and humidity features, combined with the device's operating status in different humidity and temperature ranges, triggering degree calculation and coupling degree evaluation are performed for each temperature and humidity combination condition, and feature combinations that significantly affect mating performance are screened out through perturbation optimization methods to form a temperature and humidity heterogeneous scenario group. For mechanical shock features, cluster analysis and anomaly distribution detection are performed on recorded samples with different impact intensities, impact frequencies, and directions of action to form a mechanical shock heterogeneous scenario group that can reflect various mechanical stress conditions. For thermal shock features, combined with recorded samples of the device during rapid heating and cooling cycles, comprehensive optimization of thermal cycling amplitude and rate is performed to generate a thermal shock heterogeneous scenario group that can cover multiple types of temperature abrupt change conditions.

[0024] Furthermore, optimization of multiple detection scenarios based on the device application record set includes:

[0025] The device application record set is used to identify the temperature and humidity features of the application scenarios to obtain a first temperature and humidity feature group; based on the device application record set, the trigger degree of each temperature and humidity feature of the first temperature and humidity feature group is calculated to obtain a temperature and humidity trigger degree set; based on the temperature and humidity trigger degree set, the first temperature and humidity feature group is optimized according to a predetermined temperature and humidity trigger degree to obtain a second temperature and humidity feature group; the pairwise coupling degree of the second temperature and humidity feature group is evaluated to obtain a temperature and humidity coupling degree set; the second temperature and humidity feature group is perturbed and optimized according to the temperature and humidity coupling degree set to generate the temperature and humidity heterogeneous scenario group.

[0026] Specifically, the device application record set is parsed to extract temperature and humidity-related change information, and the temperature and humidity combinations under different application scenarios are characterized and labeled to form a first temperature and humidity feature group. Based on the first temperature and humidity feature group, the frequency of occurrence of each application scenario temperature and humidity feature in the device application record set is statistically analyzed, and the frequency of occurrence is the temperature and humidity triggering degree, thereby obtaining a temperature and humidity triggering degree set. According to a pre-set temperature and humidity triggering degree threshold, temperature and humidity features with triggering degrees greater than or equal to the threshold are selected from the first temperature and humidity feature group to form a second temperature and humidity feature group. The second temperature and humidity feature group is analyzed in pairs, by calculating the Euclidean distance between any two application scenario temperature and humidity features, and mapping the inverse of the distance to the coupling degree value. Finally, the coupling degree value of all feature pairs is calculated in turn to obtain the temperature and humidity coupling degree set.

[0027] The second temperature and humidity feature group is perturbed and optimized using a temperature and humidity coupling set. This includes: identifying temperature and humidity feature pairs with high coupling based on the coupling set and retaining them as stable combinations; marking feature pairs with low coupling as potential perturbation objects; introducing parameter perturbation operations into these potential perturbation objects, such as increasing or decreasing the temperature fluctuation amplitude by a preset percentage, fine-tuning the humidity change rate, or randomly perturbing within the original value range to generate new temperature and humidity feature combinations; comparing the perturbed feature combinations with the temperature and humidity coupling set again; adding combinations that maintain a certain coupling threshold to the optimized feature set; discarding combinations that do not meet the threshold requirement. Through multiple rounds of iterative perturbation and selection, the diversity of temperature and humidity features is expanded while maintaining the main coupling relationships, thus generating a heterogeneous temperature and humidity scene group.

[0028] Optionally, based on the device application record set, the mechanical impact information involved is characterized, including parameters such as impact intensity, impact frequency, and impact direction, forming a first mechanical impact feature group. Subsequently, the frequency of occurrence of each feature within the first mechanical impact feature group in the application record set is statistically analyzed and defined as the mechanical impact triggering degree, obtaining a mechanical impact triggering degree set. Based on a preset triggering degree threshold, features with triggering degrees greater than or equal to the threshold are selected from the first mechanical impact feature group to form a second mechanical impact feature group. Further, pairwise coupling analysis is performed on the second mechanical impact feature group to calculate the correlation and synergistic effect between different impact features, obtaining a mechanical impact coupling degree set. Finally, combined with the coupling degree set, perturbation optimization is performed on the second mechanical impact feature group to generate a mechanical impact heterogeneous scenario group.

[0029] Optionally, based on the device application record set, features are extracted from the thermal shock information involved, including parameters such as temperature change amplitude, temperature change rate, and number of thermal cycles, forming a first thermal shock feature group. Subsequently, triggering degree statistics are performed on the first thermal shock feature group, with triggering degree measured by the frequency of feature occurrence in the application record set, resulting in a thermal shock triggering degree set. Based on a preset triggering degree threshold, the first thermal shock feature group is filtered to obtain a second thermal shock feature group. On this basis, pairwise coupling degrees are calculated for the second thermal shock feature group to reflect the coupling effect under different combinations of thermal shock features, resulting in a thermal shock coupling degree set. Finally, combining the thermal shock coupling degree set results, perturbation optimization is performed on the second thermal shock feature group to generate a thermal shock heterogeneous scenario group.

[0030] A connection performance variation tracing channel is established, and the connection temperature and humidity variation of the semiconductor device is detected based on the connection performance variation tracing channel and the temperature and humidity heterogeneous scenario group to obtain the first connection detection map.

[0031] In this embodiment of the application, a mating performance variation tracing channel is established to record and analyze abnormal changes in the mating performance of semiconductor devices under different conditions. The mating performance variation tracing channel is combined with a temperature and humidity heterogeneous scenario group to test the mating performance of semiconductor devices under various temperature and humidity conditions, and to trace and analyze the abnormal data generated during the testing process, thereby generating a first mating test map that reflects the change law of mating performance of semiconductor devices under temperature and humidity environment.

[0032] Furthermore, establishing a traceability channel for plug-in performance variations includes:

[0033] The semiconductor devices are interconnected with the same type of features to obtain an interconnected device group, and a set of insertion performance variation events is loaded based on the interconnected device group; fault tree training is performed based on the set of insertion performance variation events to obtain an insertion variation fault tree model; perturbation injection is performed based on the set of insertion performance variation events to obtain a set of insertion variation event perturbations; the insertion variation fault tree model is tested based on the set of insertion variation event perturbations to obtain a model test loss dataset; attention enhancement is performed on the set of insertion variation event perturbations based on the model test loss dataset to obtain a perturbation enhancement map; the insertion variation fault tree model is enhanced and trained based on the perturbation enhancement map to generate the insertion performance variation tracing channel.

[0034] Specifically, semiconductor devices are interconnected based on similar characteristics. This involves establishing a correspondence between several identical semiconductor devices in terms of appearance, material properties, and mating history, forming an interconnected device group. Based on this, mating performance anomaly event data recorded during long-term application of these devices is retrieved and loaded to construct a mating performance variation event set. Subsequently, using this event set as input, a causal inference model of mating performance anomalies is established using fault tree analysis. Iterative training yields a mating anomaly fault tree model, used to characterize the logical relationships and propagation paths between different mating anomaly events. Next, perturbation injection is introduced into the event set. This involves adding parameter perturbations, environmental perturbations, and operating condition perturbations to the original anomaly data to generate a mating anomaly event perturbation set, used to simulate the abnormal behavior of semiconductor devices under complex conditions. The fault tree model is then validated and tested against the mating anomaly event perturbation set to obtain a model test loss dataset, quantifying the model's accuracy and robustness under different perturbation conditions. Furthermore, based on the model test loss dataset, an attention mechanism is applied to the perturbation set of insertion anomaly events to enhance the weight allocation of key abnormal nodes and high-risk paths, generating an enhanced perturbation graph. Finally, the enhanced perturbation graph is fed back into the insertion anomaly fault tree model for iterative optimization training, resulting in an insertion performance anomaly tracing channel capable of continuous learning and anomaly source tracing, which can support subsequent insertion performance anomaly detection and tracing analysis in multiple scenarios.

[0035] Furthermore, based on the aforementioned insertion performance variation tracing channel and the aforementioned temperature and humidity heterogeneous scenario group, the semiconductor device is subjected to insertion temperature and humidity variation detection to obtain a first insertion detection map, including:

[0036] A semiconductor model is obtained by performing 3D modeling based on the semiconductor device; the semiconductor model is then subjected to insertion performance anomaly detection based on the temperature and humidity heterogeneous scenario group to obtain a first insertion anomaly detection group; each insertion anomaly detection sequence in the first insertion anomaly detection group is traced for anomaly based on the insertion performance anomaly tracing channel to obtain a first insertion anomaly tracing group; the first insertion anomaly tracing group is correlated and analyzed based on the temperature and humidity heterogeneous scenario group to obtain an insertion anomaly temperature and humidity correlation group; the first insertion anomaly detection group, the first insertion anomaly tracing group, and the insertion anomaly temperature and humidity correlation group are correlated and mapped to generate the first insertion detection map.

[0037] Specifically, a 3D model of the semiconductor device is performed. This 3D model includes the device's external structure, pin layout, package type, and geometric parameters related to insertion, resulting in a semiconductor model suitable for simulation analysis. The semiconductor model is input into a temperature and humidity heterogeneous scenario group for simulation testing. Multiple rounds of testing are conducted on the device's insertion performance under different temperature and humidity conditions, resulting in multiple insertion performance change sequences. These sequences are then aggregated to form a first insertion anomaly detection group. Based on the insertion performance anomaly tracing channel, each detection sequence in the first insertion anomaly detection group undergoes source analysis to identify and trace potential events or scenario factors leading to abnormal insertion performance. This yields multiple traced insertion anomaly sequences, forming a first insertion anomaly tracing group. Furthermore, combined with the temperature and humidity heterogeneous scenario group, the first insertion anomaly tracing group undergoes correlation analysis to extract the correspondence between different temperature and humidity parameters and anomaly sequences, forming an insertion anomaly temperature and humidity correlation group to characterize the coupling characteristics between temperature and humidity conditions and insertion anomalies. Finally, the first insertion anomaly detection group, the first insertion anomaly tracing group, and the insertion anomaly temperature and humidity correlation group are mapped in a multi-dimensional manner to generate the first insertion detection map. The first insertion detection map is used to characterize the evolution law of the insertion performance of semiconductor devices under temperature and humidity conditions and its abnormal distribution characteristics.

[0038] Furthermore, based on the aforementioned temperature and humidity heterogeneous scenario group, the semiconductor model is subjected to interlocking performance anomaly detection to obtain a first interlocking anomaly detection group, including:

[0039] The Kth temperature and humidity heterogeneous scenario is extracted from the temperature and humidity heterogeneous scenario group, where K is a positive integer; the semiconductor model is subjected to insertion performance testing based on the Kth temperature and humidity heterogeneous scenario to obtain the Kth insertion performance testing sequence; qualified insertion performance samples are retrieved based on the semiconductor device to obtain a qualified insertion performance library; central tendency analysis is performed based on the qualified insertion performance library to determine the insertion performance benchmark testing sequence; anomaly detection is performed on the Kth insertion performance testing sequence based on the benchmark testing sequence to obtain the Kth insertion anomaly detection sequence, and the Kth insertion anomaly detection sequence is added to the first insertion anomaly detection group.

[0040] The Kth temperature and humidity heterogeneous scenario is extracted from the temperature and humidity heterogeneous scenario group. Each temperature and humidity heterogeneous scenario corresponds to a specific temperature range, humidity level, and combination of the two. The semiconductor model is placed in the Kth temperature and humidity heterogeneous scenario for mating performance testing. Changes in electrical contact resistance, insertion and extraction forces, and performance stability under these conditions are recorded to obtain the Kth mating performance testing sequence. Based on historical and standard testing data of semiconductor devices, qualified mating performance samples are retrieved to construct a qualified mating performance library. Using the qualified mating performance library as a reference, central tendency analysis is performed, including analyzing statistical indicators such as the mean, median, and standard deviation of multiple qualified samples, to determine the benchmark mating performance testing sequence. The benchmark mating performance testing sequence is compared with the Kth mating performance testing sequence to identify performance deviations and abnormal fluctuations, completing anomaly detection and obtaining the Kth mating anomaly detection sequence, which is added to the first mating anomaly detection group. By repeating the above steps for all temperature and humidity heterogeneous scenarios, a complete first mating anomaly detection group is finally formed to reflect the abnormal mating performance characteristics of semiconductor devices under different temperature and humidity environments.

[0041] Based on the aforementioned insertion performance variation tracing channel, the semiconductor device is subjected to insertion mechanical variation detection according to the aforementioned mechanical impact heterogeneous scenario group, and a second insertion detection map is obtained.

[0042] In this embodiment of the application, based on the insertion performance variation tracing channel, the mechanical shock heterogeneous scenario group is applied to the insertion detection of semiconductor devices, simulating the operating conditions under different impact intensities, frequencies and directions, capturing and tracing the possible anomalies in the insertion performance of semiconductor devices, and mapping and summarizing the detection results in multiple dimensions, finally generating a second insertion detection map that reflects the variation law of insertion performance of semiconductor devices under mechanical shock environment.

[0043] Furthermore, based on the aforementioned insertion performance variation tracing channel, the semiconductor device is subjected to insertion mechanical variation detection according to the aforementioned mechanical shock heterogeneous scenario group to obtain a second insertion detection map, including:

[0044] The semiconductor model is subjected to insertion performance variation detection based on the aforementioned heterogeneous mechanical impact scenario group to obtain a second insertion variation detection group; the second insertion variation detection group is traced for variation according to the insertion performance variation tracing channel to obtain a second insertion variation tracing group; the second insertion variation tracing group is correlated and analyzed based on the aforementioned heterogeneous mechanical impact scenario group to obtain an insertion variation mechanical impact correlation group; the second insertion variation detection group, the second insertion variation tracing group, and the insertion variation mechanical impact correlation group are correlated and mapped to generate the second insertion detection map.

[0045] The Kth mechanical impact heterogeneous scenario is extracted from the group of mechanical impact heterogeneous scenarios, where each scenario corresponds to specific parameters such as impact intensity, impact frequency, and direction of impact. Subsequently, the semiconductor model is placed within the Kth mechanical impact heterogeneous scenario for mating performance testing, resulting in the Kth mating performance testing sequence. Next, based on historical or standard testing data of the semiconductor device, a qualified mating performance sample library is retrieved. Using this qualified sample library as a reference, central tendency analysis is performed to determine the benchmark mating performance testing sequence. Finally, the benchmark testing sequence is compared with the Kth mating performance testing sequence to identify performance deviations and abnormal patterns, resulting in the Kth mating anomaly detection sequence, which is added to the second mating anomaly detection group. By repeating the above steps for all mechanical impact heterogeneous scenarios, a complete second mating anomaly detection group is formed, used to characterize the abnormal distribution features of the mating performance of semiconductor devices under different impact conditions.

[0046] By utilizing the insertion performance anomaly tracing channel, anomalies are traced back to their source in each detection sequence of the second insertion anomaly detection group, identifying the impact factors causing performance anomalies and their propagation paths, thus obtaining the second insertion anomaly tracing group. Further, feature matching and correlation analysis are performed between the second insertion anomaly tracing group and the heterogeneous mechanical shock scenario group to extract the mapping relationship between different impact parameters and insertion anomalies, obtaining the insertion anomaly mechanical shock correlation group. Finally, multi-dimensional correlation mapping is performed on the second insertion anomaly detection group, the second insertion anomaly tracing group, and the insertion anomaly mechanical shock correlation group to generate a second insertion detection atlas, used to characterize the insertion performance anomaly patterns and evolution laws of semiconductor devices under mechanical shock conditions.

[0047] Based on the aforementioned insertion performance variation tracing channel, the semiconductor device is subjected to insertion thermal shock variation detection according to the thermal shock heterogeneous scenario group to obtain the third insertion detection map.

[0048] In this embodiment of the application, based on the insertion performance variation tracing channel, the thermal shock heterogeneous scenario group is applied to the insertion detection of semiconductor devices. By simulating different temperature change amplitudes, rates and cycles, the insertion performance anomalies that may occur under thermal shock are identified and traced. The detection results are summarized and mapped to finally form a third insertion detection map that reflects the insertion performance change characteristics of semiconductor devices under thermal shock environment.

[0049] Furthermore, based on the aforementioned insertion performance variation tracing channel, the semiconductor device is subjected to insertion thermal shock variation detection according to the aforementioned thermal shock heterogeneous scenario group to obtain a third insertion detection map, including:

[0050] The semiconductor model is subjected to insertion performance anomaly detection based on the thermal shock heterogeneous scenario group to obtain a third insertion anomaly detection group; the third insertion anomaly detection group is traced for anomalies based on the insertion performance anomaly tracing channel to obtain a third insertion anomaly tracing group; the third insertion anomaly tracing group is correlated and analyzed based on the thermal shock heterogeneous scenario group to obtain an anomaly thermal shock correlation group; the third insertion anomaly detection group, the third insertion anomaly tracing group, and the anomaly thermal shock correlation group are correlated and mapped to generate the third insertion detection map.

[0051] The Kth thermal shock heterogeneous scenario is extracted sequentially from the thermal shock heterogeneous scenario group. Each thermal shock heterogeneous scenario corresponds to specific conditions such as temperature change amplitude, temperature change rate, and number of cycles. The semiconductor model is placed in the Kth thermal shock heterogeneous scenario for mating performance testing, and its contact resistance, insertion force, structural stability, and thermal fatigue characteristics under these conditions are recorded to obtain the Kth mating performance testing sequence. Based on historical qualified data or standard samples of semiconductor devices, a qualified mating performance library is obtained. Using this qualified library as a reference, central tendency analysis is performed to statistically analyze the mean, median, and fluctuation range of qualified samples to determine the benchmark mating performance testing sequence. Finally, the benchmark testing sequence is compared with the Kth mating performance testing sequence to identify deviations and abnormal fluctuations, resulting in the Kth mating anomaly testing sequence, which is added to the third mating anomaly testing group. By repeating the above steps for all thermal shock heterogeneous scenarios, a complete third mating anomaly testing group is finally formed to characterize the abnormal mating performance modes of semiconductor devices under different thermal shock conditions.

[0052] After obtaining the third insertion anomaly detection group, the anomalies in the third insertion anomaly detection group are further traced based on the insertion performance anomaly tracing channel to obtain the third insertion anomaly tracing group. Then, combined with the thermal shock heterogeneous scenario group, the tracing group is correlated and analyzed to extract the correspondence between thermal shock parameters and insertion anomalies, resulting in the anomaly thermal shock correlation group. Finally, multi-dimensional correlation mapping is performed on the third insertion anomaly detection group, the third insertion anomaly tracing group, and the anomaly thermal shock correlation group to generate the third insertion detection map, which is used to comprehensively reveal the variation law and anomaly distribution characteristics of the insertion performance of semiconductor devices under thermal shock environment.

[0053] A fourth insertion detection map is established based on the first insertion detection map, the second insertion detection map, and the third insertion detection map.

[0054] In this embodiment, the first, second, and third insertion detection maps are fused. Specifically, the insertion performance data, anomaly distribution characteristics, and environmental parameters contained in the three maps are standardized to ensure comparability within the same data dimension. Subsequently, insertion anomaly patterns under temperature and humidity conditions, mechanical shock conditions, and thermal shock conditions are analyzed and fused. By calculating the common and dissimilar anomaly features among the different maps, a multi-scenario insertion anomaly feature set is formed. Based on this, a map mapping method is used to map the multi-scenario insertion anomaly feature set into a unified multi-dimensional correlation map structure, resulting in the fourth insertion detection map. The fourth map comprehensively reflects the changes in the insertion performance of semiconductor devices under various environmental conditions, providing a basis for comprehensively evaluating the reliability of the devices.

[0055] Furthermore, adaptive maintenance management of the semiconductor device is performed based on the fourth patch detection map.

[0056] Specifically, the system comprehensively assesses the insertion performance status of target devices based on the fourth insertion detection map, identifying abnormal distribution characteristics under various conditions such as temperature and humidity, mechanical shock, and thermal shock. Subsequently, based on the assessment results, the device operating status is classified into three maintenance levels: normal, warning, and fault. When the map shows that the device insertion performance remains stable, the system automatically maintains normal operation. When a slight local deviation or potential abnormal trend appears in the map, a warning mechanism is triggered, and lightweight maintenance operations such as parameter tuning, environmental compensation, or insertion action optimization are performed. When the map shows that the device has severe performance degradation or multiple abnormal scenarios, a fault maintenance process is triggered, including disabling the device, replacing components, or performing in-depth repairs.

[0057] In summary, the embodiments of this application have at least the following technical effects:

[0058] First, application records are retrieved for semiconductor devices to obtain a device application record set. Next, based on the device application record set, multi-dimensional detection scenario optimization is performed to construct temperature and humidity heterogeneous scenario groups, mechanical shock heterogeneous scenario groups, and thermal shock heterogeneous scenario groups. Then, a connection performance variation traceability channel is established, and connection temperature and humidity variation detection is performed on semiconductor devices based on the connection performance variation traceability channel and the temperature and humidity heterogeneous scenario groups to obtain the first connection detection spectrum. Based on the connection performance variation traceability channel, connection mechanical variation detection is performed on semiconductor devices according to the mechanical shock heterogeneous scenario group to obtain the second connection detection spectrum. Based on the connection performance variation traceability channel, connection thermal shock variation detection is performed on semiconductor devices according to the thermal shock heterogeneous scenario group to obtain the third connection detection spectrum. Finally, a fourth connection detection spectrum is established based on the first, second, and third connection detection spectra. This invention solves the technical problem that the single testing scenario for semiconductor device insertion in existing technologies makes it difficult to comprehensively and accurately evaluate the device insertion performance. It achieves the technical effect of comprehensively and accurately evaluating the insertion performance of semiconductor devices by introducing diverse and heterogeneous testing scenarios.

[0059] Example 2, based on the same inventive concept as the semiconductor device insertion detection method in the foregoing examples, such as... Figure 2 As shown, this application provides a semiconductor device insertion detection system, wherein the system includes:

[0060] Search module 11: Searches application records for semiconductor devices to obtain a set of device application records; Scene optimization module 12: Optimizes multi-dimensional detection scenarios based on the device application record set to construct temperature and humidity heterogeneous scenario groups, mechanical shock heterogeneous scenario groups, and thermal shock heterogeneous scenario groups; First detection module 13: Establishes a connection performance variation traceability channel and performs connection temperature and humidity variation detection on the semiconductor devices based on the connection performance variation traceability channel and the temperature and humidity heterogeneous scenario groups to obtain a first connection detection spectrum; Second detection module 14: Performs connection mechanical variation detection on the semiconductor devices based on the connection performance variation traceability channel and the mechanical shock heterogeneous scenario groups to obtain a second connection detection spectrum; Third detection module 15: Performs connection thermal shock variation detection on the semiconductor devices based on the connection performance variation traceability channel and the thermal shock heterogeneous scenario groups to obtain a third connection detection spectrum; Spectrum establishment module 16: Establishes a fourth connection detection spectrum based on the first connection detection spectrum, the second connection detection spectrum, and the third connection detection spectrum.

[0061] Furthermore, the scene optimization module 12 is used to perform the following method:

[0062] The device application record set is used to identify the temperature and humidity features of the application scenarios to obtain a first temperature and humidity feature group; based on the device application record set, the trigger degree of each temperature and humidity feature of the first temperature and humidity feature group is calculated to obtain a temperature and humidity trigger degree set; based on the temperature and humidity trigger degree set, the first temperature and humidity feature group is optimized according to a predetermined temperature and humidity trigger degree to obtain a second temperature and humidity feature group; the pairwise coupling degree of the second temperature and humidity feature group is evaluated to obtain a temperature and humidity coupling degree set; the second temperature and humidity feature group is perturbed and optimized according to the temperature and humidity coupling degree set to generate the temperature and humidity heterogeneous scenario group.

[0063] Furthermore, the first detection module 13 is used to perform the following method:

[0064] The semiconductor devices are interconnected with the same type of features to obtain an interconnected device group, and a set of insertion performance variation events is loaded based on the interconnected device group; fault tree training is performed based on the set of insertion performance variation events to obtain an insertion variation fault tree model; perturbation injection is performed based on the set of insertion performance variation events to obtain a set of insertion variation event perturbations; the insertion variation fault tree model is tested based on the set of insertion variation event perturbations to obtain a model test loss dataset; attention enhancement is performed on the set of insertion variation event perturbations based on the model test loss dataset to obtain a perturbation enhancement map; the insertion variation fault tree model is enhanced and trained based on the perturbation enhancement map to generate the insertion performance variation tracing channel.

[0065] Furthermore, the first detection module 13 is used to perform the following method:

[0066] A semiconductor model is obtained by performing 3D modeling based on the semiconductor device; the semiconductor model is then subjected to insertion performance anomaly detection based on the temperature and humidity heterogeneous scenario group to obtain a first insertion anomaly detection group; each insertion anomaly detection sequence in the first insertion anomaly detection group is traced for anomaly based on the insertion performance anomaly tracing channel to obtain a first insertion anomaly tracing group; the first insertion anomaly tracing group is correlated and analyzed based on the temperature and humidity heterogeneous scenario group to obtain an insertion anomaly temperature and humidity correlation group; the first insertion anomaly detection group, the first insertion anomaly tracing group, and the insertion anomaly temperature and humidity correlation group are correlated and mapped to generate the first insertion detection map.

[0067] Furthermore, the first detection module 13 is used to perform the following method:

[0068] The Kth temperature and humidity heterogeneous scenario is extracted from the temperature and humidity heterogeneous scenario group, where K is a positive integer; the semiconductor model is subjected to insertion performance testing based on the Kth temperature and humidity heterogeneous scenario to obtain the Kth insertion performance testing sequence; qualified insertion performance samples are retrieved based on the semiconductor device to obtain a qualified insertion performance library; central tendency analysis is performed based on the qualified insertion performance library to determine the insertion performance benchmark testing sequence; anomaly detection is performed on the Kth insertion performance testing sequence based on the benchmark testing sequence to obtain the Kth insertion anomaly detection sequence, and the Kth insertion anomaly detection sequence is added to the first insertion anomaly detection group.

[0069] Furthermore, the second detection module 14 is used to perform the following method:

[0070] The semiconductor model is subjected to insertion performance variation detection based on the aforementioned heterogeneous mechanical impact scenario group to obtain a second insertion variation detection group; the second insertion variation detection group is traced for variation according to the insertion performance variation tracing channel to obtain a second insertion variation tracing group; the second insertion variation tracing group is correlated and analyzed based on the aforementioned heterogeneous mechanical impact scenario group to obtain an insertion variation mechanical impact correlation group; the second insertion variation detection group, the second insertion variation tracing group, and the insertion variation mechanical impact correlation group are correlated and mapped to generate the second insertion detection map.

[0071] Furthermore, the third detection module 15 is used to perform the following method:

[0072] The semiconductor model is subjected to insertion performance anomaly detection based on the thermal shock heterogeneous scenario group to obtain a third insertion anomaly detection group; the third insertion anomaly detection group is traced for anomalies based on the insertion performance anomaly tracing channel to obtain a third insertion anomaly tracing group; the third insertion anomaly tracing group is correlated and analyzed based on the thermal shock heterogeneous scenario group to obtain an anomaly thermal shock correlation group; the third insertion anomaly detection group, the third insertion anomaly tracing group, and the anomaly thermal shock correlation group are correlated and mapped to generate the third insertion detection map.

[0073] Furthermore, the retrieval module 11 is used to perform the following method:

[0074] Obtain the application record library of the semiconductor device; clean the application record library to obtain the application record set of the device.

[0075] Furthermore, the map building module 16 is used to perform the following methods:

[0076] Adaptive maintenance management of the semiconductor device is performed based on the fourth patch detection map.

[0077] It should be noted that the order of the embodiments described above is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. Furthermore, the above description focuses on specific embodiments of this specification. The processes depicted in the accompanying drawings do not necessarily require a specific or sequential order to achieve the desired results. In some implementations, multitasking and parallel processing are possible or may be advantageous.

[0078] The above description is only a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0079] This specification and accompanying drawings are merely illustrative examples of this application and are intended to cover any and all modifications, variations, combinations, or equivalents within the scope of this application. Clearly, those skilled in the art can make various alterations and modifications to this application without departing from its scope. Therefore, if such modifications and modifications fall within the scope of this application and its equivalents, this application intends to include such modifications and modifications.

Claims

1. A method of detecting insertion of a semiconductor device, characterized by, The method comprises: application record retrieval is performed on the semiconductor device to obtain a device application record set; multi-element detection scene optimization is performed according to the device application record set to construct a temperature and humidity heterogeneous scene group, a mechanical impact heterogeneous scene group and a thermal impact heterogeneous scene group; a plug-in performance anomaly tracing channel is built, and plug-in temperature and humidity anomaly detection is performed on the semiconductor device based on the plug-in performance anomaly tracing channel and the temperature and humidity heterogeneous scene group to obtain a plug-in detection first graph; plug-in mechanical anomaly detection is performed on the semiconductor device according to the mechanical impact heterogeneous scene group based on the plug-in performance anomaly tracing channel to obtain a plug-in detection second graph; plug-in thermal impact anomaly detection is performed on the semiconductor device according to the thermal impact heterogeneous scene group based on the plug-in performance anomaly tracing channel to obtain a plug-in detection third graph; a plug-in detection fourth graph is established according to the plug-in detection first graph, the plug-in detection second graph and the plug-in detection third graph; for temperature and humidity characteristics, trigger degree calculation and coupling degree evaluation are performed on each temperature and humidity combination condition in combination with the running state of the device under different humidity and temperature intervals, and a feature combination that has a significant impact on plug-in performance is screened out through a perturbation optimization method to form the temperature and humidity heterogeneous scene group; for mechanical impact characteristics, clustering analysis and abnormal distribution detection are performed on record samples of different impact strength, impact frequency and action direction to form a mechanical impact heterogeneous scene group that can reflect multiple mechanical stress conditions; for thermal impact characteristics, comprehensive optimization of thermal cycle amplitude and rate is performed in combination with record samples of the device in the rapid temperature rise and fall cycle process to generate a thermal impact heterogeneous scene group that can cover multiple temperature mutation conditions.

2. The method of claim 1, wherein the semiconductor device is a semiconductor memory device. Multi-element detection scene optimization according to the device application record set comprises: application scene temperature and humidity characteristic identification is performed on the device application record set to obtain a first temperature and humidity characteristic group; trigger degree calculation is performed on each application scene temperature and humidity characteristic in the first temperature and humidity characteristic group based on the device application record set to obtain a temperature and humidity trigger degree set; the first temperature and humidity characteristic group is optimized according to a predetermined temperature and humidity trigger degree based on the temperature and humidity trigger degree set to obtain a second temperature and humidity characteristic group; two-by-two coupling degree evaluation is performed on the second temperature and humidity characteristic group to obtain a temperature and humidity coupling degree set; the second temperature and humidity characteristic group is subjected to perturbation optimization according to the temperature and humidity coupling degree set to generate the temperature and humidity heterogeneous scene group.

3. The method of claim 1, wherein the semiconductor device is a semiconductor memory device. Building a plug-in performance anomaly tracing channel comprises: interconnection of the same type features is performed on the semiconductor device to obtain an interconnection device group, and a plug-in performance anomaly event set is loaded according to the interconnection device group; accident tree training is performed according to the plug-in performance anomaly event set to obtain a plug-in anomaly accident tree model; perturbation injection is performed according to the plug-in performance anomaly event set to obtain a plug-in anomaly event perturbation set; the plug-in anomaly accident tree model is tested according to the plug-in anomaly event perturbation set to obtain a model test loss data set; attention reinforcement is performed on the plug-in anomaly event perturbation set according to the model test loss data set to obtain an anomaly perturbation reinforcement graph; According to the anomaly disturbance reinforcement map, the plug-in anomaly fault tree model is reinforced to generate a plug-in performance anomaly tracing channel.

4. The method of claim 1, wherein the semiconductor device is a semiconductor memory device. Based on the plug-in performance anomaly tracing channel and the temperature and humidity heterogeneous scene group, plug-in temperature and humidity anomaly detection is performed on the semiconductor device to obtain a plug-in detection first map, including: According to the semiconductor device, a three-dimensional model is established to obtain a semiconductor model; According to the temperature and humidity heterogeneous scene group, plug-in performance anomaly detection is performed on the semiconductor model to obtain a first plug-in anomaly detection group; According to the plug-in performance anomaly tracing channel, anomaly tracing is performed on each plug-in anomaly detection sequence in the first plug-in anomaly detection group to obtain a first plug-in anomaly tracing group; According to the temperature and humidity heterogeneous scene group, the first plug-in anomaly tracing group is associated and analyzed to obtain a plug-in anomaly temperature and humidity association group; The first plug-in anomaly detection group, the first plug-in anomaly tracing group and the plug-in anomaly temperature and humidity association group are associated and mapped to generate the plug-in detection first map.

5. The method of claim 4, wherein the semiconductor device is a semiconductor memory device. According to the temperature and humidity heterogeneous scene group, plug-in performance anomaly detection is performed on the semiconductor model to obtain a first plug-in anomaly detection group, including: According to the temperature and humidity heterogeneous scene group, the Kth temperature and humidity heterogeneous scene is extracted, K being a positive integer; According to the Kth temperature and humidity heterogeneous scene, plug-in performance detection is performed on the semiconductor model to obtain a Kth plug-in performance detection sequence; According to the semiconductor device, plug-in performance qualified sample retrieval is performed to obtain a plug-in performance qualified library; According to the plug-in performance qualified library, centralized trend analysis is performed to determine a plug-in performance benchmark detection sequence; According to the plug-in performance benchmark detection sequence, anomaly detection is performed on the Kth plug-in performance detection sequence to obtain a Kth plug-in anomaly detection sequence, and the Kth plug-in anomaly detection sequence is added to the first plug-in anomaly detection group.

6. The method of claim 1, wherein the semiconductor device is a memory card. Based on the plug-in performance anomaly tracing channel, according to the mechanical impact heterogeneous scene group, plug-in mechanical anomaly detection is performed on the semiconductor device to obtain a plug-in detection second map, including: According to the mechanical impact heterogeneous scene group, plug-in performance anomaly detection is performed on the semiconductor model to obtain a second plug-in anomaly detection group; According to the plug-in performance anomaly tracing channel, anomaly tracing is performed on the second plug-in anomaly detection group to obtain a second plug-in anomaly tracing group; According to the mechanical impact heterogeneous scene group, the second plug-in anomaly tracing group is associated and analyzed to obtain a plug-in anomaly mechanical impact association group; The second plug-in anomaly detection group, the second plug-in anomaly tracing group and the plug-in anomaly mechanical impact association group are associated and mapped to generate the plug-in detection second map.

7. The method of claim 1, wherein the semiconductor device is a semiconductor memory device. Based on the plug-in performance anomaly tracing channel, according to the thermal impact heterogeneous scene group, plug-in thermal impact anomaly detection is performed on the semiconductor device to obtain a plug-in detection third map, including: According to the thermal impact heterogeneous scene group, plug-in performance anomaly detection is performed on the semiconductor model to obtain a third plug-in anomaly detection group; According to the plug-in performance anomaly tracing channel, anomaly tracing is performed on the third plug-in anomaly detection group to obtain a third plug-in anomaly tracing group; According to the thermal impact heterogeneous scene group, the third plug-in anomaly tracing group is associated and analyzed to obtain a plug-in anomaly thermal impact association group; According to the thermal shock heterogeneous scene group, the third plug-in heterogeneous traceability group is associated and analyzed, and a heterogeneous thermal shock associated group is obtained; The third plug-in heterogeneous detection group, the third plug-in heterogeneous traceability group and the heterogeneous thermal shock associated group are associated and mapped, and the plug-in detection third graph is generated.

8. The method for detecting the insertion of a semiconductor device as described in claim 1, characterized in that, An application record retrieval is performed on the semiconductor device, and a device application record set is obtained, including: An application record library of the semiconductor device is obtained; The application record library is cleaned, and the device application record set is obtained.

9. The method of claim 1, wherein the semiconductor device is a semiconductor memory device. According to the plug-in detection fourth graph, adaptive maintenance management of the semiconductor device is performed.

10. A system for detecting insertion of a semiconductor device, characterized by A plug-in detection method of a semiconductor device for implementing any one of claims 1-9, the system comprising: A retrieval module: performing an application record retrieval on a semiconductor device to obtain a device application record set; A scene optimization module: performing multi-element detection scene optimization according to the device application record set, and constructing a temperature and humidity heterogeneous scene group, a mechanical impact heterogeneous scene group and a thermal shock heterogeneous scene group; A first detection module: building a plug-in performance heterogeneous traceability channel, and performing plug-in temperature and humidity heterogeneous detection on the semiconductor device based on the plug-in performance heterogeneous traceability channel and the temperature and humidity heterogeneous scene group, to obtain a plug-in detection first graph; A second detection module: performing plug-in mechanical heterogeneous detection on the semiconductor device based on the plug-in performance heterogeneous traceability channel and the mechanical impact heterogeneous scene group, to obtain a plug-in detection second graph; A third detection module: performing plug-in thermal shock heterogeneous detection on the semiconductor device based on the plug-in performance heterogeneous traceability channel and the thermal shock heterogeneous scene group, to obtain a plug-in detection third graph; A graph establishment module: establishing a plug-in detection fourth graph according to the plug-in detection first graph, the plug-in detection second graph and the plug-in detection third graph.

Images