Optical proximity correction method, electronic device, and storage medium

Abstract

The present disclosure relates to an optical proximity correction method, an electronic device and a storage medium. The method comprises: determining a cutting position of a pattern contour in a first sub-layout of higher priority and a pattern contour in a second sub-layout of lower priority within a predetermined range adjacent to the first sub-layout in sub-layouts divided by an initial layout, to cut each pattern contour into a plurality of first movable line segments and a plurality of first movable points; iteratively offsetting the first movable line segments and the first movable points until the first sub-layout is corrected to a first corrected sub-layout when the final offset is offset by a first offset amount; and offsetting the pattern contour of the second sub-layout based on the cutting position to generate a second corrected sub-layout. The scheme of the present disclosure can significantly improve the discontinuity at the layout boundary.

Description

Technical Field

[0001] The embodiments of this disclosure primarily relate to integrated circuits, and more specifically, to optical proximity correction methods, electronic devices, and computer-readable storage media. Background Technology

[0002] Chip manufacturing typically involves processing a designed circuit diagram into a photomask (also called a mask) pattern. This photomask pattern is then exposed by a photolithography system and projected onto the photoresist on the wafer. A series of chemical and physical reactions then occur to etch the chip. As the circuit dimensions on high-end chips become increasingly smaller, the optical proximity effect generated during the exposure process of the photomask pattern becomes more severe. This causes significant distortion of the lithographic pattern on the wafer, making it impossible to achieve the intended circuit design goals. The production of integrated circuit chips at advanced process nodes typically relies on patterning techniques, the core of which is optical proximity correction (OPC). OPC is widely used in chip manufacturing to reduce the difference between the wafer image and the target pattern.

[0003] In advanced manufacturing processes, the scale of OPC (Optical Processing) is only a few nanometers, while the size of the photomask layout is relatively large. Directly performing global correction on the entire photomask layout would result in an unbearable burden on runtime and storage space. Therefore, in actual OPC processes, the photomask layout is divided into multiple sub-layouts according to certain rules. These sub-layouts are processed through distributed computing on a large number of computers to improve processing efficiency, and the final global OPC result is stitched together from the OPC results of each sub-layout. Therefore, the stitching technology of sub-layout graphics is crucial for the industrial application of OPC. In traditional solutions, discontinuities often occur at the stitching boundaries, thus affecting the correction accuracy. Summary of the Invention

[0004] According to an example embodiment of this disclosure, an optical proximity correction scheme is provided to at least partially overcome the above or other potential drawbacks.

[0005] According to one aspect of this disclosure, an optical proximity correction method is provided. The method includes: determining the cutting positions of graphic contours in a higher-priority first sub-layout and graphic contours within a predetermined range adjacent to the first sub-layout in a lower-priority second sub-layout, from a plurality of sub-layouts divided by an initial layout, to cut each graphic contour into a plurality of first movable line segments and a plurality of first movable points; iteratively offsetting the plurality of first movable line segments and the plurality of first movable points until a final offset of the first offset amount is made to correct the first sub-layout into a first corrected sub-layout.

[0006] In a second aspect of this disclosure, an electronic device is provided. The electronic device includes a processor; and a memory coupled to the processor, the memory having instructions stored therein, the instructions causing the device to perform actions when executed by the processor, the actions including: determining cutting positions of graphic outlines in a higher-priority first sub-layout and graphic outlines within a predetermined range adjacent to the first sub-layout in a lower-priority second sub-layout, from a plurality of sub-layouts divided by an initial layout, to cut each graphic outline into a plurality of first movable line segments and a plurality of first movable points; iteratively offsetting the plurality of first movable line segments and the plurality of first movable points until a final offset by a first offset amount is made to correct the first sub-layout into a first corrected sub-layout; and offsetting the graphic outlines of the second sub-layout based on the cutting positions to generate a second corrected sub-layout.

[0007] In some embodiments, the graphic contours within a predetermined range in the second sub-layout are cut based on the cutting position and offset by a first offset, and the remaining graphic contours in the second sub-layout are cut based on the cutting position and iteratively offset to generate a second corrected sub-layout.

[0008] In some embodiments, the method further includes stitching together the first and second correction sub-patterns to generate a correction pattern.

[0009] In some embodiments, cutting each graphic contour into a plurality of first movable line segments and a plurality of first movable points includes: cutting the graphic contour in the corner region of the graphic into a plurality of first movable points; and cutting the graphic contour in the non-corner region of the graphic into a plurality of first movable line segments.

[0010] In some embodiments, iteratively offsetting a plurality of first movable line segments and a plurality of first movable points until a first offset is finally offset to correct the first sub-layout into a first corrected sub-layout includes: determining initial offsets for the plurality of first movable line segments and a plurality of first movable points; moving the first movable line segments and the plurality of first movable points based on the initial offsets; and correcting the corresponding first sub-layout into a first corrected sub-layout in response to the iteration satisfying a predetermined condition, wherein the final offset corresponding to satisfying the predetermined condition is the first offset.

[0011] In some embodiments, determining the initial offset of a plurality of first movable line segments and a plurality of first movable points includes: inputting portions of the first sub-layout and the second sub-layout located within a predetermined range into a photolithography simulation model to generate a light intensity distribution map; determining the corresponding light intensity signals at the plurality of first movable line segments and the plurality of first movable points; and determining the initial offset of the plurality of first movable line segments and the plurality of first movable points based on a comparison of the light intensity signals with an exposure threshold.

[0012] In some embodiments, determining the corresponding light intensity signals at a plurality of first movable line segments and a plurality of first movable points includes: setting evaluation points at each of the first movable line segments and first movable points; and determining the light intensity signals at each evaluation point as the corresponding light intensity signals at each of the first movable line segments and first movable points.

[0013] In some embodiments, iteratively offsetting a plurality of first movable line segments and a plurality of first movable points includes: moving a first movable point in any direction in the plane of the initial layout graphic; and moving a first movable line segment in the plane of the initial layout graphic along the normal direction of the line segment.

[0014] In some embodiments, the cutting position and the first offset are stored in a temporary storage area.

[0015] In some embodiments, cutting and iteratively offsetting the remaining graphic outline in the second sub-layout based on the cutting position includes: obtaining the cutting position from a temporary storage area; cutting the remaining graphic outline into a plurality of second movable line segments and a plurality of second movable points, starting from the cutting position located within a predetermined range of the second sub-layout and close to the boundary of the remaining portion of the second sub-layout; and iteratively offsetting the plurality of second movable line segments and the plurality of second movable points to generate a portion of the second corrected sub-layout.

[0016] In some embodiments, cutting a graphic outline within a predetermined range in the second sub-layout based on a cutting position and offsetting it with a first offset includes: obtaining a cutting position from a temporary storage area; cutting a portion of the graphic outline within the predetermined range based on the cutting position of a portion of the graphic outline contained in the cutting position to generate corresponding movable line segments and movable points; and offsetting the corresponding movable line segments and movable points with the first offset to generate another portion of the second corrected sub-layout.

[0017] In some embodiments, the method further includes: before separating the first correction sub-pattern from the adjacent second correction sub-pattern along the boundary, redetermining the intersection point of the graphic profile penetrating the boundary with the boundary; and modifying the original intersection point of the graphic profile penetrating the boundary with the boundary to the redetermined intersection point.

[0018] In some embodiments, redetermining the intersection of the graphic contour that runs through the boundary with the boundary includes: determining whether the original intersection point is located on a grid point; in response to determining that the original intersection point is not located on a grid point, taking one of the two grid points on the boundary adjacent to the original intersection point as the redetermined intersection point; and in response to determining that the original intersection point is located on a grid point, keeping the position of the original intersection point unchanged.

[0019] In some embodiments, cutting each graphic contour into a plurality of first movable line segments and a plurality of first movable points includes: cutting a plurality of first movable line segments at a first interval based on the position of the graphic contour, and cutting a first movable point at a second interval, wherein the first interval is greater than the second interval.

[0020] In a third aspect of this disclosure, a computer-readable storage medium is provided that stores machine-executable instructions thereon, which, when executed by a processor, implement the method according to a first aspect of this disclosure.

[0021] As will be understood from the following description, the technical solutions of the embodiments of this disclosure can significantly improve or eliminate discontinuities at the boundaries of a map.

[0022] The summary section is provided to present the chosen concepts in a simplified form, which will be further described in the detailed description below. The summary section is not intended to identify key or principal features of this disclosure, nor is it intended to limit the scope of this disclosure. Attached Figure Description

[0023] Figure 1 A schematic diagram of an example environment in which embodiments of the present disclosure can be implemented is shown;

[0024] Figure 2 A flowchart of an optical proximity correction method according to some embodiments of the present disclosure is shown;

[0025] Figure 3 A schematic diagram illustrating the cutting of the graphic outline of a sub-layout according to some embodiments of the present disclosure is shown;

[0026] Figure 4 Examples of embodiments according to this disclosure are shown. Figure 3 The diagram shows the correction result obtained after optical proximity correction of the sub-pattern shown.

[0027] Figure 5 A schematic diagram illustrating the cutting of a sub-layout graphic according to some embodiments of the present disclosure is shown;

[0028] Figure 6 A schematic flowchart of optical proximity correction using Curvilinear OPC according to some embodiments of the present disclosure is shown;

[0029] Figure 7 Schematic diagrams illustrating optical proximity correction and layout stitching using Curvilinear OPC according to some embodiments of the present disclosure are shown.

[0030] Figure 8A schematic diagram illustrating boundary smoothing of spliced ​​sub-layouts according to some embodiments of the present disclosure is shown;

[0031] Figure 9 A schematic diagram showing the layout stitching effect according to some embodiments of the present disclosure is shown;

[0032] Figure 10 A block diagram of a computing device capable of implementing several embodiments of the present disclosure is shown.

[0033] In the various figures, the same or corresponding reference numerals indicate the same or corresponding parts. Detailed Implementation

[0034] The principles of this disclosure will now be described with reference to various exemplary embodiments shown in the accompanying drawings. It should be understood that these embodiments are described merely to enable those skilled in the art to better understand and further implement this disclosure, and are not intended to limit the scope of this disclosure in any way. It should be noted that similar or identical reference numerals may be used in the figures where feasible, and similar or identical reference numerals may denote similar or identical functions. Those skilled in the art will readily recognize that alternative embodiments of the structures and methods described herein may be employed without departing from the principles of the embodiments of this disclosure described herein.

[0035] The term "comprising" and its variations as used herein signify open inclusion, i.e., "including but not limited to". Unless otherwise stated, the term "or" means "and / or". The term "based on" means "at least partially based on". The terms "one example embodiment" and "one embodiment" mean "at least one example embodiment". The term "another embodiment" means "at least one additional embodiment". The terms "first", "second", etc., may refer to different or the same objects.

[0036] As mentioned earlier, due to the increasingly smaller circuit pattern size on high-end chips, the optical proximity effect generated during the photomask exposure process is becoming more and more severe. This causes serious distortion of the photolithography pattern on the wafer, making it impossible to achieve the expected circuit design goals. Resolution enhancement techniques are a set of technologies proposed to address optical proximity effects, aiming to expand the process window of chip manufacturing at a lower cost and ensure chip manufacturing yield. These techniques typically include phase-shift mask (PSM), off-axis illumination (OAI), optical proximity effect correction, and source mask optimization (SMO).

[0037] In traditional methods, correcting a photomask layout requires dividing the graphic into movable line segments according to specific rules and setting evaluation points on these segments to control their movement. Since the OPC problem itself is a complex, nonlinear problem, an analytical solution cannot be directly obtained; therefore, OPC solvers are typically designed using iterative optimization methods.

[0038] In recent years, in addition to traditional OPC technology based on movable line segments, reverse lithography (ILT) technology has also become a research hotspot. ILT technology pixelates the mask layout and solves the corrected layout through global optimization, which can achieve high OPC accuracy, but its computation time and storage cost are high.

[0039] As mentioned earlier, the initial layout is typically divided into multiple sub-layouts, and OPC correction is performed separately through parallel computation. Since the boundary correction results of each sub-layout are influenced by adjacent sub-layouts, and the correction results at the boundaries of adjacent sub-layouts often differ, this leads to inconsistencies in the correction results at the boundaries of different sub-layouts, resulting in discontinuities during splicing. The main reasons for this discontinuity are: 1) The corrected layout graphics obtained by the sub-layouts on both sides of the boundary are not completely consistent. This is due to the inconsistency in the graphic environment (how many graphics are around, their shapes, their distribution, etc.) seen by the two sub-layouts during correction; the optical proximity effect is quite sensitive to the graphic environment. 2) The current layout graphics require meshing for OPC and subsequent processing, so there is a minimum mesh resolution. However, the intersection point of the line segment at the edge of the graphic with the sub-layout boundary may not be at a mesh point. Therefore, different sub-layouts may replace this intersection point with their own different nearest mesh points, resulting in the same line segment having two intersection points with the layout boundary, causing discontinuities.

[0040] Curvilinear OPC (also known as Curve OPC) is an improved version of traditional OPC technology. It represents the boundary of the photomask layout as a series of movable points, which can effectively alleviate the smoothing effect at the corners of the layout, while the computational cost is much lower than that of ILT technology.

[0041] Compared to ILT technology, existing curvilinear OPC technology improves computational efficiency while mitigating the corner smoothing effect in layouts. Furthermore, although there are relatively mature solutions to the layout stitching problem in traditional OPC technology, curvilinear OPC technology still has shortcomings in layout stitching: the intersection point of arbitrary angle edge segments of the curvilinear layout with the stitching boundary may deviate from the minimum precision grid point, resulting in discontinuities in edge segments at the stitching boundary.

[0042] In view of this, this disclosure provides an improved solution.

[0043] Embodiments of this disclosure provide an improved optical proximity correction method. The method includes: determining cutting positions for graphic contours in a higher-priority first sub-layout and graphic contours within a predetermined range adjacent to the first sub-layout in a lower-priority second sub-layout, from a plurality of sub-layouts divided by an initial layout, to cut each graphic contour into a plurality of first movable line segments and a plurality of first movable points; iteratively offsetting the plurality of first movable line segments and the plurality of first movable points until a final offset by a first offset amount is achieved to correct the first sub-layout into a first corrected sub-layout; and offsetting the graphic contours of the second sub-layout based on the cutting positions to generate a second corrected sub-layout.

[0044] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0045] Figure 1 A schematic diagram of an example environment 100 that can be implemented according to embodiments of the present disclosure is shown. Figure 1 As shown, the example environment 100 includes a computing device 110 and a client 120.

[0046] In some embodiments, the computing device 110 can interact with the client 120. For example, the computing device 110 can receive input messages from the client 120 and output feedback messages to the client 120. In some embodiments, the input messages from the client 120 can be design layout data. The computing device 110 can perform corresponding mathematical operations on the design layout data and output the corresponding operation results to the client 120.

[0047] In some embodiments, the computing device 110 may include, but is not limited to, a personal computer, a server computer, a handheld or laptop device, a mobile device (such as a mobile phone, a personal digital assistant PDA, a media player, etc.), a consumer electronics product, a minicomputer, a mainframe computer, cloud computing resources, etc.

[0048] It should be understood that the description of the structure and functionality of example environment 100 for illustrative purposes only is not intended to limit the scope of the subject matter described herein. The subject matter described herein may be implemented in different structures and / or functionalities. This environment is merely illustrative and is not intended to limit the application environment of the embodiments of this disclosure.

[0049] To more clearly explain the principles of this disclosure, reference will be made below. Figure 2 Let's describe it in more detail.

[0050] Figure 2 A flowchart of an optical proximity correction method 200 according to some embodiments of the present disclosure is shown.

[0051] At box 202, the cutting positions of the graphic outlines in the first sub-landscape with higher priority and the graphic outlines in the second sub-landscape with lower priority within a predetermined range adjacent to the first sub-landscape are determined in the multiple sub-landscapes divided by the initial layout, so as to cut each graphic outline into multiple first movable line segments and multiple first movable points.

[0052] Typically, initial layout (circuit design layout) graphics can be obtained from wafer fabrication plants. It should be understood that this disclosure is not restrictive, and the initial layout can also come from other sources. The initial layout graphics are the target of OPC optimization. The initial condition for OPC iteration is the circuit design layout, which is then modified (or corrected) to obtain a wafer-level pattern that closely approximates the circuit design layout after simulation using a photolithography model.

[0053] As mentioned earlier, directly modifying the entire layout using OPC is not only time-consuming but also consumes a large amount of storage space, making it difficult to apply directly to industrial production. Therefore, the initial layout is usually divided into multiple sub-layouts. In some embodiments, the initial layout is divided into multiple sub-layouts, and each sub-layout can be assigned a corresponding priority. The number of priorities can be set according to actual needs, such as two, three, four, or even more. This disclosure does not limit this. Typically, two adjacent sub-layouts are set to have different priorities.

[0054] In the actual correction process, for example, curvilinear OPC can be used to correct in order of priority. If the current sub-layout has a higher priority, the curvilinear OPC solver can be called directly for correction, and the correction results are retained; if the current sub-layout has a lower priority, the correction results of the higher priority sub-layouts are loaded first as a basis, and the remaining graphics of the current sub-layout are corrected on this basis, which will be further described later.

[0055] In some embodiments, multiple sub-layouts of the same priority are computed by different computing cores, and the same computing core is used to compute higher priority sub-layouts and lower priority sub-layouts respectively.

[0056] In some embodiments, low-priority sub-layouts are corrected only after all high-priority sub-layouts have been corrected. After all sub-layouts have been corrected, the correction results of each sub-layout are spliced ​​together to obtain the final OPC correction result of the target layout.

[0057] In some embodiments, if the current sub-layout has a higher priority, the graphics within the sub-layout can be directly cut according to the cutting rules for movable points and movable line segments. The cutting rules can be, for example, general rules. In some embodiments, the cutting position information can be saved to a temporary storage area.

[0058] In some embodiments, a plurality of first movable line segments may be cut at a first interval based on the position of the graphic outline, and a first movable point may be cut at a second interval, wherein the first interval is greater than the second interval.

[0059] In some embodiments, setting priorities aims to ensure continuity in layout stitching. The principle is to first correct a portion of the high-priority sub-layouts; this result serves as a reference for correcting lower-priority sub-layouts. Lower-priority sub-layouts will be corrected based on the existing results of the high-priority sub-layouts without altering the high-priority results. This ensures that the lower-priority results fit seamlessly into the higher-priority results. Conversely, if priorities are not differentiated and corrections are made simultaneously, the correction results at the high-low priority boundaries may differ significantly, potentially leading to stitching failure.

[0060] This high-priority-based cutting strategy in the embodiments of this disclosure ensures the consistency of cutting positions between different sub-plots, thereby providing a guarantee for subsequent placement of evaluation points and correction of plot offsets. For many long line segments spanning multiple sub-plots, the high-priority sub-plot is cut using the beginning and end of the line segment seen from the high-priority sub-plot as the cutting starting point. This cutting result is then pasted onto the low-priority sub-plot. Therefore, the cutting starting point of the low-priority sub-plot is the pasted high-priority cutting result, thus avoiding conflicts between the low-priority and high-priority cutting positions and maintaining consistency.

[0061] In some embodiments, the graphic contours can be divided into a plurality of first movable line segments and a plurality of first movable points in the following manner: the graphic contours in the corner regions of the graphic are divided into a plurality of first movable points; and the graphic contours in the non-corner regions of the graphic are divided into a plurality of first movable line segments. Movable points can move in any direction within the plane of the initial layout graphic; while movable line segments can move along the normal direction of the line segment within the plane of the initial layout graphic.

[0062] The following reference Figure 3 , Figure 3 A schematic diagram illustrating the cutting of the graphic outline of a sub-layout according to some embodiments of the present disclosure is shown. Specifically, Figure 3 A schematic diagram of the layout splicing is shown, illustrating the cutting positions of movable points and movable line segments.

[0063] like Figure 3As shown, the initial layout is divided into two adjacent sub-layouts: the first sub-layout 302 and the second sub-layout 304. The first sub-layout 302 has a higher priority than the second sub-layout 304. The small black squares (displayed as black dots on the graphic outline) represent the cutting positions of movable points and movable line segments. Cutting of movable points begins at the corner 316 of the target graphic, with a short cutting interval; while cutting of movable line segments is usually located on the longer side of the target graphic away from the corner, with a longer cutting interval. Furthermore, it should be noted that all these black dots in the diagram can be called cutting points. Additionally, the black dots at the corners (cutting points) are also movable points, which can move two-dimensionally within a plane; the two endpoints of a line segment (e.g., line segment 322) (also cutting points) need to move along the vertical direction of the line segment.

[0064] The cutting information of these areas of the first sub-pattern 302, together with a portion of the second sub-pattern 304, can be temporarily stored in a temporary storage area after the first sub-pattern 302 has been cut or corrected, for reference when cutting the second sub-pattern 304 subsequently. This will be described further later.

[0065] Each sub-plot contains multiple graphics, in which... Figure 3 The image shows eight pattern blocks 308: six dark pattern blocks and two light pattern blocks, each containing numerous graphics. The dark pattern blocks 308 indicate that a cut was made during the outline cutting process of the first sub-pattern 302. In other words, when determining the cutting position of the first sub-pattern 302 or when cutting was performed, some areas extended into the range of the second sub-pattern 304. Figure 3 The diagram also shows a long, narrow rectangular graphic 306. In some embodiments of this disclosure, during the OPC process for a higher-priority sub-layout, OPC correction is simultaneously performed on lower-priority sub-layouts within a predetermined radius around it. That is, when correcting a high-priority sub-layout, some graphics of the lower-priority sub-layouts are additionally corrected, so the lower-priority sub-layouts only need to have their remaining graphics not yet OPC corrected. This ensures the accuracy of the OPC correction result for the first sub-layout 302 and improves computational efficiency.

[0066] As mentioned above, Figure 3The pattern block 308 shown includes a large number of graphics, with the enlarged view of the small rectangle 310 as indicated by the dashed arrow 320, including multiple graphics, specifically target graphics. The black dots on the outlines of these target graphics are cutting points 314, which cut the outlines of the target graphics into multiple movable line segments and multiple movable points, such as movable line segment 322 (which can be called the first movable line segment), and movable points at corners (i.e., cutting points 314 at corners, which can be called the first movable points). Each sub-pattern has a sub-pattern boundary 318. Figure 3 The target graphic 312 is also shown in the image.

[0067] In some embodiments, referencing higher priority sub-layouts for lower priority sub-layouts involves, in short, directly pasting the already corrected graphic onto the lower priority sub-layout to obtain a partially corrected lower priority sub-layout. Then, the remaining graphics in the lower priority sub-layout can be corrected without altering the already corrected graphic result.

[0068] At box 204, multiple first movable line segments and multiple first movable points are iteratively offset until the first sub-layout is corrected to the first corrected sub-layout when the first offset is finally offset.

[0069] In some embodiments, offsets corresponding to a plurality of first movable line segments and a plurality of first movable points can be determined; initial offsets of the plurality of first movable line segments and a plurality of first movable points can be determined; the first movable line segments and a plurality of first movable points can be moved based on the initial offsets; and if the iteration satisfies predetermined conditions, the corresponding first sub-layout is corrected to a first corrected sub-layout, wherein the final offset corresponding to satisfying the predetermined conditions is the first offset. The predetermined conditions can be general conditions used to determine whether the results after iteration meet predetermined requirements, such as the difference between the offsets of two adjacent iterations being less than a predetermined threshold, the cost function being lower than a predetermined threshold, etc., which are not described in detail in this disclosure. If the predetermined conditions are met, the deviation between the simulated graphic and the target layout graphic is less than a predetermined threshold.

[0070] It should be noted that, while iteratively offsetting multiple first movable line segments and multiple first movable points to generate the first corrected sub-layout, it also generates the corrected results for the graphic contours within a predetermined range adjacent to the first sub-layout in the lower-priority second sub-layout. As is known in the industry, during the iterative offset process, the offset amount for the graphic contours within the predetermined range is the same as the offset amount for the higher-priority sub-layout. Therefore, this offset amount can be used for the subsequent correction of the lower-priority sub-layout.

[0071] In some embodiments, the initial offsets corresponding to a plurality of first movable line segments and a plurality of first movable points can be determined by: inputting portions of the first sub-layout and the second sub-layout within a predetermined range into a photolithography simulation model to generate a light intensity distribution map; determining the corresponding light intensity signals at the plurality of first movable line segments and a plurality of first movable points; and determining the initial offsets corresponding to the plurality of first movable line segments and a plurality of first movable points based on a comparison of the light intensity signals with an exposure threshold.

[0072] In some embodiments, the module in OPC software used to calculate the line segment offset based on the light intensity signal at the evaluation point is referred to as the OPC solver. Since the OPC problem itself is a complex nonlinear problem and cannot be solved analytically directly, OPC solvers are typically designed using iterative optimization methods.

[0073] In some embodiments, after the movable points and movable line segments of each sub-layout are cut, evaluation points can be placed on these points and line segments respectively. The purpose of placing evaluation points is to calculate the offset of the evaluation points using an OPC solver, such as a curvilinear OPC solver, based on the light intensity signal at the evaluation point and the exposure threshold, as a reference for the offset of the movable points and movable line segments. For example, the corresponding light intensity signals at multiple first movable line segments and multiple first movable points can be determined by setting evaluation points at each first movable line segment and first movable point respectively; and determining the light intensity signal at each evaluation point as the corresponding light intensity signal at each first movable line segment and first movable point respectively. In some embodiments, for movable points, evaluation points are set on the movable points; for movable line segments, evaluation points can be set at the midpoint of the line segment. This disclosure is not limited to this and can be varied according to actual needs.

[0074] In some embodiments, the final offsets of multiple first movable line segments and multiple first movable points are stored in a temporary storage area for reference and use by subsequent low-priority sub-layouts.

[0075] For the high-priority first sub-layout 302, portions of the graphics of its internal and surrounding low-priority sub-layouts can be input into the photolithography simulation model to generate a light intensity distribution map. An OPC solver, such as the curvilinear OPC solver, can calculate the offsets of movable line segments and movable points in the first sub-layout 302 and its boundary regions based on this map, and save this offset information to temporary storage space for subsequent OPC correction of the lower-priority second sub-layout 304. This will be further described later.

[0076] Back Figure 2 At box 206, the graphic outline of the second sub-layout is offset based on the cutting position to generate the second corrected sub-layout.

[0077] In some embodiments, the graphic outline of the second sub-layout 304 can be cut based on the cutting position determined by the processing of the high-priority first sub-layout 302. This high-priority-based cutting method ensures that movable points and movable line segments of different sub-layouts can be completely aligned during splicing, avoiding conflicts caused by inconsistent cutting positions. After cutting the graphic outline of the second sub-layout 304, corresponding offset processing is performed to generate a corrected second sub-layout.

[0078] In some embodiments, offsetting the graphic contour of the second sub-layout based on the cutting position to generate a second corrected sub-layout may include: cutting the graphic contour within a predetermined range in the second sub-layout based on the cutting position and offsetting it by a first offset amount. This allows obtaining the same correction result as the graphic contour within a predetermined range adjacent to the first sub-layout in the lower-priority second sub-layout generated during the correction process of the high-priority first sub-layout 302; and cutting and iteratively offsetting the remaining graphic contour in the second sub-layout based on the cutting position. This generates the second corrected sub-layout. This method ensures that no discontinuities occur during the splicing of the two sub-layouts. In short, the graphic contours at the splicing position of the two sub-layouts of different priorities have already been uniformly corrected during the correction process of the high-priority sub-layout. The subsequent correction process of the low-priority sub-layout directly utilizes the correction result of the low-priority portion of the graphic contour, thereby eliminating or substantially eliminating discontinuities.

[0079] In some embodiments, when the second sub-layout 304 is cut using movable points and movable line segments, information about the parts already cut in the first sub-layout 302 is imported, i.e., the position information of those parts belonging to the second sub-layout 304 but already cut in the first sub-layout 302. The second sub-layout 304 will then cut the remaining target graphic based on these existing cutting positions, instead of starting the cutting process again from the original target graphic.

[0080] In other words, if the current sub-landscape has a low priority, the cutting position information of the high-priority sub-landscape is first imported from the temporary storage area. Based on this, the remaining graphics within the current sub-landscape are cut into movable points and movable line segments according to the established cutting rules. This will be described in more detail later.

[0081] Because for many long line segments that span multiple sub-plots, each sub-plot can only see a part of the line segment, the movable points on that line segment / the starting point for cutting the line segment will be different. This is because, theoretically, the starting point for cutting is the beginning and end points of the long line segment, rather than a part seen by each sub-plot itself.

[0082] Therefore, this high-priority-based cutting method ensures that movable points and movable line segments of different sub-maps can be completely aligned during splicing, avoiding conflicts caused by inconsistent cutting positions. See below. Figure 5 This will be described further.

[0083] See Figure 5 , Figure 5 A schematic diagram illustrating the cutting of a sub-layout graphic according to some embodiments of the present disclosure is shown. For example... Figure 5 As shown, a contour line 502 is illustrated, with three cutting points P1, P2, and P3. During the OPC correction of the first sub-layout 302, the portion of the second sub-layout 304 located between boundary 318 and line L1 has already undergone OPC correction. When cutting the portion of contour line 502 located in the second sub-layout 304, the position of cutting point P3 is referenced. For example, cutting is performed starting from cutting point P3. This effectively provides some initial cutting points. Generally, movable points and movable line segments can be cut from these initial cutting points according to certain rules (such as length). In this way, it can be ensured that the same contour line remains continuous after subsequent offsetting and splicing processes.

[0084] In some embodiments, the cutting positions of the first sub-layout 302 and the final offsets of a plurality of first movable line segments and a plurality of first movable points are stored in a temporary storage area.

[0085] In some embodiments, cutting the graphic outline of the remaining portion of the second sub-layout into a plurality of second movable line segments and a plurality of second movable points based on the cutting position may include: obtaining the cutting position from a temporary storage area; and, based on the cutting position, starting from a cutting position located within a predetermined range of the second sub-layout and close to the boundary of the remaining portion of the second sub-layout, cutting the graphic outline of the remaining portion into a plurality of second movable line segments and a plurality of second movable points; and iteratively offsetting the plurality of second movable line segments and the plurality of second movable points to generate a portion of the second corrected sub-layout.

[0086] In some embodiments, when performing OPC on a high-priority sub-layout, the sub-layout boundary is expanded by a certain distance for correction, meaning that some graphics in the low-priority sub-layout are corrected. Therefore, when performing OPC on a low-priority sub-layout, points and line segments processed during the high-priority sub-layout OPC that belong to the low-priority sub-layout are offset using pre-loaded offsets. For example, for the lower-priority second sub-layout 304, offset information within the boundary range of the first sub-layout 302 can be pre-loaded from temporary storage space. Subsequently, the graphics in the second sub-layout 304 are input into the lithography simulation model to generate a light intensity distribution map. The curvilinear OPC solver calculates the offsets of movable line segments and movable points within the region of the second sub-layout 304 based on this map, while movable points and movable line segments that have already been calculated in the first sub-layout 302 directly use the pre-loaded offsets. In this way, the graphic offset of the low-priority sub-plot boundary area is forced to be consistent with the correction result of the high-priority sub-plot, thereby ensuring that the graphics at the plot boundary can be stitched together more continuously.

[0087] In some embodiments, the cutting position can be obtained from a temporary storage area; and based on the cutting position of a portion of the graphic contour within a predetermined range of the second sub-layout contained in the cutting position, the portion of the graphic contour within the predetermined range is cut to generate corresponding movable line segments and movable points; and the corresponding movable line segments and movable points are offset by a first offset to generate another part of the second corrected sub-layout.

[0088] In short, during the OPC correction process of the high-priority sub-layout, the corrected layout of the adjacent low-priority sub-layout has been obtained. Its corresponding cutting information and offset are stored in the temporary storage area for use when correcting the low-priority sub-layout later. If the corresponding offset and cutting position are known, a part of the corrected low-priority sub-layout can be directly copied and generated.

[0089] In other words, the initial layout obtained by the computational core of the low-priority sub-layout does not contain any cutting information. Therefore, the cutting information of the low-priority part that was corrected along with the high-priority part must be loaded first to generate the same movable line segments and movable points. Then, the offset is loaded to obtain the corrected low-priority sub-layout part that has already been obtained on the computational core of the high-priority sub-layout.

[0090] In some embodiments, the method further includes stitching together the corresponding first correction sub-layout and second correction sub-layout to generate a correction layout. In some embodiments, for sub-layouts comprising multiple priorities, stitching together the corresponding first correction sub-layout and second correction sub-layout may generate at least a partial correction layout.

[0091] In some embodiments, the first and second correction sub-patterns can be spliced ​​together using conventional splicing methods, which will not be described in detail here.

[0092] The following reference Figure 4 Describe it. Figure 4 Examples of embodiments according to this disclosure are shown. Figure 3 The diagram shows the correction result obtained after optical proximity correction of the sub-pattern shown.

[0093] Figure 4 and Figure 3 The difference lies in, for Figure 3 The two sub-patterns shown have undergone OPC correction, resulting in two corrected sub-patterns: the first corrected sub-pattern 402 and the second corrected sub-pattern 404. Pattern block 408 represents the pattern after OPC correction during the contour cutting process of the first sub-pattern 302. The elongated rectangular graphic 406 is the elongated rectangular graphic obtained after correction of the elongated rectangular graphic 306. An enlarged view of the small rectangle 410, as indicated by the dashed arrow 420, includes multiple corrected graphics. Figure 4 The target graphic 312 and the corrected graphic 412 are also shown.

[0094] Optical Proximity Correction (OPC) is performed on a per-sub-layout basis, and the final result after OPC for each sub-layout is the graphic within its boundary. That is, although each sub-layout undergoes additional correction during OPC, the final result preserves the graphic within the boundary after breaking at the boundary, and the final result is obtained by stitching together the graphics within the boundaries of all sub-layouts. This is a common method in distributed computing, which improves computational efficiency.

[0095] pass Figure 4 As can be seen, the splicing positions of the two sub-plots are continuous. Therefore, the OPC processing procedure shown in the aforementioned embodiment can largely avoid discontinuities in the splicing.

[0096] The following is combined with Figure 6 Another embodiment of the optical proximity correction method of this disclosure is described. Figure 6 A schematic flowchart of a method 600 for optical proximity correction using Curvilinear OPC according to some embodiments of the present disclosure is shown. Figure 6 The document clearly defines the priority handling strategy for sub-maps.

[0097] Import the initial layout graphic at box 602.

[0098] At frame 604, the graphic is divided into a series of sub-pages according to predetermined rules. For example, it can be divided according to general rules.

[0099] At box 606, set the priority for the sub-plots. As mentioned earlier, you can set the priority category as needed.

[0100] At box 608, determine whether the priority of the current sub-plot is high or low. If the priority is high, proceed to box 612; otherwise, proceed to box 610.

[0101] At box 612, curvilinear OPC is invoked for layout correction. That is, for high-priority sub-layouts, OPC correction can be performed directly.

[0102] At box 614, store the OPC results for the region adjacent to the low-priority sub-layout. For example, store the offset.

[0103] At box 610, the OPC results of the adjacent high-priority sub-layout are loaded as a reference. Specifically, the results of the correction of the surrounding low-priority sub-layouts during the OPC process of the high-priority sub-layout can be directly referenced. That is, the parts of the low-priority sub-layouts that have already been corrected do not need to be corrected again by OPC, and the existing results can be directly used as the correction results of the corresponding sub-layouts.

[0104] At box 616, curvilinear OPC is invoked to perform layout correction. This correction applies to the portions of the sub-layout that were not addressed during the correction of higher-priority sub-layouts. In other words, the remaining lower-priority sub-layouts are corrected.

[0105] At frame 618, the various sub-maps are stitched together to complete the overall map correction.

[0106] It should be noted that in some embodiments of this disclosure, the movable points and the endpoints of the line segments, as well as the two adjacent movable points, are connected by line segments. This disclosure is not limited to this and the connection can also be made by curves.

[0107] The optical proximity correction method according to embodiments of this disclosure is further referred to below. Figure 7 To provide a more detailed description.

[0108] Figure 7 A schematic diagram of an optical proximity correction and layout stitching method 700 using Curvilinear OPC according to some embodiments of the present disclosure is shown. Figure 7 The document details the specific algorithms for curvilinear OPC correction and layout stitching.

[0109] Import the initial layout graphic at box 702.

[0110] At box 704, determine whether the current sub-plot has a low priority.

[0111] If the current sub-layout has a high priority (N), then OPC correction is performed on that sub-layout first. Specifically, the offsets of movable points and movable line segments are calculated directly based on the light intensity error of the evaluation points. After these movable points and movable line segments are moved according to the offsets, new points and line segments are formed, which are then connected sequentially to form a closed shape, resulting in the corrected layout of the current sub-layout. Finally, the offsets of the movable points and movable line segments of the current sub-layout are exported to a temporary storage area for use when correcting lower-priority sub-layouts. Specifically, this process first proceeds to box 708.

[0112] At frame 708, movable line segments and movable points are cut on the layout graphic according to predetermined rules.

[0113] At box 710, store the results of cutting movable line segments and movable points of the current layout (or store them after correction as needed).

[0114] At point 711, assign evaluation points to the movable points and movable line segments.

[0115] At frame 713, the sub-pattern graphic is fed into the forward lithography model for simulation to obtain the light intensity distribution spectrum.

[0116] At frame 715, the light intensity error at the evaluation point is calculated. That is, the evaluation point is set, and the light intensity error at the evaluation point is determined.

[0117] At box 717, the Curvilinear OPC solver performs the solution. The offset is obtained by solving the problem.

[0118] At box 726, the movable line segments and movable points are iteratively offset to form a correction sub-layout.

[0119] At box 730, the offsets of movable points and movable line segments for this sub-layout are stored. At this point, the OPC correction for this high-priority sub-layout is complete.

[0120] If the current sub-layout is determined to have a lower priority (Y) at box 704, then the OPC correction for the lower-priority sub-layout begins after the OPC correction for the adjacent higher-priority sub-layout is completed. The offsets of movable points and movable segments of the higher-priority sub-layout can be pre-loaded from a temporary storage area as a reference. When correcting the current sub-layout, these pre-loaded offsets are kept unchanged, and the curvilinear OPC solver is called to calculate the offsets of the remaining movable points and movable segments. Ultimately, the correction result for the lower-priority sub-layout is the superposition of the correction result passed from the higher-priority sub-layout and the lower-priority sub-layout's own correction result. This is described in detail below.

[0121] At box 706, load the movable line segments and movable point cut results of the adjacent high-priority layout.

[0122] At box 712, referencing the existing cutting results, cut the movable selection and movable points on the remaining graphic according to the rules.

[0123] At box 714, assign evaluation points to the movable points and movable line segments.

[0124] At frame 716, the sub-pattern graphic is fed into the forward lithography model for simulation to obtain the light intensity distribution spectrum.

[0125] At frame 718, the light intensity error at the evaluation point is calculated.

[0126] At box 720, the Curvilinear OPC solver performs the solution.

[0127] At box 724, load the movable line segments and movable point offsets of the adjacent high-priority sub-layout.

[0128] At box 728, using the existing offset results as a reference, the remaining movable points and movable line segments are offset to form a new layout graphic.

[0129] At box 732, the new layout graphic is output as the iteration result of the current OPC solver, and iterative processing is performed until the predetermined requirements are met to obtain the final corrected sub-layout.

[0130] At frame 734, the corrected sub-maps are stitched together.

[0131] In this embodiment, OPC correction is first performed on high-priority sub-layouts. After all high-priority sub-layouts have undergone OPC correction, lower-priority sub-layouts are then corrected. Regardless of the number of priority types set, the process can be carried out in the above manner.

[0132] A core issue in layout stitching technology lies in the continuity of line segments intersecting with sub-layout boundaries. During OPC processing, the layout is divided based on a predefined resolution precision, and the entire layout is segmented into a series of grid points, with all vertices of the layout graphics located at these grid points. Using the high-low priority sub-layout stitching technology shown in the embodiments of this disclosure, the continuity problem of line segments at boundaries can be effectively resolved by grid point processing for vertical and horizontal layout graphics. This is mainly because the intersection points of vertical and horizontal line segments with sub-layout boundaries are usually also located at grid points. However, for line segments at arbitrary angles, their intersection points with sub-layout boundaries may not fall on grid points, potentially leading to slight discontinuities (such as small jumps) when the same line segment crosses a sub-layout boundary.

[0133] To address the aforementioned potential problems, some embodiments of this disclosure propose a smoothing process.

[0134] In some embodiments, before separating the first correction sub-pattern from the adjacent second correction sub-pattern along the boundary, the intersection point of the graphic profile penetrating the boundary and the boundary is redefined; the original intersection point of the graphic profile penetrating the boundary and the boundary is modified to the redefined intersection point.

[0135] In some embodiments, redetermining the intersection point of the graphic profile that runs through the boundary and the boundary includes: determining whether the original intersection point is located on a grid point; in response to determining that the original intersection point is not located on a grid point, taking one of the two grid points on the boundary adjacent to the original intersection point as the redetermined intersection point; and in response to determining that the original intersection point is located on a grid point, keeping the position of the original intersection point unchanged.

[0136] In some embodiments, the new position of the intersection point of the graphic contour that runs through the boundary and the boundary can be determined based on the coordinate values. For example, for a vertical boundary, the grid point with the smaller vertical coordinate value is chosen by default; for a horizontal boundary, the grid point with the larger horizontal coordinate value is chosen by default. It should be understood that this disclosure is not limited thereto, and various changes can be made as needed. See below for reference. Figure 8 Describe it.

[0137] Figure 8 A schematic diagram illustrating boundary smoothing of spliced ​​sub-layouts according to some embodiments of the present disclosure is shown. Figure 8 In the diagram, the target map spans two sub-maps, one with high priority and the other with low priority. A, B, C, and D are the initial movable points after the cut. After... Figure 4 After curvilinear OPC solving and high-priority offset storage and import processing, these initial movable points were moved to positions A1, B1, C1, and D1. The intersection of line segment B1C1 and the sub-layout boundary is E1. If E1 is not on a grid point, and the two grid points closest to E1 and located on the sub-layout boundary are E0 and E2, then line segment B1C1 is cut along the sub-layout boundary, and the sub-layout... Figure 1 This might result in line segment B1E0, while the sub-version... Figure 2 This could result in line segment E2C1. In this case, the original line segment B1C1 would have discontinuous jumps between E0 and E2, which is generally not allowed.

[0138] In some embodiments, when correcting high-priority sub-versions Figure 1At this point, it checks whether the intersection point E1 of line segment B1C1 and the sub-plot boundary is located on a grid point. If E1 is not on a grid point, E1 is switched to E2 first, and the offset position of the movable point C is re-determined as C2 on the extension line of B1E2 based on the distance from E1C1. The final corrected target plot boundary is A1B1E2C2D1. It should be understood that, depending on the actual situation, E1 can also be switched to E0.

[0139] pass Figure 8 This method of recalculating boundary intersections ensures the continuity of line segments when splicing sub-maps, thereby achieving the continuity of the entire map splicing.

[0140] Figure 9 A schematic diagram showing the layout stitching effect according to some embodiments of the present disclosure is provided.

[0141] To verify the effectiveness of the curvilinear OPC layout pattern stitching algorithm in this embodiment, a metal layer layout was selected as a case study for photolithography simulation verification. In the photolithography model, the wavelength was set to 193 nm, the numerical aperture was 1.35, and the light source shape was cquad (quadripolar illumination), a common term in photolithography. The external sigma value was 0.95, and the internal sigma value was 0.8. External and internal sigma values ​​are two parameters that determine the position and size of the four-level illumination, and are also common terms in photolithography. The mask pattern is a typical metal layer line segment type, with a critical dimension (CD) of 45 nm and a minimum spacing (SP) of 48 nm. The layout was divided into 16 sub-layouts, with one CPU allocated to every four sub-layouts for distributed computing.

[0142] Figure 9 The image stitching results after correction by each CPU are shown. It can be seen that some corrected graphics in the high-priority and low-priority sub-layouts are at arbitrary angles, but these arbitrary-angled graphics can achieve continuous and smooth stitching at the sub-layout boundaries without sharp corners. For example, at the intersection of two sub-layouts, such as the area circled in the dashed ellipse 902, the outline is smooth without sharp corners. This indicates that the layout stitching algorithm in this embodiment is effective.

[0143] Some embodiments of this disclosure provide optical proximity correction methods. Specifically, some embodiments of this disclosure propose movable point cutting and cutting position stitching techniques based on sub-layout priority; furthermore, they propose a layout stitching technique based on movable point offsets of sub-layout priority.

[0144] It should be noted that the examples given in the above embodiments are only for illustrating the solutions of the embodiments of this disclosure and are not intended to limit the solutions of this disclosure. For example, some of the above embodiments mention the use of Curvilinear OPC technology for optical proximity correction. It should be understood that the embodiments of this disclosure are not limited to this, but other OPC technologies can be used as needed.

[0145] The core of layout stitching mainly includes key steps such as cutting and stitching movable points / line segments and stitching the corrected graphic boundaries. The layout correction and stitching technology of some embodiments disclosed herein has the following significant advantages: it can effectively solve the problem of smooth stitching at the boundaries of different sub-layouts, avoiding abrupt changes in lithography signals due to stitching discontinuities; it provides a reliable stitching foundation for distributed computing of ultra-large-scale layout correction, significantly improving the overall efficiency of layout correction.

[0146] It should be understood that the embodiments shown in the accompanying drawings are merely illustrative of some embodiments of this disclosure and are not intended to limit this disclosure. Embodiments of this disclosure may also have various other forms.

[0147] An electronic device is also disclosed in embodiments of this disclosure. The electronic device includes: a processor; and a memory coupled to the processor, the memory having instructions stored therein, the instructions causing the device to perform actions when executed by the processor. These actions include: determining cutting positions of graphic contours in a higher-priority first sub-layout and graphic contours within a predetermined range adjacent to the first sub-layout in a lower-priority second sub-layout, from a plurality of sub-layouts divided by an initial layout, to cut each graphic contour into a plurality of first movable line segments and a plurality of first movable points; iteratively offsetting the plurality of first movable line segments and the plurality of first movable points until a first offset is finally made to correct the first sub-layout into a first corrected sub-layout; and offsetting the graphic contours of the second sub-layout based on the cutting positions to generate a second corrected sub-layout.

[0148] The embodiments of this disclosure also disclose a computer-readable storage medium having machine-executable instructions stored thereon, which, when executed by a processor, implement the optical proximity correction method according to the embodiments of this disclosure.

[0149] Figure 10Schematic block diagrams of electronic devices according to some exemplary embodiments of the present disclosure are shown. The electronic devices are intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic devices may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0150] like Figure 10 As shown, device 1000 includes a CPU 1001, which can perform various appropriate actions and processes according to a computer program stored in read-only memory (ROM) 1002 or a computer program loaded from storage unit 1008 into random access memory (RAM) 1003. The RAM 1003 may also store various programs and data required for the operation of device 1000. The CPU 1001, ROM 1002, and RAM 1003 are interconnected via bus 1004. Input / output (I / O) interface 1005 is also connected to bus 1004.

[0151] Multiple components in device 1000 are connected to I / O interface 1005. These components include: input unit 1006, such as a keyboard or mouse; output unit 1007, such as various types of displays or speakers; storage unit 1008, such as a hard disk or optical disk; and communication unit 1009, such as a network interface card (NIC), modem, or wireless transceiver. Communication unit 1009 allows device 1000 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0152] The various processes and procedures described above, such as method 200, can be executed by CPU 1001. For example, in some embodiments, method 200 can be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 1008. In some embodiments, part or all of the computer program can be loaded and / or installed on device 1000 via ROM 1002 and / or communication unit 1009. When the computer program is loaded into RAM 1003 and executed by CPU 1001, one or more steps of method 200 described above can be performed.

[0153] The embodiments of this disclosure may be methods, apparatus, systems, and / or computer program products. A computer program product may include a computer-readable storage medium on which computer-readable program instructions for performing various aspects of this disclosure are loaded. The computer-readable storage medium may be a tangible device capable of holding and storing instructions used by an instruction execution device. The computer-readable program instructions may be downloaded from the computer-readable storage medium to various computing / processing devices, or downloaded via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network, to an external computer or external storage device.

[0154] The various embodiments of this disclosure have been described above. These descriptions are exemplary and represent only optional embodiments of this disclosure, and are not exhaustive, nor are they intended to limit this disclosure. Although the claims in this application have been formulated for specific combinations of features, it should be understood that the scope of this disclosure also includes any novel feature or any novel combination of features, whether express or implied or generalized herein, whether or not it relates to the same scheme in any currently claimed claim. It should be understood that new claims may be formulated as these features and / or combinations of these features during the examination of this application or in any further applications derived therefrom.

[0155] The terminology used herein is chosen to best explain the principles, practical applications, or technological improvements of the various embodiments, or to enable those skilled in the art to understand the embodiments disclosed herein. Various modifications and variations can be made to this disclosure by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. An optical proximity correction method, comprising: Determine the cutting positions of the graphic outlines in the first sub-landscape with higher priority and the graphic outlines in the second sub-landscape with lower priority within a predetermined range adjacent to the first sub-landscape, in order to cut each graphic outline into multiple first movable line segments and multiple first movable points. Iteratively offset the plurality of first movable line segments and the plurality of first movable points until the final offset reaches the first offset amount, then correct the first sub-layout to a first corrected sub-layout; and The graphic outline of the second sub-layout is offset based on the cutting position to generate a second corrected sub-layout.

2. The method according to claim 1, wherein offsetting the graphic outline of the second sub-layout based on the cutting position to generate the second corrected sub-layout comprises: Based on the cutting position, the graphic contours within the predetermined range in the second sub-layout are cut and offset by the first offset, and the remaining graphic contours in the second sub-layout are cut and iteratively offset based on the cutting position to generate a second corrected sub-layout.

3. The method according to claim 2, further comprising: The first correction sub-pattern and the second correction sub-pattern are spliced ​​together to generate a correction pattern.

4. The method of claim 1, wherein cutting each graphic contour into a plurality of first movable line segments and a plurality of first movable points comprises: The graphic outline in the corner area of ​​the graphic is cut into the plurality of first movable points; as well as The graphic outline in the non-corner area of ​​the graphic is cut into the plurality of first movable line segments.

5. The method according to claim 1, wherein iteratively offsetting the plurality of first movable line segments and the plurality of first movable points until the final offset is a first offset amount, and then correcting the first sub-layout to a first corrected sub-layout, comprises: Determine the initial offsets of the plurality of first movable line segments and the plurality of first movable points; Move the first movable line segment and the plurality of first movable points based on the initial offset; as well as In response to the iteration satisfying a predetermined condition, the corresponding first sub-layout is corrected to the first corrected sub-layout, wherein the final offset corresponding to satisfying the predetermined condition is the first offset.

6. The method of claim 5, wherein determining the initial offset of the plurality of first movable line segments and the plurality of first movable points comprises: The portions of the first sub-pattern and the second sub-pattern located within the predetermined range are input into the photolithography simulation model to generate a light intensity distribution map. Determine the corresponding light intensity signals at the plurality of first movable line segments and the plurality of first movable points; as well as The initial offset of the plurality of first movable line segments and the plurality of first movable points is determined based on the comparison between the light intensity signal and the exposure threshold.

7. The method of claim 6, wherein determining the corresponding light intensity signals at the plurality of first movable line segments and the plurality of first movable points comprises: Evaluation points are set at each of the first movable line segments and the first movable points; as well as The light intensity signal at each evaluation point is determined as the corresponding light intensity signal at each first movable line segment and the first movable point.

8. The method of claim 1, wherein iteratively offsetting the plurality of first movable line segments and the plurality of first movable points comprises: The first movable point can be moved in any direction within the plane of the initial layout graphic; as well as The first movable line segment is moved along the normal direction of the line segment in the plane of the initial layout graphic.

9. The method of claim 1, wherein the cutting position and the first offset are stored in a temporary storage area.

10. The method of claim 9, wherein cutting and iteratively offsetting the remaining graphic outline in the second sub-layout based on the cutting position comprises: Obtain the cutting position from the temporary storage area; Based on the cutting position, starting from the cutting position located within the predetermined range of the second sub-map and close to the boundary of the remaining part of the second sub-map, the graphic outline of the remaining part is cut into a plurality of second movable line segments and a plurality of second movable points; as well as The plurality of second movable line segments and the plurality of second movable points are iteratively offset to generate a portion of the second correction sub-layout.

11. The method of claim 9, wherein cutting the graphic outline within the predetermined range in the second sub-layout based on the cutting position and offsetting it by the first offset includes: Obtain the cutting position from the temporary storage area; Based on the cutting position of a portion of the graphic outline within the predetermined range of the second sub-map included in the cutting position, the portion of the graphic outline within the predetermined range is cut to generate corresponding movable line segments and movable points. as well as The corresponding movable line segments and movable points are offset by the first offset to generate another part of the second correction sub-layout.

12. The method of claim 1, further comprising: Before separating the first correction sub-pattern from the adjacent second correction sub-pattern along the boundary, the intersection point of the graphic outline that runs through the boundary and the boundary is redefined; as well as The original intersection point of the graphic outline that runs through the boundary and the boundary is modified to a newly determined intersection point.

13. The method of claim 12, wherein redetermining the intersection point of the graphic profile penetrating the boundary with the boundary comprises: Determine whether the original intersection point is located on a grid point; In response to determining that the original intersection point is not located on a grid point, one of the two grid points on the boundary adjacent to the original intersection point is taken as the newly determined intersection point; And in response to determining that the original intersection point is located on a grid point, the position of the original intersection point remains unchanged.

14. The method according to any one of claims 1 to 13, wherein cutting the respective graphic contours into a plurality of first movable line segments and a plurality of first movable points comprises: Based on the position of the graphic outline, the plurality of first movable line segments are cut at a first interval, and the first movable point is cut at a second interval, wherein the first interval is greater than the second interval.

15. An electronic device comprising: processor; as well as A memory coupled to a processor, containing instructions stored therein, which, when executed by the processor, cause the device to perform actions, including: Determine the cutting positions of the graphic outlines in the first sub-landscape with higher priority and the graphic outlines in the second sub-landscape with lower priority within a predetermined range adjacent to the first sub-landscape, in order to cut each graphic outline into multiple first movable line segments and multiple first movable points. Iteratively offset the plurality of first movable line segments and the plurality of first movable points until the final offset reaches the first offset amount, then correct the first sub-layout to a first corrected sub-layout; and The graphic outline of the second sub-layout is offset based on the cutting position to generate a second corrected sub-layout.

16. A computer-readable storage medium storing machine-executable instructions that, when executed by a processor, cause the processor to perform the method according to any one of claims 1 to 14.

Images