Data processing method, integrated circuit, radio device and terminal equipment

Abstract

The embodiment of the invention relates to the technical field of data processing, and discloses a data processing method, an integrated circuit, a radio device and terminal equipment. The data processing method comprises the following steps: in an ith data processing cycle, determining a target storage position of jth to-be-read data according to an association relationship between a reading sequence and a writing sequence; i is an integer greater than 1, j is equal to 1, 2,..., Q, and Q is the total number of data needing to be processed in each data processing period; the reading sequence is not consistent with the writing sequence; reading the data at the target storage position to obtain the jth to-be-read data; and writing the jth data to be written in the ith data processing cycle into the target storage position. At least the size of a storage space on which data depends is reduced, so that the data processing cost is reduced.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of data processing, in particular to a data processing method, an integrated circuit, a radio device and a terminal device. BACKGROUND

[0002] In a Multiple-In Multiple-Out (MIMO) radar, a radar signal processing flow (for example, FFT) is generally processed in series in units of RX (receive antenna). However, at the receiving end, due to multiple receive antennas, multiple Analog to Digital Converter (ADC) data samples of the receive antennas will be obtained at the same time, and thus, the write order and the read order will be different.

[0003] In a radar signal processing engine, the processing of the radar signal is in units of a chirp transmission period, and the data processing will not be started until the receive data in the chirp transmission period is buffered. Moreover, the idle time length between the transmitted chirps is determined by the specific application and is not determined by the radar signal processing module, and thus, after the Nth chirp is received, the transmission of the N+1th chirp will be started immediately, which will result in that the data of the N+1th chirp will be buffered and the data of the Nth chirp will be read from the buffer for radar signal processing at the same time.

[0004] At this time, two memory pools (memory pool0 and memory pool1) are needed to support the read operation and the write operation at the same time. Specifically, the calling of the memory pool0 and the memory pool1 will be as shown in FIG. 1 (each small square in the figure corresponds to a memory unit), and the first chirp (chirp0) has not received data, and thus, only the write operation is needed, and the read operation is not needed. At this time, in the chirp0, the memory unit of the memory pool0 is occupied by the write operation (this case is represented by the square filled with a horizontal line in FIG. 1). However, after the second chirp (chirp1) and the chirps thereafter, due to the inconsistent read and write orders, the read operation is needed to transmit the chirp signal, and the write operation is also needed to store the echo data. Taking the chirp1 and the chirp2 as examples, during the transmission of the chirp1, the memory unit of the memory pool0 is occupied by the read operation (this case is represented by the square filled with a vertical line in FIG. 1). However, during the transmission of the chirp2, the memory unit of the memory pool1 is occupied by the write operation (this case is represented by the square filled with a horizontal line in FIG. 1). Figure 1 Figure 1 Figure 1 Figure 1 ​​​The data written in chirp0 is read (indicated by the square filled with horizontal lines), and the memory unit of memory pool1 is occupied by a write operation (this case is indicated by the square filled with diagonal lines) Figure 1 The echo data received in chirp1 is written (indicated by the square filled with diagonal lines), and the memory unit of memory pool1 is occupied by a read operation (this case is indicated by the square filled with horizontal lines) during the transmission of chirp2. Figure 1 The data written in chirp1 is read (indicated by the square filled with horizontal lines), and the memory unit of memory pool0 is occupied by a write operation (this case is indicated by the square filled with diagonal lines) Figure 1 The echo data received in chirp2 is written (indicated by the square filled with diagonal lines). That is, two memory pools are finally needed.

[0005] However, with the development of radars and their related algorithms, more and more data need to be read and written, and the storage space required is also increasing. SUMMARY

[0006] The embodiments of the present application provide a data processing method, an integrated circuit, a radio device and a terminal device, which at least have the advantage of reducing the size of the storage space on which data depends, thereby reducing the data processing cost.

[0007] According to some embodiments of the present application, the embodiments of the present application provide a data processing method, comprising: in the i th data processing period, determining a target storage location of the j th to-be-read data according to an association relationship between a read sequence and a write sequence; i is an integer greater than 1, j = 1, 2, …, Q, Q is the total number of data to be processed in each data processing period; the read sequence and the write sequence are inconsistent; reading the data at the target storage location to obtain the j th to-be-read data; and writing the j th to-be-written data in the i th data processing period to the target storage location.

[0008] In some embodiments, the association relationship includes an association relationship among the number of receiving antennas, the depth of the storage space, and the amount of data allowed to be stored in each physical address in the storage space.

[0009] In some embodiments, the target storage location of the jth data to be read is determined according to the correlation between the read order and the write order, including: Address = [(((R / P)^N)*k) / M] + (((R / P)^N)*k)%M, where Address represents the target storage location, R is the number of receiving antennas, N represents the sequence number of the current data processing period, M represents the depth of the storage space, k represents the number of times of reading the storage space, P is the multiple of the amount of data allowed to be stored in each address in the storage space relative to the amount of data of a single point total antenna, N = 0, 1, 2, …, k = 0, 1, 2, …; [] represents a down rounding operation, and % represents a remainder operation.

[0010] In some embodiments, the amount of data allowed to be stored in each physical address in the storage space is an integer multiple of the number of receiving antennas.

[0011] In some embodiments, the jth data to be written in the i th data processing period is written into the target storage location, including: after obtaining the j+t-s th data to be read, the j-t+s th data to be read to the j+t-s th data to be read in the i th data processing period are written into the respective target storage locations, s = k%t, t is an integer multiple of the amount of data allowed to be stored in each physical address in the storage space for reading and writing, and % represents a remainder operation.

[0012] In some embodiments, the reading speed of the jth data to be read is greater than or equal to the writing speed of the jth data to be written.

[0013] In some embodiments, the reading bandwidth of the jth data to be read is greater than or equal to the writing bandwidth of the jth data to be written.

[0014] According to some embodiments of the present application, another aspect of the embodiments of the present application further provides an integrated circuit, including: an addressing module configured to determine a target storage location of jth data to be read in an i th data processing period according to a correlation between a write order and a read order; i is a positive integer greater than 1, k = 1, 2, …, Q, Q is the total amount of data to be processed in each data processing period; the write order and the read order are inconsistent; a reading module configured to read data located in the target storage location to obtain the jth data to be read; and a writing module configured to write jth data to be written in the i th data processing period into the target storage location.

[0015] According to some embodiments of the present application, another aspect of the embodiments of the present application further provides a radio device, comprising: a carrier; an integrated circuit as described above, arranged on the carrier; an antenna, arranged on the carrier, or the antenna is integrated with the integrated circuit and arranged on the carrier; wherein the integrated circuit is connected with the antenna, and is configured to process the received echo signal data.

[0016] According to some embodiments of the present application, another aspect of the embodiments of the present application further provides a terminal device, comprising: a device body; and a radio device as described above arranged on the device body; wherein the radio device is configured to target detection, to provide reference information for operation of the device body.

[0017] The technical solutions provided by the embodiments of the present application have at least the following advantages:

[0018] In the case that the write order and the read order are inconsistent, the target storage position of the jth data to be read in the ith data processing period is determined according to the association relationship between the write order and the read order, so that the jth data to be read required can be read from the target storage position, and read-write parallel operation is realized. That is, even if the read-write order of the data is inconsistent, the same storage space can still be used for reading data and writing data in the same data processing period, without the need to use two storage spaces, reducing the storage space required in the data processing period, and further reducing the data processing cost. BRIEF DESCRIPTION OF DRAWINGS

[0019] One or more embodiments are illustrated by way of example in the drawings in which like reference numerals indicate like elements, and in which:

[0020] Figure 1 is a storage resource calling schematic diagram of an existing data processing method;

[0021] Figure 2 is a flowchart of a data processing method provided in the embodiments of the present application;

[0022] Figure 3 is a storage resource calling schematic diagram corresponding to the data processing method provided in the embodiments of the present application;

[0023] Figure 4 is a structural schematic diagram of an integrated circuit provided in the embodiments of the present application. DETAILED DESCRIPTION

[0024] For the purposes of the present application, the technical solutions and advantages of the embodiments will be more apparent, the embodiments of the present application will be described in detail below with reference to the drawings. However, those skilled in the art can understand that in the embodiments of the present application, many technical details are proposed in order to make the reader better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed by the present application can be implemented.

[0025] The division of the various embodiments is for the convenience of description, and should not constitute any limitation on the specific implementation mode of the present application. The various embodiments can be combined and referred to each other without contradiction.

[0026] The present application provides a data processing method, and the flow thereof is as shown in Figure 2 The data processing method comprises the following steps:

[0027] In step 201, in the i th data processing cycle, the target storage location of the j th data to be read is determined according to the association relationship between the read order and the write order.

[0028] In step 202, the data located in the target storage location is read to obtain the j th data to be read.

[0029] In step 203, the j th data to be written in the i th data processing cycle is written into the target storage location.

[0030] In this way, in the case where the write order and the read order are inconsistent, the target storage location of the j th data to be read in the i th data processing cycle is determined according to the association relationship between the write order and the read order, so that the j th data to be read required can be read from the target storage location, and the read-write parallel operation is realized. That is, even if the read-write order of the data is inconsistent, the same storage space can still be used for reading data and writing data in the same data processing cycle, without the need to use two storage spaces, thereby reducing the storage space required in the data processing cycle.

[0031] In order for those skilled in the art to better understand the above-mentioned embodiments, the data processing method provided by the embodiment as shown in Figure 2 will be explained and described.

[0032] In step 201, in the i th data processing cycle, the target storage location of the j th data to be read is determined according to the association relationship between the read order and the write order. Wherein, i is an integer greater than 1, j = 1, 2, …, Q, Q is the total number of data to be processed in each data processing cycle; the read order and the write order are inconsistent.

[0033] It can be understood that the data processing method provided in the embodiment is applied to the process of radar digital signal processing of echo data. In this scenario, the situation of the radar can affect the data characteristics of the obtained echo data. For example, in a Multiple-In Multiple-Out (MIMO) radar, the echo signal will alias on different receiving channels. Therefore, when processing such signals, the influence of aliasing on the signals must be considered, and the association between the reading order and the writing order is more complex. Obviously, the single-antenna radar does not have the above problems. It can also be understood that the MIMO radar is more complex, and the echo data of the single-antenna radar can be regarded as an edge case in which the number of antennas of the MIMO radar gradually decreases to 1. Therefore, the MIMO radar will be mainly used as an example for illustration in the following.

[0034] In some embodiments, in the multi-antenna scenario (such as the application of MIMO radar, etc.), the association relationship can include the association relationship between the number of receiving antennas, the depth of the storage space, and the amount of data allowed to be stored in each physical address in the storage space.

[0035] Further, the scenario is further limited to the multi-antenna and the scenario of reading data in the dimension of the antenna. At this time, the target storage location Address of the jth data to be read is:

[0036] Address=[(((R / P)^N)*k) / M]+(((R / P)^N)*k)%M,

[0037] wherein R is the total number of receiving antennas, N represents the sequence number of the current data processing period, M represents the depth of the storage space, k represents the number of times of reading the storage space, P is the multiple of the amount of data of each address in the storage space relative to the amount of data of a single point total antenna number, N=0, 1, 2……, k=0, 1, 2……; [] represents the down rounding operation, and % represents the remainder operation.

[0038] wherein the amount of data of a single point total antenna number=antenna number*amount of data of one sampling point.

[0039] Through the above expression, the read data can meet the requirement of reading data in the dimension of the antenna, thereby facilitating subsequent data processing, such as digital signal processing of echo data to obtain the distance, speed, angle, etc. of the target.

[0040] In some embodiments, the amount of data allowed to be stored in each physical address in the storage space is an integer multiple of the number of receiving antennas. In this way, each physical address can store multiple data of the same antenna, and thus, in the scenario of reading data in the dimension of antennas, since the data stored in each physical address is multiple data of the same antenna, it is not necessary to identify which antenna the data belongs to, and thus, it is beneficial to reduce the implementation difficulty of reading.

[0041] In step 202, data located at the target storage position is read to obtain the jth to-be-read data. The reading method here is roughly the same as the existing data reading, and the difference mainly lies in that the positions of writing and reading in the present embodiment adopt a special way, and thus, the target storage position determined in step 201 needs to be read, and thus, the same parts will not be described here.

[0042] In step 203, the jth to-be-written data of the i th data processing period is written to the target storage position.

[0043] It can be understood that the target storage position has been read in step 202, and thus, the target storage position can be used to maintain new data, i.e., to allow data to be written. Here, the jth to-be-written data of the i th data processing period is written, which can continue to satisfy the corresponding association relationship between the writing order and the reading order, i.e., subsequent data reading and data writing can be realized by repeatedly executing the data processing method provided in the present embodiment, and in this process, the data association is guaranteed not to be destroyed, so that accurate results can be obtained when it is applied.

[0044] In some embodiments, writing the jth to-be-written data of the i th data processing period to the target storage position can be realized by the following way: after obtaining the j+t-s th to-be-read data, writing the j-t+s th to-be-read data to the j+t-s th to-be-read data of the i th data processing period to the respective corresponding target storage positions, s=k%t, t is an integer multiple of the amount of data allowed to be stored in each physical address in the storage space. That is, multiple data are stored at a time, which is beneficial to simplify the subsequent reading process and reduce the difficulty of reading, and % represents the modulo operation.

[0045] In some examples, the possible values of t can be 4, 8, 12, or 16, which can better adapt to the processing of 4 (or 8, 12, 16, etc.)-way accumulation involved in the current echo data processing algorithm, and is beneficial to improve the efficiency of echo signal processing.

[0046] In some embodiments, the read speed of the jth data to be read is greater than or equal to the write speed of the jth data to be written. In this way, the read speed of the jth data to be read is greater than or equal to the write speed of the jth data to be written, so that the target storage location where the jth data to be read is located always occurs the read operation first, and then the write operation, that is, the data in the same storage location is always read first and then written, which is beneficial to improve the data read-write accuracy.

[0047] In some embodiments, the read bandwidth of the jth data to be read is greater than or equal to the write bandwidth of the jth data to be written. That is, by controlling the bandwidth, the read efficiency is greater than or equal to the write efficiency, so that the data in the same storage location is always read first and then written, which is beneficial to improve the data read-write accuracy.

[0048] In order to further facilitate those skilled in the art to understand the data processing method provided in the above embodiments, the following will be exemplarily described taking the processing of echo data as an example.

[0049] In the formula, it is assumed that the echo data is obtained by sampling the echo signal received by a radar with 4 receiving antennas by an ADC with a sampling frequency of 60MHz, the data bit width of the ADC is 32bits (I / Q), the cache capacity is 4*4096*32bits=64KB, the radar signal processing frequency (Radar signal process freq) is 240MHz, and the signal of the detected target (the signal is reflected by the target to obtain the aforementioned echo signal) is an FMCW signal composed of a plurality of chirps. The maximum sampling data that can be obtained by sampling each chirp is (Maximum Sample Number per Chirp) 4096. At the same time, the performance of the storage space (Memory) in the ADC is as follows: one memory address caches 4 samples, that is, the memory bit width is 4*32bits=128bits, and in the specific implementation, it can be realized by 1 or more memory instances; the depth of the memory is 4096, and in the specific implementation, it can be realized by 1 or more memory instances; the memory read-write frequency is 240Mhz, the sampling rate of the ADC is 4Sample / cycle@60Mhz, that is, 1Sample / Cycle@240Mhz; the data processing capacity of the ADC matches the sampling rate, which is also 1Sample / Cycle@240Mhz; in the data writing process of the ADC, 4 cycles@240Mhz are allowed to be cached in the same memory address, and in the data reading process of the ADC, 4 cycles@240Mhz are also allowed to read a memory address.

[0050] Therefore, in the data processing method of echo data on the ADC, the correlation between the read order and the write order is as follows:

[0051] Address = [((4^N)*k) / 4096] + ((4^N)*k) % 4096;

[0052] wherein N is a chirp number (in the case that the chirp needs to start from 0, since data reading and data writing will be performed synchronously within the transmission period of one chirp, one chirp transmission period can correspond to one data processing period), and k represents the number of times of reading the storage space for reading and writing.

[0053] Obviously, the above scenario satisfies that the amount of data allowed to be stored in each physical address of the storage space for reading and writing is an integer multiple of the number of receiving antennas (i.e., the data storage of Memory, the number of ADC data points stored in each entry is an integer multiple of the number of RXs); and the reading speed of the jth data to be read is greater than or equal to the writing speed of the jth data to be written (further, the reading bandwidth of the data is greater than or equal to the writing bandwidth of the data, i.e., in the signal processing application, the data processing capability equivalent to the Fourier transform is greater than or equal to the data rate of the ADC).

[0054] It should be noted that for the above formula, this is because there are 4 receiving antennas, and each chirp received on each antenna can obtain 4096 (data) points for the echo signal, and 4 points are read each time, so k = 0, 1, 2, 3, …, 4095.

[0055] As can be seen from the above formula, the operation order of the physical addresses in the storage space in the data processing period presents a periodic change, specifically, 6 data processing periods corresponding to 6 chirps form a large period, and in different periods, data reading will be performed according to the same address reading order, and data writing will be performed according to the same address writing order. For example, the address order of the 0th Chirp write is special, and is consistent with the address order of the 6th Chirp write. In addition, it can also be known that the reading order of the echo data corresponding to the Nth Chirp is completely consistent with the writing order of the echo data corresponding to the N+1th Chirp.

[0056] Specifically, taking the above example of each 6 chirps forming a large cycle, the data arrangement of the first chirp received by the receiving antenna after the radar is started in the memory at the end of the first data processing cycle, and the data arrangement of the third chirp received by the receiving antenna in the memory at the end of the third data processing cycle are described. Among them, RxNy represents the yth data received by the xth receiving antenna, RX0, RX1, RX2, RX3 are the aforementioned four receiving antennas (RX).

[0057] Table 1 Data arrangement of the first chirp (chirp0) in the memory at the end of the first data processing cycle

[0058]

[0059]

[0060] In the first data processing cycle, only writing is needed. At the same time, since the subsequent data processing is based on the data received by each antenna, specifically, the data corresponding to the signals received by each antenna in the previous data processing cycle are continuously read and processed as a whole, therefore, the data corresponding to the same antenna need to be continuously read to facilitate subsequent processing. Taking an example of 4096 data in total for each antenna in a data processing cycle, occupying 1024 physical addresses, 1024 physical addresses need to be reserved for the data received by the same antenna, that is, a group of data received by different antennas at the same time will be spaced by 1024 physical addresses when writing. Therefore, at the end of the first data processing cycle, the data writing in the storage space will be as shown in the above table, the data written in Address0-1023 is all the data corresponding to antenna RX0, the data written in Address1024-2047 is all the data corresponding to antenna RX1, the data written in Address2048-3071 is all the data corresponding to antenna RX2, and the data written in Address3072-4095 is all the data corresponding to antenna RX3, and the data in Address0-1023 is arranged in the order of the data received by antenna RX0, the data in Address1024-2047 is arranged in the order of the data received by antenna RX1, the data in Address2048-3071 is arranged in the order of the data received by antenna RX2, and the data in Address3072-4095 is arranged in the order of the data received by antenna RX3.

[0061] Table 2 The arrangement of data in the Memory after the end of the second data processing cycle for the second chirp (chirpl)

[0062]

[0063]

[0064] During the data receiving period of the second chirp (i.e. the second data processing cycle), the data read from the antennas is first processed, as shown in Table 1. For example, the data corresponding to antenna RXO is read in the order of AddressO-Addressl023. At the same time, since antennas RXO, RXl, RX2 and RX3 receive data simultaneously and need to write data, the data received by antennas RXO, RXl, RX2 and RX3 will be written simultaneously to the data that has been read, i.e. the physical addresses of the data that has been read, in the order of RXO, RXl, RX2, RX3, RXO, RXl, RX2, RX3, RXO, and so on. Specifically, the first read physical address AddressO will write data to antenna RXO, the second read physical address Addressl will write data to antenna RXl, the third read physical address Address2 will write data to antenna RX2, the fourth read physical address Address3 will write data to antenna RX3, the fifth read physical address Address4 will write data to antenna RXO, the sixth read physical address Address5 will write data to antenna RXl, the seventh read physical address Address6 will write data to antenna RX2, the eighth read physical address Address7 will write data to antenna RX3, and so on.

[0065] Table 3 The arrangement of data in the Memory after the end of the third data processing cycle for the third chirp (chirp2)

[0066]

[0067]

[0068] When the data of chirp2 is received, the data of the antennas RX0, RX1, RX2, RX3 are still read out in turn, that is, Address0, 4, 8, 12, 16…4084, 4088, 4092, 1, 5, 9, 13, 17…4085, 4093, 2, 6, 10, 14, 18…4086, 4090, 4094, 3, 7, 11, 15, 19…4087, 4091, 4095 in Table 2 will be read in turn; based on the characteristics of the received data, the physical addresses that are read will be written into the data in the order of antenna RX0, antenna RX1, antenna RX2, antenna RX3, antenna RX0, antenna RX1, antenna RX2, antenna RX3, antenna RX0…, that is, the data of the antennas RX0, RX1, RX2, RX3, RX0, RX1, RX2, RX3, RX0… will be written in Address0, 4, 8, 12, 16…4084, 4088, 4092, 1, 5, 9, 13, 17…4085, 4093, 2, 6, 10, 14, 18…4086, 4090, 4094, 3, 7, 11, 15, 19…4087, 4091, 4095 in turn. Specifically, Address0 is written into the data of the antenna RX0, Address4 is written into the data of the antenna RX1, Address8 is written into the data of the antenna RX2, Address12 is written into the data of the antenna RX3, Address16 is written into the data of the antenna RX0…Address4084 is written into the data of the antenna RX1, Address4088 is written into the data of the antenna RX2, Address4092 is written into the data of the antenna RX3, Address1 is written into the data of the antenna RX0, Address5 is written into the data of the antenna RX1, Address9 is written into the data of the antenna RX2…

[0069] For better understanding of the data processing method of the present application by those skilled in the art, the following will be described in combination with Figure 1 、 Figure 3 . Among them, Figure 1 the storage resource (memory pool 0 and memory pool 1) calling condition when the existing data processing method is applied, Figure 3 the storage resource (memory pool) calling condition when the data processing method provided by the embodiment of the present application is applied, Figure 3 the small squares in the figure are storage units.

[0070] As described above, during a certain chirp transmission, one of the memory pool 0 and the memory pool 1 can only support a read operation, and the other can only support a write operation, and two memories, i.e., the memory pool 0 and the memory pool 1, must be used. However, the data processing method provided in the embodiment of the present application can be used to Figure 3 read and write the target storage location in sequence, so that, in the chirp 1 and the chirp 2, the chirp 3, and the like after the chirp 1, the memory pool 0 has the storage unit occupied by the read operation (this case is represented by the square filled with Figure 3 horizontal lines) and the storage unit occupied by the write operation (this case is represented by the square filled with Figure 3 oblique lines) at the same time, i.e., after reading from the current target storage location, new data can be written into the target storage location, and therefore, it is no longer necessary to use different memory pools to maintain the read operation and the write operation, and only one memory pool is needed.

[0071] That is, the data processing method provided in the embodiment of the present application changes the data of different memory pools in the existing scheme at the same time to process the same memory pool at the same time, effectively reduces the memory size of the minimum cache 2 chirp data in the existing scheme to cache 1 chirp data. In particular, with the development of MIMO technology, the number of RXs and the sampling frequency will be improved, which will significantly reduce the demand for storage resources. The implementation greatly reduces the storage resources required for caching without increasing the inter-chirp wave transmission delay constraint and reducing the radar digital signal processing capability. Moreover, the required hardware resources are reduced, and the data storage and transmission efficiency is improved.

[0072] In addition, the data processing method provided in the embodiment of the present application can not be constrained by the number of receiving antennas, the number of chirps in the frame, and the sample size of each chirp. Under the conditions of different numbers of receiving antennas, the number of chirps in the frame, and the sample size, the ADC memory can be shared through the above scheme to reduce the cache ADC data capacity. This can also be seen from the expression of the above association relationship.

[0073] The step division of the above various methods is only for the purpose of clear description, and can be combined into one step or split into multiple steps in implementation, as long as the same logical relationship is included, and all are within the protection scope of the patent; adding insignificant modifications or introducing insignificant designs in the algorithm or process, but not changing the core design of the algorithm and process, are within the protection scope of the patent.

[0074] Another embodiment of the present application relates to an integrated circuit, comprising an addressing module, a reading module and a writing module. Figure 4 As shown, the integrated circuit comprises an addressing module 401, a reading module 402 and a writing module 403.

[0075] The addressing module 401 is configured to determine a target storage location of the jth data to be read according to an association between a writing sequence and a reading sequence in the ith data processing period; i is a positive integer greater than 1, k = 1, 4, …, Q, Q is the total number of data to be processed in each data processing period; the writing sequence and the reading sequence are inconsistent. The reading module 402 is configured to read the data in the target storage location to obtain the jth data to be read. The writing module 403 is configured to write the jth data to be written in the ith data processing period into the target storage location.

[0076] It is worth mentioning that each module involved in the embodiment can be a physical unit, a part of a physical unit, or a combination of multiple physical units. In addition, in order to highlight the innovative part of the present application, units not closely related to solving the technical problems proposed in the present application are not introduced in the embodiment, but this does not mean that there are no other units in the embodiment.

[0077] Another embodiment of the present application relates to a wireless radio device, comprising a carrier, the above-mentioned integrated circuit arranged on the carrier, and an antenna arranged on the carrier, or the antenna and the integrated circuit are integrated and arranged on the carrier. The integrated circuit is connected with the antenna and is configured to process the received echo signal data.

[0078] When the antenna and the integrated circuit are not integrated, the integrated circuit is connected with the antenna through a first transmission line, which can be a PCB trace. The carrier can be a printed circuit board (PCB), such as a development board, a data acquisition board or a mainboard of a device, etc., which will not be described one by one here.

[0079] The structure and working principle of the integrated circuit included in the wireless radio device have been described in detail in the above embodiments, which will not be described one by one here.

[0080] Another embodiment of the present application relates to a terminal device, comprising: a device body; and a radio device as described above arranged on the device body; wherein the radio device is configured to target detection to provide reference information for operation of the device body.

[0081] In one embodiment of the present application, the radio device can be arranged outside the device body, in another embodiment of the present application, the radio device can also be arranged inside the device body, and in other embodiments of the present application, the radio device can be partially arranged inside the device body and partially arranged outside the device body. The embodiments of the present application do not limit this, and the specific arrangement is determined as appropriate.

[0082] It should be noted that the radio device can achieve functions such as target detection by transmitting and receiving radio signals to provide measurement information of the detected target to the device body, thereby assisting or even controlling the operation of the device body. The measurement information includes, for example, at least one of relative distance, relative speed, and relative angle.

[0083] In an optional embodiment, the device body described above can be components and products applied to fields such as transportation, consumer electronics, monitoring, cabin detection, and health care. For example, the device body can be intelligent transportation devices (such as cars, motorcycles, ships, subways, trains, etc.), security devices (such as cameras), liquid level / flow rate detection devices, smart wearable devices (such as bracelets, glasses, etc.), smart home devices (such as sweeping robots, door locks, televisions, air conditioners, smart lights, etc.), various communication devices (such as mobile phones, tablet computers, etc.), and the like, and can also be various instruments for detecting life characteristic parameters and various devices carrying the instruments, such as cabin detection of a car, indoor personnel monitoring, intelligent medical devices, consumer electronic devices, etc.

[0084] In yet another optional embodiment, when the device body described above is applied to an advanced driver assistance system (i.e., ADAS), the radio device as a vehicle-mounted sensor can provide various functional safety for the ADAS system, such as automatic brake assistance (i.e., AEB), blind spot detection warning (i.e., BSD), auxiliary lane change warning (i.e., LCA), and reverse auxiliary warning (i.e., RCTA).

[0085] It can be found that the above embodiments are product embodiments corresponding to the method embodiments, and the above embodiments can be implemented in cooperation with the method embodiments. The related technical details mentioned in the method embodiments are still valid in the above embodiments, and in order to reduce repetition, they will not be described here. Correspondingly, the related technical details mentioned in the above embodiments can also be applied to the method embodiments.

[0086] In addition, the examples mentioned in the above embodiments can be freely combined, and any combination can be understood as an embodiment. The "embodiment" or "example" appearing at various positions in the specification does not necessarily mean the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. Those skilled in the art can understand that the embodiments described herein can be combined with other embodiments.

[0087] Those skilled in the art can understand that the above embodiments are specific embodiments for implementing the present application, and in actual applications, various changes can be made in form and details without departing from the spirit and scope of the present application.

Claims

1. A data processing method, characterized in that, include: In the i-th data processing cycle, the target storage location of the j-th data to be read is determined based on the correlation between the reading order and the writing order. i is an integer greater than 1, j = 1, 2, ..., Q, where Q is the total amount of data to be processed in each data processing cycle; the reading order and the writing order are not the same. Read the data located at the target storage location to obtain the j-th data to be read; Write the j-th data to be written in the i-th data processing cycle to the target storage location.

2. The data processing method according to claim 1, characterized in that, The correlation includes the correlation between the number of receiving antennas, the depth of the storage space, and the amount of data that can be stored at each physical address in the storage space.

3. The data processing method according to claim 2, characterized in that, The step of determining the target storage location of the j-th data to be read based on the correlation between the read order and the write order includes: Address=[(((R / P)^N)*k) / M]+(((R / P)^N)*k)%M, Where Address represents the target storage location, R is the number of receiving antennas, N represents the sequence number of the current data processing cycle, M represents the depth of the storage space, k represents the number of times the storage space is read, P is the multiple of the amount of data that can be stored at each address in the storage space relative to the total amount of data of the single-point antennas, N = 0, 1, 2, ..., k = 0, 1, 2, ...; [] represents the floor operation, and % represents the modulo operation.

4. The data processing method according to any one of claims 1 to 3, characterized in that, The amount of data that can be stored at each physical address in the storage space is an integer multiple of the number of receiving antennas.

5. The data processing method according to any one of claims 1 to 3, characterized in that, The step of writing the j-th data to be written in the i-th data processing cycle to the target storage location includes: After obtaining the (j+ts)th data to be read, the data from the (j-t+s)th data to the (j+ts)th data to be read in the i-th data processing cycle are written to their respective target storage locations, where s = k%t, t is an integer multiple of the amount of data that can be stored at each physical address in the storage space used for reading and writing, and % represents the modulo operation.

6. The data processing method according to any one of claims 1 to 3, characterized in that, The reading speed of the j-th data to be read is greater than or equal to the writing speed of the j-th data to be written.

7. The data processing method according to claim 6, characterized in that, The read bandwidth of the j-th data to be read is greater than or equal to the write bandwidth of the j-th data to be written.

8. An integrated circuit, characterized in that, include: The addressing module is used to determine the target storage location of the j-th data to be read in the i-th data processing cycle based on the correlation between the writing order and the reading order. i is a positive integer greater than 1, k = 1, 2, ..., Q, where Q is the total amount of data to be processed in each data processing cycle; the writing order and the reading order are not the same. The reading module is used to read data located at the target storage location to obtain the j-th data to be read; The writing module is used to write the j-th data to be written in the i-th data processing cycle to the target storage location.

9. A wireless device, characterized in that, include: Carrier; The integrated circuit as described in claim 8 is disposed on the carrier. An antenna is disposed on the carrier, or the antenna is integrated with the integrated circuit and disposed on the carrier. The integrated circuit is connected to the antenna and is used to process the received echo signal data.

10. A terminal device, comprising: Equipment body; as well as The wireless device as described in claim 9 is disposed on the device body; The wireless device is used for target detection to provide reference information for the operation of the device body.

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