Memory management method and memory controller

Abstract

The invention provides a memory management method and a memory controller. The method establishes a target logical section to manage a plurality of physical blocks in the memory module, where the host system is only accessible to the first logical section and the second logical section is inaccessible to the host system. According to the method, a first logic section is configured for first type data, a second logic section is configured for second type data, and mapping information of target data is recorded in a unified logic-to-entity mapping table. Different types of blocks subjected to traditional classification management are integrated into the same storage pool in a unified manner, so that storage space waste caused by upward alignment of all types of blocks to entity blocks is eliminated, the compatibility of FTL to large-capacity entity blocks is improved, meanwhile, mapping relation management is simplified, and the garbage collection operation efficiency is optimized.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of storage, and in particular, to a memory management method and a memory controller for using the same data block pool for user data and system data. BACKGROUND

[0002] A flash translation layer (FTL) is an important mechanism for managing physical blocks in a NAND flash memory. A conventional FTL divides the physical blocks into three independent types for management, namely, a data block for storing user data, a mapping block for storing mapping data of logical addresses and physical addresses, and a log block for storing log data generated in the FTL operation.

[0003] At present, with the increasing number of stacked layers of flash memory, the capacity of a single physical block is becoming larger and larger, which leads to a challenge in the compatibility of the conventional FTL for large physical blocks. SUMMARY

[0004] Therefore, the present disclosure provides a memory management method and a memory controller, which integrates the data blocks, mapping blocks, and log blocks managed by the conventional classification into the same storage pool for unified management, thereby eliminating the storage space waste caused by the respective types of blocks being respectively aligned to the physical blocks, and improving the compatibility of the FTL for large physical blocks.

[0005] One or more embodiments of the present disclosure provide a memory management method applied to a storage device configured with a memory module. The method comprises: establishing a target logical section to manage a plurality of physical blocks in the memory module, wherein the target logical section comprises a first logical section and a second logical section, and a host system connected to the storage device can only access the first logical section; configuring the first logical section for a first type of data, and configuring the second logical section for a second type of data; and when performing an access operation on target data, recording mapping information corresponding to the target data in a unified logical-to-physical mapping table according to the data type of the target data.

[0006] One or more embodiments of the present disclosure provide a memory controller for controlling a storage device configured with a memory module. The memory controller comprises a memory interface control circuit electrically connected to the memory module, and a processor electrically connected to the memory interface control circuit, wherein the processor is further electrically connected to a connection interface circuit of the storage device to be electrically connected to a host system. The processor is configured to: establish a target logical section to manage a plurality of physical blocks in the memory module, wherein the target logical section comprises a first logical section and a second logical section, and a host system connected to the storage device can only access the first logical section; configure the first logical section for a first type of data, and configure the second logical section for a second type of data; and when performing an access operation on target data, record mapping information corresponding to the target data in a uniform logical-to-physical mapping table according to a data type of the target data.

[0007] Based on the above, the memory management method and the memory controller provided by the present disclosure establish a target logical section management mechanism to integrate the data blocks, the mapping blocks, and the log blocks managed by the traditional classification management into the same storage pool for management, thereby eliminating the storage space waste caused by the upward alignment of each type of block to the physical block. The uniform management mechanism distinguishes between different data types by expanding the logical address space, so that the first type of data and the second type of data can share the same physical block space, thereby improving the utilization rate of the storage space. When the system calculates the total capacity requirement and performs upward rounding alignment, the number of physical blocks required is reduced compared to the traditional classification management method, thereby improving the compatibility of FTL with large-capacity physical blocks of flash memory. In addition, the establishment of the uniform logical-to-physical mapping table simplifies the management complexity of the mapping relationship. When performing a garbage collection operation, the system can more efficiently identify valid data and perform selective copying, thereby reducing unnecessary data migration operations. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a block schematic diagram of a host system and a storage device according to an embodiment of the present disclosure;

[0009] Figure 2 is a flowchart of a memory management method according to an embodiment of the present disclosure;

[0010] Figure 3 is a schematic diagram of a traditional memory management method;

[0011] Figure 4 is a schematic diagram of a target logical section architecture and a uniform data block pool according to an embodiment of the present disclosure;

[0012] Figure 5A diagram illustrating a unified logical-to-physical entity mapping table according to an embodiment of the present disclosure;

[0013] Figure 6 A diagram illustrating a data access flow according to an embodiment of the present disclosure;

[0014] Figure 7 A diagram illustrating a large unified logical-to-physical entity mapping table according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0015] Reference will now be made in detail embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

[0016] Figure 1 A block diagram of a host system and a storage device according to an embodiment of the present disclosure. Please refer to Figure 1 The host system 10 is, for example, a personal computer, a notebook computer, a server. The host system 10 includes a processor 110 (also referred to as a second processor) and a host memory 120 (also referred to as a host internal memory), a data transfer interface circuit 130. In this embodiment, the processor 110 is coupled to (also referred to as electrically connected to) the host memory 120 and the data transfer interface circuit 130. In another embodiment, the processor 110, the host memory 120 and the data transfer interface circuit 130 are electrically connected to each other by a system bus. In this embodiment, the processor 110, the host memory 120 and the data transfer interface circuit 130 can be disposed on a host board of the host system 10.

[0017] The storage device 20 includes a memory controller 210, a memory module 220 (also referred to as a rewritable non-volatile memory module), a connection interface circuit 230. The memory controller 210 includes a processor 211 (also referred to as a first processor), a data management circuit 212, a memory interface control circuit 213 and a buffer memory 214.

[0018] In this embodiment, the memory module 220 is a flash (NAND Flash) memory module, which includes a plurality of physical blocks, each of which has a fixed storage capacity. As the number of stacked layers of the flash increases, the capacity of a single physical block is constantly increasing, which poses a challenge to the traditional FTL management method. The memory management method proposed by the present disclosure can effectively solve the problem of storage space waste in the environment of large-capacity physical blocks by establishing a target logical section to uniformly manage different types of data.

[0019] In this embodiment, the host system 10 is electrically connected to the storage device 20 through the data transmission interface circuit 130 and the connection interface circuit 230 of the storage device 20 to perform data access operations. For example, the host system 10 can store data to the storage device 20 or read data from the storage device 20 via the data transmission interface circuit 130.

[0020] In this embodiment, the number of data transmission interface circuits 130 can be one or more. Through the data transmission interface circuit 130, the host board can be electrically connected to the storage device 20 via wired or wireless means. The storage device 20 can be, for example, a U disk, a memory card, a solid state drive (SSD), or a wireless memory storage device. The wireless memory storage device can be, for example, a near field communication (NFC) memory storage device, a wireless fidelity (WiFi) memory storage device, a Bluetooth memory storage device, or a Bluetooth low energy memory storage device (e.g., iBeacon) and other memory storage devices based on various wireless communication technologies. In addition, the host board can also be electrically connected to various I / O devices such as a global positioning system (GPS) module, a network interface card, a wireless transmission device, a keyboard, a screen, a loudspeaker, etc. through a system bus.

[0021] In this embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the peripheral component interconnect express (PCI Express) standard. Moreover, the data transmission between the data transmission interface circuit 130 and the connection interface circuit 230 is performed using the non-volatile memory express (NVMe) communication protocol.

[0022] In another embodiment, the connection interface circuit 230 can be packaged in a chip with the memory controller 210, or the connection interface circuit 230 is disposed outside a chip including the memory controller 210.

[0023] In the embodiment, the host memory 120 is used to temporarily store instructions or data executed by the processor 110. In the embodiment, the host memory 120 can be a dynamic random access memory (DRAM), a static random access memory (SRAM), or the like. However, it must be understood that the present disclosure is not limited thereto, and the host memory 120 can also be other suitable memories.

[0024] The memory controller 210 is used to execute a plurality of logic gates or control instructions implemented in a hardware type or a firmware type, and perform data writing, reading, and erasing operations in the memory module 220 according to instructions of the host system 10.

[0025] In more detail, the processor 211 in the memory controller 210 is a hardware with computing capability, which is used to control the overall operation of the memory controller 210. Specifically, the processor 211 is programmed by a plurality of control instructions / program codes, and when the memory device 20 operates, the control instructions / program codes are executed to perform data writing, reading, and erasing operations. In addition, the processor 211 is configured to execute the memory management method provided by the present disclosure.

[0026] In other embodiments, the control instructions / program codes corresponding to the data reading method can also be implemented as circuit units in a hardware form to realize the memory management method provided by the present disclosure.

[0027] It is worth mentioning that, in the embodiment, the processor 110 and the processor 211 are, for example, a central processing unit (CPU), a micro-processor, or other programmable processing units (Microprocessor), a digital signal processor (DSP), a programmable controller, an application specific integrated circuit (ASIC), a programmable logic device (PLD), or other similar circuit components, and the present disclosure is not limited thereto.

[0028] In this embodiment, as mentioned above, the memory controller 210 further comprises a data management circuit 212 and a memory interface control circuit 213. It should be noted that the operations performed by the components of the memory controller 210 can also be considered as operations performed by the memory controller 210.

[0029] The data management circuit 212 is electrically connected to the processor 211, the memory interface control circuit 213 and the connection interface circuit 230. The data management circuit 212 is configured to accept instructions from the processor 211 for data transfer. For example, data is read from the host system 10 (e.g. the host memory 120) via the connection interface circuit 230 and the read data is written into the memory module 220 via the memory interface control circuit 213 (e.g. according to write instructions from the host system 10 for corresponding write operations). For another example, according to read instructions from the host system 10 for read operations, data is read from one or more physical units of the memory module 220 (the data can be read from one or more memory cells of the one or more physical units) via the memory interface control circuit 213 and the read data is written into the host system 10 (e.g. the host memory 120) via the connection interface circuit 230. In another embodiment, the data management circuit 212 can also be integrated into the processor 211.

[0030] The memory interface control circuit 213 is configured to accept instructions from the processor 211 for write (also referred to as programming), read or erase operations to the memory module 220 in cooperation with the data management circuit 212.

[0031] In addition, data to be written into the memory module 220 is converted into a format acceptable by the memory module 220 via the memory interface control circuit 213. Specifically, if the processor 211 wants to access the memory module 220, the processor 211 transmits corresponding instruction sequences to the memory interface control circuit 213 to instruct the memory interface control circuit 213 to perform corresponding operations. For example, the instruction sequences can include write instruction sequences for instructing write data, read instruction sequences for instructing read data, erase instruction sequences for instructing erase data, and corresponding instruction sequences for instructing various memory operations. The instruction sequences can include one or more signals, or data on a bus. The signals or data can include instruction codes or program codes. For example, in the read instruction sequences, identification codes of read, memory addresses, physical addresses and the like information are included.

[0032] In addition, the memory controller 210 can establish a mapping table to record the mapping information between the logical addresses and the physical addresses. In conventional memory management, the memory controller usually establishes a logical to physical address mapping table and a physical to logical address mapping table to find the physical unit (e.g. physical erase unit / physical block, physical page) mapped by a logical unit (e.g. logical block, logical page) and to find the logical unit mapped by a physical unit, respectively. In addition, the physical to logical address mapping table can also be used to determine the valid data and the invalid data in a specific physical block. In another embodiment, each logical to physical mapping record in the logical to physical mapping table includes a data type field, a logical address field and a physical address field; and each physical to logical mapping record in the physical to logical mapping table includes a data type field, a logical address field and a physical address field.

[0033] However, in the present disclosure, the memory controller 210 establishes a unified logical to physical address mapping table to record the mapping information between the logical addresses in the target logical section and the physical addresses in the memory module 220. The design of the unified logical to physical address mapping table is more simplified, and there is no need to store an additional data type field because the processor 211 can directly determine the data type by analyzing the logical address range to which the target logical address belongs. Specifically, when the target logical address is located in the first logical section, it corresponds to the first type of data; when the target logical address is located in the first sub-section of the second logical section, it corresponds to the mapping table data; and when the target logical address is located in the second sub-section of the second logical section, it corresponds to the log data. In other words, the memory controller 210 can use the unified logical to physical address mapping table to find the physical address mapped by any logical address in the target logical section, and at the same time determine the data type corresponding to the logical address according to the range characteristics of the logical address, thereby achieving unified and efficient management of different types of data.

[0034] The buffer memory 214 is electrically connected to the processor 211 and is used to temporarily store data and instructions from the host system 10, data from the memory module 220, and various system data for managing the storage device 20.

[0035] In this embodiment, the buffer memory 214 is configured to provide the required cache resource and system data (e.g. the unified logical-to-physical mapping table and related logical-to-physical mapping tables or physical-to-logical mapping tables, etc.) when the processor 211 performs the memory management method of the present disclosure. Specifically, when the processor 211 establishes the target logical section and performs the unified mapping management, the buffer memory 214 is used to temporarily store the unified logical-to-physical mapping table and temporary data from the first type of data and the second type of data. In addition, when part of the logical-to-physical mapping table or the physical-to-logical mapping table is activated (needs to be accessed), the processor 211 reads and caches these activated mapping tables to the buffer memory 214. On the other hand, the buffer memory 214 is also configured to provide a temporary storage space during the garbage collection operation to ensure that the valid data can be successfully copied from the source physical block to the target physical block.

[0036] The processor 211 is configured to establish a target logical section to manage a plurality of physical blocks in the memory module 220, which can be managed as a same unified data block pool. The processor 211 allocates the first type of data to the first logical section and the second type of data (including mapping table data and log data) to the second logical section according to the data type from the host system 10. The processor 211 is also configured to maintain a unified logical-to-physical mapping table to record the mapping relationship between each logical address in the target logical section and the physical address in the memory module 220 (each physical address of the unified data block pool).

[0037] The memory module 220 is electrically connected to the memory controller 210 (specifically to the memory interface control circuit 213) and is used to store the user data sent by the host system 10.

[0038] Specifically, the memory module 220 includes a plurality of chips, each of which is further subdivided into a plurality of planes, and each plane contains a plurality of physical blocks. In addition, each physical block in the memory module 220 also includes a plurality of physical pages, each of which contains a plurality of storage units. It should be noted that the present disclosure is not limited to the size of each physical page and logical page.

[0039] Figure 2 is a flowchart of the memory management method according to the embodiment of the present disclosure. Referring to Figure 2 In an embodiment, the memory management method provided by the present disclosure includes the following main flow steps:

[0040] First, in step S210, the processor 211 of the memory controller 210 establishes a target logical section to manage a plurality of physical blocks in the memory module 220.

[0041] In an embodiment, the target logical section adopts a dual-section architecture design, including a first logical section and a second logical section, wherein the host system 10 connected to the storage device 20 can only access the first logical section.

[0042] In an embodiment, in the address space configuration strategy, the processor 211 determines the overall size range of the target logical section according to the total capacity specification of the memory module 220 and the system estimated data type distribution requirement. The first logical section is specially configured as the accessible area of the host system 10, containing a plurality of user logical addresses arranged continuously, for carrying data access requests from the host system 10. The second logical section is set as the inaccessible area of the host system 10, whose address range is arranged continuously after the maximum logical address of the first logical section, forming a unified and orderly target logical section architecture.

[0043] In an embodiment, in order to realize more fine-grained system data management, the processor 211 further divides the second logical section into a first sub-section and a second sub-section. The first sub-section includes a plurality of mapping table logical addresses, which are specially used for the storage management of mapping table data, and the starting mapping table logical address is accurately positioned based on a first preset offset value. The second sub-section includes a plurality of log logical addresses, which are specially used for the storage management of log data, and the starting log logical address is determined based on a second preset offset value. It should be noted that in another embodiment, the order of the first sub-section and the second sub-section can be reversed.

[0044] Then, in step S220, the processor 211 performs a data type-oriented logical section configuration operation.

[0045] Specifically, the system configures the first logical section to the first type of data and configures the second logical section to the second type of data, establishing a clear data type and address space correspondence.

[0046] In an embodiment, the first type of data mainly covers user data, i.e. application layer data content from the host system 10. The second type of data includes two key components, mapping table data and log data. The mapping table data is responsible for recording the detailed mapping relationship between a plurality of logical addresses of part of the logical section in the target logical section and the corresponding entity addresses, providing an index basis for data positioning. The log data is responsible for recording the storage module 220 operation state information involving a specific logical address, including operation history, performance indicators and system events, and other key management parameters.

[0047] In an embodiment, the processor 211 divides the first logical section into a plurality of fixed-size logical address segments, each of which corresponds to a mapping table logical address in the first sub-section, which is used to store mapping information of a plurality of logical addresses of the corresponding logical address segment, so as to establish a hierarchical mapping management mechanism. For example, the mapping information can be read from the entity address mapped to the mapping table logical address.

[0048] In step S230, when performing an access operation on the target data, the processor 211 records the mapping information of the target data in the unified logical-to-physical mapping table according to the data type of the target data. The "at least" expression herein embodies the technical feature that the system adopts a differentiated mapping recording strategy for different data types.

[0049] In an embodiment, the processor 211 determines the data type of the target data by analyzing the logical address range to which the target logical address belongs: when the target logical address is located in the first logical section, it is determined that the data type of the target data is the first type of data; when the target logical address is located in the first sub-section, it is determined that the data type of the target data is mapping table data; and when the target logical address is located in the second sub-section, it is determined that the data type of the target data is log data.

[0050] In more detail, when the target data belongs to the second type of data (mapping table data or log data), the processor 211 only needs to directly record a piece of mapping information in the unified logical-to-physical mapping table. For example, when the system needs to store log data to the entity address PBA606, the processor 211 records the mapping relationship between the logical address LBA606 of the log data and the entity address PBA606 in the unified logical-to-physical mapping table. In this case, the system only needs to record one layer of mapping information to complete the data positioning requirement.

[0051] However, when the target data belongs to the first type of data (user data), the processor 211 needs to perform a multi-layer mapping recording operation. First, the processor 211 determines the logical address segment to which the target logical address belongs according to the predetermined segmentation rule. For example, when the target logical address of the user data is LBA001, the system determines that the logical address belongs to the first logical address segment (LBA000-LBA099) in the first logical section, which corresponds to the mapping table logical address LBA600 in the first sub-section.

[0052] Next, the processor 211 records the mapping relationship between user data LBA001 and its allocated entity address PBA001 in the corresponding logical-to-entity mapping table, which is stored at entity address PBA600. Subsequently, the processor 211 must also record the storage location mapping relationship of the logical-to-entity mapping table itself in the unified logical-to-entity mapping table, that is, record the mapping relationship between the mapping table logical address LBA600 of the corresponding logical-to-entity mapping table and the entity address PBA600 where the logical-to-entity mapping table is stored.

[0053] Through this two-layer mapping recording mechanism, the processor 211 not only records the direct mapping relationship of LBA001→PBA001 in the logic-to-entity mapping table, but also records the mapping table storage location relationship of LBA600→PBA600 in the unified logic-to-entity mapping table. This design enables the system to locate the corresponding hierarchical mapping table through the unified logic-to-entity mapping table, and then obtain the specific entity address of the user data from the hierarchical mapping table.

[0054] It should be noted that the actual numerical format of the physical address PBA001 can be determined by the system settings of the storage device 20. The physical address PBA001 does not represent a physical address ordered as 001, but only represents a physical address mapped to LBA001.

[0055] In another embodiment, if using Figure 7 In a specific embodiment of the large unified logic-to-entity mapping table UL2P' shown, the mapping information recording mechanism is further simplified. Under this architecture, regardless of whether the target data belongs to the first type of data or the second type of data, the processor 211 only needs to record a single level of mapping information in the large unified logic-to-entity mapping table UL2P'.

[0056] Specifically, when user data LBA001 needs to be stored in entity address PBA001, the system directly records the mapping relationship between LBA001 and PBA001 in the large unified logical-to-entity mapping table UL2P', without having to maintain intermediate-level mapping table data or its corresponding mapping records.

[0057] Similarly, system data such as log data LBA698 is also directly recorded in the large unified logical-to-entity mapping table UL2P', showing the mapping relationship from LBA698 to PBA698. This single-level mapping design eliminates the complexity of multi-level mapping records, enabling the mapping information of all data types to be managed through a unified recording mechanism. This further simplifies the system's mapping table maintenance operations and improves the directness of data access.

[0058] In summary, the innovative address range identification technique described above brings efficiency to the system. Since the processor 211 is able to determine the data type directly from the numerical range of the logical address, the design of the unified logical-to-physical mapping table becomes more concise, and there is no need to configure an additional data type identification field for each mapping record, thereby saving storage space and speeding up the lookup.

[0059] In an embodiment, in an actual data access operation, when the host system 10 needs to read a specific data in the first logical segment, the processor 211 first applies the pre-set segmentation algorithm to determine which logical address segment the target logical address belongs to, and then the system automatically locates the mapping table logical address corresponding to the address segment in the first sub-segment.

[0060] Through this mapping table logical address, the processor 211 is able to find the physical location where the related mapping information is stored, and read the detailed mapping table data therefrom. Finally, the system uses these mapping table data to accurately locate the physical address corresponding to the target logical address, and completes the accurate access to the target data.

[0061] Figure 3 A schematic diagram of a conventional memory management method.

[0062] Referring to Figure 3 In another embodiment, in order to better understand the advantages of the technical solutions of the present disclosure, the architectural features of the conventional memory management method and the technical defects thereof are described below.

[0063] In the conventional flash translation layer management architecture, the system adopts a strict classification management strategy to handle different types of data. As shown in Figure 3 The conventional solution divides the physical blocks in the memory module into three independent data block pools: a user data block pool DBP, a mapping table data block pool MBP, and a log data block pool LBP. Each data block pool is responsible for managing its corresponding type of data, and maintains an independent operation mode from each other. Figure 3 The arrows between the multiple physical addresses and the multiple logical addresses in the user data block pool represent the mapping relationship.

[0064] In the conventional logical address space configuration, the host system can only use the logical address range pre-allocated to the user data, which is usually managed through a logical block address group LBAG having multiple logical addresses. The system does not allocate a dedicated logical address space for the mapping table data and the log data, but uses an independent indexing mechanism to manage these internal system data.

[0065] Specifically, when the system needs to store user data, the flash translation layer allocates the data into available physical blocks in the user data block pool DBP and establishes the corresponding logical-to-physical address mapping. At the same time, in order to record and maintain these mapping relationships, the system needs to store the mapping table data separately in the physical blocks in the mapping table block pool MBP. In addition, various state information and operation records generated by the flash translation layer during operation are classified as log data and are stored in the log data block pool LBP.

[0066] However, this traditional classification management method exposes a serious space utilization efficiency problem when facing large-capacity physical blocks. Since each data block pool needs to be rounded up to the size of a complete physical block according to its actual capacity requirement, when the capacity of a single physical block becomes large, a large amount of space may be wasted in each pool.

[0067] For example, even if the mapping table data only needs a capacity of 0.3 physical blocks, the system still has to allocate a complete physical block to it, and the remaining 0.7 physical block capacity is idle and wasted. The same problem also occurs in the management of the log data block pool LBP and the user data block pool DBP, resulting in low overall storage space utilization and affecting the compatibility of the flash translation layer with large-capacity physical block flash devices.

[0068] Figure 4 A schematic diagram of the target logical segment architecture and the unified data block pool according to an embodiment of the present disclosure.

[0069] Reference Figure 4 In an embodiment, the present disclosure uses a unified storage pool in combination with the management architecture of a target logical segment to solve the space waste problem of traditional classification management. As shown in Figure 4 As shown in the upper half, the target logical segment established by the processor 211 includes two main address ranges: the first logical segment LAS1 and the second logical segment LAS2.

[0070] Among them, the first logical segment LAS1 is completely open to the host system 10, allowing the host system 10 to perform normal data access operations in this range. In contrast, the second logical segment LAS2 is completely hidden from the access authority of the host system 10 and is used exclusively for the internal management needs of the memory controller 210. Of course, the memory controller 210 can access the target logical segment, whether the first logical segment LAS1 or the second logical segment LAS2. Figure 4 The arrows between the multiple physical addresses and the multiple logical addresses in the unified data block pool UDBP represent the mapping relationship.

[0071] In the internal architecture of the second logical section LAS2, the processor 211 further subdivides it into two sub-sections: a first sub-section LSS1 and a second sub-section LSS2. In an embodiment, the first sub-section LSS1 is tasked with address allocation of the mapping table data, whose starting address is precisely located by a first preset offset value, ensuring a proper address interval from the first logical section LAS1. The second sub-section LSS2 is then exclusively responsible for address management of the log data, whose starting address is calculated based on a second preset offset value, forming an orderly and non-interfering address space layout.

[0072] In the design of the address allocation priority sequence, the processor 211 arranges the first sub-section LSS1 to process the mapping table data before the second sub-section LSS2, which is based on the predictable feature of the capacity requirement of the mapping table data.

[0073] Specifically, the capacity requirement of the mapping table data is usually directly related to the total capacity of the memory module 220 and the preset mapping granularity, so the required storage space can be accurately calculated during the system initialization phase, which belongs to a relatively fixed capacity requirement. In contrast, the amount of log data generated varies with factors such as system running state, write mode, and garbage collection frequency, and has strong dynamic characteristics.

[0074] The mapping table data managed by the first sub-section LSS1 covers various types of address mapping information, including logical-to-physical mapping table data, physical-to-logical mapping table data, and other auxiliary mapping table data for optimizing data access paths, which collectively form the core index architecture of the memory management system. After storing each mapping table data to a physical address, the processor 211 can assign a logical address in the first sub-section LSS1 to allow the processor 211 to access the stored mapping table data through this logical address later.

[0075] Of course, in another embodiment, the first sub-section LSS1 can be changed to be responsible for address management of the log data; the first sub-section LSS1 can be changed to be responsible for address allocation of the mapping table data.

[0076] In the implementation of the storage architecture, the present disclosure adopts a unified data block pool UDBP to replace the traditional multiple independent data block pools. Each physical block in the unified data block pool UDBP, as shown in block B40, has the ability to accommodate multiple data types simultaneously. This design breaks the strict binding relationship between data types and storage locations in traditional solutions, allowing user data, mapping table data, and log data to be stored in multiple physical pages of the same physical block.

[0077] As Figure 4As shown in the detailed example of the lower half, as indicated by block B40, the unified data block pool UDBP allows mixed storage of various data types. For example, user data 10 is stored at location entity address 0x0001, corresponding to logical address LBA000; immediately following, mapping table data 1 is stored at location 0x0002, corresponding to logical address LBA600; then, user data 20 is stored at location 0x0003, corresponding to logical address LBA001; and at location 0x0004, log data 1 is stored, corresponding to logical address LBA606. This cross-mixed storage mode fully utilizes the storage space of each entity block, avoiding the problem of space fragmentation caused by type separation in traditional schemes.

[0078] Through this unified management architecture, the processor 211 can dynamically allocate storage space according to actual capacity requirements, without being limited by data types. When the demand for a certain type of data increases, the system can flexibly find available space in the unified data block pool UDBP, without considering the capacity limitations between various independent pools in traditional schemes. This design not only improves the utilization efficiency of storage space, but also enhances the adaptability of the system to different workloads.

[0079] In an embodiment, the memory management method of the present disclosure first performs a system compatibility pre-evaluation mechanism before establishing the target logical section, to ensure that the memory management method can effectively match the target memory module.

[0080] Specifically, the processor 211 performs a data type-oriented capacity demand analysis operation according to the demand information sent by the host system 10. Specifically, the host system 10 sends demand information containing storage configuration requirements to the storage device 20 through the connection interface circuit 230, which details the system's expectations for storage capacity of different data types.

[0081] The processor 211 determines the first capacity demand and the second capacity demand corresponding to the first type of data and the second type of data, respectively, by analyzing the demand information. The first capacity demand mainly reflects the actual need of the host system 10 for user data storage space, which is usually determined based on the data size of the application program, the expected data growth rate, and the user's storage configuration preferences. The second capacity demand covers the storage space requirements of mapping table data and log data, which is usually directly related to the address space size of the memory module 220, the mapping granularity setting, and the system log recording strategy.

[0082] In an embodiment, after obtaining the capacity requirements of various types of data, the processor 211 determines the total capacity requirement by merging the first capacity requirement and the second capacity requirement in a unified calculation manner. The core advantage of this unified calculation strategy is to integrate the independent capacity calculation in the traditional classification management into a single overall demand evaluation, thereby providing a basis for subsequent unified alignment operations.

[0083] Through this pre-evaluation mechanism, the processor 211 can determine the compatibility status of the memory management method and the specific memory module 220 before system deployment. When the compatibility evaluation result is a positive match, the system continues to perform the establishment operation of the target logical section; when the evaluation result shows that the capacity is insufficient, the processor 211 can adjust the capacity allocation strategy or suggest using a larger capacity memory module.

[0084] By merging the capacity requirements of different types of data and performing unified alignment, the compatibility evaluation mechanism of the present disclosure can reduce the waste of storage space caused by multiple independent upward rounding.

[0085] In more detail, in an embodiment, during the implementation of the compatibility evaluation mechanism, the processor 211 uses a comprehensive capacity analysis method to ensure the matching between the memory management method and the memory module 220.

[0086] First, the processor 211 obtains the user data capacity requirement, the mapping table data capacity requirement, and the log data capacity requirement, which are three key parameters. The user data capacity requirement is usually determined according to the configuration requirements of the host system 10, the mapping table data capacity requirement is calculated based on the address space size and mapping granularity of the memory module 220, and the log data capacity requirement considers the amount of state information that needs to be recorded during system operation.

[0087] Next, the processor 211 merges the capacity requirements of the three types of data to obtain a unified total capacity requirement value. This total capacity requirement reflects the actual storage space size required under the unified data block pool UDBP architecture. Subsequently, the processor 211 rounds up the total capacity requirement based on the entity block capacity of each entity block in the memory module 220, and calculates the actual number of entity blocks required by the system.

[0088] Finally, the processor 211 compares the calculated required entity block quantity with the total number of available entity blocks of the memory module 220, to evaluate the compatibility of the memory management method of the present disclosure and the specific memory module 220.

[0089] The evaluation mechanism can identify potential capacity mismatching issues in advance before system deployment, ensuring that the memory management system can run stably on the target hardware platform. Compared with the traditional classification management mode, the unified data block pool (UDBP) architecture of the present disclosure can effectively solve the problem of space waste caused by upward alignment.

[0090] Taking specific numerical values as an example, it is assumed that the memory module 220 contains 10 physical blocks, each with a capacity of 10 MB, and the system needs to manage 81 MB of user data, 8 MB of mapping table data, and 5 MB of log data.

[0091] In the traditional scheme, the user data needs to be upwardly aligned to 90 MB (9 physical blocks), the mapping table data needs to be aligned to 10 MB (1 physical block), the log data needs to be aligned to 10 MB (1 physical block), and in addition, 30 MB of reserved space (3 physical blocks) is needed, totaling 140 MB (14 physical blocks), which exceeds the available capacity of 100 MB.

[0092] However, when using the unified data block pool (UDBP) architecture, the processor 211 only needs to upwardly align the total capacity requirement of 94 MB (81+8+5) to 100 MB (10 physical blocks), which exactly matches the available capacity of the memory module 220, thereby successfully achieving compatibility matching. This unified management mode eliminates the redundant overhead of independent alignment of each type of data, enabling the system to support larger capacity physical block configurations.

[0093] Figure 5 A schematic diagram of a unified logical-to-physical mapping table according to an embodiment of the present disclosure.

[0094] Referring to Figure 5 In another embodiment, the present disclosure shows a detailed segmentation architecture of the target logical section and a specific implementation of the unified logical-to-physical mapping table (UL2P).

[0095] As Figure 5 As shown in the upper half, in an embodiment, the processor 211 further divides the first logical section LAS1 into a plurality of fixed-size logical address sections, including LAS11, LAS12, LAS13, LAS14, LAS15, and LAS16, etc. Each logical address section covers 100 consecutive logical addresses, for example, LAS11 corresponds to LBA000 to LBA099, LAS12 corresponds to LBA100 to LBA199, and so on until LAS16 corresponds to LBA500 to LBA599. This fixed-size segmentation strategy provides a basic architecture for hierarchical management of the mapping table.

[0096] In one embodiment, in the configuration of the second logical section LAS2, the processor 211 arranges the starting positions of the two sub-sections according to pre-set offset value rules. The first sub-section LSSl starts from logical address LBA 600 and is dedicated for storing mapping table data, while the second sub-section LSS2 starts from logical address LBA 606 and is dedicated for storing log data. Each mapping table logical address in the first sub-section LSSl corresponds to a specific logical address segment in the first logical section LASl, for example, logical address LBA 600 corresponds to the mapping table data of LASl l, LBA 601 corresponds to the mapping table data of LAS 12, and so on.

[0097] Specifically, in the actual configuration as shown in Figure 5 the first pre-set offset value and the second pre-set offset value embody the precise planning strategy of the system address space. In this embodiment, the address range of the first logical section LASl covers LBA 000 to LBA 599, a total of 600 logical addresses. The processor 211 sets the first pre-set offset value as 600, so that the starting mapping table logical address of the first sub-section LSSl is determined as LBA 600 (i.e. LBA 000 + 600). The selection of this offset value ensures that the first sub-section LSSl is immediately after the first logical section LASl, avoiding the problem of gap or overlap of address space.

[0098] In another embodiment, the first pre-set offset value is set as 1, so that the starting mapping table logical address of the first sub-section LSSl is determined as the last logical address LBA 599 of the first logical section LASl plus the first pre-set offset value "1", i.e. LBA 600 (599 + 1 = 600).

[0099] In one embodiment, for the configuration of the second sub-section LSS2, the processor 211 takes into account the address space capacity required by the first sub-section LSSl. In this embodiment, the first sub-section LSSl requires 6 logical addresses (LBA 600 to LBA 605) to correspond to the 6 fixed size logical address segments (LASl l to LAS 16) in the first logical section LASl. Therefore, the processor 211 sets the second pre-set offset value as 606 (i.e. 600 + 6), so that the starting log logical address of the second sub-section LSS2 is determined as LBA 606.

[0100] In another embodiment, the second pre-set offset value is set as 7, so that the starting mapping table logical address of the second sub-section LSS2 is determined as the last logical address LBA 599 of the first logical section LASl plus the second pre-set offset value "7", i.e. LBA 606 (599 + 7 = 606). It should be noted that the second pre-set offset value can be set corresponding to the pre-set length of the first sub-section.

[0101] In an embodiment, in the design of the segmentation rule of the mapping table data, the processor 211 adopts an adaptive configuration mechanism to optimize the storage efficiency. Specifically, the determination of the segmentation size is based on the calculation of the storage density of the mapping information and the capacity characteristics of the physical address.

[0102] Assuming that each piece of mapping information requires 4 bytes of storage space, and the available storage capacity of a single physical address is 400 bytes, then the physical address can accommodate a maximum of 100 pieces of mapping information (400 ÷ 4 = 100). In this configuration, the processor 211 sets the value of N to 100, so that each logical address segment contains exactly 100 logical addresses, ensuring that the corresponding mapping table data can be completely stored in a single physical address.

[0103] This segmentation standard based on capacity matching not only maximizes the utilization of storage space, but also simplifies the reading operation of the mapping table, because the system only needs to access one physical address to obtain the complete logical address segment mapping information. When the storage environment or the mapping information format changes, the processor 211 can dynamically adjust the value of N to maintain the optimal match between the segmentation strategy and the hardware characteristics.

[0104] This capacity-demand-based offset value calculation method ensures that the address allocation between each subsegment is continuous and does not interfere with each other, providing a reliable infrastructure for subsequent address range identification and data type judgment. Through this preset offset value mechanism, the system can quickly determine the segment type to which any logical address belongs at runtime, thereby achieving efficient data management operations.

[0105] The unified logical-to-physical mapping table UL2P adopts a simplified data structure design, containing only logical address fields and physical address / mapping address fields, without additional data type identification fields. The processor 211 automatically determines the data type by analyzing the value range of the logical address: when the logical address is in the range of LBA000 to LBA599, the system identifies it as the first type of data; when the logical address is in the range of LBA600 to LBA605, the system identifies it as mapping table data; when the logical address is in the range of LBA606 and its subsequent range, the system identifies it as log data.

[0106] In specific data access operations, the present disclosure implements a multi-layer mapping management mechanism. As shown by arrow A50, when the host system 10 needs to access the target data of logical address LBA001, the processor 211 first determines that LBA001 belongs to logical address segment LAS11 according to the preset segmentation rule, and then determines that the corresponding target mapping table logical address is LBA600.

[0107] In another embodiment, the unified logical-to-physical mapping table UL2P can record the logical address of the corresponding mapping table (e.g., "(LBA600)" of the mapping table corresponding to logical address LBA001) in the physical address (or referred to as mapping address) field corresponding to the first logical segment. When reading from the physical address (or referred to as mapping address) to LBA600, the processor 211 can recognize that the corresponding mapping table data at logical address LBA600 needs to be read to find the real physical address corresponding to logical address LBA001.

[0108] Then, as shown by arrow A51, the processor 211 then checks whether the mapping table data corresponding to LBA600 has been loaded in the buffer memory 214. If the buffer memory 214 does not contain the required mapping table, as shown by arrow A52, the processor 211 will find the physical address PBA600 corresponding to logical address LBA600 through the unified logical-to-physical mapping table UL2P, and read the mapping table L2P1 from the physical address. After obtaining the mapping table L2P1, the processor 211 can find the specific physical address mapped by logical address LBA001 through the mapping table, and complete the accurate positioning of the target data.

[0109] For the acquisition of log data, as shown by arrow A53, when the system needs to access specific log data LOG1, the processor 211 directly finds the corresponding log logical address, for example, LBA606, through the unified logical-to-physical mapping table UL2P. As shown by arrow A54, the system then locates the corresponding physical address PBA606, and reads the required log data LOG1 from the location. This unified mapping management manner enables the access operations of different types of data to be implemented through the same mapping table structure, and simplifies the overall architecture complexity of the system.

[0110] Figure 6 FIG. 2 shows a schematic diagram of a data access flow according to an embodiment of the present disclosure.

[0111] Referring to Figure 6 In another embodiment, the present disclosure shows a complete data access flow, and details how to achieve accurate positioning and acquisition of target data through a hierarchical mapping mechanism.

[0112] [Mapping table data acquisition phase]

[0113] When the host system 10 initiates a data access request for the logical address LBA001, the processor 211 first performs a mapping table locating operation. As shown by arrow A61, the system determines that the LBA001 belongs to the management scope of the first sub-section LSS1, and calculates the corresponding target mapping table logical address as LBA600 through the preset segmentation rule. As shown by arrow A62, the processor 211 then looks up the physical address PBA600 corresponding to the logical address LBA600 through the unified logical-to-physical mapping table, and reads the mapping table data L2P1 from the physical location. This mapping table L2P1 contains detailed mapping information of all logical addresses in the logical address section LAS11 (LBA000 to LBA099).

[0114] [Target data locating phase]

[0115] After obtaining the mapping table L2P1, as shown by arrow A63, the processor 211 searches for the mapping record of the logical address LBA001 in the mapping table. As shown by arrow A64, through the lookup operation of the mapping table L2P1, the system determines that the physical address corresponding to the logical address LBA001 is PBA001. This two-stage mapping resolution mechanism realizes accurate conversion from a logical address to a physical address, and provides accurate physical positioning information for subsequent data reading operations.

[0116] [Target data reading phase]

[0117] After the address conversion is completed, as shown by arrow A65, the processor 211 instructs the memory interface control circuit 213 to read the target data TD from the physical address PBA001. The entire data access flow is implemented through the architecture of the unified data block pool DBP, which embodies the technical advantages of the unified management mechanism of the present disclosure. After the target data TD is successfully read, the system transmits it to the host system 10, and completes the entire data access operation.

[0118] [Log data reading mechanism]

[0119] For the reading operation of the log data, the present disclosure provides a more direct access path. When the system needs to access specific log information, the processor 211 directly locates the corresponding log logical address in the second sub-section LSS2, for example, LBA606. As shown by arrow A66, the system determines the corresponding physical address PBA606 through the unified logical-to-physical mapping table, and directly reads the log data LOG from the location as shown by arrow A67. Since the log data does not require an additional mapping table level, its access flow is relatively simplified, which improves the efficiency of obtaining system state information. This differentiated access strategy fully considers the characteristic requirements of different data types, optimizes the access performance of various data while maintaining the unified management architecture.

[0120] Through the complete data access process described above, the memory management method of the present disclosure realizes unified and efficient management of all data types, while ensuring the accuracy and reliability of data access through the hierarchical mapping mechanism.

[0121] Figure 7 A schematic diagram of a large unified logical-to-physical mapping table according to another embodiment of the present disclosure.

[0122] Referring to Figure 7 In another embodiment, the present disclosure provides an alternative implementation of a large unified logical-to-physical mapping table UL2P', which uses a single mapping table architecture to simplify the mapping management complexity of the system.

[0123] Unlike the aforementioned hierarchical mapping mechanism, the processor 211 in this embodiment establishes a large unified logical-to-physical mapping table UL2P' that directly contains mapping information for all logical addresses in the target logical section, without the need for intermediate-level mapping table lookup operations. The large unified logical-to-physical mapping table UL2P' uses a linear organization structure to sequentially record the mapping relationship between each logical address and its corresponding physical address in increasing order of logical address.

[0124] In terms of address space configuration strategy, the processor 211 maintains the segmented architecture of the first logical section LAS1 and the second logical section LAS2. It should be noted that the second logical section LAS2 is configured as a storage area for system data, and is no longer subdivided into a first sub-section and a second sub-section, but directly accommodates mapping table data, log data, and other types of data required for system management.

[0125] In terms of data access operation implementation, this embodiment provides a more direct mapping lookup path. As shown by arrow A70, when the host system 10 needs to access data at logical address LBA000, the processor 211 directly retrieves the mapping record corresponding to this logical address in the large unified logical-to-physical mapping table UL2P', without the need for intermediate resolution steps for mapping table logical addresses. As shown by arrow A71, the system immediately obtains the physical address PBA000 corresponding to the logical address LBA000, and directly reads the target data TD from this physical location. This single-step mapping resolution mechanism eliminates the time overhead of multi-layer lookup, improving the response speed of data access.

[0126] For access operations on system data, the embodiment also adopts a direct mapping approach. As shown by arrow A72, when the system needs to obtain the entity-to-logical mapping table P2L data of logical address LBA600, the processor 211 directly looks up the mapping record of the logical address in the large unified logical-to-entity mapping table UL2P'. As shown by arrow A73, the system determines the corresponding entity address PBA600 and reads the entity-to-logical mapping table P2L1 from the location. Similarly, as shown by arrow A74, the access operation of the log data is implemented by directly looking up the mapping record of logical address LBA698, and as shown by arrow A75, the system reads the log data LOG1 from the corresponding entity address PBA698.

[0127] The large unified logical-to-entity mapping table UL2P' architecture of the embodiment has specific technical advantages in certain application scenarios. First, the single mapping table structure simplifies the logical complexity of mapping management and reduces the number of mapping tables that the system needs to maintain. Second, the direct mapping access mechanism eliminates the processing steps of multi-layer lookup and can provide better access performance under workloads that frequently perform small-range random access.

[0128] However, this implementation also needs to consider the configuration requirements of memory resources. Since the large unified logical-to-entity mapping table UL2P' needs to maintain the mapping information of all logical addresses at the same time, the required memory space will increase compared to the hierarchical mapping approach. Therefore, when selecting the mapping table architecture, the processor 211 will comprehensively evaluate factors such as the memory capacity of the system, the access pattern characteristics, and the performance requirements to determine the most suitable implementation for the specific application environment.

[0129] It is worth mentioning that in a modified embodiment, the processor 211 adopts a hybrid mapping table management strategy to balance the memory usage efficiency and access performance requirements. Specifically, the processor 211 establishes a corresponding segmented unified mapping table UL2P' for each fixed-size logical address segment (such as LAS11-LAS16) in the first logical segment LAS1, and each segmented unified mapping table UL2P' only contains complete mapping records within its corresponding logical address segment range.

[0130] In addition, the system data involved in the plurality of logical addresses of the second logical section of the segment-uniform mapping table UL2P' is also associated with the corresponding logical address section. Specifically, the processor 211 employs a segment-association management strategy to centrally configure the system data related to a specific logical address section in the second logical section LAS2. For example, the plurality of logical addresses of the second logical section of the segment-uniform mapping table corresponding to the logical address section LAS11 are used for the system data related to the plurality of logical addresses LBA000-LBA099 of the logical address section LAS11 (such as the physical-to-logical mapping table data of the section, the garbage collection log, the wear leveling record, etc.). Because, when reading the user data of the logical address section LAS11, there is a high probability of accessing the corresponding system data. By configuring the logical addresses of the related system data in the same segment-uniform mapping table, the processing efficiency of the system can be improved.

[0131] In another embodiment, when the processor 211 loads the segment-uniform mapping table UL2P' corresponding to the logical address section LAS11, the system simultaneously loads the system data related to the section into the buffer memory 214, including the state record of the physical blocks within the range of LAS11, the P2L mapping information of the section, and the related operation log data. This associated loading mechanism ensures that all necessary system data is ready when processing various operations of a specific logical address section, avoiding additional access delays.

[0132] This segment-association management strategy further enhances the improvement of management efficiency. First, the associated loading mechanism reduces the scattered access of system data, and when performing operations such as garbage collection or wear leveling, the processor 211 can quickly obtain complete section state information. Second, the segment-association management provides a more fine-grained resource control granularity, enabling the system to adopt differentiated memory management strategies according to the activity level of different logical address sections. Finally, when a specific logical address section has not been accessed for a long time, the processor 211 can release the segment-uniform mapping table UL2P' of the section and its associated system data from the buffer memory 214, further optimizing the utilization efficiency of memory resources.

[0133] This technical architecture realizes the modular design of mapping table management, while maintaining the advantage of direct mapping lookup, and effectively balances the relationship between system performance and resource consumption through the on-demand loading and association management mechanism.

[0134] The core technical feature of the improved embodiment is to optimize the memory resource configuration by using an on-demand loading mechanism. When the host system 10 initiates an access request for a specific logical address, the processor 211 first determines the logical address segment to which the logical address belongs, and checks whether the corresponding segment unified mapping table UL2P' has been loaded into the buffer memory 214. If the relevant segment unified mapping table UL2P' has not been loaded, the processor 211 reads the segment mapping table data from the second logical segment LAS2 and temporarily stores it in the buffer memory 214 for subsequent mapping lookup operations.

[0135] This on-demand loaded segment mapping table architecture realizes the optimal configuration of memory usage efficiency. Compared with the way of maintaining a complete large unified logical-to-physical mapping table UL2P', the segment loading mechanism only needs to save the mapping information of the currently active access region in the buffer memory 214, thereby reducing the continuous memory occupancy. At the same time, since each segment unified mapping table UL2P' covers a fixed range of logical addresses, the system does not need additional loading delay for subsequent access operations within the segment range, maintaining the performance advantage of direct mapping lookup. In addition, the processor 211 can dynamically manage the residence state of multiple segment unified mapping tables UL2P' in the buffer memory 214 according to the locality characteristics of the access pattern, further improving the response efficiency of the overall system.

[0136] Through this flexible architecture selection mechanism, the memory management method of the present disclosure can adapt to different hardware configurations and application requirements, while maintaining the advantages of unified data pool management, providing more implementation options for system design.

[0137] In another embodiment, the memory management method of the present disclosure further integrates the garbage collection operation mechanism and the physical-to-logical mapping table management function to realize more efficient storage space management and data integrity protection.

[0138] In addition to maintaining the unified logical-to-physical mapping table, the processor 211 also establishes a unified physical-to-logical mapping table, which uses a structured record format to record the reverse mapping relationship from physical addresses to logical addresses. Each physical-to-logical mapping record includes three key fields: a data type field, a logical address field, and a physical address field. The data type field is used to identify which type of data the mapping record corresponds to, i.e., first type data, mapping table data, or log data; the logical address field records the corresponding logical address value; and the physical address field records the specific physical address position mapped by the logical address.

[0139] With this structured entity-to-logical mapping table design, the processor 211 is able to determine the distribution of valid and invalid data in a specific entity block. When the system needs to evaluate the data validity of a certain entity block, the processor 211 can directly query the mapping records of all entity addresses within the entity block range, and determine the current validity status of the corresponding data according to the information of the data type field and the logical address field. This fast positioning mechanism replaces the inefficient way of scanning and verifying each storage location one by one in traditional garbage collection, enabling the system to immediately identify which data needs protective migration and which data has become invalid and can be directly discarded.

[0140] In addition, the validity judgment mechanism of the unified entity-to-logical mapping table is also applicable to the management of mapping table data and log data. The processor 211 can accurately identify the validity status of these system data by checking the mapping records with the data type field as mapping table data or log data, and comparing with the current system state. For example, when a certain mapping table data becomes an outdated version due to system updates, the processor 211 can locate the entity location of the outdated data in the unified entity-to-logical mapping table and mark it as invalid data. This accurate invalidity identification capability avoids wasting resources to move system data that has become outdated during garbage collection.

[0141] When a certain source entity block in the memory module 220 needs to perform garbage collection operations, the processor 211 adopts an intelligent data classification processing mechanism based on the unified mapping table. First, the processor 211 scans the source entity block according to the unified entity-to-logical mapping table, and immediately identifies the distribution of user data, mapping table data and log data through the data type field. Subsequently, the system cross- verifies with the unified logical-to-entity mapping table to ensure that the identified data is indeed in a valid state.

[0142] In terms of data processing strategy, the processor 211 adopts a differentiated migration method to optimize garbage collection efficiency. For the first type of data confirmed to be valid (user data), the system performs complete copy migration operations to move these data from the source entity block to another target entity address in the unified data block pool. For mapping table data and log data, the processor 211 adopts a regeneration strategy rather than direct migration, because these system data have a high update frequency, and direct migration often causes resource waste. Specifically, the mapping table data is regenerated according to the new location of the user data, and the historical log data is replaced by new garbage collection operation records.

[0143] After the data migration and regeneration are completed, the processor 211 performs a comprehensive mapping information update operation. The system regenerates another log data corresponding to the valid target data and the garbage collection operation, which details the key parameters of the garbage collection operation, including the source entity block identifier, the target entity block identifier, the actual migrated data volume, the skipped invalid data volume, and the operation timestamp, and the like. The processor 211 stores the another log data to a specified log logical address in a second logical section of the memory module 220.

[0144] Finally, the processor 211 performs a batch synchronization update operation of the unified logical-to-entity mapping table and the unified entity-to-logical mapping table based on the another target logical address of the valid target data and the another log logical address corresponding to the another log data. The system adopts an atomic update mechanism to ensure that all related records in the two mapping tables can simultaneously reflect the latest address mapping relationship, avoiding the problem of mapping inconsistency in the update process.

[0145] By integrating the garbage collection operation and the unified mapping table management mechanism, the present disclosure realizes the efficiency improvement of storage space management. The scanning capability of the unified entity-to-logical mapping table eliminates the time overhead of traditional one-by-one checking, and the intelligent classification processing mechanism reduces unnecessary I / O load by avoiding invalid data moving operations.

[0146] Taking an actual scenario as an example, when the source entity block contains 50 MB of valid user data, 10 MB of outdated mapping table data, and 5 MB of historical log data, the traditional method needs to move all 65 MB of data, while the method of the present disclosure only needs to move 50 MB of user data and regenerate about 8 MB of new mapping table data and 1 MB of new log data, reducing about 6 MB (65-50-8-1=6) of data transmission volume in total. More importantly, the present method avoids invalid moving of 10 MB of outdated mapping table data and 5 MB of historical log data, improving the efficiency of the garbage collection operation.

[0147] This optimization strategy not only shortens the execution time of the garbage collection operation, but also reduces the degree of interference of the garbage collection process on normal read-write operations of the system, maintaining the response performance of the storage system during maintenance. In addition, the synchronization update mechanism of the mapping information ensures that the system can maintain accurate address mapping relationships after data reorganization, providing a reliable positioning basis for subsequent data access operations, further enhancing the adaptability of the memory management system to large-capacity entity block environments.

[0148] The embodiment also provides a computer program product comprising computer readable code or a non-volatile computer readable storage medium carrying computer readable code, which, when executed in a processor, causes the processor to perform the steps of the memory management method described above. The computer program product can be implemented by hardware, firmware, software or a combination thereof. In an optional embodiment, the computer program product is embodied as a computer storage medium. In another optional embodiment, the computer program product is embodied as a software product, such as a software development kit (SDK) or the like.

[0149] Based on the above, the memory management method and the memory controller provided by the disclosure exhibit the following technical improvement effects in terms of large-capacity physical block compatibility and storage efficiency optimization:

[0150] Unified storage pool architecture advantage: The unified data block pool architecture fundamentally solves the inherent alignment waste problem in the traditional classification management system. By integrating data blocks, mapping blocks and log blocks into a single storage pool, the system eliminates the additional overhead generated by the alignment requirement of independent blocks. This integration enables the flash translation layer to achieve compatibility with large-capacity physical blocks that would exceed the system capacity limit under traditional management.

[0151] Address space management optimization: The target logical segment mechanism provides fine-grained address space partitioning while maintaining a simplified mapping table structure. Through intelligent address range analysis, the system can automatically determine the data type without additional metadata fields, thereby reducing the complexity of the mapping table and accelerating the lookup operation. Hierarchical mapping implementation provides flexible deployment options, supporting both hierarchical mapping for efficient memory operation and large unified mapping table for performance optimization scenarios.

[0152] Garbage collection performance improvement: The integrated garbage collection mechanism implements intelligent data processing through dual mapping tables. The system locates data distribution using the physical-to-logical mapping table, identifies the validity of user data, mapping table data and log data, and cross- verifies through the logical-to-physical mapping table to ensure accuracy. During data migration, the system performs complete migration of valid user data and regenerates frequently updated system data to avoid invalid migration, reducing data transmission volume and I / O operations. This optimization mechanism shortens the garbage collection time, reduces interference with normal read-write operations, maintains mapping table consistency, and maintains response performance during storage management, effectively controlling overhead.

[0153] Adaptive compatibility evaluation: The capacity requirement integration method realizes active compatibility evaluation between the storage management algorithm and the target storage module. By aggregating user data, mapping data and log data requirements into a unified capacity calculation, the system can accurately predict resource utilization and prevent deployment failures in large-scale storage environments.

[0154] Through the technical innovation described by the plurality of embodiments of the present disclosure, the memory management method of the present disclosure realizes the compatibility improvement with large-capacity physical block configuration while maintaining the running efficiency and data integrity.

[0155] On the other hand, the core advantage of the unified logical-to-physical mapping table is to include all data types in a single logical address indexing system, allocate dedicated logical address space for system data, eliminate the management complexity of traditional multiple independent indexing mechanisms, and support dynamic adjustment of storage space distribution ratio for different types of data according to actual needs.

[0156] At the same time, the hybrid storage architecture of the unified data block pool allows user data, mapping table data and log data to be distributed across the same physical block, breaking the spatial barriers of traditional classified management, avoiding the spatial fragmentation problem caused by data type separation, and realizing flexible deployment and maximum utilization of storage capacity.

[0157] Through the compatibility evaluation mechanism of merging and aligning the capacity requirements of different types of data, the system can reduce the cumulative waste caused by multiple independent rounding up compared to the traditional separate alignment method, making the memory management method adapt to larger-capacity physical block configurations, expanding the hardware compatibility range, and suitable for a variety of storage workload scenarios.

[0158] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A memory management method, applied to a storage device configured with a memory module, characterized in that, The method includes: A target logical segment is established to manage multiple entity blocks in the memory module, wherein the target logical segment includes a first logical segment and a second logical segment, and the host system connected to the storage device can only access the first logical segment; Configure the first logical segment for the first type of data, and configure the second logical segment for the second type of data; and When performing access operations on target data, based on the data type of the target data, at least the mapping information corresponding to the target data is recorded in the unified logic to entity mapping table.

2. The memory management method according to claim 1, characterized in that, Before establishing the target logical segment to manage the plurality of physical blocks in the memory module, the method further includes: Based on the demand information sent by the host system, determine the first capacity demand and the second capacity demand corresponding to the first type of data and the second type of data, respectively. The total capacity requirement is determined based on the first capacity requirement and the second capacity requirement; Based on the physical block capacity of each physical block in the memory module, the total capacity requirement is rounded up to obtain the required number of physical blocks; and The required number of physical blocks is compared with the total number of available physical blocks in the memory module to assess the compatibility of the memory management method and the memory module.

3. The memory management method according to claim 2, characterized in that, in The first type of data includes user data, wherein the first capacity requirement corresponds to the capacity requirement for storing the user data; and The second type of data includes mapping table data and log data, wherein the second capacity requirement corresponds to the capacity requirement for storing the mapping table data and the log data.

4. The memory management method according to claim 1, characterized in that, The method further includes: When garbage collection is performed on the source entity block: Based on the unified logic-to-entity mapping table, identify the valid target data in the source entity block, wherein the valid target data belongs to the first type of data; Copy the valid target data and store it at another target entity address; Regenerate another log data corresponding to the valid target data and the garbage collection operation, and store the other log data in the memory module; and Based on another target logical address of the valid target data and another log logical address corresponding to the other log data, update multiple mapping records about the valid target data and the log data to the unified logic-to-entity mapping table.

5. The memory management method according to claim 1, characterized in that, The method further includes: Establish a unified entity-to-logical mapping table for recording entity-to-logical address mapping records, wherein each entity-to-logical mapping record includes a data type field, a logical address field, and an entity address field; and The valid and invalid data in a specific entity block are determined by the unified entity-to-logic mapping table.

6. The memory management method according to claim 3, characterized in that, in The first logical segment includes multiple user logical addresses for the user data; Multiple logical addresses of the second logical segment are consecutively arranged after the maximum logical address of the first logical segment; The second logical segment includes: The first sub-segment includes multiple mapping table logical addresses for the mapping table data, wherein the starting mapping table logical address is determined based on a first preset offset value; as well as The second sub-segment includes multiple log logical addresses for the log data, wherein the starting log logical address is determined based on a second preset offset value.

7. The memory management method according to claim 6, characterized in that, The method further includes: By analyzing the logical address range to which the target logical address belongs, the data type of the target data is determined: When the target logical address is located in the first logical segment, the data type of the target data is determined to be the first type of data; When the target logical address is located in the first sub-segment, the data type of the target data is determined to be the mapping table data; and When the target logical address is located in the second sub-segment, the data type of the target data is determined to be the log data.

8. The memory management method according to claim 6, characterized in that, The method further includes: The first logical segment is divided into multiple fixed-size logical address segments, each of which corresponds to a mapping table logical address in the first sub-segment; When it is necessary to access the target logical address in the first logical segment, the target logical address segment to which the target logical address belongs is calculated according to the preset segmentation rules, and the target mapping table logical address corresponding to the target logical address segment in the first sub-segment is determined. Obtain the target mapping table data from the target mapping table entity address corresponding to the logical address of the target mapping table; and By using the target mapping table data, the target entity address mapped to the target logical address is found, so as to access the data stored at the target entity address.

9. A memory controller for controlling a storage device configured with a memory module, characterized in that, The memory controller includes: A memory interface control circuit, for electrically connecting to the memory module; and The processor is electrically connected to the memory interface control circuit, wherein the processor is further electrically connected to the connection interface circuit of the storage device for electrical connection to the host system. The processor is configured to: A target logical segment is established to manage multiple entity blocks in the memory module, wherein the target logical segment includes a first logical segment and a second logical segment, and the host system connected to the storage device can only access the first logical segment; Configure the first logical segment for the first type of data, and configure the second logical segment for the second type of data; and When performing access operations on target data, based on the data type of the target data, at least the mapping information corresponding to the target data is recorded in the unified logic to entity mapping table.

10. The memory controller according to claim 9, characterized in that, Before establishing the target logical segment to manage the plurality of physical blocks in the memory module, the processor is further configured to: Based on the demand information sent by the host system, determine the first capacity demand and the second capacity demand corresponding to the first type of data and the second type of data, respectively. The total capacity requirement is determined based on the first capacity requirement and the second capacity requirement; Based on the physical block capacity of each physical block in the memory module, the total capacity requirement is rounded up to obtain the required number of physical blocks; as well as The required number of physical blocks is compared with the total number of available physical blocks in the memory module to assess the compatibility of the memory management method and the memory module.

11. The memory controller according to claim 10, characterized in that, in The first type of data includes user data, wherein the first capacity requirement corresponds to the capacity requirement for storing the user data; and The second type of data includes mapping table data and log data, wherein the second capacity requirement corresponds to the capacity requirement for storing the mapping table data and the log data.

12. The memory controller according to claim 9, characterized in that, The processor is also configured to: When garbage collection is performed on the source entity block: Based on the unified logic-to-entity mapping table, identify the valid target data in the source entity block, wherein the valid target data belongs to the first type of data; Copy the valid target data and store it at another target entity address; Regenerate another log data corresponding to the valid target data and the garbage collection operation, and store the other log data in the memory module; as well as Based on another target logical address of the valid target data and another log logical address corresponding to the other log data, update multiple mapping records about the valid target data and the log data to the unified logic-to-entity mapping table.

13. The memory controller according to claim 9, characterized in that, The processor is also configured to: Establish a unified entity-to-logical mapping table for recording entity-to-logical address mapping records, wherein each entity-to-logical mapping record includes a data type field, a logical address field, and an entity address field; and The valid and invalid data in a specific entity block are determined by the unified entity-to-logic mapping table.

14. The memory controller according to claim 11, characterized in that, in The first logical segment includes multiple user logical addresses for the user data; Multiple logical addresses of the second logical segment are consecutively arranged after the maximum logical address of the first logical segment; The second logical segment includes: The first sub-segment includes multiple mapping table logical addresses for the mapping table data, wherein the starting mapping table logical address is determined based on a first preset offset value; as well as The second sub-segment includes multiple log logical addresses for the log data, wherein the starting log logical address is determined based on a second preset offset value.

15. The memory controller according to claim 14, characterized in that, The processor is also configured to: By analyzing the logical address range to which the target logical address belongs, the data type of the target data is determined: When the target logical address is located in the first logical segment, the data type of the target data is determined to be the first type of data; When the target logical address is located in the first sub-segment, the data type of the target data is determined to be the mapping table data; as well as When the target logical address is located in the second sub-segment, the data type of the target data is determined to be the log data.

16. The memory controller according to claim 14, characterized in that, The processor is also configured to: The first logical segment is divided into multiple fixed-size logical address segments, each of which corresponds to a mapping table logical address in the first sub-segment; When it is necessary to access the target logical address in the first logical segment, the target logical address segment to which the target logical address belongs is calculated according to the preset segmentation rules, and the target mapping table logical address corresponding to the target logical address segment in the first sub-segment is determined. Obtain the target mapping table data from the target mapping table entity address corresponding to the logical address of the target mapping table; as well as By using the target mapping table data, the target entity address mapped to the target logical address is found, so as to access the data stored at the target entity address.

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