Instruction exception processing method, electronic equipment and program product

Abstract

The embodiment of the invention provides an instruction exception handling method, electronic equipment and a program product. The instruction exception handling method comprises the steps that instruction exception information is obtained; the instruction exception information is used for indicating the occurrence of instruction exception; based on the instruction exception information, determining the occurrence position of an exception instruction according to the characteristics of the memories at all levels; the characteristics are used for indicating interrupts supported by the memories at all levels; and carrying out corresponding abnormity repairing operation on the occurrence position. According to the scheme of the embodiment, the corresponding exception repair operation is carried out at the occurrence position of the exception instruction, so that positive correction is carried out when the instruction error occurs, the original program is ensured to be continuously executed, deviation of the original program is avoided, and an expected program function is achieved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the field of instruction processing, and in particular, to an instruction exception processing method, an electronic device and a program product. BACKGROUND

[0002] In the related art, due to various conditions such as voltage fluctuation, electromagnetic interference, cosmic rays, temperature, etc. of the outside world, errors may occur in the unpredictable transmission path on the storage and transmission path of the computer system, thereby causing instruction code exception.

[0003] At present, there are two kinds of ideas for processing instruction code exception: the first idea is to skip the current error instruction and continue to execute the instruction after the exception instruction; the other is to adopt an exception instruction replacement strategy. Obviously, these two solutions are non-positive correction strategies when an instruction error occurs. Whether successful or not, they cannot execute the instructions that the system should have completed, or more or less cause deviation to the original program, resulting in the original program unable to achieve its intended function, which is unacceptable in many cases. SUMMARY

[0004] Embodiments of the present disclosure provide an instruction exception processing method, an electronic device and a program product.

[0005] In a first aspect, embodiments of the present disclosure provide an instruction exception processing method, which includes:

[0006] obtaining instruction exception information; the instruction exception information is used to indicate that an instruction exception occurs;

[0007] determining the occurrence position of the exception instruction according to the characteristics of each level of memory based on the instruction exception information; the characteristics are used to indicate the interruption supported by the each level of memory;

[0008] performing a corresponding exception repair operation on the occurrence position.

[0009] In a second aspect, embodiments of the present disclosure provide an electronic device, which includes:

[0010] one or more processors;

[0011] a memory having one or more programs stored thereon, when the one or more programs are executed by the one or more processors, the one or more processors implement the instruction exception processing method;

[0012] one or more input / output (I / O) interfaces connected between the processor and the memory, configured to realize information interaction of the processor and the memory.

[0013] In a third aspect, the present disclosure provides a computer program product comprising a computer program which, when executed by a processor, implements the instruction exception processing method.

[0014] In the embodiment of the present disclosure, instruction exception information is obtained, which is used to indicate that an instruction exception occurs. Based on the instruction exception information, the occurrence position of the exception instruction is determined according to the characteristics of the memory at each level. The characteristics are used to indicate the interruption supported by the memory at each level. The occurrence position is subjected to corresponding exception repair operations. The embodiment of the present disclosure realizes positive correction when an instruction error occurs, guarantees the original program to continue to execute, avoids causing deviation of the original program, and achieves the intended program function by performing corresponding exception repair operations at the occurrence position of the exception instruction. BRIEF DESCRIPTION OF DRAWINGS

[0015] In the drawings of the embodiment of the present disclosure:

[0016] Figure 1 A schematic diagram of a processor storage composition system in the related art is shown.

[0017] Figure 2 A schematic diagram of instruction storage and delivery sequence in the related art is shown.

[0018] Figure 3 A flowchart of the instruction exception processing method provided by the embodiment of the present disclosure is shown.

[0019] Figure 4 A flowchart of the occurrence position determination method of the exception instruction in the case of not supporting interruption provided by the embodiment of the present disclosure is shown.

[0020] Figure 5 A flowchart of the occurrence position determination method of the exception instruction in the case of not supporting interruption provided by the embodiment of the present disclosure is shown.

[0021] Figure 6 A schematic diagram of the instruction exception processing method in the case of not supporting interruption provided by the embodiment of the present disclosure is shown.

[0022] Figure 7 A schematic diagram of the instruction exception processing method in the case of supporting interruption provided by the embodiment of the present disclosure is shown.

[0023] Figure 8 A flowchart of the processing method when the ECC or parity interruption processing is completed provided by the embodiment of the present disclosure is shown.

[0024] Figure 9 A flowchart of the processing method of frequent instruction exceptions provided by the embodiment of the present disclosure is shown.

[0025] Figure 10 A flowchart of the processing method of frequent instruction exceptions provided by the embodiment of the present disclosure is shown.

[0026] Figure 11 This is a block diagram of an electronic device provided in an embodiment of the present disclosure. Detailed Implementation

[0027] To enable those skilled in the art to better understand the technical solutions of this disclosure, the communication-sensing data processing method and computer-readable storage medium provided in the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0028] The present disclosure will be described more fully below with reference to the accompanying drawings; however, the embodiments shown may be embodied in different forms, and the present disclosure should not be construed as limited to the embodiments set forth below. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will enable those skilled in the art to fully understand the scope of the disclosure.

[0029] The accompanying drawings of the embodiments disclosed herein are provided to further illustrate the embodiments of this disclosure and form part of the specification. They are used together with the detailed embodiments to explain this disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the description of the detailed embodiments with reference to the accompanying drawings.

[0030] This disclosure may be described with reference to plan and / or cross-sectional views using the ideal schematic diagrams of this disclosure. Therefore, the example illustrations may be modified according to manufacturing techniques and / or tolerances.

[0031] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.

[0032] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. The term "and / or" as used in this disclosure includes any and all combinations of one or more of the associated enumerated entries. The singular forms "a" and "the" as used in this disclosure are also intended to include the plural forms, unless the context clearly indicates otherwise. The terms "comprising," "made of," etc., as used in this disclosure specify the presence of the stated feature, integral, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0033] Unless otherwise specified, all terms used in this disclosure (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined in this disclosure.

[0034] Figure 1 A typical modern processor memory hierarchy system is shown. Core0 and Core1 represent two CPU (Central Processing Unit) processors in a multi-core system. L1 Cache (first level cache, which can be referred to as L1, and can include instruction cache L1-I and data cache L1-D) is usually private to each Core in the processor, and L2 Cache (second level cache, which can be referred to as L2, and some CPUs have lower level Lx Cache, which has a similar principle) is shared by all Cores. The CPU is connected to the system bus through the L2 Cache. There are also SDRAM (Synchronous Dynamic Random Access Memory) and other non-volatile storage devices such as ROM (Read-Only Memory), hard disk or Flash (Flash memory) on the system bus. Usually, program code is stored in non-volatile storage devices and loaded into SDRAM space after power-on.

[0035] Because the delay of each level of storage device interacting with the CPU is not the same, as shown in Figure 1 , the delay of registers R1, R2...Rn to the CPU Core is the least, and the delay of non-volatile storage device ROM to the CPU is the largest. Therefore, in order to improve the running efficiency, the CPU always reads the program instructions from SDRAM space through the system bus, through the L2 Cache to the L1 Cache when running program instructions, so that the instructions are taken directly from the L1 Cache each time, thereby reducing the access delay and improving the instruction execution efficiency. Therefore, a complete instruction storage and delivery sequence should be transmitted and executed in the manner of Figure 2 .

[0036] Under normal circumstances, the above Figure 1 , Figure 2 access flow is an ideal operation model of a reliable closed loop. However, in actual operation, the system will cause unpredictable errors in the transmission path due to changes in various conditions such as voltage fluctuations, electromagnetic interference, cosmic rays, temperature, etc.

[0037] Although the above error eventually comes out as an instruction exception on the operating system, due to different causes, the corresponding processing method is also different. An instruction from the memory to the execution unit of the CPU needs to go through multiple levels of delivery and transmission. Usually when sending an instruction exception, theoretically, each level of storage or each level of transmission, or even the entire CPU pipeline register, may be disturbed by the above external factors and have errors.

[0038] To solve the above problems, the embodiment of the present disclosure obtains instruction exception information; the instruction exception information is used to indicate that an instruction exception occurs; based on the instruction exception information, the occurrence position of the exception instruction is determined according to the characteristics of the memory at each level; the characteristics are used to indicate the interruption supported by the memory at each level; and a corresponding exception repair operation is performed on the occurrence position. The embodiment scheme realizes positive correction when an instruction error occurs, guarantees the original program to continue to execute, avoids causing deviation of the original program, and achieves the intended program function, by performing a corresponding exception repair operation on the occurrence position of the exception instruction.

[0039] The embodiment scheme of the present disclosure can be applied to any computer system with a multi-level storage system, especially in some high-reliability telecommunication-level products. In the high-reliability and stability requirements of system operation, the system exception or serious consequences such as system downtime restart caused by the occurrence of instruction exception during operation can be solved. Moreover, the embodiment scheme of the present disclosure can be applied to any CPU exception instruction scene, especially the processing of CPU exception instruction during operation.

[0040] The embodiment scheme of the present disclosure will be described in detail below.

[0041] The embodiment of the present disclosure provides an instruction exception processing method, as shown in Figure 3 The method comprises steps S11-S13:

[0042] S11, obtaining instruction exception information.

[0043] The embodiment scheme of the present disclosure obtains instruction exception information; based on the instruction exception information, the occurrence position of the exception instruction is determined according to the characteristics of the memory at each level; the characteristics are used to indicate the interruption supported by the memory at each level; and a corresponding exception repair operation is performed on the occurrence position. The embodiment scheme realizes positive correction when an instruction error occurs, guarantees the original program to continue to execute, avoids causing deviation of the original program, and achieves the intended program function, by performing a corresponding exception repair operation on the occurrence position of the exception instruction.

[0044] In the embodiment of the present disclosure, the instruction exception information is used to indicate that an instruction exception occurs, and the CPU internal circuit can automatically detect the exception instruction information.

[0045] In the embodiment of the present disclosure, in the case that the memory at each level supports instruction exception interruption, the exception interruption information can be detected as the instruction exception information. The exception interruption information can include but is not limited to ECC (Error Correction) or Parity (Parity) interruption information.

[0046] S12, based on the instruction exception information, the occurrence position of the exception instruction is determined according to the characteristics of the memory at each level.

[0047] In the embodiments of the present disclosure, in the case of receiving the instruction exception information, a flow of determining the occurrence position of the exception instruction according to the characteristics of the memory at each level can be entered.

[0048] In the embodiments of the present disclosure, the characteristics of the memory at each level can include:

[0049] The memory at each level supports instruction exception interruption; or,

[0050] The memory at each level does not support instruction exception interruption.

[0051] In the embodiments of the present disclosure, the occurrence position determination scheme of the present disclosure is explained below respectively for the case that the memory at each level does not support instruction exception interruption and the case that the memory at each level supports instruction exception interruption.

[0052] Case one (the memory at each level does not support instruction exception interruption)

[0053] In the embodiments of the present disclosure, determining the occurrence position of the exception instruction according to the characteristics of the memory at each level can include:

[0054] In response to the memory at each level not supporting instruction exception interruption, reading the instructions of the memory at each level from the lowest level memory step by step, and comparing the instructions of each level memory with the instructions of the corresponding higher level memory, and determining the occurrence position of the exception instruction according to the comparison result; wherein the lowest level memory is a non-volatile memory.

[0055] In the embodiments of the present disclosure, the stored instructions in the non-volatile memory can be used as an anchor point, and each level of memory and storage path can be checked one by one to determine the occurrence position of the exception instruction.

[0056] In the embodiments of the present disclosure, in a reliable system, basic reliability benchmarks are always to be achieved. For this purpose, the master-backup redundant storage technology can be used to achieve the backup of instruction code, and when the reading and checking of the storage content of an area fails, the system is automatically switched to another area, and this area is used as the anchor point of the correct instruction to measure and detect the correctness of the storage content of each level of memory. Since the path from the external non-volatile memory to the execution unit of the CPU is very long, any part of the path can have errors. Therefore, in the usual case, it is necessary to check each level of memory one by one starting from the lowest level of non-volatile memory in order to reload the instructions and repair the exception flow.

[0057] In the embodiments of the present disclosure, the memory at each level can include any two adjacent levels of memory; the any two adjacent levels of memory include the current level memory and the higher level memory of the current level memory.

[0058] In the embodiments of the present disclosure, as Figure 4As shown, starting from the lowest level memory, the instructions of each level memory are read level by level, and the instructions of each level memory are compared with the instructions of the corresponding higher level memory, and the occurrence position of the abnormal instruction is determined according to the comparison result, which can include steps S21-S23:

[0059] S21, compare the instructions of the current level memory and the instructions of the higher level memory.

[0060] S22, in response to the instructions of the current level memory being different from the instructions of the higher level memory, determining that the occurrence position is the transmission path between the higher level memory and / or the current level memory and the higher level memory.

[0061] S23, in response to the instructions of the current level memory being the same as the instructions of the higher level memory, taking the higher level memory as the current memory in the next set of adjacent memories, and returning to the step of comparing the instructions of the current level memory and the instructions of the higher level memory until the occurrence position is determined.

[0062] In the embodiments of the present disclosure, the level memories can include a first level memory, a second level memory, a third level memory and a fourth level memory; the first level memory is the lowest level memory, and the fourth level memory is the memory unique to the core of the processor.

[0063] In the embodiments of the present disclosure, the memories of any two adjacent levels between the first level memory, the second level memory, the third level memory and the fourth level memory can be taken as the current level memory and the corresponding higher level memory. For example, the first level memory and the second level memory are adjacent, the first level memory is the current level memory, and the second level memory is the higher level memory; the second level memory and the third level memory are adjacent, the second level memory is the current level memory, and the third level memory is the higher level memory; the third level memory and the fourth level memory are adjacent, the third level memory is the current level memory, and the fourth level memory is the higher level memory.

[0064] In the embodiments of the present disclosure, as shown, Figure 5 As shown, starting from the lowest level memory, the instructions of each level memory are read level by level, and the instructions of each level memory are compared with the instructions of the corresponding higher level memory, and the occurrence position of the abnormal instruction is determined according to the comparison result, which can include steps S31-S40:

[0065] S31, reading a first instruction corresponding to the abnormal instruction from the first level memory, and reading a second instruction corresponding to the abnormal instruction from the first level memory;

[0066] S32, comparing the first instruction with the second instruction;

[0067] S33, in response to the first instruction being different from the second instruction, determining that the occurrence position is the second-level memory and / or a first transmission path from the first-level memory to the second-level memory;

[0068] S34, in response to the first instruction being same as the second instruction, reading a third instruction corresponding to the exception instruction from the third-level memory;

[0069] S35, comparing the second instruction with the third instruction;

[0070] S36, in response to the second instruction being different from the third instruction, determining that the occurrence position is the third-level memory and / or a second transmission path from the second-level memory to the third-level memory;

[0071] S37, in response to the second instruction being same as the third instruction, reading a fourth instruction corresponding to the exception instruction from the fourth-level memory;

[0072] S38, comparing the third instruction with the fourth instruction;

[0073] S39, in response to the third instruction being different from the fourth instruction, determining that the occurrence position is the fourth-level memory and / or a third transmission path from the third-level memory to the fourth-level memory;

[0074] S40, in response to the third instruction being same as the fourth instruction, determining that the occurrence position is a core of the memory and / or a fourth transmission path from the fourth-level memory to the core of the memory.

[0075] In the embodiments of the present disclosure, the first, second, third and fourth in the first instruction, the second instruction, the third instruction and the fourth instruction are only used to indicate different positions of the instructions.

[0076] In the embodiments of the present disclosure, the first-level memory can include a read-only memory (ROM), the second-level memory can include a synchronous dynamic random access memory (SDRAM), the third-level memory includes a first cache shared by a plurality of cores between the core and the second-level memory (for example, including but not limited to L2 Cache), and the fourth-level memory includes a second cache unique to each core (for example, including but not limited to L1 Cache).

[0077] In the embodiments of the present disclosure, for the path and place of the instruction exception in the system running, the following scenarios can be summarized:

[0078] 1) If the instruction exception occurs in the decoding stage, it can occur in the internal PipeLine register, L1 Cache, L2...Lx Cache, SDRAM, or an error occurs in the transmission path of the instructions in these components.

[0079] 2) If the instruction exception occurs on the L1 Cache, it is possible that the L1 Cache, L2...Lx Cache, SDRAM memory or the instruction error occurs in the transmission path of these components.

[0080] 3) If the instruction exception occurs on the L2 (if L3, Lx, etc. needs the same operation) Cache, it is possible that the L2 Cache, SDRAM memory or the instruction error occurs in the transmission path of these components.

[0081] 4) If the instruction exception occurs on the SDRAM memory, it is possible that the SDRAM particle of the SDRAM memory or the instruction error occurs in the transmission path of reading the non-volatile memory.

[0082] In the embodiment of the present disclosure, as shown in Figure 6 After obtaining the instruction exception information and determining that the instruction exception occurs, the current normal instruction (i.e. the first instruction) corresponding to the abnormal instruction can be read from the main area or the backup area of the non-volatile memory, the second instruction in the SDRAM is read, and the first instruction is compared with the second instruction. If the first instruction is inconsistent with the second instruction, it indicates that there is a problem in the first transmission path between the non-volatile memory and the SDRAM (i.e. the occurrence position of the abnormal instruction is the first transmission path), and the abnormal instruction in the code segment position in the SDRAM needs to be corrected to the normal instruction in the non-volatile memory.

[0083] In the embodiment of the present disclosure, if the first instruction is consistent with the second instruction, it indicates that there is no problem in the first transmission path between the non-volatile memory and the SDRAM, the third instruction in the L2 Cache is read, and the second instruction is compared with the third instruction. If the second instruction stored in the SDRAM is inconsistent with the third instruction stored in the L2 Cache, it indicates that there is a problem in the second transmission path between the SDRAM and the L2 Cache (i.e. the occurrence position of the abnormal instruction is the second transmission path). If the current system has other Lx level Cache, the processing method is similar, and needs to be processed from Lx to L2.

[0084] In the embodiment of the present disclosure, if the second instruction is consistent with the third instruction, it indicates that there is no problem in the second transmission path between the SDRAM and the L2 Cache, the fourth instruction in the L1 Cache (specifically, the L1 I-Cache) is read, and the third instruction is compared with the fourth instruction. If the third instruction stored in the L2 Cache is inconsistent with the fourth instruction stored in the L1 Cache, it indicates that there is a problem in the third transmission path between the L2 Cache and the L1 Cache (i.e. the occurrence position of the abnormal instruction is the third transmission path).

[0085] In the embodiments of the present disclosure, if the third instruction is consistent with the fourth instruction, it indicates that the instructions stored in the SDRAM, the L2 Cache and the L1 Cache are all consistent with the first instruction in the non-volatile memory, and it indicates that there is a problem in the fourth transmission path between the L1 Cache and the internal register of the Core (core).

[0086] Case two (instruction exception interruption supported by each level of memory)

[0087] In the embodiments of the present disclosure, the position of the abnormal instruction is determined according to the characteristics of each level of memory, which can include:

[0088] In response to the instruction exception interruption supported by each level of memory, the instruction exception interruption is obtained;

[0089] The interruption position of the instruction exception interruption is determined;

[0090] The memory corresponding to the interruption position and / or the transmission path between the memory and the lower level memory of the memory is taken as the position of the abnormal instruction.

[0091] In the embodiments of the present disclosure, the instruction exception interruption can include but is not limited to ECC or parity exception interruption.

[0092] In the embodiments of the present disclosure, each level of memory can include a first level of memory, a second level of memory, a third level of memory and a fourth level of memory; the first level of memory is the lowest level of memory, and the fourth level of memory is the memory unique to the core of the processor.

[0093] In the embodiments of the present disclosure, the first level of memory can include a ROM, the second level of memory can include an SDRAM, the third level of memory includes a plurality of first cache registers shared by the cores between the core and the second level of memory, and the fourth level of memory includes a second cache register unique to each core.

[0094] In the embodiments of the present disclosure, as shown in Figure 7 In the system in which the CPU supports the ECC or parity exception interruption function, the interruption indication flag is generally used on each level of memory in the SDRAM or the L1 Cache, the L2 Cache (or Lx...L2 multi-level), and the operating system can quickly detect such instruction exceptions by registering the interruption hook. Therefore, if the ECC or parity interruption occurs during the instruction transmission process, it indicates that the instruction exception reason can only occur in the module between the current level and the adjacent level, and only the part of the memory path needs to be processed in the exception processing process, without the need to read the instructions level by level for comparison.

[0095] S13, performing corresponding exception repair operation on the occurrence position.

[0096] In the embodiments of the present disclosure, the exception repair operation scheme of the present disclosure is explained below for the two cases of each level of memory not supporting instruction exception interruption and supporting instruction exception interruption respectively.

[0097] Case one (each level of memory does not support instruction exception interruption)

[0098] In the embodiments of the present disclosure, performing corresponding exception repair operation on the occurrence position can include:

[0099] In response to the occurrence position being the second level of memory and / or the first transmission path, correcting the instruction at the instruction position in the second level of memory to be the corresponding instruction in the first level of memory; or,

[0100] In response to the occurrence position being the third level of memory and / or the second transmission path, clearing and invalidating the third level of memory, invalidating the fourth level of memory, and cleaning the instruction pipeline of the core; or,

[0101] In response to the occurrence position being the fourth level of memory and / or the third transmission path, invalidating the fourth level of memory and cleaning the instruction pipeline of the core; or,

[0102] In response to the occurrence position being the core of the processor and / or the fourth transmission path, cleaning the instruction pipeline of the core.

[0103] In the embodiments of the present disclosure, in the case where the first level of memory includes a read-only memory ROM, the second level of memory includes a synchronous dynamic random access memory SDRAM, the third level of memory includes a first cache such as an L2 Cache, and the fourth level of memory includes a second cache such as an L2 Cache, performing corresponding exception repair operation on the occurrence position can include:

[0104] In response to the occurrence position being the SDRAM and / or the first transmission path, correcting the instruction at the instruction position in the SDRAM to be the corresponding instruction (i.e. normal instruction such as the first instruction described above) in the ROM, clearing and invalidating the third level of memory, invalidating the fourth level of memory, and cleaning the instruction pipeline of the core; or,

[0105] In response to the occurrence position being the first cache and / or the second transmission path, clearing and invalidating the first cache, invalidating the second cache, and cleaning the instruction pipeline of the core; or,

[0106] In response to the occurrence position being the second cache and / or the third transmission path, invalidating the second cache and cleaning the instruction pipeline of the core; or,

[0107] In response to the occurrence position being the core and / or the fourth transmission path, the instruction pipeline of the core is cleaned.

[0108] In the embodiment of the present disclosure, the flow of modifying the instruction at the instruction position (or code segment position) in the SDRAM to the corresponding instruction (i.e., normal instruction) in the ROM can include: first, closing the protection of the instruction position in the SDRAM (i.e., closing the code segment protection), and then re-reading the normal instruction stored in the non-volatile memory to the instruction position in the SDRAM. Since the L2 Cache is shared by instructions and data, a Clean operation must be performed to complete the L2 D-Cache (which can be abbreviated as L2-D) some Write Back operation purposes, and then Invalidate the L2 Cache. If the current system supports more Lx Cache, it needs to be executed from Lx to L2 in turn. And the L1 I-Cache (which can be abbreviated as L1-I) is instruction-specific and is exclusively used by the core and does not support Write Back operation, so it is necessary to Invalidate the L1 I-Cache immediately, and finally Flush the Pipeline in the Core, so that the repaired normal instruction reaches all possible paths, and the repair instruction purpose is completed.

[0109] In the embodiment of the present disclosure, the first cache is cleaned and invalidated, and the second cache is invalidated, and the instruction pipeline of the core is cleaned, which can include: performing Clean and Invalidate operations on the L2 Cache, then performing Invalidate operation on the L1 Cache, and finally Flush the Pipeline in the Core. If the current system has other Lx level Cache, the processing method is similar to this, and needs to be processed from Lx to L2 step by step.

[0110] In the embodiment of the present disclosure, the second cache is invalidated, and the instruction pipeline of the core is cleaned, which can include: first, performing Invalidate on the L1 I-Cache, and then Flush the Pipeline in the Core.

[0111] In the embodiment of the present disclosure, in the case where the occurrence position is the fourth transmission path, only Flush the Pipeline in the Core is needed.

[0112] Case two (each level of memory supports instruction exception interruption)

[0113] In the embodiment of the present disclosure, the corresponding exception repair operation on the occurrence position can include:

[0114] in response to the occurrence of the position being the second level memory and / or the first transmission path between the second level memory and the first level memory, the instruction at the instruction position in the second level memory is corrected to be the corresponding instruction in the ROM; or

[0115] in response to the occurrence of the position being the third level memory and / or the second transmission path between the third level memory and the second level memory, the third level memory is subjected to a clean and invalidation process; or

[0116] in response to the occurrence of the position being the fourth level memory and / or the third transmission path between the fourth level memory and the third level memory, the fourth level memory is subjected to an invalidation process; or

[0117] in response to the occurrence of the position being the core and / or the fourth transmission path between the core and the fourth level memory, the instruction pipeline of the core is cleaned.

[0118] In the embodiments of the present disclosure, if the CPU is running in the process, the ECC of the SDRAM is interrupted, and the exception instruction address occurs in the instruction code segment space of the SDRAM, the normal instruction needs to be reacquired from the external nonvolatile memory, if the reading of the preferred nonvolatile memory CRC fails, the reading is switched to another piece of nonvolatile memory. For this purpose, the code segment protection can be closed first, then the instruction stored in the same offset address in the nonvolatile memory is re-read to the code segment position in the specified SDRAM address space according to the offset address of the exception instruction, and then the code segment execution attribute is restored.

[0119] In the embodiments of the present disclosure, if the CPU is running in the process, the exception interrupt is triggered by the L2 (or Lx) Cache ECC or Cache Partity exception, which indicates that there is a problem in the transmission process from the SDRAM to the L2 (or Lx) Cache, and the L2 (or Lx) can be subjected to a Clean and Invalidate operation, respectively.

[0120] In the embodiments of the present disclosure, similarly, if the L1 Cache occurs an instruction exception interrupt during the normal operation of the Core, it indicates that there is a problem in the transmission process from the L2 Cache to the L1 I-Cache, and therefore the L1 Cache only needs to be subjected to an Invalidate operation.

[0121] In the embodiments of the present disclosure, if the current Core is in normal operation, the cause of the exception is the pipeline exception of the Core, and the instruction exception occurs generally in the last level cache to the internal register of the CPU or in the instruction pipeline of the Core. Since each level of memory itself supports ECC or parity interruption, at this time, only flushing the pipeline can complete the correct instruction loading.

[0122] In the embodiments of the present disclosure, after obtaining the instruction exception information, the method can further include: recording the instruction address of the exception instruction.

[0123] After the corresponding exception repair operation on the occurrence position, the method can further include: taking the instruction address as the instruction address of the next execution.

[0124] In the embodiments of the present disclosure, according to the foregoing scheme, after the instruction exception and the related ECC or parity interruption are generated and captured by the exception program, the normal instruction can be obtained again through the occurrence position determination scheme and the exception repair operation scheme in the foregoing two cases, and then the normal instruction needs to be executed again. However, the foregoing exception repair operation is usually an additional action and behavior inserted into the normal running instruction stream, and is not the original processing logic behavior. Therefore, after the exception repair operation action is completed, it is necessary to return to the normal program instruction stream, that is, to continue running from the instruction of the instruction exception. Therefore, the instruction address (PC) of the exception instruction can be recorded in advance, and after the exception repair operation of the ECC or parity interruption is completed, the next instruction to be executed is replaced by the recorded instruction address (PC) before returning to the previous normal flow, so as to ensure that the repaired exception instruction is executed again.

[0125] In the embodiments of the present disclosure, as shown in FIG. 4, a processing method when the ECC or parity interruption processing is returned is shown, which includes steps S41-S45. Figure 8

[0126] S41, the ECC or parity instruction exception interruption enters.

[0127] S42, the instruction address (PC) of the exception instruction is recorded.

[0128] S43, the exception repair operation is performed.

[0129] S44, before returning to the previous normal flow, the next instruction to be executed is specified as the instruction address (PC).

[0130] S45, the repaired correct instruction is re-executed. ​

[0131] In the embodiments of the present disclosure, after the above operation is completed, the interruption of instruction transmission caused by the abnormal instruction due to bus transmission can be continued to be executed, so that the abnormal instruction can be corrected smoothly without the user's awareness, and the stability and maintainability of the system are improved.

[0132] In the embodiments of the present disclosure, before the instruction abnormality information is obtained, the method can further include: dividing the processor into multiple regions according to a preset division rule.

[0133] In the embodiments of the present disclosure, as shown in FIG. 1, after the instruction abnormality information is obtained, the method can further include steps S51-S52: Figure 9

[0134] S51, the number of abnormalities of the region corresponding to the instruction abnormality information is increased by one;

[0135] S52, in response to the number of abnormalities of the region corresponding to the instruction abnormality information reaching a preset number threshold within a first preset time length, performing corresponding abnormality processing on the memory in the region corresponding to the instruction abnormality information.

[0136] In the embodiments of the present disclosure, frequent execution of the Flush, Invalidate or re-reading operation of the memory will greatly affect the CPU execution efficiency, thereby affecting the overall system performance, and indirectly affecting the stability of the system, so it is necessary to statistically arrange the instruction abnormality of the system, and to reduce the occurrence of such situation as much as possible, and even to physically intervene manually when necessary.

[0137] In the embodiments of the present disclosure, the current CPU is a multi-core scene, and even supports single-core dynamic power-off and dynamic cache enabling and other advanced behaviors. Therefore, in order to minimize the impact of abnormal instructions, the above abnormal situations can be isolated and repaired to the maximum extent in units of cores. In actual use, it can be further refined according to the structure and hierarchy of the actual memory, and different situations such as specific abnormal address, and the processor can be divided into multiple regions, which can include but are not limited to: different address regions of the same level of memory, the same address region of the same level of memory, different address regions of different memories, and the like.

[0138] ​In the embodiments of the present disclosure, since the CPU performance and the processing exception ability are positively correlated, the frequency threshold of the exception occurrence in the different regions (i.e., the number threshold) can be determined according to the CPU main frequency. For example, the Perf tool (Perf is a tool for software performance analysis) can be used to capture the number of Cache-Miss (cache miss) or specified IRQ (Interrupt Request) triggers in a unit of time, and if the number is more than twice the normal value, it is considered that the specified frequency threshold is exceeded.

[0139] In the embodiments of the present disclosure, when the number of exception instructions exceeds the frequency threshold, the memory in the region corresponding to the instruction exception information can be processed according to the corresponding exception, as shown in the following. Figure 10

[0140] In the embodiments of the present disclosure, the exception processing can be divided into two processing schemes according to whether the storage address space is dynamically locked or the Cache operation is dynamically closed. The following will be described in detail with respect to the two schemes.

[0141] Scheme one (processor supports dynamic locking of storage address space or dynamic closing of Cache operation)

[0142] In the embodiments of the present disclosure, for the processor supporting dynamic locking of storage address space or dynamic closing of Cache operation, the following method can be used to process the exception instruction according to the specific CPU architecture characteristics.

[0143] In the embodiments of the present disclosure, the memory in the region corresponding to the instruction exception information can be processed according to the corresponding exception, which can include:

[0144] In response to the region corresponding to the instruction exception information being an identification Tag address in the shared buffer of the plurality of cores, and the same Tag address being abnormal multiple times within a second preset time length, dynamically disabling the cache line corresponding to the Tag address, or locking the cache line corresponding to the Tag address by filling invalid data; or

[0145] In response to the region corresponding to the instruction exception information being a Tag address in the shared buffer of the plurality of cores, and the abnormal Tag address being distributed in disorder, locking the region corresponding to the instruction exception information by filling invalid data, or closing the corresponding shared buffer; or

[0146] ​In response to the instruction exception information corresponding to the region being a Tag address in an arbitrary private cache of the core, and the number of exceptions of different Tag addresses in different private caches in the core reaching a threshold, the core is marked as an unusable core, and the task running queue of the core is migrated to the task running queue of another idle core for execution, or the corresponding shared cache is closed; or the processor in which the core is located is switched from a master to a backup; or

[0147] In response to the instruction exception information corresponding to the region being a Synchronous Dynamic Random Access Memory (SDRAM) address, and a single address in the SDRAM address occasionally being abnormal, a normal instruction corresponding to the abnormal instruction is re-read from an upper-level memory of the SDRAM; or

[0148] In response to the instruction exception information corresponding to the region being an SDRAM address, and a same address in the SDRAM address being abnormal for multiple times in succession, a current instruction transmission process is terminated, a code segment space is re-applied to the system to store a normal instruction, and the instruction transmission process is started again, and an address space that is abnormal for multiple times in succession is set as a system isolation region through an interface provided by an operating system.

[0149] In an embodiment of the present disclosure, the shared cache of the plurality of cores can be Lx Cache…L2 Cache, and if the same Tag address in the Lx Cache…L2 Cache frequently appears to be abnormal within a certain time, it is considered that the Cache Line itself is damaged, and the Cache Line can be dynamically disabled by using the low-power mode characteristics of the Cache. If the CPU system does not provide an instruction to disable certain Cache Line, the Cache Line can be locked by using the invalid data filling method, so that the system does not use the Cache Line for storage in subsequent running, thereby avoiding the problem of frequent instruction exceptions.

[0150] In an embodiment of the present disclosure, if it is found that the abnormal Tag addresses in a certain Lx Cache…L2 Cache are distributed in disorder within a certain time, the entire region needs to be locked by using the invalid data filling method. If dynamic closing is supported, the corresponding Cache can be directly closed to protect the system running as much as possible.

[0151] In the embodiments of the present disclosure, if the number of different Tag address exceptions in different L1 Cache of a certain Core exceeds the frequency threshold in the statistical data, it can be considered that the Core has a problem. In this scenario, if there is an idle Core resource in the current system, the current Core needs to be marked as unusable (CPU_DEAD), and the task running queue (run-queue) of the Core needs to be migrated to the task running queue of other idle Core for execution. If there is a master-slave CPU protection, the host needs to be switched or the CPU needs to be switched, because in the case of closing some L1 Cache, the performance of the CPU will decrease linearly.

[0152] In the embodiments of the present disclosure, if the ECC exception occurs in the SDRAM scenario, and it is a single address sporadic problem, the instruction can be directly re-read from the non-volatile memory. If the SDRAM ECC problem occurs continuously at the same address for multiple times, it indicates that the hardware SDRAM at the address may have been damaged. In order to prevent further expansion of the instruction exception, the current instruction transmission process can be terminated, and the code segment space for storing normal instructions needs to be applied to the system again. The space required for applying the code segment (that is, the space required for applying normal instructions) is required, and the instruction transmission process is started again. In addition, the damaged SDRAM address space needs to be placed in the system isolation area through the interface (memblock_reserve) provided by the operating system to prevent other programs and data from being contaminated again.

[0153] Solution two (processor does not support dynamic locking of storage address space or dynamic closing of Cache operation)

[0154] In the embodiments of the present disclosure, for the processor that does not support dynamic locking of storage address space or dynamic closing of Cache operation, the following method can be used to process the abnormal instruction according to the specific CPU system characteristics.

[0155] In the embodiments of the present disclosure, in the case that the processor does not support dynamic locking of storage address space or dynamic closing of Cache, the corresponding exception processing is performed on the memory in the region corresponding to the instruction exception information, which can include:

[0156] In response to the instruction exception information corresponding region being a Tag address in the private Cache of any core, the core is marked as an unusable core, the task running queue of the core is migrated to the task running queue of other idle core for execution, and an alarm log information is added.

[0157] In the embodiments of the present disclosure, for the case that some processors do not support dynamic closing or locking Lx Cache, if it is found that the Lx Cache ECC count of some cores reaches the threshold number of times, the current core also needs to be marked as unusable (CPU_DEAD), and the task running queue (run-queue) of the core is migrated to the task running queue of other cores for execution, so as to avoid the risk of problems of the core caused by multiple instruction exceptions, and logs and alarm information can be added to make the maintenance personnel give a decision as soon as possible.

[0158] The embodiments of the present disclosure also provide an electronic device 100, as shown in the accompanying drawings, comprising: Figure 11

[0159] one or more processors 101;

[0160] a memory 102, on which one or more programs are stored, when the one or more programs are executed by the one or more processors, the one or more processors 101 implement the instruction exception processing method;

[0161] one or more input / output I / O interfaces 103 connected between the processor 101 and the memory 102, configured to realize the information interaction of the processor 101 and the memory 102.

[0162] The embodiments of the present disclosure also provide a computer readable storage medium, on which a computer program is stored, and the computer program is executed by a processor to implement the instruction exception processing method.

[0163] The embodiments of the present disclosure also provide a computer program product, which comprises a computer program, and the computer program is executed by a processor to implement the instruction exception processing method.

[0164] In the embodiments of the present disclosure, any of the foregoing instruction exception processing methods is applicable to the electronic device, storage medium and program product embodiments, and will not be repeated here.

[0165] Those skilled in the art can understand that all or some of the functions of the modules / units disclosed above can be implemented as software, firmware, hardware and their appropriate combinations.

[0166] In the hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component can have multiple functions, or one function or step can be executed by several physical components in cooperation.

[0167] ​Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit (CPU), a digital signal processor, or a microprocessor, or hardware, or a combination of software and / or hardware. Such software can be distributed on computer readable media, which can comprise computer storage media (or non-transitory media), and communication media (or transitory media). Computer storage media, as used herein, includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Computer storage media includes, but is not limited to, random access memory (RAM), such as SDRAM, DDR, or other RAM, read only memory (ROM), electrically erasable programmable read only memory (EEPROM), flash memory, or other memory technology, compact disc read only memory (CD-ROM), digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and that can be accessed by a computer. Further, it should be appreciated by those skilled in the art that computer storage media generally includes computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media. Communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media. Examples of communication media include, but are not limited to, coaxial cable, fiber optics, wave guides, wired communication media, wireless communication media, and other like mediums that can be used to carry desired information and that can be accessed by a computer.

[0168] The present disclosure has disclosed example embodiments, and while specific terminology has been employed, it is merely in the nature of description and should not be taken as limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics or / and elements described in connection with a particular embodiment can be used in conjunction with other embodiments unless otherwise explicitly stated. As such, it will be understood that various changes in form and details can be made without departing from the scope of the disclosure as set forth in the appended claims.

Claims

1. A method for handling instruction exceptions, comprising: Obtain instruction exception information; The instruction exception information is used to indicate that an instruction exception has occurred; Based on the instruction exception information, the location of the exception instruction is determined according to the characteristics of each level of memory; the characteristics are used to indicate the interrupts supported by each level of memory. Perform corresponding anomaly repair operations based on the location where the anomaly occurred.

2. The instruction exception handling method according to claim 1, wherein, The characteristics of each level of memory include: The memory levels mentioned above support instruction exception interrupts; or... The memory levels do not support instruction exception interrupts.

3. The instruction exception handling method according to claim 2, wherein, Determining the location of the abnormal instruction based on the characteristics of each level of memory includes: In response to the fact that the memory at each level does not support the instruction exception interrupt, the instructions of each memory level are read sequentially starting from the lowest level memory, and the instructions of each memory level are compared with the instructions of the corresponding higher level memory. The location of the exception instruction is determined based on the comparison result; wherein, the lowest level memory is non-volatile memory.

4. The instruction exception handling method according to claim 3, wherein, Each level of memory includes any two adjacent levels of memory; The memory between any two adjacent levels includes: the current level memory and the memory at the next higher level than the current level memory; The process of reading instructions from each memory level sequentially, starting from the lowest-level memory, and comparing the instructions in each memory level with the instructions in the corresponding higher-level memory, and determining the location of the abnormal instruction based on the comparison results, includes: Compare the instructions in the current memory level with the instructions in the next higher memory level; In response to the fact that the instruction in the current level memory is different from the instruction in the higher level memory, the occurrence location is determined to be the higher level memory and / or the transmission path between the current level memory and the higher level memory; In response to the instruction in the current memory level being identical to the instruction in the higher-level memory level, the higher-level memory level is designated as the current memory in the next group of adjacent memories, and the process of comparing the instruction in the current memory level with the instruction in the higher-level memory level is returned until the location of the occurrence is determined.

5. The instruction exception handling method according to claim 3, wherein, The memory levels include a first-level memory, a second-level memory, a third-level memory, and a fourth-level memory; the first-level memory is the lowest-level memory, and the fourth-level memory is a memory unique to the processor core. The process of reading instructions from each memory level sequentially, starting from the lowest-level memory, comparing the instructions in each memory level with those in the next higher-level memory, and determining the location of the abnormal instruction based on the comparison results includes: Read the first instruction corresponding to the abnormal instruction from the first-level memory, and read the second instruction corresponding to the abnormal instruction from the first-level memory; Compare the first instruction with the second instruction; In response to the difference between the first instruction and the second instruction, the location of occurrence is determined to be the second-level memory and / or the first transmission path from the first-level memory to the second-level memory; In response to the first instruction being the same as the second instruction, a third instruction corresponding to the abnormal instruction is read from the third-level memory; Compare the second instruction with the third instruction; In response to the difference between the second instruction and the third instruction, the location of occurrence is determined to be the third-level memory and / or the second transmission path from the second-level memory to the third-level memory; In response to the second instruction being the same as the third instruction, the fourth instruction corresponding to the abnormal instruction is read from the fourth-level memory; Compare the third instruction with the fourth instruction; In response to the difference between the third instruction and the fourth instruction, the occurrence location is determined to be the fourth-level memory and / or the third transmission path from the third-level memory to the fourth-level memory. In response to the third instruction being identical to the fourth instruction, the location of occurrence is determined to be the core of the processor and / or the fourth transfer path from the fourth level memory to the core of the processor.

6. The instruction exception handling method according to claim 5, wherein, The corresponding anomaly repair operation at the location where the anomaly occurred includes: In response to the occurrence location being the second-level memory and / or the first transmission path, the instruction at the instruction location in the second-level memory is corrected to the corresponding instruction in the first-level memory, the third-level memory is cleared and invalidated, the fourth-level memory is invalidated, and the core instruction pipeline is cleaned; or, In response to the occurrence location being the third-level memory and / or the second transmission path, the third-level memory is cleared and invalidated, the fourth-level memory is invalidated, and the core instruction pipeline is cleaned; or, In response to the occurrence location being the fourth-level memory and / or the third transfer path, the fourth-level memory is invalidated, and the core instruction pipeline is cleaned; or, In response to the occurrence location being the processor core and / or the fourth transmission path, the instruction pipeline of the core is cleaned.

7. The instruction exception handling method according to claim 1, wherein, Determining the location of the abnormal instruction based on the characteristics of each level of memory includes: In response to the fact that the memory at each level supports the instruction exception interrupt, the instruction exception interrupt is acquired; Determine the location of the interruption caused by the abnormal interruption of the instruction; The memory corresponding to the interrupt location and / or the transmission path between the memory and the memory at the next lower level is taken as the location where the abnormal instruction occurred.

8. The instruction exception handling method according to claim 7, wherein, The memory levels include a first-level memory, a second-level memory, a third-level memory, and a fourth-level memory; the first-level memory is the lowest-level memory, and the fourth-level memory is a memory unique to the processor core. The corresponding anomaly repair operation at the location where the anomaly occurred includes: In response to the occurrence location being the second-level memory and / or the first transmission path between the second-level memory and the first-level memory, the instruction at the instruction location in the second-level memory is corrected to the corresponding instruction in the ROM; or, In response to the occurrence location being the third-level memory and / or the second transmission path between the third-level memory and the second-level memory, the third-level memory is cleared and invalidated; or... In response to the occurrence location being the fourth-level memory and / or the third transmission path between the fourth-level memory and the third-level memory, the fourth-level memory is invalidated; or... In response to the occurrence location being the core and / or the fourth transfer path between the core and the fourth level memory, the instruction pipeline of the core is cleaned.

9. The instruction exception handling method according to claim 1, wherein, After obtaining the instruction exception information, the method further includes: recording the instruction address of the exception instruction; After performing the corresponding anomaly repair operation on the location where the anomaly occurred, the method further includes: using the instruction address as the address of the next instruction to be executed.

10. The instruction exception handling method according to claim 1, wherein, Before obtaining the instruction exception information, the method further includes: dividing the processor into multiple regions according to a preset partitioning rule; After obtaining the instruction exception information, the method further includes: Increment the number of anomalies in the area corresponding to the instruction anomaly information by one; In response to the occurrence of anomalies in the region corresponding to the instruction anomaly information reaching a preset threshold within a first preset time period, corresponding anomaly processing is performed on the memory within the region corresponding to the instruction anomaly information.

11. The instruction exception handling method according to claim 10, wherein, When the processor supports dynamically locking the memory address space or dynamically disabling the cache, the corresponding exception handling for the memory in the region corresponding to the instruction exception information includes: In response to the instruction exception information corresponding to an identifier tag address within a shared cache of multiple cores, and the same tag address experiencing multiple exceptions within a second preset time period, the cache line corresponding to the tag address is dynamically disabled, or the cache line corresponding to the tag address is locked by filling in invalid data; or... In response to the instruction exception information corresponding to a tag address within a shared cache of multiple cores, and the disordered distribution of the abnormal tag addresses, the region corresponding to the instruction exception information is locked by filling in invalid data, or the corresponding shared cache is shut down; or, In response to the instruction exception information corresponding to a tag address within a dedicated cache of any core, and the number of exceptions for different tag addresses in different dedicated caches of the core reaching the specified threshold, the core is marked as an unavailable core, and its task execution queue is migrated to the task execution queue of other idle cores for execution; or, the corresponding shared cache is shut down; or, a primary / standby switch is performed on the processor containing the core; or... In response to the instruction exception information corresponding to a Synchronous Dynamic Random Access Memory (SDRAM) address, and the single address in the SDRAM address being an occasional exception, the normal instruction corresponding to the exception instruction is reread from the next higher level memory of the SDRAM; or, In response to the instruction error information corresponding to an SDRAM address, and the same address in the SDRAM address being an error multiple times consecutively, the current instruction transmission process is terminated, and a new code segment space is requested from the system to store the normal instruction. The instruction transmission process is then restarted, and the address space with the multiple consecutive errors is set as a system isolation area through an interface provided by the operating system.

12. The instruction exception handling method according to claim 10, wherein, When the processor does not support dynamically locking the memory address space or dynamically disabling the cache, the corresponding exception handling for the memory in the region corresponding to the instruction exception information includes: In response to the instruction exception information corresponding to a Tag address in a dedicated cache of any core, the core is marked as an unavailable core, and the task execution queue of the core is moved to the task execution queue of other idle cores for execution.

13. An electronic device, comprising: One or more processors; A memory having stored one or more programs, which, when executed by one or more processors, cause the one or more processors to implement the instruction exception handling method according to any one of claims 1-12; One or more input / output (I / O) interfaces are connected between the processor and the memory and configured to enable information exchange between the processor and the memory.

14. A computer program product comprising a computer program that, when executed by a processor, implements the instruction exception handling method according to any one of claims 1-12.

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