PCI bus arbitrary frequency pulse quantity output and self-checking method based on FPGA

Abstract

The invention relates to an FPGA (Field Programmable Gate Array)-based PCI (Peripheral Component Interconnect) bus arbitrary frequency pulse quantity output and self-checking method, which comprises the following steps that: an FPGA main control circuit realizes the conversion from a PCI bus to a Local Bus and controls the acquisition and output of a pulse quantity signal; the channel selection circuit realizes switching between a normal mode and a self-checking mode; the optical isolation and output driving circuit is used for isolating input and output signals from an external system; the PCI soft core module compiles a read-write state machine to realize PCI protocol conversion and read-write control between a host and the PCI soft core module; the pulse quantity frequency multiplication operation module realizes pulse quantity signal output and input detection of corresponding frequency and duty ratio; and the self-checking module realizes self-checking of any frequency pulse quantity output. According to the invention, the PCI bus random frequency pulse quantity output and self-checking function can be realized through a software algorithm under the FPGA, a bus controller chip is replaced by the PCI soft core, and meanwhile, the function self-checking of all channel signals can be automatically completed without the help of external equipment and manual assistance, and the information such as the frequency of the output pulse quantity signal can be displayed in real time.

Description

Technical Field

[0001] This invention belongs to the field of pulse output and self-test control technology, specifically relating to an FPGA-based PCI bus arbitrary frequency pulse output and self-test method. Background Technology

[0002] The PCI bus is a traditional computer bus that connects to the host computer CPU via a main bridge circuit. Because the PCI bus specification defines strict electrical characteristics and timing requirements, custom development is very difficult. Therefore, most products require a bus controller chip to be added to the function board to convert the PCI bus to a local bus before subsequent functional design. The bus controller chip has complex internal functions, but generally only a small portion of these functions are needed on the function board, leading to resource waste. Furthermore, bus controller chips are expensive, which is detrimental to the research and development and production of small function boards.

[0003] Pulse signals are generally used in industrial control and are usually directly output to external devices. Signal detection can only be performed using an oscilloscope to verify whether the output is normal. However, when the number of pulse channels increases or mass production occurs, it will consume a lot of verification time.

[0004] In the current context, the development of lightweight, intelligent, and automated products is accelerating. To address the high cost and testing difficulties of conventional PCI bus pulse output technology, this invention proposes an FPGA-based method for arbitrary frequency pulse output and self-testing on the PCI bus. This method replaces the bus controller chip with a PCI soft core and provides a self-testing method that automatically performs functional self-tests on all channel signals without external equipment or manual assistance, and displays information such as the frequency of the output pulse signal in real time. Therefore, implementing FPGA-based arbitrary frequency pulse output and self-testing technology for the PCI bus will provide stronger support for the development of the arbitrary frequency pulse output field on the PCI bus, and also aligns with the future trend of related technologies. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a PCI bus arbitrary frequency pulse quantity output and self-test method based on FPGA, which can realize the PCI bus arbitrary frequency pulse quantity output and self-test function through software algorithm under FPGA.

[0006] The technical problem solved by this invention is achieved through the following technical solution:

[0007] A method for arbitrary frequency pulse output and self-testing on a PCI bus based on FPGA, wherein the system used in the method includes an FPGA main control circuit, a channel selection circuit, an optical isolator and output driving circuit, and an FPGA program unit, wherein the FPGA program unit includes a PCI soft core module, a pulse frequency multiplication module, and a self-test module; the steps of the method are as follows:

[0008] The FPGA main control circuit implements the functions of converting PCI bus to Local Bus and controlling the acquisition and output of pulse signals through the FPGA program unit and its peripheral circuits.

[0009] The channel selection circuit switches between normal mode and self-test mode through a three-way bus transceiver;

[0010] The optical isolation and output driving circuit achieves isolation between input and output signals and external systems through opto-isolation chips and bus transceiver chips, enhances the driving capability of output pulse signals, and reduces interference from external systems to internal signals.

[0011] The PCI soft core module implements PCI protocol conversion and read / write control between the host and this module by configuring IP core parameters and writing a read / write state machine;

[0012] The pulse quantity frequency multiplication and division calculation module realizes the output and input detection of pulse quantity signals with corresponding frequency and duty cycle through the frequency multiplication and division transmission algorithm of clock frequency;

[0013] The self-test module achieves self-testing of pulse output at any frequency through a self-testing algorithm, and the working status and self-test results of the module can be indicated by an external indicator light.

[0014] Moreover, the FPGA main control circuit implements three functions: PCI soft core bridging function, address decoding and read / write control logic function, and pulse acquisition and output logic control function.

[0015] CPCI bus signals enter the FPGA directly through the CPCI connector. The CPCI soft core within the FPGA performs the conversion from CPCI to local bus. Simultaneously, the FPGA decodes the data address according to the received instructions and manipulates the values ​​of each register to acquire and control the output of n pulse signals. The frequency and duty cycle of the output pulses can be controlled by changing the values ​​of the registers.

[0016] The FPGA main control circuit can control the switching between normal mode and self-test mode.

[0017] Furthermore, the channel selection circuit enables switching between normal mode and self-test mode. The bus transceiver has enable control and direction control pins. The direction of signal transmission is determined by setting pull-up and pull-down resistors on the direction control pin, and the selection between normal mode and self-test mode is determined by the control signal on the enable control pin. When using normal mode, setting EN1 signal low and EN2 and EN3 signals high allows the main control circuit to communicate directly with the optocoupler and output drive circuit, enabling the acquisition and output of external system pulses. When using self-test mode, setting EN1 signal high and EN2 and EN3 signals low allows the FPGA's input and output to perform a self-test by loopback.

[0018] Moreover, the optical isolation and output driving circuit achieves two functions: optical isolation of input and output signals and driving enhancement of output signals; the optocoupler achieves signal isolation at both ends of the optocoupler through the "electric-optical-electric" conversion of signals, and the use of optical medium can effectively avoid electromagnetic signal interference.

[0019] The isolation power supply isolates the optocoupler from the normal signal ground, avoiding crosstalk between the two; the bus transceiver can increase the output current to enhance the driving capability of the optocoupler's output signal, avoiding communication abnormalities caused by insufficient driving capability when connected to external systems.

[0020] Moreover, the PCI soft core module implements two functions: PCI protocol conversion and read / write control. First, it implements protocol conversion by configuring the IP core and underlying parameters. Then, it implements write control by configuring the write register and related parameters, and implements read control by configuring the read register and related parameters.

[0021] Moreover, the pulse frequency multiplication module implements three functions: clock frequency multiplication, frequency division and transmission calculation, and signal output control. First, the clock frequency is multiplied by the frequency multiplication algorithm to increase the clock frequency and reduce the error of the pulse signal frequency. Then, the frequency division and transmission algorithm is used to calculate the pulse signal frequency at the input and output ends. By judging the magnitude of the count value and the high-level count value transmitted during the calculation process, the output high level is used to output the transmission parameter or the output low level is used to output the transmission parameter, thereby realizing the waveform output of the corresponding frequency and duty cycle.

[0022] Furthermore, the self-test module determines whether to enter self-test mode by checking if the self-test register is high. If it enters self-test mode, it closes the loop between the FPGA's output and input by configuring the enable pins of the relevant chips in the channel selection circuit, thereby achieving self-testing of the output and input signals. If the frequency values ​​displayed at the output and input are consistent, the self-test is considered successful, and a successful self-test flag is reported to the host computer via the PCI bus. If the self-test fails, an external fault indicator light is illuminated by outputting a high level. Simultaneously, the module can also determine whether it can normally receive instructions from the host computer by checking whether the running light flashes when the PCI read / write flag signal is high.

[0023] The advantages and beneficial effects of this invention are as follows:

[0024] The present invention relates to an FPGA-based PCI bus arbitrary frequency pulse output and self-test method, which can realize the PCI bus arbitrary frequency pulse output and self-test function through software algorithm under FPGA. This method replaces the bus controller chip with PCI soft core, and can automatically complete the functional self-test of all channel signals without the need for external equipment and manual assistance, and display information such as the frequency of the output pulse signal in real time, which greatly increases the openness and flexibility of PCI bus arbitrary frequency pulse output technology. Attached Figure Description

[0025] Figure 1 This is a flowchart of the present invention;

[0026] Figure 2 This is a diagram illustrating the overall architecture of the present invention;

[0027] Figure 3 This is a block diagram of the FPGA main control circuit of the present invention;

[0028] Figure 4 This is a block diagram of the channel selection circuit of the present invention;

[0029] Figure 5 This is a block diagram of the optical isolation and output driving circuit of the present invention;

[0030] Figure 6 This is a signal flow diagram of the self-test module of the present invention. Detailed Implementation

[0031] The present invention will be further described in detail below through specific embodiments. The following embodiments are merely descriptive and not limiting, and should not be used to limit the scope of protection of the present invention.

[0032] like Figure 1As shown, an FPGA-based PCI bus arbitrary frequency pulse output and self-test method is innovative in that: the system used in the method includes an FPGA main control circuit, a channel selection circuit, an optical isolation and output driving circuit, and an FPGA program unit. The FPGA program unit includes a PCI soft core module, a pulse frequency multiplication operation module, and a self-test module. The steps of the method are as follows:

[0033] The FPGA main control circuit implements the functions of converting PCI bus to Local Bus and controlling the acquisition and output of pulse signals through the FPGA program unit and its peripheral circuits.

[0034] The channel selection circuit switches between normal mode and self-test mode through a three-way bus transceiver;

[0035] The optical isolation and output driving circuit achieves isolation between input and output signals and external systems through opto-isolation chips and bus transceiver chips, enhances the driving capability of output pulse signals, and reduces interference from external systems to internal signals.

[0036] The PCI soft core module implements PCI protocol conversion and read / write control between the host and this module by configuring IP core parameters and writing a read / write state machine;

[0037] The pulse quantity frequency multiplication and division calculation module realizes the output and input detection of pulse quantity signals with corresponding frequency and duty cycle through the frequency multiplication and division transmission algorithm of clock frequency;

[0038] The self-test module achieves self-testing of pulse output at any frequency through a self-testing algorithm, and the working status and self-test results of the module can be indicated by an external indicator light.

[0039] For ease of understanding, this example uses an 8-channel design. It should be noted that the 8-channel design is just an example, and this method can be extended to any number of channels.

[0040] This example module uses a PCI bus IP core design, integrating bus protocol conversion and control functions into the FPGA. It also provides 8 pulse input interfaces and 8 pulse output interfaces. Its overall architecture diagram is shown below. Figure 2As shown. The FPGA main control circuit uses the FPGA and its peripheral circuits to convert the PCI bus to a Local Bus and control the acquisition and output of pulse signals. The channel selection circuit uses a three-way bus transceiver to switch between normal and self-test modes. The opto-isolation and output drive circuit uses opto-isolation chips and bus transceiver chips to isolate input / output signals from external systems, enhance the driving capability of output pulse signals, and reduce interference from external systems to internal signals. The PCI soft core module configures IP core parameters and writes a read / write state machine to achieve PCI protocol conversion and read / write control between the host and this module. The pulse frequency multiplication and division algorithm uses clock frequency multiplication and division to achieve pulse signal output and input detection at corresponding frequencies and duty cycles. The self-test module uses a self-test algorithm to achieve self-testing of pulse output at any frequency, and an external indicator light shows the module's operating status and self-test results.

[0041] The FPGA main control circuit primarily implements three functions: PCI soft-core bridging, address decoding and read / write control logic, and pulse acquisition and output logic. CPCI bus signals enter the FPGA directly through the CPCI connector, and the CPCI soft core within the FPGA performs the CPCI-to-local bus conversion. Simultaneously, the FPGA decodes the data address according to the received instructions and manipulates the values ​​of various registers to acquire and control the output of eight pulse signals. The frequency and duty cycle of the output pulses can be controlled by changing the register values. Furthermore, this circuit can switch between normal mode and self-test mode. Its block diagram is shown below. Figure 3 As shown.

[0042] The channel selection circuit primarily switches between normal mode and self-test mode. The bus transceiver has enable and direction control pins. The direction control pin's pull-up / pull-down resistors determine the signal transmission direction, while the enable pin's control signal determines the selection between normal and self-test modes. In normal mode, setting EN1 low and EN2 and EN3 high allows direct communication between the main control circuit and the opto-isolated and output drive circuits, enabling the acquisition and output of pulses from external systems. In self-test mode, setting EN1 high and EN2 and EN3 low performs a self-test of the FPGA's input and output loopback mechanism. The block diagram is shown below. Figure 4 As shown.

[0043] The optocoupler and output drive circuit primarily perform two functions: opto-isolation of input and output signals and enhancement of output signal drive. The optocoupler achieves signal isolation at both ends through "electro-optical-electro-optical" signal conversion. Simultaneously, the use of an optical medium effectively avoids electromagnetic interference. An isolation power supply isolates the optocoupler from the normal signal ground, preventing electrical signal crosstalk between them. A bus transceiver increases the output current, enhancing the drive capability of the optocoupler's output signal and preventing communication abnormalities due to insufficient drive capability when connecting to external systems. Its principle block diagram is shown below. Figure 5 As shown.

[0044] The PCI soft core module mainly implements two functions: PCI protocol conversion and read / write control. First, it implements protocol conversion by configuring the IP core and underlying parameters. Then, it implements write control by configuring the write register and related parameters, and read control by configuring the read register and related parameters.

[0045] The pulse frequency multiplication module mainly implements three functions: clock frequency multiplication, frequency division and transmission operation, and signal output control. First, the clock frequency is multiplied by a frequency multiplication algorithm to increase the clock frequency and reduce the error of the pulse signal frequency. Then, the frequency division and transmission algorithm is used to calculate the pulse signal frequency at the input and output ends. By judging the magnitude of the count value and the high-level count value transmitted during the operation, the module determines whether to output a high level to the output transmission parameter or output a low level to the output transmission parameter, thereby realizing the waveform output of the corresponding frequency and duty cycle.

[0046] The self-test module determines whether to enter self-test mode by checking if the self-test register is high. If in self-test mode, it configures the enable pins of relevant chips in the channel selection circuit to close the loop between the FPGA's output and input, thus achieving self-testing of the output and input signals. If the frequency values ​​displayed at the output and input are consistent, the self-test is considered successful, and a successful self-test flag is reported to the host computer via the PCI bus. If the self-test fails, an external fault indicator light is illuminated by outputting a high level. Simultaneously, this module can also determine whether it can correctly receive commands from the host computer by checking if the operation light flashes when the PCI read / write flag signal is high. Its signal flow diagram is shown below. Figure 6 As shown.

[0047] In summary, this invention proposes an FPGA-based method for arbitrary frequency pulse output and self-testing of the PCI bus. This method enables arbitrary frequency pulse output and self-testing of the PCI bus via software algorithms within an FPGA. By replacing the bus controller chip with a PCI soft core, this invention also proposes a self-testing method that automatically performs functional self-tests of all channel signals without the need for external devices or manual assistance. It also displays information such as the frequency of the output pulse signal in real time, greatly increasing the openness and flexibility of the arbitrary frequency pulse output technology for the PCI bus.

[0048] To fully verify the functionality and performance of this module, a test program was written under the Dao OS to test both normal mode and self-test mode. After passing the tests in both modes, a long-term stability test was conducted. In the stability test, the normal mode was used, and the output and input terminals were cascaded externally. The test program was run continuously for 48 hours, totaling 21,800 runs, without any recognition errors, proving that the module can still achieve good performance indicators under long-term working conditions.

[0049] Although embodiments and drawings of the present invention have been disclosed for illustrative purposes, those skilled in the art will understand that various substitutions, variations and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the scope of the present invention is not limited to the contents disclosed in the embodiments and drawings.

Claims

1. A method for outputting and self-testing arbitrary frequency pulse quantities on a PCI bus based on an FPGA, characterized in that: The system employed in the method includes an FPGA main control circuit, a channel selection circuit, an optical isolation and output driving circuit, and an FPGA program unit. The FPGA program unit includes a PCI soft core module, a pulse frequency multiplication module, and a self-test module. The steps of the method are as follows: The FPGA main control circuit implements the functions of converting PCI bus to Local Bus and controlling the acquisition and output of pulse signals through the FPGA program unit and its peripheral circuits. The channel selection circuit switches between normal mode and self-test mode through a three-way bus transceiver; The optical isolation and output driving circuit achieves isolation between input and output signals and external systems through opto-isolation chips and bus transceiver chips, enhances the driving capability of output pulse signals, and reduces interference from external systems to internal signals. The PCI soft core module implements PCI protocol conversion and read / write control between the host and this module by configuring IP core parameters and writing a read / write state machine; The pulse quantity frequency multiplication and division calculation module realizes the output and input detection of pulse quantity signals with corresponding frequency and duty cycle through the frequency multiplication and division transmission algorithm of clock frequency; The self-test module achieves self-testing of pulse output at any frequency through a self-testing algorithm, and the working status and self-test results of the module can be indicated by an external indicator light.

2. The FPGA-based PCI bus arbitrary frequency pulse output and self-test method according to claim 1, characterized in that: The FPGA main control circuit implements three functions: PCI soft core bridging function, address decoding and read / write control logic function, and pulse acquisition and output logic control function. CPCI bus signals enter the FPGA directly through the CPCI connector. The CPCI soft core within the FPGA performs the conversion from CPCI to local bus. Simultaneously, the FPGA decodes the data address according to the received instructions and manipulates the values ​​of each register to acquire and control the output of n pulse signals. The frequency and duty cycle of the output pulses can be controlled by changing the values ​​of the registers. The FPGA main control circuit can control the switching between normal mode and self-test mode.

3. The FPGA-based PCI bus arbitrary frequency pulse output and self-test method according to claim 1, characterized in that: The channel selection circuit enables switching between normal mode and self-test mode. The bus transceiver has enable control and direction control pins. The direction of signal transmission is determined by setting pull-up and pull-down resistors on the direction control pin, and the selection between normal mode and self-test mode is determined by the control signal on the enable control pin. In normal mode, EN1 signal is set low and EN2 and EN3 signals are set high, allowing the main control circuit to communicate directly with the optocoupler and output drive circuit to acquire and output pulses from external systems. In self-test mode, EN1 signal is set high and EN2 and EN3 signals are set low, enabling the FPGA's input and output self-loop self-test.

4. The FPGA-based PCI bus arbitrary frequency pulse output and self-test method according to claim 1, characterized in that: The optical isolation and output driving circuit achieves two functions: optical isolation of input and output signals and driving enhancement of output signals; Optocouplers achieve signal isolation at both ends by converting signals from electricity to light to electricity. At the same time, using optical media can effectively avoid interference from electromagnetic signals. An isolation power supply isolates the optocoupler from the normal signal ground, preventing electrical signal crosstalk between the two. Bus transceivers can increase the output current to enhance the driving capability of the optocoupler's output signal, thus avoiding communication abnormalities caused by insufficient driving capability when connecting to external systems.

5. The FPGA-based PCI bus arbitrary frequency pulse output and self-test method according to claim 1, characterized in that: Therefore, the PCI soft core module implements two functions: PCI protocol conversion and read / write control. First, it implements protocol conversion by configuring the IP core and underlying parameters. Then, it implements write control by configuring the write register and related parameters, and it implements read control by configuring the read register and related parameters.

6. The FPGA-based PCI bus arbitrary frequency pulse output and self-test method according to claim 1, characterized in that: The pulse frequency multiplication module performs three functions: clock frequency multiplication, frequency division and transmission, and signal output control. First, it multiplies the clock frequency using a frequency multiplication algorithm to increase the clock frequency and reduce the error of the pulse signal frequency. Then, it calculates the frequency of the pulse signal at the input and output ends using a frequency division and transmission algorithm. By judging the magnitude of the count value and the high-level count value transmitted during the operation, it determines whether to output a high level to the output transmission parameter or output a low level to the output transmission parameter, thereby realizing the waveform output of the corresponding frequency and duty cycle.

7. The FPGA-based PCI bus arbitrary frequency pulse output and self-test method according to claim 1, characterized in that: The self-test module determines whether to enter self-test mode by checking if the self-test register is high. If it enters self-test mode, it closes the loop between the FPGA's output and input by configuring the enable pins of the relevant chips in the channel selection circuit, thereby achieving self-testing of the output and input signals. If the frequency values ​​displayed at the output and input are consistent, the self-test is considered successful, and a successful self-test flag is reported to the host computer via the PCI bus. If the self-test fails, an external fault indicator light is illuminated by outputting a high level. Simultaneously, the module can also determine whether it can normally receive instructions from the host computer by checking whether the running light flashes when the PCI read / write flag signal is high.

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