Floating point calculation verification method and device of processor, electronic equipment, computer readable storage medium and computer program product

Abstract

The invention provides a floating point calculation verification method and device of a processor, electronic equipment, a computer readable storage medium and a computer program product. The method comprises the steps of determining a verification model in response to a received verification instruction for a floating point calculation unit of the processor; operating the input data through a floating point calculation unit to obtain a first operation result; performing operation on the input data through each verification model to obtain each second operation result; for each verification model, determining a first comparison result corresponding to the verification model based on an error comparison mechanism corresponding to the verification model, the second operation result and the first operation result; and generating a verification log of the floating point calculation unit based on the first comparison result and the second operation result corresponding to each verification model and the first operation result. According to the method and the device, the comprehensiveness and the accuracy of verifying the floating point computing unit can be improved, and the verification reliability and the traceability are improved by generating the verification log.

Description

TECHNICAL FIELD

[0001] The present application relates to integrated circuit design verification technology, and in particular to a floating point calculation verification method and device for a processor, an electronic device, a computer readable storage medium and a computer program product. BACKGROUND

[0002] With the rapid penetration of artificial intelligence (AI) technology in various fields, the demand for data processing speed, accuracy and parallel computing capability of artificial intelligence systems is increasing exponentially, thereby driving the urgent demand for high-performance floating point calculation units. As the key component of AI chips that undertakes core floating point operations, the performance of the floating point calculation unit determines the overall computing power of the chip, and the functional integrity is the core to ensure the calculation accuracy and reliability of the model. However, the increasing demand for computing power has continuously increased the design complexity and functional diversity of floating point calculation units. If there are design flaws in the floating point calculation unit, it will not only cause distortion of AI model calculation and performance damage, but also may cause serious reliability problems. Therefore, it is crucial to comprehensively and efficiently verify the floating point calculation unit. SUMMARY

[0003] The embodiments of the present application provide a floating point calculation verification method and device for a processor, a computer readable storage medium and a computer program product, which can improve the comprehensiveness and accuracy of verifying the floating point calculation unit, and improve the verification reliability and traceability by generating a verification log.

[0004] The technical solutions of the embodiments of the present application are as follows: The embodiments of the present application provide a floating point calculation verification method for a processor, the method comprising: In response to receiving a verification instruction for a floating point calculation unit of the processor, determining a verification model based on configuration information of the verification instruction, the verification model comprising at least two of an algorithm reference model, a behavior equivalent reference model and an algorithm prototype benchmark reference model; Performing operations on input data through the floating point calculation unit to obtain a first operation result; Performing operations on the input data through each of the verification models to obtain a second operation result; For each of the verification models, determining a first comparison result corresponding to the verification model based on an error comparison mechanism corresponding to the verification model and the second operation result, and the first operation result; Based on the first comparison result corresponding to each of the verification models and the second operation result, and the first operation result, generating a verification log of the floating point calculation unit.

[0005] The embodiments of the present application provide a floating point calculation verification device for a processor, comprising: determining, in response to receiving a verification instruction for a floating point calculation unit of the processor, a verification model based on configuration information of the verification instruction, the verification model comprising at least two of an algorithm reference model, a behavior equivalent reference model, and an algorithm prototype benchmark reference model; operating, by the floating point calculation unit, input data to obtain a first operation result; and operating, by each of the verification models, the input data to obtain a second operation result; The determining module is further configured to, for each of the verification models, determine a first comparison result corresponding to the verification model based on an error comparison mechanism corresponding to the verification model and the second operation result, and the first operation result. generating, based on the first comparison result corresponding to each of the verification models and the second operation result, and the first operation result, a verification log of the floating point calculation unit.

[0006] An electronic device is provided in an embodiment of the present application, and the electronic device comprises: a memory configured to store computer executable instructions or computer programs; a processor configured to execute the computer executable instructions or computer programs stored in the memory to implement the floating point calculation verification method provided in the embodiments of the present application.

[0007] A computer readable storage medium is provided in an embodiment of the present application, and the computer readable storage medium stores computer programs or computer executable instructions, and is configured to be executed by a processor to implement the floating point calculation verification method provided in the embodiments of the present application.

[0008] A computer program product is provided in an embodiment of the present application, and the computer program product comprises computer programs or computer executable instructions, and the computer programs or computer executable instructions are executed by a processor to implement the floating point calculation verification method provided in the embodiments of the present application.

[0009] The embodiments of the present application have the following beneficial effects: In the embodiment of the present application, in response to the verification instruction determining the verification model containing at least two of the algorithm reference model, the behavior equivalent reference model and the algorithm prototype benchmark reference model, the verification benchmark can be constructed from different dimensions, the mathematical logic correctness is guaranteed through the algorithm reference model, the hardware behavior logic is matched through the behavior equivalent reference model, and the actual application scene is approached through the algorithm prototype benchmark reference model, thereby avoiding the limitation of a single reference model and realizing multi-dimensional coverage of the floating point calculation unit verification. By operating the same input data by the floating point calculation unit and each verification model to obtain a first operation result and a plurality of second operation results, a direct comparison basis of the hardware actual output and the multiple reference outputs can be established, the consistency and comprehensiveness of the comparison objects are ensured, and the differences between the hardware operation and the reference standards at different levels are facilitated to be found. For each verification model, the corresponding error comparison mechanism is used to determine the first comparison result, which can combine the characteristics of different models to formulate adaptive comparison rules, avoid misjudgment caused by unified comparison standards, and improve the accuracy and rationality of the first comparison result. Finally, the verification log is generated based on each first comparison result, the first operation result and the second operation result, which can completely retain the hardware output, the multiple reference outputs and the dimensional comparison conclusions, and provide comprehensive basis for subsequent problem positioning, verification process backtracking and analysis. Therefore, through the embodiment of the present application, the comprehensiveness, accuracy and traceability of the floating point calculation unit verification can be significantly improved, and the correctness and reliability of the hardware operation can be effectively guaranteed. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 is a structural schematic diagram of a floating point calculation verification system architecture of a processor provided by the embodiment of the present application; Figure 2 is a structural schematic diagram of a server 200 provided by the embodiment of the present application; Figure 3 is a flow schematic diagram of a floating point calculation verification method of a processor provided by the embodiment of the present application; Figure 4 is a flow schematic diagram of determining a first comparison result provided by the embodiment of the present application; Figure 5 is another flow schematic diagram of determining a first comparison result provided by the embodiment of the present application; Figure 6 is a flow schematic diagram of determining an error threshold provided by the embodiment of the present application; Figure 7 is a whole architecture diagram of a high-performance floating point unit verification system based on multi-language reference models provided by the embodiment of the present application. DETAILED DESCRIPTION

[0011] In order to make the purposes, technical solutions and advantages of the present application clearer, the following further describes the present application in conjunction with the accompanying drawings, the described embodiments should not be regarded as limiting the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the present application.

[0012] In the following description, "some embodiments" are referred to, which describe a subset of all possible embodiments, but it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0013] In the following description, the terms "first\second\third" are only to distinguish similar objects, and do not represent a specific order of the objects, and it can be understood that "first\second\third" can be interchanged in a specific order or sequence as allowed, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0014] In the embodiments of the present application, the term "module" or "unit" refers to a computer program or a part of a computer program with a predetermined function, and works together with other related parts to achieve a predetermined target, and can be implemented entirely or partially by using software, hardware (such as a processing circuit or a memory) or a combination thereof. Similarly, one processor (or multiple processors or memories) can be used to implement one or more modules or units. In addition, each module or unit can be a part of an integral module or unit that includes the functions of the module or unit.

[0015] Unless otherwise defined, all technical and scientific terms used in the embodiments of the present application have the same meanings as commonly understood by those skilled in the art. The terms used in the embodiments of the present application are only for the purpose of describing the embodiments of the present application and are not intended to limit the present application.

[0016] The relevant data collection process in the embodiments of the present application should strictly comply with the requirements of relevant laws and regulations, obtain the informed consent or separate consent of the personal information subject, and within the scope of authorization of laws and regulations and the personal information subject, carry out subsequent data use and processing.

[0017] Before further detailing the embodiments of the present application, the terms and terms related to the embodiments of the present application are explained, and the terms and terms related to the embodiments of the present application are applicable to the following explanations.

[0018] 1) In response to: indicating the conditions or states that the operation depends on, when the dependent conditions or states are met, one or more operations performed can be real-time or have a set delay; in the absence of special instructions, there is no restriction on the execution order of multiple operations performed.

[0019] 2) Floating-point unit (FPU): A hardware module in a computer or chip that is specifically responsible for handling floating-point operations, mainly used for performing numerical calculations involving decimals. The core function is to efficiently complete basic floating-point operations such as addition, subtraction, multiplication, and division, as well as complex mathematical operations such as square root, trigonometric functions, and exponential functions.

[0020] 3) Algorithm reference model (Python reference model): A model based on a scientific computing library, focusing on algorithm-level verification, designed specifically for the special needs of matrix operations of high-performance floating-point units in the field of artificial intelligence. The core feature of this model is the automatic error threshold checking mechanism, which can automatically adjust the error threshold according to the precision of the input / output data type (such as brain floating-point precision BF16, single-precision FP32, double-precision FP64, etc.) and numerical range.

[0021] 4) Behaviorally equivalent reference model (SystemVerilog reference model): A hardware verification benchmark built according to the register transfer level (RTL) implementation idea. It strictly adheres to the architecture scheme and supports the Institute of Electrical and Electronics Engineers (IEEE) standard custom compressed floating-point format in the field of artificial intelligence. During verification, it simulates the RTL operation logic to generate results, which are compared bit by bit with the output of the floating-point unit to be verified, achieving error-free verification and ensuring that the hardware behavior meets the architecture requirements.

[0022] 5) Algorithm prototype benchmark reference model (C language reference model): A benchmark model that runs the core logic code of the algorithm team, which can generate gold standard results. By comparing the first operation results output by the floating-point calculation unit to be verified, the corresponding first comparison results are obtained, providing an authoritative reference at the algorithm level for verification.

[0023] 6) Error tolerance: The maximum value of the error allowed in a measurement, calculation, or control process, which is a pre-set, non-negative threshold value used to determine whether a result is acceptable.

[0024] 7) Mantissa bit number: that is, the first bit number in the embodiment of the application, which is the core part of the floating-point data type that determines the numerical accuracy, used to record the significant digits of the floating-point number, and determines the range of significant digits that the floating-point number can accurately describe. The more bits, the higher the precision (such as FP32 mantissa 23 bits, BF16 mantissa 7 bits).

[0025] 8) Exponent bit number: that is, the second bit number in the embodiment of the application, which is one of the core components of the floating-point data type, mainly to determine the "magnitude range" of the floating-point number, that is, the maximum and minimum value interval that the numerical value can cover, and together with the mantissa bit (which determines the precision) to form the core logic of floating-point representation.

[0026] At present, the floating-point unit verification method in the related art mainly uses a single language reference model or a limited combination of cross-language models for verification, and such verification method has the following problems: 1. Single language reference model verification coverage is limited: only relying on the SystemVerilog model cannot take into account the flexibility of algorithm-level verification, and only relying on the Python model cannot accurately match the hardware implementation details, resulting in insufficient verification depth and breadth.

[0027] 2. Error threshold control is difficult: AI field floating-point calculation involves multiple data type precision and numerical range, and the verification method in the related art lacks an automatic error threshold adjustment mechanism for different input / output data types, which is prone to false positives or false negatives.

[0028] 3. Semantic conversion error exists in cross-team collaboration: the language and model used by the algorithm team and the hardware implementation team are different, and semantic deviation is easy to occur in the process of requirement transmission and logic conversion, affecting the verification accuracy.

[0029] 4. Verification scene flexibility is insufficient: it is difficult to quickly switch verification models and scenes according to different verification requirements, the verification efficiency is low, and the support for non-IEEE standard data types is not perfect.

[0030] The embodiment of the application provides a floating-point calculation verification method, device, equipment, computer readable storage medium and computer program product of a processor, which can improve the comprehensiveness and accuracy of verifying the floating-point calculation unit, and improve the verification reliability and traceability by generating a verification log. The following describes an exemplary application of the electronic device provided by the embodiment of the application. The electronic device provided by the embodiment of the application can be implemented as a notebook computer, a tablet computer, a desktop computer, a set-top box, a smart phone, a smart speaker, a smart watch, a smart television, a vehicle-mounted terminal, and various types of terminals. It can also be implemented as a server. The following describes an exemplary application of the electronic device implemented as a server.

[0031] Referring to Figure 1, Figure 1 is a structural schematic diagram of a floating point calculation verification system of a processor provided by an embodiment of the present application, Figure 1 The database 100, the server 200, the network 300 and the terminal 400 are involved in the embodiment. The terminal 400 is connected with the server 200 through the network 300. The network 300 can be a wide area network or a local area network, or a combination of the two. The algorithm reference model, the behavior equivalent reference model and the algorithm prototype benchmark reference model can be stored in the database 100. The database 100 can be independent of the server 200, or can be deployed in the server 200. Figure 1 In the embodiment, the database 100 is independent of the server 200.

[0032] The terminal 400 is configured to provide an operation interaction entrance for a user (such as a chip verification engineer) on the display interface 410. First, the user initiates a verification instruction for the floating point calculation unit on the display interface 410 of the terminal 400, and configures key information (including selecting a verification model combination to be enabled, such as “algorithm reference model + behavior equivalent reference model”, and setting configuration information such as input data and operation type) in the instruction. Then, the terminal 400 transmits the verification instruction and the input data to the server 200 through the network 300. The server is configured to receive the verification instruction and the input data transmitted by the terminal 400 through the network 300, parse the configuration information in the verification instruction, determine a verification model containing at least two of the algorithm reference model, the behavior equivalent reference model and the algorithm prototype benchmark reference model from a preset model library, then call the floating point calculation unit to be verified, input the input data into the floating point calculation unit to perform a specified operation to obtain a first operation result, simultaneously call each verification model to input the same input data into each model to perform the same operation to obtain each second operation result, then for each verification model, call an error comparison mechanism corresponding to the verification model, compare the second operation result with the first operation result to determine a first comparison result corresponding to each verification model, finally integrate the first operation result, all the second operation results and the first comparison results, generate a verification log in a preset format, and feed back the verification log to the terminal 400 through the network 300. The terminal 400 is further configured to receive the verification log fed back by the server 200 through the network 300, and provide a log viewing interface for the user on the display interface 410, so as to facilitate the user to view the verification log.

[0033] In some embodiments, the server 200 can be a stand-alone physical server, or a server cluster or distributed system composed of multiple physical servers, or a cloud server providing cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery networks (CDN), and basic cloud computing services such as big data and artificial intelligence platforms. The terminal and the server can be connected directly or indirectly through wired or wireless communication, which is not limited in the embodiments of the present application.

[0034] Taking the electronic device for verification as an example, the server in the foregoing is taken as an example, referring to Figure 2 , Figure 2 is a structural schematic diagram of the server 200 provided by the embodiments of the present application, Figure 2 The server 200 shown in the figure includes at least one processor 210, a memory 230, and at least one network interface 220. The various components in the server 200 are coupled together through a bus system 240. It can be understood that the bus system 240 is used to realize the connection communication between the components. In addition to the data bus, the bus system 240 also includes a power bus, a control bus, and a status signal bus. However, for the purpose of clear illustration, all kinds of buses are marked as the bus system 240 in the Figure 2 .

[0035] The processor 210 can be an integrated circuit chip with signal processing capability, such as a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc., wherein the general-purpose processor can be a microprocessor or any conventional processor.

[0036] The memory 230 can be removable, non-removable, or a combination thereof. Exemplary hardware devices include solid state memory, hard disk drives, optical drives, etc. The memory 230 can optionally include one or more storage devices physically located in proximity to the processor 210.

[0037] The memory 230 includes volatile memory or non-volatile memory, and can also include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), and the volatile memory can be random access memory (RAM). The memory 230 described in the embodiments of the present application is intended to include any suitable type of memory.

[0038] In some embodiments, the memory 230 is capable of storing data to support various operations, examples of which include programs, modules, and data structures or a subset or superset thereof, which are exemplarily illustrated below.

[0039] The operating system 231 includes system programs for processing various basic system services and performing hardware-related tasks, such as a framework layer, a core library layer, a driver layer, and the like, for implementing various basic services and processing hardware-based tasks. The network communication module 232 is used to reach other electronic devices via one or more (wired or wireless) network interfaces 220, exemplary network interfaces 220 including Bluetooth, Wireless Fidelity (WiFi), and Universal Serial Bus (USB), and the like.

[0040] In some embodiments, the apparatus provided by the embodiments of the present application can be implemented in software, Figure 2 A floating point calculation verification apparatus 233 of the processor stored in the memory 230 is shown, which can be software in the form of programs and plug-ins, including the following software modules: a determination module 2331, an operation module 2332, and a generation module 2333. These modules are logical, and thus can be combined or further split according to the implemented functions. The functions of each module will be described below.

[0041] In other embodiments, the apparatus provided by the embodiments of the present application can be implemented in hardware, as an example, the apparatus provided by the embodiments of the present application can be a processor in the form of a hardware decoding processor, which is programmed to perform the floating point calculation verification method of the processor provided by the embodiments of the present application. For example, the processor in the form of a hardware decoding processor can use one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Programmable Logic Devices (PLDs), Complex Programmable Logic Devices (CPLDs), Field-Programmable Gate Arrays (FPGAs), or other electronic elements.

[0042] The floating point calculation verification method of the processor provided by the embodiments of the present application will be described in conjunction with exemplary applications and implementations of the server provided by the embodiments of the present application.

[0043] The following describes the floating-point calculation verification method for a processor provided in the embodiments of this application. As mentioned above, the electronic device implementing the floating-point calculation verification method for a processor in the embodiments of this application can be a terminal, a server, or a combination of both. Therefore, the executing entity of each step will not be described again below.

[0044] See Figure 3 , Figure 3 This is a flowchart illustrating the floating-point calculation verification method for a processor provided in this application embodiment, which will be combined with... Figure 3 The steps shown are explained.

[0045] In step 101, in response to receiving a verification instruction for the floating-point computing unit of the processor, a verification model is determined based on the configuration information of the verification instruction.

[0046] Here, the validation model includes at least two of the following: an algorithm reference model, a behavioral equivalence reference model, and an algorithm prototype benchmark reference model. The algorithm reference model is built based on a scientific computing library, focusing on algorithm-level validation and supporting automatic error threshold checking. The behavioral equivalence reference model is built according to the RTL implementation approach, supporting non-IEEE standard data types and used for error-free bit-by-bit comparisons. The algorithm prototype benchmark reference model runs the algorithm team's core code to generate standard results, serving as an authoritative reference for the algorithm logic. The validation instruction is the command that triggers the floating-point unit validation process and can include configuration information such as the validation scenario, model combination, input data, validation range, precision standard, and data type. The configuration information consists of parameters carried in the validation instruction, used to specify the validation scenario (e.g., validating FP32 precision operations or custom format operations) and determine the combination of validation models to be used. It is possible to specify one of the algorithm reference model, behavioral equivalence reference model, and algorithm prototype benchmark reference model as the validation model, or to use any two or all of these models.

[0047] In step 102, the input data is processed by the floating-point calculation unit to obtain the first calculation result.

[0048] Here, the floating-point computing unit refers to the hardware component in the chip responsible for performing floating-point operations, and is the object to be verified. The input data is used to test the floating-point computing unit and can include regular values, boundary values ​​(such as maximum / minimum values), and special values. The first operation result is the output of the floating-point computing unit to be verified after performing operations on the input data; this is the object being tested and compared.

[0049] In step 103, the input data is processed by each verification model to obtain the second calculation results.

[0050] Here, the second calculation result is the output of each verification model after processing the input data, and is used as a benchmark to judge whether the first calculation result is correct.

[0051] In step 104, for each verification model, the first comparison result corresponding to the verification model is determined based on the error comparison mechanism and the second calculation result corresponding to the verification model, as well as the first calculation result.

[0052] Here, the error comparison mechanism refers to the comparison rules adopted by different verification models. For example, the algorithm reference model compares based on a custom error tolerance or an automatic error threshold, and the acceptable error range can be adjusted according to the data accuracy; the behavioral equivalence reference model uses bit-by-bit error-free comparison, which usually requires that the first operation result is completely consistent with its output second operation result; the algorithm prototype benchmark reference model is used to rigorously compare the first operation result with its output standard result, which usually requires zero error or minimal error. The first comparison result is the comparison conclusion of a single verification model between the first operation result and the second operation result (such as comparison passed, comparison failed, or a specific description of the differences), which is used to reflect the degree of agreement between the hardware output and the model benchmark.

[0053] In some embodiments, see Figure 4 When the verification model includes an algorithm reference model, step 104, "determining the first comparison result corresponding to the verification model based on the error comparison mechanism and the second operation result, and the first operation result," can be implemented through steps 1041A to 1044A, including: In step 1041A, the absolute error and relative error between the second operation result and the first operation result corresponding to the algorithm reference model are determined.

[0054] Here, for the second computational result (baseline value) output by the algorithm reference model and the first computational result (hardware value) output by the floating-point computing unit to be verified, the absolute error and relative error between them are calculated respectively. This quantifies the degree of deviation between the hardware result and the algorithm baseline, providing data basis for subsequent judgment. The absolute error measures the direct difference between the two results, calculated as |first computational result - second computational result| (the absolute value is used to ensure the error is non-negative), reflecting the actual magnitude of the deviation. For example, if the hardware result is 3.1415928 and the baseline result is 3.1415926, the absolute error is 0.0000002. The relative error measures the proportion of the absolute error relative to the baseline result, calculated as |(first computational result - second computational result) / second computational result|, reflecting the relative severity of the deviation. In the example above, the relative error ≈ .

[0055] In step 1042A, when the error comparison mechanism corresponding to the algorithm reference model is a custom type, the pre-set absolute error tolerance and relative error tolerance, as well as the logical operation rules between the absolute error tolerance and relative error tolerance, are obtained.

[0056] Here, the custom error comparison mechanism is a mechanism that flexibly sets comparison rules based on specific verification needs (such as floating-point operations with different precisions, different application scenarios). Unlike general rules such as fixed thresholds, its absolute error tolerance and relative error tolerance are pre-set by the user according to their needs. The absolute error tolerance refers to the pre-set maximum allowable absolute error value (e.g., 0.000001 for FP32 precision operations). If the actual absolute error is less than or equal to this value, it indicates that the absolute error is within an acceptable range. The relative error tolerance is the pre-set maximum allowable relative error value (e.g., set to...). If the actual relative error is less than or equal to this value, it indicates that the relative deviation is within an acceptable range. Logical operation rules include "AND" and "OR" rules, which define how the absolute error judgment result and the relative error judgment result must be combined to ultimately determine if the comparison passes. For example, logical "AND" means that both the absolute error tolerance and the relative error tolerance must be satisfied simultaneously, while logical "OR" means that either the absolute error tolerance or the relative error tolerance is satisfied.

[0057] In step 1043A, a second alignment result is determined based on the absolute error and the absolute error tolerance, and a third alignment result is determined based on the relative error and the relative error tolerance.

[0058] Here, the second comparison result is a preliminary comparison conclusion on the absolute error. If the absolute error is less than or equal to the absolute error tolerance, the second comparison result is considered passed, and its logical value can be represented as 1; otherwise, the comparison fails, and its logical value can be represented as 0. The third comparison result is a preliminary comparison conclusion on the relative error. If the actual relative error is less than or equal to the relative error tolerance, the third comparison result is considered passed, and its logical value can be represented as 1; otherwise, the comparison fails, and its logical value can be represented as 0.

[0059] In some embodiments, determining the second alignment result based on the absolute error and the absolute error tolerance can be achieved through the following process: When the absolute error is less than or equal to the absolute error tolerance, the second comparison result is determined as the first result value; when the absolute error is greater than the absolute error tolerance, the second comparison result is determined as the second result value.

[0060] Here, when the calculated absolute error is less than or equal to the preset absolute error tolerance, the absolute error is determined to be within the allowable range, and the second comparison result is the first result value; when the absolute error is greater than the absolute error tolerance, the absolute error is determined to be outside the allowable range, and the second comparison result is the second result value. The first result value represents a "compliant" identifier (such as the logical value "true", the Boolean value "1", etc., the specific form of which is defined by the verification system). The second result value represents a "non-compliant" identifier (such as the logical value "false", the Boolean value "0", etc., corresponding to the first result value).

[0061] The third alignment result is determined based on the relative error and the relative error tolerance, which can be achieved through the following process: When the relative error is less than or equal to the relative error tolerance, the third comparison result is determined as the first result value; when the relative error is greater than the relative error tolerance, the third comparison result is determined as the second result value.

[0062] Here, when the calculated relative error is less than or equal to the preset relative error tolerance, the relative error is determined to be within the allowable range, and the third comparison result is the first result value; when the relative error is greater than the relative error tolerance, the relative error is determined to be beyond the allowable range, and the third comparison result is the second result value.

[0063] In this embodiment, when the absolute error is less than or equal to the absolute error tolerance, the second alignment result is determined as the first result value; when the absolute error is greater than the absolute error tolerance, the second alignment result is determined as the second result value; when the relative error is less than or equal to the relative error tolerance, the third alignment result is determined as the first result value; and when the relative error is greater than the relative error tolerance, the third alignment result is determined as the second result value. This clearly quantifies whether the error is within an acceptable range, providing a clear and unified basis for determining the first alignment result, thereby improving the accuracy of determining the first alignment result.

[0064] In step 1044A, logical operations are performed on the second and third alignment results based on logical operation rules to obtain the first alignment result corresponding to the algorithm reference model.

[0065] Here, the first comparison result is the algorithm reference model's final judgment on whether the first operation result conforms to the algorithm logic, including whether the comparison passes or fails. For example, if the logical operation rule is "AND", and the second and third comparison results are both "passed" (logical value is 1), then the first comparison result is "passed" (logical value is 1); if the logical operation rule is "AND", the second comparison result is "passed" (logical value is 1) and the third comparison result is "failed" (logical value is 0), then the first comparison result is "failed" (logical value is 0); if the logical operation rule is "OR", the second comparison result is "passed" (logical value is 1) and the third comparison result is "failed" (logical value is 0), then the first comparison result is "passed" (logical value is 1).

[0066] In this embodiment, the absolute and relative errors between the second and first computation results corresponding to the algorithm reference model are determined. When the error comparison mechanism corresponding to the algorithm reference model is a custom type, a pre-set absolute error tolerance and relative error tolerance, as well as the logical operation rules between the absolute error tolerance and relative error tolerance, are obtained. A second comparison result is determined based on the absolute error and absolute error tolerance, and a third comparison result is determined based on the relative error and relative error tolerance. Logical operations are performed on the second and third comparison results based on the logical operation rules to obtain the first comparison result corresponding to the algorithm reference model. Thus, by quantifying the error and combining custom tolerances with logical rules for hierarchical comparison, the accuracy requirements of different scenarios can be flexibly adapted, the consistency between the hardware results and the algorithm benchmark can be accurately determined, and the flexibility and accuracy of determining the first comparison result corresponding to the algorithm reference model can be improved.

[0067] In some embodiments, see Figure 5 When the verification model includes an algorithm reference model, step 104, "determining the first alignment result corresponding to the verification model based on the error comparison mechanism and the second operation result, and the first operation result," can also be implemented through steps 1041B to 1045B, including: In step 1041B, the absolute error and relative error between the second operation result and the first operation result corresponding to the algorithm reference model are determined.

[0068] Here, for the second computational result (baseline value) output by the algorithm reference model and the first computational result (hardware value) output by the floating-point computing unit to be verified, the absolute error and relative error between the two are calculated respectively. This quantifies the degree of deviation between the hardware result and the algorithm baseline, providing data basis for subsequent judgment. The absolute error measures the direct difference between the two results, calculated as |first computational result - second computational result| (the absolute value is used to ensure the error is non-negative), reflecting the actual magnitude of the deviation. The relative error measures the proportion of the absolute error relative to the baseline result, calculated as |(first computational result - second computational result) / second computational result|, reflecting the relative severity of the deviation.

[0069] In step 1042B, when the error comparison mechanism corresponding to the algorithm reference model is of the automatic type, the first bit of the mantissa, the second bit of the exponent, and the actual value of the exponent of the floating-point calculation unit are determined.

[0070] Here, the automatic error comparison mechanism does not require manual threshold setting. Instead, it automatically generates comparison rules for error thresholds based on the hardware parameters of the floating-point computing unit (mantissa bits, exponent bits, etc.), adapting to different precision types. The first digit of the mantissa, or the number of mantissa bits, is the total number of mantissa bits in the floating-point computing unit and determines the basis of numerical precision. The second digit of the exponent, or the number of exponent bits, is the total number of exponent bits in the floating-point computing unit and determines the magnitude range of the value. The actual value of the exponent is the specific value of the exponent in the current operation, determined by the input data, reflecting the actual magnitude of the value.

[0071] In step 1043B, the absolute error threshold and the relative error threshold are determined based on the first digit, the actual value of the exponent, and the second digit.

[0072] Here, the absolute error threshold is the maximum acceptable absolute deviation automatically generated based on the number of mantissa digits (the first digit) and the actual value of the exponent digit (e.g., the more mantissa digits, the smaller the threshold, and the higher the precision requirement). The relative error threshold is the maximum acceptable relative deviation automatically generated based on the number of exponent digits (the second digit) and the number of mantissa digits (the first digit) (e.g., the threshold may be adjusted adaptively as the range of exponent digits increases).

[0073] In some embodiments, see Figure 6 Step 1043B, "Determining the absolute error threshold and relative error threshold based on the first digit, the actual value of the exponent, and the second digit," can be implemented through steps 1043B1 to 1043B6, including: In step 1043B1, the basic threshold of the floating-point calculation unit is determined based on the first digit, the actual value of the exponent, and the preset exponent compensation coefficient.

[0074] Here, the process of calculating the basic threshold is shown in formula (1): (1) Wherein, n_M is the first digit, which determines the minimum quantization interval; E is the actual value of the exponent, reflecting the magnitude of the numerical value; k is the exponent compensation coefficient (usually taken as 1e-5), which is used to fine-tune the threshold difference of numerical values ​​of different magnitudes, so that the basic threshold is more in line with the cross-magnitude accuracy characteristics.

[0075] In step 1043B2, the low interval, middle interval, and high interval are determined based on the first and second digits.

[0076] Here, based on the first and second digits, the possible numerical range of the input data is divided into three levels: low, medium, and high. Different ranges correspond to different error sensitivities. The low, medium, and high ranges are defined by numerical magnitude; values ​​in the low range must be smaller than those in the medium range, and values ​​in the medium range must be smaller than those in the high range.

[0077] In some embodiments, "determining the low interval, middle interval, and high interval based on the first and second digits" can be achieved through the following steps: First, the minimum positive value of the floating-point calculation unit is determined based on the second bit, and the maximum positive value of the floating-point calculation unit is determined based on the second bit and the first bit.

[0078] Here, the process for calculating the minimum positive value is shown in formula (2): (2) Where Bias is the exponential offset, Bias = , It is the second digit.

[0079] For the process of calculating the maximum positive value, please refer to formula (3): (3) Where n_M is the first digit, It is the second digit.

[0080] Then, the threshold for the lower interval is determined based on the first digit and the minimum positive value; the threshold for the higher interval is determined based on the maximum positive value and the dynamic contraction coefficient.

[0081] Here, the low-interval threshold is the maximum value of the low interval and also the minimum value of the middle interval; the high-interval threshold is the minimum value of the high interval and also the maximum value of the middle interval. The low-interval threshold L = max(Vmin × C_L, 1), where C_L is the dynamic expansion coefficient, C_L = Based on the adaptive adjustment of the mantissa length, the expansion of high-precision types is more reasonable. The high-interval threshold H = Vmax × C_H, where C_H is the dynamic shrinkage coefficient (initial value 0.01, dynamically optimized through the adaptive learning module: when the high-interval error pass rate is <90%, the dynamic shrinkage coefficient is reduced to 0.005, and when the high-interval error pass rate is >95%, the dynamic shrinkage coefficient is increased to 0.02).

[0082] Then, the low interval threshold is used as the first upper bound value, and a low interval is constructed based on the first preset value and the first upper bound value; the high interval threshold is used as the second upper bound value, and the low interval threshold is used as the first lower bound value, and a middle interval is constructed based on the first lower bound value and the second upper bound value; the high interval threshold is used as the second lower bound value, and a high interval is constructed based on the second lower bound value and positive infinity.

[0083] Here, the upper bound refers to the maximum value of the interval, the lower bound refers to the minimum value of the interval, and the first preset value is usually 0. For example, if the lower interval threshold is 100, the higher interval threshold is 10000, and the first preset value is 0, then the lower interval is [0, 100) (lower bound 0, first upper bound 100), the middle interval is [100, 10000) (first lower bound 100, second upper bound 10000), and the higher interval is [10000, +∞) (second lower bound 10000, upper bound positive infinity). If the input data is 50, it belongs to the lower interval; if the input data is 5000, it belongs to the middle interval; and if the input data is 20000, it belongs to the higher interval.

[0084] In this embodiment, the minimum positive value of the floating-point calculation unit is determined based on the second number of bits, and the maximum positive value of the floating-point calculation unit is determined based on the second number of bits and the first number of bits. A low-interval threshold is determined based on the first number of bits and the minimum positive value. A high-interval threshold is determined based on the maximum positive value and a dynamic shrinkage coefficient. The low-interval threshold is used as a first upper bound value, and a low-interval is constructed based on a first preset value and the first upper bound value. The high-interval threshold is used as a second upper bound value, and the low-interval threshold is used as a first lower bound value. A middle-interval is constructed based on the first lower bound value and the second upper bound value. The high-interval threshold is used as a second lower bound value, and a high-interval is constructed based on the second lower bound value and positive infinity. In this way, by automatically determining the interval thresholds and dividing the low, middle, and high intervals using dynamic coefficients, the interval division can conform to the hardware precision characteristics and numerical range, improving the accuracy and reliability of the constructed intervals.

[0085] In step 1043B3, the target interval corresponding to the input data is determined from the low interval, the middle interval and the high interval, and the interval coefficient of the target interval is determined.

[0086] Here, the system determines which interval (low / medium / high) the current input data value belongs to and extracts the corresponding interval coefficient to adjust the base threshold (different intervals have different tolerances for error). The target interval refers to the interval to which the input data belongs, and the interval coefficient is the adjustment factor for the corresponding target interval. For example, the interval coefficient for the low interval is 1.5, and the interval coefficient for the medium interval is... (x is the value of the input data). The interval coefficient for the high interval is 20. The larger the value of the interval coefficient, the greater the error allowed in that interval.

[0087] In step 1043B4, the scene coefficients are determined based on the operation type of the input data.

[0088] Here, the operation type refers to the specific operation performed by the floating-point computing unit on the input data (such as simple addition, complex convolution, etc.). Different operation types have different error propagation characteristics. The scenario coefficient is an adjustment factor for different operation types (e.g., addition coefficient is 1.0, multiplication coefficient is 1.2, convolution coefficient is 1.5). For example, operation types include: matrix operations, tensor decomposition, and convolution. The scenario coefficient for the matrix operation scenario is... K represents the matrix dimension. The larger the dimension, the more non-linearly the threshold relaxation increases, adapting to high-dimensional error accumulation. The scene coefficient for tensor decomposition scenarios is 1+ ×0.1, where n is the decomposition order, increasing by the square root to avoid excessive relaxation of the threshold for higher-order decompositions; the scenario coefficient for convolution operations is 1 + (convolution kernel size - 1) × 0.05, and the larger the convolution kernel size, the more linearly the sliding window error is relaxed.

[0089] In step 1043B5, the product of the interval coefficient, the scene coefficient, and the basic threshold is determined as the absolute error threshold.

[0090] Here, the absolute error threshold is the maximum absolute deviation value allowed by the system. The absolute error threshold = dynamic adjustment value of the base threshold = base threshold × interval coefficient × scenario coefficient. For example, if the base threshold is 0.0001, the interval coefficient is 1.5, and the scenario coefficient is 1.2, then the absolute error threshold is 0.0001 × 1.5 × 1.2 = 0.00018.

[0091] In step 1043B6, the ratio of the absolute error threshold to the input data is determined as the relative error threshold.

[0092] Here, the relative error threshold is the maximum allowable relative deviation ratio of the system. The relative error threshold R = absolute error threshold ÷ |input value| (when the input value ≠ 0).

[0093] In this embodiment, the basic threshold of the floating-point calculation unit is determined based on the first digit, the actual value of the exponent, and a preset exponent compensation coefficient; the low, middle, and high intervals are determined based on the first and second digits; the target interval corresponding to the input data is determined from the low, middle, and high intervals, and the interval coefficient of the target interval is determined; the scenario coefficient is determined based on the operation type of the input data; the product of the interval coefficient, the scenario coefficient, and the basic threshold is determined as the absolute error threshold; and the ratio of the absolute error threshold to the input data is determined as the relative error threshold. This allows the error threshold to accurately adapt to hardware characteristics, data range, and operation scenario, avoiding the limitations of fixed thresholds and improving the adaptability and accuracy of verification.

[0094] In step 1044B, the fourth alignment result is determined based on the absolute error and the absolute error threshold, and the fifth alignment result is determined based on the relative error and the relative error threshold.

[0095] Here, the absolute error is compared with the automatically generated absolute error threshold, and the relative error is compared with the automatically generated relative error threshold, outputting two comparison results: a fourth comparison result and a fifth comparison result. The fourth comparison result is the judgment result for the absolute error; if the absolute error is less than or equal to the absolute error threshold, the fourth comparison result is considered a pass; otherwise, the comparison fails. The fifth comparison result is the judgment result for the relative error; if the relative error is less than or equal to the relative error threshold, the fifth comparison result is considered a pass; otherwise, the comparison fails.

[0096] In step 1045B, based on the fourth and fifth alignment results, the first alignment result corresponding to the algorithm reference model is determined.

[0097] Here, based on the default rules of the automatic type mechanism (such as "the comparison is considered successful only if both comparisons pass", "the comparison is considered successful if the fourth comparison result passes", and "the comparison is considered successful if the fifth comparison result passes"), the fourth and fifth comparison results are comprehensively judged to obtain the first comparison result.

[0098] In some embodiments, "determining the first alignment result corresponding to the algorithm reference model based on the fourth and fifth alignment results" can be achieved through the following process, including: When the target interval is the lower interval and the fourth alignment result indicates that the absolute error is less than or equal to the absolute error threshold, the first alignment result is determined to be an alignment pass. When the target interval is the middle interval and the fourth alignment result indicates that the absolute error is less than or equal to the absolute error threshold, and the fifth alignment result indicates that the relative error is less than or equal to the relative error threshold, the first alignment result is determined to be an alignment pass. When the target interval is the higher interval and the fifth alignment result indicates that the relative error is less than or equal to the relative error threshold, the first alignment result is determined to be an alignment pass.

[0099] Here, when the target interval is low, the focus is on absolute error, ignoring small fluctuations in relative error. The first alignment result is considered passed only if the absolute error is less than or equal to the absolute error threshold. When the target interval is medium, a strict dual-condition judgment is applied; both the absolute error and the relative error must be less than or equal to the absolute error threshold simultaneously for the first alignment result to be considered passed. When the target interval is high, the focus is on relative error, adapting to the characteristics of large absolute errors. The first alignment result is considered passed only if the relative error is less than or equal to the relative error threshold.

[0100] In this embodiment, when the target interval is the lower interval and the fourth comparison result indicates that the absolute error is less than or equal to the absolute error threshold, the first comparison result is determined to be a pass. When the target interval is the middle interval and the fourth comparison result indicates that the absolute error is less than or equal to the absolute error threshold, and the fifth comparison result indicates that the relative error is less than or equal to the relative error threshold, the first comparison result is determined to be a pass. When the target interval is the higher interval and the fifth comparison result indicates that the relative error is less than or equal to the relative error threshold, the first comparison result is determined to be a pass. In this way, by flexibly adopting differentiated comparison rules for absolute error, absolute and relative error, and relative error according to different numerical intervals, the verification standard can be made to fit the error characteristics of each interval, thereby improving the accuracy and rationality of the first comparison result.

[0101] In some embodiments, when the input data is zero, the product between the absolute error threshold and the second preset value is determined; when the absolute error is less than or equal to the product between the absolute error threshold and the second preset value, the first comparison result is determined to be a successful comparison.

[0102] Here, the second preset value is an integer greater than zero, which is set to 10. For example, when the absolute error is ≤ absolute error threshold × 10, the first comparison result is determined to be a successful comparison.

[0103] In this embodiment, when the input data is zero, the product between the absolute error threshold and the second preset value is determined; when the absolute error is less than or equal to the product between the absolute error threshold and the second preset value, the first comparison result is determined to be a successful comparison. This preserves the zero-value sensitivity of the relaxed logic adaptation, improving the rationality and reliability of the verification.

[0104] In this embodiment, the absolute error and relative error between the second and first operation results corresponding to the algorithm reference model are determined. When the error comparison mechanism corresponding to the algorithm reference model is automatic, the first digit of the mantissa, the second digit of the exponent, and the actual value of the exponent are determined. Based on the first digit, the actual value of the exponent, and the second digit, the absolute error threshold and the relative error threshold are determined. Based on the absolute error and the absolute error threshold, the fourth comparison result is determined, and based on the relative error and the relative error threshold, the fifth comparison result is determined. Based on the fourth and fifth comparison results, the first comparison result corresponding to the algorithm reference model is determined. In this way, by automatically generating error thresholds by combining the hardware parameters of the floating-point calculation unit, and then comprehensively judging through error comparison results, the automation and hardware adaptability of error verification are realized, and the efficiency and accuracy of determining the first comparison result are improved.

[0105] In some embodiments, when the verification model includes a behavioral equivalent reference model or an algorithm prototype benchmark reference model, the step 104 of "determining the first comparison result corresponding to the verification model based on the error comparison mechanism and the second calculation result corresponding to the verification model, and the first calculation result" can be implemented through the following process, including: Based on the error comparison mechanism corresponding to the behavioral equivalent reference model, the second operation result and the first operation result corresponding to the behavioral equivalent reference model are compared to obtain the first comparison result corresponding to the behavioral equivalent reference model; or, based on the error comparison mechanism corresponding to the algorithm prototype benchmark reference model, the second operation result and the first operation result corresponding to the algorithm prototype benchmark reference model are compared to obtain the first comparison result corresponding to the algorithm prototype benchmark reference model.

[0106] Here, when the verification model is based on a behavioral equivalence reference model, the second operation result and the first operation result corresponding to the behavioral equivalence reference model are compared bit by bit to obtain the first comparison result corresponding to the behavioral equivalence reference model. For example, if all bits (sign bit, exponent bit, mantissa bit) of the second operation result and the first operation result are completely identical, the first comparison result corresponding to the behavioral equivalence reference model passes the comparison; if there is any difference in any bit, the first comparison result fails the comparison. When the verification model is an algorithm prototype benchmark reference model, the second operation result and the first operation result corresponding to the algorithm prototype benchmark reference model are compared to obtain the first comparison result corresponding to the algorithm prototype benchmark reference model. The comparison rules for the algorithm prototype benchmark reference model can be set according to requirements (such as zero error requirement or minimal error tolerance). If the second operation result and the first operation result meet the preset rules, the first comparison result corresponding to the algorithm prototype benchmark reference model passes the comparison; otherwise, the comparison fails.

[0107] In this embodiment, based on the error comparison mechanism corresponding to the behavioral equivalent reference model, the second operation result and the first operation result corresponding to the behavioral equivalent reference model are compared to obtain the first comparison result corresponding to the behavioral equivalent reference model; or, based on the error comparison mechanism corresponding to the algorithm prototype benchmark reference model, the second operation result and the first operation result corresponding to the algorithm prototype benchmark reference model are compared to obtain the first comparison result corresponding to the algorithm prototype benchmark reference model. Thus, through bit-by-bit comparison of the behavioral equivalent reference model and benchmark comparison of the algorithm prototype benchmark reference model, the floating-point computing unit can be rigorously verified from both hardware implementation consistency and algorithm logic correctness dimensions, comprehensively ensuring the functional accuracy of the floating-point computing unit.

[0108] In step 105, a verification log for the floating-point computing unit is generated based on the first comparison result and the second operation result corresponding to each verification model, as well as the first operation result.

[0109] Here, the verification log is a document containing information about the entire verification process. This may include input data, the first calculation result, the second calculation results for each model, comparison conclusions for each model, error details, etc., and is a crucial basis for analyzing floating-point computing unit design problems. By summarizing the first comparison results of all verification models, the second calculation results of each model, and the first calculation results of the floating-point computing unit, a document containing the complete verification process, comparison details, and result judgments is generated—this is the verification log—used to record verification conclusions and locate problems.

[0110] In this embodiment, in response to a verification instruction, a verification model is determined that includes at least two of the following: an algorithm reference model, a behavioral equivalence reference model, and an algorithm prototype benchmark reference model. This allows for the construction of verification benchmarks from different dimensions. The algorithm reference model ensures the correctness of mathematical logic, the behavioral equivalence reference model matches hardware behavioral logic, and the algorithm prototype benchmark reference model closely approximates real-world application scenarios, avoiding the limitations of a single reference model and achieving multi-dimensional coverage of floating-point computing unit verification. By having the floating-point computing unit and each verification model perform operations on the same input data to obtain a first operation result and multiple second operation results, a direct comparison basis between the actual hardware output and multiple types of reference outputs can be established, ensuring the consistency and comprehensiveness of the comparison objects and facilitating the discovery of differences between hardware operations and reference standards at different levels. For each verification model, its corresponding error comparison mechanism is used to determine the first comparison result. This allows for the formulation of appropriate comparison rules based on the characteristics of different models, avoiding misjudgments caused by a unified comparison standard and improving the accuracy and rationality of the first comparison result. Finally, a verification log is generated based on the first comparison results, the first operation results, and the second operation results. This log can completely retain the hardware output, multiple reference outputs, and comparison conclusions from various dimensions, providing a comprehensive basis for subsequent problem localization, verification process backtracking, and analysis. Therefore, the embodiments of this application can significantly improve the comprehensiveness, accuracy, and traceability of floating-point computing unit verification, effectively ensuring the correctness and reliability of hardware operations.

[0111] The following will describe an exemplary application of the embodiments of this application in a real-world application scenario.

[0112] This application discloses a high-performance floating-point unit verification system based on a multi-language reference model, particularly suitable for verifying complex floating-point computing units in the AI ​​field. The system achieves multi-level, comprehensive verification coverage by coordinating reference models built in three different programming languages: 1) The algorithm reference model utilizes scientific computing libraries for algorithm-level verification, and sets up an automatic error threshold checking mechanism based on the precision and numerical range of input / output data types to address the specific needs of high-performance floating-point units in the AI ​​field (such as matrix operations and tensor decomposition); 2) The behavioral equivalence reference model is built according to the Register-Transfer Level (RTL) implementation approach, providing error-free comparison to ensure the design conforms to the architecture scheme; 3) The algorithm prototype benchmark reference model, as the gold standard provided by the algorithm department, directly connects to the core logic of the algorithm team, eliminating semantic conversion errors from algorithm to hardware implementation, enabling cross-team collaborative optimization, and ensuring the correctness of the algorithm implementation. The three models are configurable and callable within the Universal Verification Methodology (UVM) framework. The coordination of the three models in different verification scenarios is controlled by switches, and comparison result logs are automatically generated. The embodiments of this application significantly improve the verification efficiency and accuracy of high-performance floating-point units through collaborative verification of multi-language models, reduce design risks, and are particularly suitable for the verification needs of floating-point computing units dedicated to the AI ​​field.

[0113] This application aims to address the problems existing in current high-performance floating-point unit (HMU) verification methods, such as incomplete verification coverage, difficulty in controlling error thresholds, large semantic conversion errors in cross-team collaboration, and insufficient flexibility in verification scenarios. It provides a verification system and method based on multilingual reference models working collaboratively to meet the verification needs of dedicated floating-point computing units in the AI ​​field. The system uses the UVM verification framework at its core, integrating an algorithm reference model, a behavioral equivalence reference model, and an algorithm prototype baseline reference model. A unified control mechanism enables the collaborative operation of these three models. The external HMU to be verified serves as the verification object, interacting with the three reference models for data exchange and result comparison. Parameter configuration, scene switching, and result recording during the verification process are all managed uniformly by the UVM verification framework.

[0114] The following explains the functionality and verification mechanism of each reference model: 1. Algorithm Reference Model: Built upon a scientific computing library, this model focuses on algorithm-level verification. Addressing the specific needs of high-performance floating-point unit matrix operations in the AI ​​field, this model incorporates an automatic error threshold checking mechanism. This mechanism automatically adjusts the error threshold based on the precision of the input / output data types (e.g., BF16 floating-point precision, FP32 single-precision, FP64 double-precision) and their numerical range. The specific details of this automatic error threshold checking mechanism will be explained below. After receiving input data, the model performs algorithm-level calculations, adhering to the mathematical rules of the algorithm function library without involving specific hardware circuit implementations. The output result is compared with the output result of the floating-point unit to be verified, and the verification is determined based on the automatic error threshold checking mechanism.

[0115] 2. Behavioral Equivalent Reference Model: Constructed according to the RTL implementation approach, this model provides error-free comparison. It strictly adheres to the architectural scheme and supports non-IEEE standard data types (such as custom compressed floating-point formats), ensuring that the design of the floating-point unit to be verified conforms to the architectural requirements. During verification, the model simulates the RTL operation logic to generate the output result, which is then compared bit-by-bit with the output result of the floating-point unit to be verified, achieving error-free verification.

[0116] 3. Algorithm Prototype Benchmark Reference Model: Serving as the gold standard provided by the algorithm department, this model directly interfaces with the core logic of the algorithm team. It employs code implementation approved by the algorithm team, eliminating semantic translation errors during the algorithm-to-hardware implementation process and providing a foundation for cross-team collaborative optimization. During verification, the model directly runs the algorithm's core logic to generate results, which are then compared with the output of the floating-point unit to be verified, ensuring the correctness of the algorithm implementation.

[0117] Within the UVM validation framework, three reference models are configurable and can be invoked. The framework includes multiple control switches, allowing for switching between different validation scenarios through combinations of these switches (e.g., invoking a single model for validation, or simultaneously invoking two or three models for collaborative validation). During validation, the framework automatically collects the comparison results of each model and generates detailed comparison result logs (corresponding to the validation logs in other embodiments). The logs include input data, output results of each model, comparison conclusions, error values, and other information.

[0118] The following describes the process of automatically setting the error comparison threshold, that is, the process of determining the absolute error threshold and the relative error threshold, including: 1. Basic threshold calculation process: Based on the binary structure of the floating-point type (sign bit s, exponent bit E, mantissa bit M), calculate the basic threshold reflecting its inherent precision, see formula (1): (1) Wherein, n_M is the number of mantissa bits (adding 1 bit when including implicit integer bits, corresponding to the first bit in other embodiments), which determines the minimum quantization interval; E is the actual value of the exponent, reflecting the magnitude of the numerical value; k is the exponent compensation coefficient (usually taking the value 1e-5), used to fine-tune the threshold difference of different magnitude values, so that the basic threshold is more in line with the cross-magnitude precision characteristics.

[0119] 2. Calculation process of characteristic value intervals (low interval, middle interval, high interval): Based on the exponent and mantissa structure of floating-point types, the characteristic interval of the numerical range is determined, providing a boundary basis for dynamic adjustment: Determine the minimum positive value Vmin: Calculate based on the minimum non-zero value of the exponent and all zeros in the mantissa, see formula (2): (2) Where Bias is the exponential offset, Bias = , This refers to the number of exponent bits (corresponding to the second number in other embodiments).

[0120] Determine the maximum positive value Vmax: Calculate based on the maximum significant value of the exponent and all 1s in the mantissa, see formula (3): (3) Where n_M is the number of mantissa bits. The number of exponents.

[0121] Determine the low-interval threshold L = max(Vmin × C_L, 1), where C_L is the dynamic expansion coefficient, C_L = Based on the adaptive adjustment of the mantissa length, the expansion of high-precision types is more reasonable. The high-interval threshold H is determined as H = Vmax × C_H, where C_H is the dynamic shrinkage coefficient (initial value 0.01, dynamically optimized through the adaptive learning module: the dynamic shrinkage coefficient is reduced to 0.005 when the high-interval error pass rate is <90%, and increased to 0.02 when the high-interval error pass rate is >95%).

[0122] 3. Dynamic adjustment process of dual threshold fusion: Based on the basic threshold, the effective threshold for judgment is generated by dynamically adjusting the input value range and the calculation scenario. The dynamic adjustment value of the basic threshold = basic threshold × range coefficient × scenario coefficient.

[0123] The interval coefficients are adapted according to the numerical range: low interval (absolute value of input value ≤ L): 1.5 (enhancing sensitivity to small absolute errors); middle interval (L < absolute value of input value ≤ H, corresponding to the middle interval in other embodiments): absolute value of input value ^ 0.3 (improving the distinguishability of the middle value compared to the original 0.2 exponent); high interval (absolute value of input value > H): 20 (tolerating large absolute errors).

[0124] Scenario coefficients are adapted according to operation type: Matrix operation scenario: K represents the matrix dimension. The larger the dimension, the more non-linearly the threshold relaxation increases, adapting to high-dimensional error accumulation. Tensor decomposition scenario: 1+ ×0.1, where n is the decomposition order, increasing by the square root to avoid excessively widening the threshold for higher-order decompositions; Convolution operation scenario: 1 + (convolution kernel size - 1) × 0.05, the larger the kernel size, the more linearly the sliding window error is accommodated.

[0125] 4. The dual-threshold fusion judgment process uses dynamic logic based on absolute and relative errors to determine whether the error is acceptable. First, define the thresholds: Absolute error threshold A = dynamic adjustment value of the base threshold; Relative error threshold R = dynamic adjustment value of the base threshold ÷ |input value| (when the input value ≠ 0).

[0126] The judgment rules include: For the low interval (≤L): only "absolute error value ≤ A" needs to be satisfied (emphasizing absolute error and ignoring small numerical relative error fluctuations); For the middle interval (L<……≤H): both "absolute error value ≤ A and absolute error value ÷ |input value| ≤ R" need to be satisfied (strict judgment under two conditions); For the high interval (>H): only "absolute error value ÷ |input value| ≤ R" needs to be satisfied (emphasizing relative error and adapting to the characteristics of large numerical absolute error); For zero value handling: absolute error value ≤ A×10 (retaining relaxed logic to adapt to zero value sensitivity).

[0127] See Figure 7 , Figure 7This is an overall architecture diagram of the high-performance floating-point unit verification system based on a multilingual reference model provided in this application embodiment, showing the system composition and the connection relationships between the parts. Through the above figures, the system structure and workflow of this application embodiment can be clearly understood. Virtual interface 42 connects floating-point computing unit 41 and driver 43. Sequencer 44 provides stimulus to driver 43 according to stimulus sequence 45, and driver 43 inputs the stimulus to floating-point computing unit 41. Monitor 46 collects the input and output of floating-point computing unit 41. Verification model set 47 includes algorithm reference model 471, behavioral equivalent reference model 472, and algorithm prototype baseline reference model 473. Each model is controlled by an enable signal and calculates a reference result (corresponding to the second calculation result in other embodiments) based on the input data. Scoring board 48 receives the actual result output by floating-point computing unit 41 (corresponding to the first calculation result in other embodiments) collected by monitor 46 and the reference result output by verification model set 47. By comparison, it determines whether the function of floating-point computing unit 41 meets expectations, and thus outputs a verification log. The entire architecture enables the complete process of activation injection, data acquisition and verification log generation for floating-point computing units.

[0128] The embodiments of this application will be further described in detail below with reference to specific examples. When verifying the high-performance floating-point computing unit in an AI chip, the verification system of this application embodiment is used for verification. The specific steps are as follows: 1. System Configuration: Set control switches in the UVM verification framework. Based on the configuration information, the algorithm reference model, behavioral equivalence reference model, and algorithm prototype benchmark reference model can be called for collaborative verification.

[0129] 2. Data Input: Input the same input data, as well as configuration parameters such as data precision and calculation method, into the floating-point computing unit to be verified and the three reference models, which conforms to typical AI computing scenarios such as matrix operations.

[0130] 3. Model Validation: 1) The algorithm reference model uses a scientific computing library to perform matrix operations to obtain the desired result, i.e., the second operation result corresponding to the algorithm reference model. An error comparison mechanism calculates the error threshold or tolerance, and compares the output of the second operation result with the output of the first operation result of the floating-point computing unit to be verified, obtaining the first comparison result corresponding to the algorithm reference model. The error comparison mechanism employs a dual-threshold fusion mechanism of relative and absolute errors. The relative and absolute error tolerances can be pre-configured, and the AND / OR logical operation rules between the two can be configured to determine the comparison strictness. Alternatively, an automatic error threshold algorithm can be used to determine the relative and absolute error thresholds.

[0131] 2) The behavioral equivalent reference model performs calculations according to the RTL implementation approach to generate an error-free reference result, namely the second calculation result corresponding to the behavioral equivalent reference model. This result is compared bit by bit with the first calculation result output by the floating-point calculation unit to be verified to obtain the first comparison result corresponding to the behavioral equivalent reference model.

[0132] 3) The algorithm prototype benchmark reference model runs the core logic code provided by the algorithm team to generate the gold standard result, that is, the second operation result corresponding to the algorithm prototype benchmark reference model. It is compared with the first operation result of the output of the floating-point calculation unit to be verified to obtain the first comparison result corresponding to the algorithm prototype benchmark reference model.

[0133] 4. Result Processing: The UVM verification framework collects the first comparison results of the three models and automatically generates a comparison result log (corresponding to the verification log in other embodiments). The log clearly records the comparison conclusion and error value of each model (such as the comparison error of the algorithm reference model).

[0134] 5. Scene Switching: Switch the verification scene by controlling the switch. For example, call the behavioral equivalent reference model to verify non-IEEE standard data types, or call the algorithm prototype benchmark reference model to verify the correctness of the implementation of the algorithm's core logic. Repeat the above steps to complete the verification under different scenarios.

[0135] Compared with related technologies, the embodiments of this application have the following beneficial effects: First, the comprehensiveness of verification coverage is improved. Through the collaborative work of three different language reference models, multi-level and all-round verification coverage from the algorithm level to the hardware implementation level is achieved, which not only focuses on the correctness of the algorithm logic, but also ensures that the hardware implementation meets the architectural requirements. Second, the verification accuracy is improved. The automatic error threshold checking mechanism adapts to the complex data type requirements of the AI ​​field, the error-free comparison ensures the accuracy of the hardware implementation, and the algorithm prototype benchmark reference model eliminates cross-team semantic conversion errors, which significantly improves the verification accuracy. Third, the verification efficiency is optimized. The configurable calling mechanism and automatic log generation function under the UVM framework make the verification scenario switching flexible and the result analysis convenient, which greatly improves the verification efficiency. Fourth, the design risk is reduced. The collaborative verification of multi-language models can discover problems in the design early and reduce design risks from different levels, which is especially suitable for the high reliability requirements of dedicated floating-point computing units in the AI ​​field.

[0136] The following continues to describe the exemplary structure of the processor floating-point calculation verification device 233 provided in the embodiments of this application as a software module. In some embodiments, such as Figure 2 As shown, the software modules in the processor's floating-point calculation verification device 233 stored in memory 230 may include: The determination module 2331 is configured to, in response to receiving a verification instruction for the floating-point computing unit of the processor, determine a verification model based on the configuration information of the verification instruction, wherein the verification model includes at least two of an algorithm reference model, a behavioral equivalence reference model, and an algorithm prototype baseline reference model; The arithmetic module 2332 is used to perform calculations on the input data through the floating-point calculation unit to obtain a first calculation result; and to perform calculations on the input data through each of the verification models to obtain each of the second calculation results. The determining module 2331 is further configured to determine, for each verification model, a first comparison result corresponding to the verification model based on the error comparison mechanism corresponding to the verification model, the second operation result, and the first operation result; The generation module 2333 is used to generate the verification log of the floating-point calculation unit based on the first comparison result and the second operation result corresponding to each verification model, as well as the first operation result.

[0137] In some embodiments, the determining module 2331 is further configured to determine the absolute error and relative error between the second operation result and the first operation result corresponding to the algorithm reference model; when the error comparison mechanism corresponding to the algorithm reference model is a custom type, obtain a pre-set absolute error tolerance and relative error tolerance, as well as a logical operation rule between the absolute error tolerance and the relative error tolerance; determine a second comparison result based on the absolute error and the absolute error tolerance, and determine a third comparison result based on the relative error and the relative error tolerance; perform logical operations on the second comparison result and the third comparison result based on the logical operation rule to obtain a first comparison result corresponding to the algorithm reference model.

[0138] In some embodiments, the determining module 2331 is further configured to: determine the second comparison result as a first result value when the absolute error is less than or equal to the absolute error tolerance; determine the second comparison result as a second result value when the absolute error is greater than the absolute error tolerance; determine the third comparison result as the first result value when the relative error is less than or equal to the relative error tolerance; and determine the third comparison result as the second result value when the relative error is greater than the relative error tolerance.

[0139] In some embodiments, the determining module 2331 is further configured to determine the absolute error and relative error between the second operation result and the first operation result corresponding to the algorithm reference model; when the error comparison mechanism corresponding to the algorithm reference model is of the automatic type, determine the first number of mantissa bits, the second number of exponent bits, and the actual value of exponent bits of the floating-point calculation unit; determine the absolute error threshold and the relative error threshold based on the first number of mantissa bits, the actual value of exponent bits, and the second number of mantissa bits; determine the fourth comparison result based on the absolute error and the absolute error threshold, and determine the fifth comparison result based on the relative error and the relative error threshold; and determine the first comparison result corresponding to the algorithm reference model based on the fourth comparison result and the fifth comparison result.

[0140] In some embodiments, the determining module 2331 is further configured to: determine a basic threshold for the floating-point calculation unit based on the first number of bits, the actual value of the exponent, and a preset exponent compensation coefficient; determine a low interval, a middle interval, and a high interval based on the first number of bits and the second number of bits; determine a target interval corresponding to the input data from the low interval, the middle interval, and the high interval, and determine the interval coefficient of the target interval; determine a scene coefficient based on the operation type of the input data; determine an absolute error threshold by multiplying the interval coefficient, the scene coefficient, and the basic threshold; and determine a relative error threshold by the ratio of the absolute error threshold to the input data.

[0141] In some embodiments, the determining module 2331 is further configured to: determine the minimum positive value of the floating-point calculation unit based on the second number of bits; determine the maximum positive value of the floating-point calculation unit based on the second number of bits and the first number of bits; determine a low interval threshold based on the first number of bits and the minimum positive value; determine a high interval threshold based on the maximum positive value and a dynamic shrinkage coefficient; construct the low interval based on the low interval threshold as a first upper bound value and a first preset value and the first upper bound value; construct the middle interval based on the high interval threshold as a second upper bound value and the low interval threshold as a first lower bound value and the first lower bound value and the second upper bound value; and construct the high interval based on the high interval threshold as a second lower bound value and positive infinity.

[0142] In some embodiments, the determining module 2331 is further configured to: determine the first alignment result as having passed the alignment when the target interval is the lower interval and the fourth alignment result indicates that the absolute error is less than or equal to the absolute error threshold; determine the first alignment result as having passed the alignment when the target interval is the middle interval and the fourth alignment result indicates that the absolute error is less than or equal to the absolute error threshold and the fifth alignment result indicates that the relative error is less than or equal to the relative error threshold; and determine the first alignment result as having passed the alignment when the target interval is the higher interval and the fifth alignment result indicates that the relative error is less than or equal to the relative error threshold.

[0143] In some embodiments, the determining module 2331 is further configured to determine the product between the absolute error threshold and the second preset value when the input data is zero; and to determine the first comparison result as a successful comparison when the absolute error is less than or equal to the product between the absolute error threshold and the second preset value.

[0144] In some embodiments, the determining module 2331 is further configured to compare the second operation result and the first operation result corresponding to the behavior equivalent reference model based on the error comparison mechanism corresponding to the behavior equivalent reference model to obtain the first comparison result corresponding to the behavior equivalent reference model; or, based on the error comparison mechanism corresponding to the algorithm prototype benchmark reference model, compare the second operation result and the first operation result corresponding to the algorithm prototype benchmark reference model to obtain the first comparison result corresponding to the algorithm prototype benchmark reference model.

[0145] This application provides a computer program product, which includes a computer program or computer-executable instructions stored in a computer-readable storage medium. The processor of an electronic device reads the computer-executable instructions from the computer-readable storage medium and executes the computer-executable instructions, causing the electronic device to perform the floating-point calculation verification method for the processor described in this application embodiment.

[0146] This application provides a computer-readable storage medium storing computer-executable instructions or a computer program. When the computer-executable instructions or the computer program are executed by a processor, the processor will execute the floating-point calculation verification method provided in this application. For example, ... Figure 3 The method for verifying floating-point calculations of the processor is shown.

[0147] In some embodiments, the computer-readable storage medium may be a memory such as RAM, ROM, flash memory, magnetic surface memory, optical disk, or CD-ROM; or it may be a variety of devices including one or any combination of the above-mentioned memories.

[0148] In some embodiments, computer-executable instructions may take the form of programs, software, software modules, scripts, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as stand-alone programs or as modules, components, subroutines, or other units suitable for use in a computing environment.

[0149] As an example, computer-executable instructions may, but do not necessarily, correspond to files in a file system. They may be stored in a portion of a file that holds other programs or data, for example, in one or more scripts in a Hyper Text Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple co-located files (e.g., a file that stores one or more modules, subroutines, or code sections).

[0150] As an example, computer-executable instructions can be deployed to execute on a single electronic device, or on multiple electronic devices located at one location, or on multiple electronic devices distributed across multiple locations and interconnected via a communication network.

[0151] In summary, through the embodiments of this application, a verification model is determined in response to a verification instruction, comprising at least two of the following: an algorithm reference model, a behavioral equivalence reference model, and an algorithm prototype benchmark reference model. This allows for the construction of verification benchmarks from different dimensions. The algorithm reference model ensures the correctness of mathematical logic, the behavioral equivalence reference model matches hardware behavioral logic, and the algorithm prototype benchmark reference model closely approximates real-world application scenarios, avoiding the limitations of a single reference model and achieving multi-dimensional coverage of floating-point computing unit verification. By having the floating-point computing unit and each verification model perform operations on the same input data to obtain a first operation result and multiple second operation results, a direct comparison basis between the actual hardware output and multiple types of reference outputs can be established, ensuring the consistency and comprehensiveness of the comparison objects and facilitating the discovery of differences between hardware operations and reference standards at different levels. For each verification model, its corresponding error comparison mechanism is used to determine the first comparison result. This allows for the formulation of appropriate comparison rules based on the characteristics of different models, avoiding misjudgments caused by a unified comparison standard and improving the accuracy and rationality of the first comparison result. Finally, a verification log is generated based on the first comparison results, the first operation results, and the second operation results. This log can completely retain the hardware output, multiple reference outputs, and comparison conclusions from various dimensions, providing a comprehensive basis for subsequent problem localization, verification process backtracking, and analysis. Therefore, the embodiments of this application can significantly improve the comprehensiveness, accuracy, and traceability of floating-point computing unit verification, effectively ensuring the correctness and reliability of hardware operations.

[0152] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and scope of this application are included within the scope of protection of this application.

Claims

1. A method for verifying floating-point calculations of a processor, characterized in that, The method includes: In response to receiving a verification instruction for the floating-point computing unit of the processor, a verification model is determined based on the configuration information of the verification instruction, the verification model including at least two of an algorithm reference model, a behavioral equivalence reference model, and an algorithm prototype baseline reference model; The floating-point calculation unit performs calculations on the input data to obtain the first calculation result. The input data is processed by each of the verification models to obtain the second calculation results. For each of the verification models, a first comparison result corresponding to the verification model is determined based on the error comparison mechanism corresponding to the verification model, the second calculation result, and the first calculation result. Based on the first comparison result and the second operation result corresponding to each verification model, and the first operation result, a verification log for the floating-point calculation unit is generated.

2. The method according to claim 1, characterized in that, When the verification model includes the algorithm reference model, determining the first alignment result corresponding to the verification model based on the error comparison mechanism corresponding to the verification model, the second calculation result, and the first calculation result includes: Determine the absolute error and relative error between the second operation result and the first operation result corresponding to the algorithm reference model; When the error comparison mechanism corresponding to the algorithm reference model is a custom type, the pre-set absolute error tolerance and relative error tolerance, as well as the logical operation rules between the absolute error tolerance and the relative error tolerance, are obtained. A second alignment result is determined based on the absolute error and the absolute error tolerance, and a third alignment result is determined based on the relative error and the relative error tolerance. Based on the logical operation rules, logical operations are performed on the second comparison result and the third comparison result to obtain the first comparison result corresponding to the algorithm reference model.

3. The method according to claim 2, characterized in that, The determination of the second alignment result based on the absolute error and the absolute error tolerance includes: When the absolute error is less than or equal to the absolute error tolerance, the second comparison result is determined as the first result value; when the absolute error is greater than the absolute error tolerance, the second comparison result is determined as the second result value. The determination of the third alignment result based on the relative error and the relative error tolerance includes: When the relative error is less than or equal to the relative error tolerance, the third comparison result is determined to be the first result value; when the relative error is greater than the relative error tolerance, the third comparison result is determined to be the second result value.

4. The method according to claim 1, characterized in that, When the verification model includes the algorithm reference model, determining the first alignment result corresponding to the verification model based on the error comparison mechanism corresponding to the verification model, the second calculation result, and the first calculation result includes: Determine the absolute error and relative error between the second operation result and the first operation result corresponding to the algorithm reference model; When the error comparison mechanism corresponding to the algorithm reference model is of the automatic type, the first digit of the mantissa, the second digit of the exponent, and the actual value of the exponent of the floating-point calculation unit are determined. Based on the first bit, the actual value of the exponent, and the second bit, determine the absolute error threshold and the relative error threshold; The fourth alignment result is determined based on the absolute error and the absolute error threshold, and the fifth alignment result is determined based on the relative error and the relative error threshold; Based on the fourth and fifth alignment results, the first alignment result corresponding to the algorithm reference model is determined.

5. The method according to claim 4, characterized in that, The step of determining the absolute error threshold and the relative error threshold based on the first bit, the actual value of the exponent, and the second bit includes: Based on the first bit, the actual value of the exponent bit, and the preset exponent compensation coefficient, the basic threshold of the floating-point calculation unit is determined; Based on the first digit and the second digit, the low interval, the middle interval, and the high interval are determined; From the low interval, the middle interval, and the high interval, determine the target interval corresponding to the input data, and determine the interval coefficient of the target interval; Determine the scenario coefficients based on the operation type of the input data; The product of the interval coefficient, the scene coefficient, and the basic threshold is determined as the absolute error threshold; The ratio of the absolute error threshold to the input data is determined as the relative error threshold.

6. The method according to claim 5, characterized in that, The determination of the low interval, middle interval, and high interval based on the first digit and the second digit includes: The minimum positive value of the floating-point calculation unit is determined based on the second bit number, and the maximum positive value of the floating-point calculation unit is determined based on the second bit number and the first bit number. The low-interval threshold is determined based on the first digit and the minimum positive value; the high-interval threshold is determined based on the maximum positive value and the dynamic contraction coefficient. The low interval threshold is used as the first upper bound value, and the low interval is constructed based on the first preset value and the first upper bound value; The high interval threshold is used as the second upper bound, the low interval threshold is used as the first lower bound, and the middle interval is constructed based on the first lower bound and the second upper bound. The high interval threshold is used as the second lower bound, and the high interval is constructed based on the second lower bound and positive infinity.

7. The method according to claim 5, characterized in that, The step of determining the first alignment result corresponding to the algorithm reference model based on the fourth alignment result and the fifth alignment result includes: When the target interval is the lower interval and the fourth comparison result indicates that the absolute error is less than or equal to the absolute error threshold, the first comparison result is determined to be a successful comparison. When the target interval is the middle interval, and the fourth comparison result indicates that the absolute error is less than or equal to the absolute error threshold, and the fifth comparison result indicates that the relative error is less than or equal to the relative error threshold, the first comparison result is determined to be a successful comparison. When the target interval is the high interval and the fifth comparison result indicates that the relative error is less than or equal to the relative error threshold, the first comparison result is determined to be a successful comparison.

8. The method according to claim 7, characterized in that, The method further includes: When the input data is zero, determine the product between the absolute error threshold and the second preset value; When the absolute error is less than or equal to the product of the absolute error threshold and the second preset value, the first comparison result is determined to be a successful comparison.

9. The method according to claim 1, characterized in that, When the verification model includes the behavioral equivalent reference model or the algorithm prototype benchmark reference model, determining the first comparison result corresponding to the verification model based on the error comparison mechanism corresponding to the verification model, the second calculation result, and the first calculation result includes: Based on the error comparison mechanism corresponding to the behavioral equivalent reference model, the second calculation result and the first calculation result corresponding to the behavioral equivalent reference model are compared to obtain the first comparison result corresponding to the behavioral equivalent reference model. Alternatively, based on the error comparison mechanism corresponding to the algorithm prototype benchmark reference model, the second operation result and the first operation result corresponding to the algorithm prototype benchmark reference model are compared to obtain the first comparison result corresponding to the algorithm prototype benchmark reference model.

10. A floating-point calculation verification device for a processor, characterized in that, The device includes: A determination module is configured to, in response to receiving a verification instruction for the floating-point computing unit of the processor, determine a verification model based on configuration information of the verification instruction, wherein the verification model includes at least two of an algorithm reference model, a behavioral equivalence reference model, and an algorithm prototype baseline reference model; The arithmetic module is used to perform calculations on the input data through the floating-point calculation unit to obtain a first calculation result; and to perform calculations on the input data through each of the verification models to obtain each of the second calculation results. The determining module is further configured to, for each verification model, determine a first comparison result corresponding to the verification model based on the error comparison mechanism corresponding to the verification model, the second operation result, and the first operation result; The generation module is used to generate the verification log of the floating-point calculation unit based on the first comparison result and the second operation result corresponding to each verification model, as well as the first operation result.

11. An electronic device, characterized in that, The electronic device includes: Memory is used to store executable instructions or computer programs. A processor, when executing computer-executable instructions or computer programs stored in the memory, implements the method according to any one of claims 1 to 9.

12. A computer-readable storage medium storing computer-executable instructions or a computer program, characterized in that, When the computer-executable instructions or computer program are executed by a processor, they implement the method described in any one of claims 1 to 9.

13. A computer program product comprising computer-executable instructions or a computer program, characterized in that, When the computer-executable instructions or computer program are executed by a processor, they implement the method according to any one of claims 1 to 9.

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