A layout method, device, and storage medium for logic system design.

Abstract

This application provides a layout method, device, and storage medium for logic system design. The method includes: responding to detection of reading a logic description file containing a preset number of circuit units; determining a structured circuit corresponding to the preset number of circuit units based on the logic description file; the structured circuit includes a local physical layout of the circuit units within the structured circuit; generating virtual units and constraint information of the virtual units based on the structured circuit and the logic description file; the logical function of the virtual units is consistent with the preset number of circuit units, and the constraint information of the virtual units is determined based on the structured circuit and the logic description file; performing a global physical layout of the virtual units based on the constraint information to obtain the layout result of the logic system design. This avoids the layout quality degradation caused by oversimplification of physical information in traditional layout compression and expands the scale of circuits that the layout tool can directly lay out.

Description

Technical Field

[0001] This application relates to the field of chip design technology, and in particular to a layout method, device and storage medium for logic system design. Background Technology

[0002] Floorplanning is a crucial step in the back-end design of digital integrated circuits. As digital chips become increasingly large, the gate-level netlists of some SoCs often exceed 1000M gates. Since current place and route tools can only support designs with a relatively small scale compared to the floorplan, typically 5-10M gates, the floorplanning of the floorplanning process requires dividing the floorplan into sections that the place and route tools can support. This process is called partitioning. However, existing partitioning methods fall into two categories. One method forcibly compresses the entire circuit to the size supported by the placement engine, leading to the loss of some circuit information due to over-compression, resulting in a significant decrease in global placement quality compared to a complete gate-level netlist. Furthermore, it is limited by the data base (DB), meaning current place and route tools cannot directly read designs exceeding 1000M gates. The other partitioning method involves manually partitioning the modules based on the data flow and related constraints provided by the front-end, determining the size, shape, and location of each module. This process is time-consuming and labor-intensive, and it relies heavily on the experience of backend design engineers. It usually requires multiple iterations to barely meet the design requirements, resulting in problems such as low layout planning efficiency and easy errors. Summary of the Invention

[0003] In view of this, the purpose of this application is to provide a layout method, device and storage medium for logic system design.

[0004] In a first aspect, this application provides a layout method for designing a logic system, including:

[0005] In response to detecting that a logic description file of a preset number of circuit units has been read, a structured circuit corresponding to the preset number of circuit units is determined based on the logic description file; the structured circuit includes a local physical layout of the circuit units in the structured circuit.

[0006] Virtual units and constraint information of the virtual units are generated based on the structured circuit and the logic description file; the logical function of the virtual unit is consistent with the circuit unit of a preset number of units, and the constraint information of the virtual unit is determined based on the structured circuit and the logic description file.

[0007] Based on the constraint information, a global physical layout is performed on the virtual unit to obtain the layout result of the logic system design.

[0008] In a second aspect, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the program, implements the method described in the first aspect.

[0009] In a third aspect, this application provides a non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform the method described in the first aspect.

[0010] As described above, this application provides a layout method, device, and storage medium for logic system design. By parsing the logic description file of circuit units, a structured circuit containing local physical layout information is automatically constructed. Based on this, virtual units with equivalent logical functions and integrated layout constraints are generated. Subsequently, constraint information (such as timing paths, winding density, design rules, etc.) is used to globally optimize the layout of the virtual units, ultimately outputting a layout scheme that balances logical correctness and physical realizability. On the one hand, the structured circuit generated by parsing the logic description file retains the local physical relationships between the original circuit units and transforms them into constraints for the virtual units. This avoids the layout quality degradation caused by oversimplification of physical information in traditional cluster compression. On the other hand, it decomposes ultra-large-scale designs into a set of virtual units with equivalent logical functions but controllable scale. Each virtual unit aggregates a preset number of circuit unit information from the original design. Through the joint parsing of the logic description file and the structured circuit, the limitation of the direct reading capability of layout tools in traditional methods is overcome, expanding the scale of circuits that layout tools can directly lay out. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 A schematic diagram of the structure of an exemplary electronic device according to an embodiment of this application is shown.

[0013] Figure 2 This is a schematic flowchart illustrating a layout method for a logic system design according to an embodiment of this application. Detailed Implementation

[0014] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0015] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0016] Partitioning is a crucial step in distributing the entire design logic rationally across physical space. Currently, there are two common approaches: The first is an automated method. During the placement process, clustering algorithms are used to reduce the size of the top-level design to a size supported by the placement and routing tools. Then, the placement and routing tools perform a global coarse placement on the top-level design, followed by module partitioning based on the global placement result. The drawback of this approach is that the clusters are typically based on the interconnections of standard cells, and each cluster is treated as a fake macro, forcibly compressing the entire circuit to a size supported by the placement engine. This leads to the loss of some circuit information due to over-compression, and the global placement quality is significantly lower than a complete circuit gate-level netlist. This method is also limited by the data base (DB), meaning that current placement and routing tools cannot directly read designs exceeding 1000M gates. The second approach is a manual method, where module partitioning is performed manually based on the data flow provided by the front end and related constraints, determining the size, shape, and location of each module. This process is time-consuming and labor-intensive, and heavily reliant on the experience of backend design engineers. It usually requires multiple iterations to barely meet the design requirements.

[0017] Therefore, the clustering compression circuit in the top-level automated layout planning leads to a significant decrease in the global layout quality, and the data base of the layout tool cannot support direct reading of large-scale designs, which have become urgent technical problems to be solved.

[0018] Figure 1 A schematic diagram of an electronic device 100 according to an embodiment of this application is shown. The electronic device 100 may be an electronic device running a simulation system. For example... Figure 1As shown, the electronic device 100 may include: a processor 102, a memory 104, a network interface 106, a peripheral interface 108, and a bus 110. The processor 102, memory 104, network interface 106, and peripheral interface 108 are interconnected within the electronic device via the bus 110.

[0019] Processor 102 may be a Central Processing Unit (CPU), a graphics processor, a neural network processor (NPU), a microcontroller (MCU), a programmable logic device, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), or one or more integrated circuits. Processor 102 can be used to perform functions related to the techniques described in this application. In some embodiments, processor 102 may also include multiple processors integrated into a single logic component. Figure 1 As shown, processor 102 may include a first processor 102a, a second processor 102b, and a third processor 102c.

[0020] Memory 104 can be configured to store data (e.g., instruction sets, computer code, intermediate data, etc.). In some embodiments, a simulation test system for simulation test design can be a computer program stored in memory 104. Figure 1 As shown, the data stored in the memory may include program instructions (e.g., program instructions for implementing the verification system of this application) and data to be processed (e.g., the memory may store temporary code generated during the compilation process). The processor 102 may also access the program instructions and data stored in the memory and execute the program instructions to operate on the data to be processed. The memory 104 may include a volatile storage device or a non-volatile storage device. In some embodiments, the memory 104 may include random access memory (RAM), read-only memory (ROM), optical disk, magnetic disk, hard disk, solid-state drive (SSD), flash memory, memory stick, etc.

[0021] Network interface 106 can be configured to provide communication with other external devices to electronic device 100 via a network. This network can be any wired or wireless network capable of transmitting and receiving data. For example, the network can be a wired network, a local wireless network (e.g., Bluetooth, WiFi, Near Field Communication (NFC), etc.), a cellular network, the Internet, or a combination thereof. It is understood that the type of network is not limited to the specific examples described above. In some embodiments, network interface 106 may include any combination of any number of network interface controllers (NICs), radio frequency modules, transceivers, modems, routers, gateways, adapters, cellular network chips, etc.

[0022] The peripheral interface 108 can be configured to connect the electronic device 100 to one or more peripheral devices to enable information input and output. For example, peripheral devices may include input devices such as keyboards, mice, touchpads, touch screens, microphones, and various sensors, as well as output devices such as displays, speakers, vibrators, and indicator lights.

[0023] Bus 110 can be configured to transfer information between various components of electronic device 100 (e.g., processor 102, memory 104, network interface 106, and peripheral interface 108), such as internal buses (e.g., processor-memory bus), external buses (USB port, PCI-E bus), etc.

[0024] It should be noted that although the above electronic device architecture only shows the processor 102, memory 104, network interface 106, peripheral interface 108, and bus 110, in specific implementations, this electronic device architecture may also include other components necessary for normal operation. Furthermore, those skilled in the art will understand that the above electronic device architecture may only include the components necessary for implementing the embodiments of this application, and does not necessarily include all the components shown in the figures.

[0025] Chip design is divided into front-end design and back-end design. Front-end design generally includes multiple stages such as specification definition, RTL (Register Transfer Level) design, simulation verification, logic synthesis, static timing analysis (STA), and formal verification. Front-end design is the process of determining design requirements and outputting a netlist (usually a gate-level netlist circuit). Back-end design includes multiple stages such as design for test (DFT), physical implementation, clock tree synthesis (CTS), placement and routing, parasitic parameter extraction, and layout physical verification. The physical layout is delivered to the chip foundry in GDSII file format, where the actual circuit is fabricated on the silicon wafer, and then packaged and tested to obtain the chip.

[0026] The physical implementation phase of the back-end design is the process of converting the logic design into actual chip placement and interconnection. Its main task is floorplanning, which determines the overall placement of various functional circuits such as IP modules, RAM, and I / O pins. Floorplanning directly affects the final chip area. Treating IP modules, RAM, I / O pins, and other functional circuits as cells, the chip placement problem can be described as: given the size and connection relationships of standard cells and macrocells, constraints (e.g., no component overlap) and optimization objectives (e.g., minimizing bus length), the cell positions are solved.

[0027] The chip layout method provided in this application can be applied to the physical implementation stage or layout planning stage in chip design application scenarios.

[0028] See Figure 2 , Figure 2 A schematic flowchart illustrating a layout method for a logical system design according to an embodiment of this application is shown. The layout method for a logical system design according to an embodiment of this application can be deployed on a terminal or server. Figure 2 In the layout method 200 of the logic system design, the following steps may be further included.

[0029] In step S210, in response to detecting that a logic description file of a preset number of circuit units has been read, a structured circuit corresponding to the preset number of circuit units is determined based on the logic description file; the structured circuit includes the local physical layout of the circuit units in the structured circuit.

[0030] In this context, a preset number of circuit units can refer to a set of logic units divided into preset sizes in the design, such as sub-modules or circuits of a certain scale (e.g., 5000 gates). The logic description file can be a text or binary file (such as a gate-level netlist) containing the logic functions of the circuit units. It defines the connection relationships between units, timing constraints, power consumption parameters, and other design intents, serving as the input for layout planning. A structured circuit can refer to the local physical layout automatically constructed for the preset number of circuit units by parsing the logic description file. For example, it can automatically identify structured circuits where the preset number of circuit units will be placed close together during future layout. Local physical layout can refer to the physical attributes such as the relative positional relationships of circuit units within a structured circuit.

[0031] In some embodiments, determining the structured circuit corresponding to a preset number of circuit units based on the logic description file includes:

[0032] Based on the trained structured circuit generation model, feature extraction is performed on the logic description file to obtain the association features of the circuit units in a preset number of units; the association features are used to indicate the connection relationship and timing association characteristics between the circuit units.

[0033] The associated features are matched with the template features of existing structured circuit templates to determine the structured circuit template corresponding to the template feature that matches the associated features as the target template; the circuit units are laid out based on the physical layout of the target template to obtain the structured circuit;

[0034] Alternatively, the physical layout of the circuit units can be predicted based on the associated features to obtain the structured circuit.

[0035] The structured circuit template generation model learns local clustering patterns of gate circuits from the already laid-out physical design and generates reusable "structured circuit templates." These templates are used in the subsequent netlist reading stage to automatically identify and compress gate circuit combinations that conform to specific layout characteristics, thereby reducing the processing scale of the placement and routing tools while retaining key physical and timing information. Specifically, a pre-trained structured circuit template generation model (such as a neural network GNN or Transformer) extracts the associated features of circuit cells (including connection topology, timing path dependence, fan-out distribution, etc.) from the logic description file, and then generates structured circuits through two paths, improving placement efficiency. The template matching path compares the associated features with the existing template library for similarity, reusing physical layout patterns validated in historical designs (such as the regular grid of MAC arrays and the proximity constraints of HBM interfaces) to ensure physical feasibility and timing convergence. The prediction generation path directly predicts the physical coordinates and density distribution of the cells end-to-end based on the associated features.

[0036] In some embodiments, method 200 further includes:

[0037] The initial model is trained based on the training data to obtain the trained structured circuit generation model; wherein, the training data includes logic system design samples, sample constraint information and corresponding physical layout samples.

[0038] The system can take pre-laid logical system design samples (such as Verilog / SPICE netlists) as input, and simultaneously introduce corresponding sample constraint information (time path priority, fan-out density upper limit, functional module boundary and other design rules) and physical layout samples (such as cell coordinates and metal layer distribution in GDSII files) as triple training data. It adopts graph neural network (GNN) or diffusion model architecture, and through comparative learning (such as constraint violation penalty term) and physical rationality regularization (such as line length / congestion prediction loss), the model learns the mapping law from logical description to physical layout, thereby improving layout efficiency.

[0039] Specifically, local clustering patterns of gate circuits can be extracted from the already laid-out physical design to generate a reusable structured circuit template library and construct a structured circuit generation model. For example, a physical design with completed placement and routing (such as a GDSII file, DEF file, or placement database), including the physical location, connection relationships, timing information, and area occupancy of gate circuits, can be used as training data. First, gate circuit information can be extracted, and standard cells and macros in the physical design can be parsed, recording the type, location, port connections, and timing constraints of each cell. Then, a connection graph can be constructed, using gate circuits as nodes and nets as edges, to build the physical connection graph of the circuit, and edge weights (such as net length and signal type) can be labeled. Next, layout features are labeled, adding physical layout feature labels (such as spacing, winding congestion, and chip utilization) to each gate circuit combination. Then, feature extraction is performed, yielding at least one of the following features: spatial features, i.e., the physical distance and arrangement direction (e.g., horizontal / vertical alignment) between gate circuits; connectivity features, i.e., the interconnection density and critical path participation (e.g., whether it belongs to a timing-constrained path); timing features, i.e., signal delay, clock skew, and setup / hold time constraints; and area features, i.e., the total area of ​​the gate circuit combination, cell spacing, and winding resource usage. The initial model can then be trained based on one or more of the extracted features to obtain a trained structured circuit generation model.

[0040] In some embodiments, the initial model is trained based on training data to obtain the trained structured circuit generation model, including:

[0041] The initial model is embedded based on the sample constraint information to obtain a constrained model architecture;

[0042] Feature extraction is performed on the logic system design sample to obtain sample features; and feature extraction is performed on the physical layout sample to obtain physical layout features;

[0043] Based on the model architecture and the sample features, the physical layout of the logic system design sample is predicted to obtain the predicted layout features;

[0044] The corresponding loss function is determined based on the cross-entropy loss between the predicted layout features and the physical layout features;

[0045] The model parameters of the model architecture are adjusted to minimize the loss function, thereby obtaining the trained structured circuit generation model.

[0046] Specifically, sample constraint information (such as temporal path priority, density upper limit, functional module division, etc.) can be encoded into model-analyzable constraint vectors through an embedding layer, and fused with the initial model (such as GNN or Transformer) to form a constraint-aware architecture. Subsequently, the topological features (such as unit connection relationships, fan-out distribution) of the logic system design samples and the spatial features (such as unit coordinate distribution, metal layer density) of the physical layout samples are extracted in parallel, and the predicted layout features corresponding to the logic design are predicted by the model. Furthermore, a composite loss function based on cross-entropy can be used to simultaneously measure the deviation between the predicted layout and the actual layout in terms of topological consistency (connection relationship matching degree) and physical rationality (temporal path length, congestion index). Finally, the model parameters are dynamically adjusted through the gradient descent algorithm to make the loss function converge to the minimum value.

[0047] In step S220, virtual units and constraint information of the virtual units are generated based on the structured circuit and the logic description file; the logical function of the virtual unit is consistent with the circuit unit of a preset number of units, and the constraint information of the virtual unit is determined based on the structured circuit and the logic description file.

[0048] This process utilizes the physical connections and signal flow characteristics of structured circuits, along with the functional logic relationships defined in the logic description file, for comprehensive processing. Specifically, virtual units are logically equivalent to a predetermined number of actual circuit units, capable of simulating their input-output relationships and internal logic operations. When determining the constraints of virtual units, the physical limitations of the structured circuit (such as signal transmission delay and power supply requirements) and the specifications for circuit operating conditions and performance indicators in the logic description file can be used to accurately determine the constraints of the virtual units, including timing constraints and electrical constraints. This allows for the efficient and accurate creation of virtual units that meet specific logical function requirements and have clearly defined constraints, improving the overall efficiency and quality of circuit layout.

[0049] In some embodiments, the constraint information of the virtual unit includes physical constraint information and timing constraint information;

[0050] The constraint information of the virtual unit is determined based on the structured circuit and the logic description file, including:

[0051] Extract the unit physical parameters and unit timing parameters of the circuit unit based on the logic description file;

[0052] The physical constraint information of the virtual module is determined based on the unit physical parameters and the structured circuit.

[0053] The timing constraint information of the virtual module is determined based on the unit timing parameters and the structured circuit.

[0054] For virtual cell constraint information that includes both physical and timing parameters, the physical and timing parameters of the circuit cells are first extracted from the logic description file. These parameters carry key information about the physical characteristics and timing relationships of the circuit cells. Next, using the extracted physical parameters and the physical layout and connection relationships of the structured circuit, the physical constraints of the virtual cells are determined, such as size and pin positions. Simultaneously, based on the timing parameters and the signal transmission paths and clock relationships of the structured circuit, the timing constraints of the virtual cells are determined, such as signal delays and setup / hold times. This approach accurately determines comprehensive and realistic constraints for the virtual cells, enabling them to more closely resemble the operation of real circuits in subsequent placement processes, whether for functional verification or physical implementation. This effectively improves the accuracy and reliability of the physical layout and reduces design iterations and potential errors caused by inaccurate constraint information.

[0055] In some embodiments, the unit physical parameters include the circuit unit size, circuit unit pin positions, and circuit unit obstacle information;

[0056] Determining the physical constraint information of the virtual module based on the unit physical parameters and the structured circuit includes:

[0057] The virtual cell size of the virtual cell is determined based on the circuit cell size and the physical layout indicated by the structured circuit.

[0058] Based on the structured circuit, the pin positions of the circuit units are mapped to the virtual units to determine the virtual unit pin positions;

[0059] Based on the structured circuit, the obstacle information of the circuit units is merged to obtain virtual unit obstacle information;

[0060] The physical constraint information is generated based on the virtual unit size, the virtual unit pin position, and the virtual unit obstacle information.

[0061] Among these, the physical parameters of a unit can include the circuit unit size, i.e., the physical space occupied by the circuit unit on the chip or circuit board. For example, an amplifier circuit unit may be 2 mm long and 1.5 mm wide. The pin position of a circuit unit can refer to the specific coordinates of the pins that connect to the outside of the circuit unit on the unit. For example, the pins of a digital logic circuit unit are distributed on the four sides of the unit, and each pin has precise x and y coordinate values. The obstacle information of a circuit unit can indicate the obstacle areas inside or around the circuit unit that may affect the layout. For example, for some circuit units with heat sinks, the area where the heat sink is located cannot be covered by other components.

[0062] Since the physical parameters of a unit encompass circuit unit size, pin positions, and obstacle information, the dimensions of the virtual unit are first determined based on the circuit unit size and the physical layout presented by the structured circuit. Then, using the information from the structured circuit, the pin positions of the actual circuit units are accurately mapped to the virtual units, thus clarifying the pin positions of the virtual units. Simultaneously, the obstacle information of the circuit units is merged through the structured circuit to obtain the obstacle information of the virtual units. Finally, the physical constraint information is generated by combining the virtual unit size, pin positions, and obstacle information. This allows for the detailed and precise construction of the physical constraints of the virtual units, ensuring that the virtual units closely match the physical characteristics of the actual circuit units. This provides extremely accurate basic information for subsequent layout planning based on virtual units, effectively avoiding layout conflicts caused by unclear physical constraints, and significantly improving the efficiency and quality of circuit layout.

[0063] In some embodiments, the unit timing parameters include circuit unit delay information and circuit unit power consumption information of the circuit unit;

[0064] Determining the timing constraint information of the virtual module based on the unit timing parameters and the structured circuit includes:

[0065] Based on the circuit unit delay information and the connection relationship indicated by the structured circuit, the sum of the unit delay and interconnection delay of the circuit unit is determined to obtain the virtual unit delay information of the virtual unit.

[0066] Based on the power consumption information of the circuit unit and the connection relationship indicated by the structured circuit, the sum of the dynamic power consumption and static power consumption of the circuit unit is determined to obtain the virtual unit power consumption information of the virtual unit.

[0067] The timing constraint information is obtained based on the virtual unit delay information and the virtual unit power consumption information.

[0068] For virtual cell delay information, the delay information of circuit units can be combined with the connection relationships of structured circuits. For example, in a circuit structure consisting of multiple logic gates connected in series, each logic gate's corresponding circuit unit has its own delay time. Adding the unit delay of each circuit unit to the interconnection delay generated by the interconnection lines between them yields the overall delay of the virtual cell. For virtual cell power consumption information, the power consumption information of circuit units can be combined with the connection relationships of structured circuits. For example, the dynamic and static power consumption of a circuit unit at a specific operating frequency, and considering the influence of other connected units on power consumption, the total power consumption of the virtual cell can be obtained by adding the power consumption of each part. Finally, the virtual cell delay information and virtual cell power consumption information are combined to form timing constraint information. This can avoid signal transmission errors caused by inaccurate timing estimation, such as data instability near the clock edge. At the same time, reasonable power consumption constraints help optimize the power distribution network, prevent circuit overheating caused by excessive power consumption, and improve circuit stability and reliability.

[0069] In some embodiments, the unit timing parameters may further include the unit circuit setup and hold time of the circuit unit; then the timing constraint information of the virtual module may further include the virtual unit setup and hold time. Specifically, when a preset number of circuit units contain timing circuits (e.g., flip-flops), the timing path corresponding to the timing circuits can be identified. For each timing path, the virtual cell setup time Tsetup = Tclk − (Tco + Tlogic + T_net + Tsetup slack − Tskew). Here, Tclk is the system clock cycle, Tco is the register clock-to-Q delay (i.e., the delay from clock input to data output within the source register), Tlogic is the combinational logic delay (i.e., the delay of combinational logic gates on the data path), T_net is the routing delay (i.e., the delay of data routing on the PCB or chip), Tsetup is the destination register setup time (i.e., the minimum time the data in the destination register must remain stable before the rising edge of the clock), Tskew is the clock skew (i.e., the delay difference between the destination clock path and the source clock path), and Tsetup slack is the preset setup time margin. The virtual cell hold time Thold = (Tco + Tlogic + T_net) − (Tskew + Thold slack), where Thold is the destination register hold time (i.e., the minimum time the data in the destination register must remain stable after the rising edge of the clock), and Tholdslack is the preset hold time margin.

[0070] Specifically, the netlist of the logic system design can be read in using layout tools, the structured circuits matching the template can be dynamically identified, virtual cells (Fake Cells) can be generated and replaced with the original circuits, thus achieving netlist compression. Netlist reading can be based on a hierarchical design (processing step-by-step by sub-module) or by gate size in batches (e.g., compression is triggered every 5000 gates read). For example, compression can be triggered when reading a sub-module or when the cumulative number of gates read reaches a threshold (e.g., 5000 gates).

[0071] For the currently read circuit segment (such as a submodule or a 5000-gate circuit), a local connection graph is constructed. Using the index structure of the template library, templates similar to the current circuit segment are quickly matched. The similarity between the circuit segment and the template can be checked for isomorphism in gate combinations and connections, or the similarity between the circuit segment's feature vectors (such as spatial, connectivity, and temporal features) and the template can be calculated. If the similarity exceeds a threshold, a successful match is achieved. If no matching template is found, the online learning function of the pre-trained model can be invoked to generate a new template based on the current circuit segment and update the template library.

[0072] The function of a fake cell is equivalent to a pre-defined number of matching circuit cells, but its physical and timing information is defined by a structured template. Fake LEF files and fake Lib Cell files required for physical layout can be generated. The fake LEF file defines the physical placeholders (such as bounding boxes and port locations), metal layer usage rules, and wiring constraints of the fake cell. The fake Lib Cell file defines the timing model (such as delay, input capacitance, and output load), power consumption model, and area information of the fake cell. LEF / Lib files can be automatically generated using EDA tool APIs or scripts.

[0073] For one or more preset number of circuit units, the corresponding virtual cells (Fake Cells) are replaced, and the connection relationships in the netlist are updated. The input / output ports of the original gate circuits are mapped to the ports of the virtual cells (Fake Cells) to ensure that the external connections remain unchanged. The timing model of the virtual cells (Fake Cells) is appended to the netlist for use by subsequent placement and routing tools. Thus, according to the method of this application, netlist compression is achieved during the placement process, enabling direct reading of the netlist of a large-scale system logic design in one operation, overcoming the limitations of placement tools. For example, assuming the original number of gate circuits is N and the average equivalent number of gates in the structured circuit template is M, the compressed gate size is approximately N / M. Simultaneously, the original information is preserved through the Fake LEF file and Fake Lib Cell file of the virtual cells (Fake Cells), namely physical information (such as the placeholders and port positions of the Fake Cells retaining the physical layout characteristics of the original gate circuits) and timing information (such as the timing model of the Fake Cells retaining the delays and constraints of the original critical paths). While compressing the netlist to a size that the place-and-route tool DB can support, the impact of loss of circuit information after netlist compression and simplification on global placement quality is minimized to the greatest extent.

[0074] In step S230, the virtual unit is physically laid out globally based on the constraint information to obtain the layout result of the logic system design.

[0075] Based on the established physical constraint information (such as size, pin position, obstacle information, etc.) and timing constraint information (delay, power consumption, setup and hold time, etc.) of the virtual cells, these constraints are used as key guiding factors for layout. Using a global layout algorithm, the virtual cells are rationally distributed and placed by comprehensively considering factors such as available space, signal transmission path, and power distribution, thereby obtaining the layout result of the logic system design. This enables efficient and rational layout of virtual cells in physical space.

[0076] In some embodiments, a global physical layout of the virtual units is performed based on the constraint information to obtain the layout result of the logic system design, including:

[0077] In response to the detection that all of the logic description files have been read, a plurality of virtual units and corresponding constraint information are obtained; the number of virtual units is within the allowable range of the layout tool;

[0078] The virtual unit is physically laid out globally using the layout tool to generate the layout result that satisfies the constraint information.

[0079] This process involves compressing the logic description file while reading it, until the entire file is fully read. This allows for the extraction of multiple virtual cells and their corresponding constraint information, while ensuring the number of virtual cells remains within the processing capacity of the placement tool. Based on this constraint information (including physical constraints such as size and pin positions, and timing constraints such as delays and setup / hold times), the placement tool can scientifically and rationally plan the placement of virtual cells in the global physical space, ultimately generating a placement result that meets all constraints. This enables precise and reasonable distribution of virtual cells, improving the performance and stability of the logic system design. It achieves a single, direct reading of the netlist for a large-scale system logic design, overcoming the size limitations of placement tools.

[0080] For example, in logic system design A, the original netlist may contain approximately B gates. Submodule A_1 in the original netlist can be read; submodule A_1 corresponds to C_1 gates. The structured circuit generation model can identify the structured circuit template corresponding to submodule A_1. Then, based on this structured circuit template, a virtual cell FC_1 for submodule A_1 is generated, along with the constraint information corresponding to this virtual cell FC_1 (i.e., physical placeholder Fake LEF and timing information Fake Lib Cell). Submodule A_1 in the original netlist is replaced with one virtual cell FC_1, compressing the C gates of submodule A_1 into approximately one virtual cell FC_1. Next, submodule A_2 in the original netlist can be read; submodule A_2 corresponds to C_2 gates. Similarly, submodule A_2 in the original netlist can be replaced with one virtual cell FC_2, compressing the C_2 gates of submodule A_2 into approximately one virtual cell FC_2. The remaining netlist is read in, and the matching-replacement process described above is repeated until the entire netlist is compressed. Finally, the placement tool directly uses the physical placeholders (Fake LEF) and timing information (Fake Lib Cell) of the Fake Cell to complete the global placement, while maintaining the timing performance of the logic system design A. For example, based on the physical placeholder information of the Fake Cell, the placement tool can prioritize placing matching gates together, reducing subsequent placement adjustments. Furthermore, the timing model of the Fake Cell can be used to optimize the placement of critical paths, avoiding timing degradation caused by compression.

[0081] The layout method for logic system design according to embodiments of this application involves reading in a certain number of pre-laid physical designs, pre-training a structured circuit template generation model, and then automatically identifying structured circuits that will be placed nearby during future layout and creating virtual cells during the netlist reading process, compressing the netlist as it is read. While compressing the netlist to a size supported by the placement and routing tool's data base, the impact of circuit information loss after netlist compression and simplification on the global layout quality is minimized, thus improving the layout efficiency and quality of the logic system design.

[0082] It should be noted that the above description describes some embodiments of this application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0083] Based on the same inventive concept, corresponding to the methods of any of the above embodiments, this application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement a layout method of a logic system design as described in any of the above embodiments.

[0084] Based on the same inventive concept, corresponding to the methods of any of the above embodiments, this application also provides a non-transitory computer-readable storage medium storing computer instructions for causing the computer to execute a layout method of a logic system design as described in any of the above embodiments.

[0085] The computer-readable medium of this embodiment includes permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by a computing device.

[0086] The computer instructions stored in the storage medium of the above embodiments are used to cause the computer to execute a layout method of a logic system design as described in any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0087] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this application (including the claims) is limited to these examples; within the framework of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the embodiments of this application as described above, which are not provided in the details for the sake of brevity.

[0088] Additionally, to simplify the description and discussion, and to avoid obscuring the embodiments of this application, the well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the provided drawings. Furthermore, the apparatus may be shown in block diagram form to avoid obscuring the embodiments of this application, and this also takes into account the fact that the details of the implementation of these block diagram apparatuses are highly dependent on the platform on which the embodiments of this application will be implemented (i.e., these details should be fully understood by those skilled in the art). While specific details (e.g., circuits) have been set forth to describe exemplary embodiments of this application, it will be apparent to those skilled in the art that the embodiments of this application can be implemented without these specific details or with variations thereof. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0089] Although this application has been described in conjunction with specific embodiments thereof, many substitutions, modifications, and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may be used with the embodiments discussed.

[0090] The embodiments of this application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of this application should be included within the protection scope of this application.

Claims

1. A layout method of a logic system design, comprising: in response to detecting reading a preset number of units of a circuit cell, determining a structured circuit corresponding to the preset number of units of the circuit cell based on a logic description file of the circuit cell; the structured circuit comprising a local physical layout of the circuit cell in the structured circuit; generating a virtual cell and constraint information of the virtual cell based on the structured circuit and the logic description file; the logic function of the virtual cell is consistent with the preset number of units of the circuit cell, and the constraint information of the virtual cell is determined based on the structured circuit and the logic description file; performing global physical layout on the virtual cell based on the constraint information to obtain a layout result of the logic system design; wherein the determination of the structured circuit corresponding to the preset number of units of the circuit cell based on the logic description file comprises: performing feature extraction on the logic description file based on a trained structured circuit generation model to obtain associated features of the preset number of units of the circuit cell; the associated features are used to indicate the connection relationship and timing association characteristics between the circuit cells; determining the structured circuit corresponding to the preset number of units of the circuit cell based on the associated features.

2. The method of claim 1, wherein, The determination of the structured circuit corresponding to the preset number of units of the circuit cell based on the associated features comprises: matching the associated features with template features of existing structured circuit templates to determine that the structured circuit template corresponding to the matched template features is a target template; performing layout processing on the circuit cell based on the physical layout of the target template to obtain the structured circuit; or, predicting the physical layout of the circuit cell based on the associated features to obtain the structured circuit.

3. The method of claim 1, wherein, The constraint information of the virtual cell comprises physical constraint information and timing constraint information; then the constraint information of the virtual cell is determined based on the structured circuit and the logic description file, comprising: extracting cell physical parameters and cell timing parameters of the circuit cell based on the logic description file; determining the physical constraint information of the virtual cell based on the cell physical parameters and the structured circuit; determining the timing constraint information of the virtual cell based on the cell timing parameters and the structured circuit.

4. The method of claim 3, wherein, The cell physical parameters comprise circuit cell size, circuit cell pin position and circuit cell obstacle information of the circuit cell; determining the physical constraint information of the virtual cell based on the cell physical parameters and the structured circuit comprises: determining virtual cell size of the virtual cell based on the circuit cell size and the physical layout indicated by the structured circuit; mapping the circuit cell pin position to the virtual cell based on the structured circuit to determine virtual cell pin position of the virtual cell; combining the circuit cell obstacle information based on the structured circuit to obtain virtual cell obstacle information; generate the physical constraint information based on the virtual cell size, the virtual cell pin location, and the virtual cell obstacle information.

5. The method of claim 3, wherein, The cell timing parameter includes circuit cell delay information and circuit cell power consumption information of the circuit cell; determine the timing constraint information of the virtual cell based on the cell timing parameter and the structured circuit, including: determine a sum of a cell delay and an interconnection delay of the circuit cell based on the circuit cell delay information and a connection relationship indicated by the structured circuit, to obtain virtual cell delay information of the virtual cell; determine a sum of dynamic power consumption and static power consumption of the circuit cell based on the circuit cell power consumption information and the connection relationship indicated by the structured circuit, to obtain virtual cell power consumption information of the virtual cell; obtain the timing constraint information based on the virtual cell delay information and the virtual cell power consumption information.

6. The method of claim 1, wherein, perform global physical layout on the virtual cell based on the constraint information, to obtain a layout result of the logic system design, including: in response to detecting reading all the logic description files, obtain a plurality of the virtual cells and corresponding constraint information; the number of the virtual cells is within an allowable range of a layout tool; perform global physical layout on the virtual cell based on the layout tool, to generate the layout result satisfying the constraint information.

7. The method of claim 2, further comprising: train an initial model based on training data to obtain a trained structured circuit generation model; wherein the training data includes a logic system design sample, sample constraint information, and a corresponding physical layout sample.

8. The method of claim 7, wherein, train an initial model based on training data to obtain a trained structured circuit generation model, including: embed the initial model based on the sample constraint information to obtain a model architecture with constraints; perform feature extraction on the logic system design sample to obtain sample features, and perform feature extraction on the physical layout sample to obtain physical layout features; predict a physical layout of the logic system design sample based on the model architecture and the sample features to obtain predicted layout features; determine a corresponding loss function based on a cross-entropy loss between the predicted layout features and the physical layout features; adjust model parameters of the model architecture to minimize the loss function to obtain the trained structured circuit generation model.

9. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, the processor implementing the method of any one of claims 1 to 8 when executing the program.

10. A non-transitory computer-readable storage medium storing computer instructions for causing a computer to execute the method of any one of claims 1 to 8.

Images