Display device and electronic device including the same

Abstract

A display device and an electronic device including the same are provided. The display device includes a first sub-pixel and a second sub-pixel. The first sub-pixel includes: a first transistor connected between a first node and a second node, and including a gate electrode connected to a third node; a second transistor connected between the third node and the fourth node; a first capacitor connected between the second node and the third node; and a first light emitting element connected between the second node and the second power line. The second sub-pixel includes: a third transistor connected between a fifth node and a sixth node, and including a gate electrode connected to a fourth node; a fourth transistor connected between a jth data line and a fourth node; a second capacitor connected between the fourth node and the sixth node; and a second light emitting element connected between the sixth node and the second power line.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0059144, filed on May 3, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Embodiments of this disclosure relate to display devices and electronic devices including display devices. Background Technology

[0004] With the development of information technology, the importance of display devices as the connection medium between users and information has become apparent. As a result, display devices such as liquid crystal displays (LCDs) and organic light-emitting diode (OLED) displays are being used more and more frequently.

[0005] Recently, head-mounted display devices (HMDs) have been developed. A head-mounted display device is a display device worn by a user in the form of glasses or a helmet to focus images at a distance close to the user's eyes, enabling virtual reality (VR) or augmented reality (AR). High-resolution panels can be used in head-mounted display devices, and therefore, it is desirable to have a high number of pixels that can be applied to these panels.

[0006] The information disclosed in this background section is intended to enhance understanding of the background of this disclosure, and therefore may contain information that does not constitute prior art. Summary of the Invention

[0007] One or more embodiments of this disclosure may relate to a display device for supplying a data voltage corresponding to each sub-pixel.

[0008] According to one or more embodiments of this disclosure, a display device includes: a first sub-pixel and a second sub-pixel connected to a first scan line, a second scan line, and a j-th data line, where j is an integer greater than 1; the first scan line is configured to receive a first scan signal, and the second scan line is configured to receive a second scan signal. The first sub-pixel is located in the i-th pixel row and the j-th pixel column, where i is an integer greater than 0, and the first sub-pixel includes: a first transistor connected between a first node and a second node, and including a gate electrode connected to a third node; the first node being configured to receive a first driving power supplied from a first power line; a second transistor connected between a third node and a fourth node, and configured to conduct when the second scan signal is supplied to the second scan line; a first capacitor connected between the second node and the third node; and a first light-emitting element connected between the second node and a second power line configured to receive the second driving power. The second sub-pixel is located in the i-th pixel row and the (j-1)-th pixel column, and includes: a third transistor connected between the fifth node and the sixth node, and including a gate electrode connected to the fourth node, the fifth node being configured to receive a first driving power supplied from the first power line; a fourth transistor connected between the j-th data line and the fourth node, and configured to be turned on when the first scan signal is supplied to the first scan line; a second capacitor connected between the fourth node and the sixth node; and a second light-emitting element connected between the sixth node and the second power line.

[0009] In an embodiment, the first sub-pixel may further include: a fifth transistor connected between the second node and a third power line configured to receive initialization power, the fifth transistor being configured to turn on when the first scan signal is supplied to the first scan line; and the second sub-pixel may further include: a sixth transistor connected between the sixth node and the third power line, the sixth transistor being configured to turn on when the first scan signal is supplied to the first scan line.

[0010] In an embodiment, during a horizontal time period, the supply stop time of the second scan signal may be earlier than the supply stop time of the first scan signal.

[0011] In an embodiment, a horizontal time period may include a first time period and a second time period. The start time of the second time period may be after the end time of the first time period. During the first time period, a first scan signal and a second scan signal may be supplied, and during the second time period, the first scan signal may be supplied and the supply of the second scan signal may be stopped.

[0012] In an embodiment, the third node and the fourth node can be configured to receive a first data voltage corresponding to the first sub-pixel during a first time period, and the fourth node can be configured to receive a second data voltage corresponding to the second sub-pixel during a second time period.

[0013] In an embodiment, a horizontal time period may further include a third time period, the start time of the first time period may be after the end time of the third time period, and the second scan signal may be supplied and the first scan signal may be stopped during the third time period.

[0014] In an embodiment, the first sub-pixel may further include a third capacitor connected between the third node and the first power line.

[0015] According to one or more embodiments of the present disclosure, a display device includes: a first sub-pixel and a second sub-pixel connected to a first scan line, a second scan line, a j-th data line and an emission control line, wherein j is an integer greater than 1, the first scan line is configured to receive a first scan signal, and the second scan line is configured to receive a second scan signal. The first sub-pixel is located in the i-th pixel row and j-th pixel column, where i is an integer greater than 0, and the first sub-pixel includes: a first transistor connected between the first node and the second node, and including a gate electrode connected to the third node; a second transistor connected between the third node and the fourth node, and configured to be turned on when the second scan signal is supplied to the second scan line; a third transistor connected between the first node and a first power line configured to receive the first driving power, and configured to be turned on when the first transmission signal is supplied to the first transmission control line in the transmission control lines; a fourth transistor connected between the second node and the fifth node, and configured to be turned on when the second transmission signal is supplied to the second transmission control line in the transmission control lines; a first capacitor connected between the second node and the third node; and a first light-emitting element connected between the fifth node and the second power line configured to receive the second driving power. The second sub-pixel is located in the i-th pixel row and the (j-1)-th pixel column, and includes: a fifth transistor connected between the sixth and seventh nodes, and including a gate electrode connected to the fourth node; a sixth transistor connected between the j-th data line and the fourth node, and configured to be turned on when a first scan signal is supplied to the first scan line; a seventh transistor connected between the sixth node and the first power line, and configured to be turned on when a first transmit signal is supplied to the first transmit control line; an eighth transistor connected between the seventh and eighth nodes, and configured to be turned on when a second transmit signal is supplied to the second transmit control line; a second capacitor connected between the fourth and seventh nodes; and a second light-emitting element connected between the eighth node and the second power line.

[0016] In an embodiment, the first sub-pixel may further include: a ninth transistor connected between the fifth node and a third power line configured to receive initialization power, the ninth transistor being configured to turn on when a second scan signal is supplied to the second scan line; and the second sub-pixel may further include: a tenth transistor connected between the eighth node and the third power line, the tenth transistor being configured to turn on when a second scan signal is supplied to the second scan line.

[0017] In an embodiment, the first sub-pixel and the second sub-pixel may be further connected to a third scan line configured to receive a third scan signal; the first sub-pixel may further include an eleventh transistor connected between the third node and a fourth power line configured to receive reference power, the eleventh transistor being configured to turn on when the third scan signal is supplied to the third scan line; and the second sub-pixel may further include a twelfth transistor connected between the fourth node and the fourth power line, the twelfth transistor being configured to turn on when the third scan signal is supplied to the third scan line.

[0018] In an embodiment, the voltage level of the reference power may be higher than the voltage level of the initial power.

[0019] In an embodiment, the first sub-pixel may further include a third capacitor connected between the second node and the first power line, and the second sub-pixel may further include a fourth capacitor connected between the seventh node and the first power line.

[0020] In an embodiment, during a horizontal time period, the supply stop time of the second scan signal may be earlier than the supply stop time of the first scan signal.

[0021] In an embodiment, a horizontal time period may include a first time period, a second time period, a third time period, a fourth time period, and a fifth time period; the start time of the second time period may be after the end time of the first time period; during the first time period, a second scan signal, a third scan signal, and a second transmission signal may be supplied, and the supply of the first scan signal and the first transmission signal may be stopped; and during the second time period, a second scan signal, a third scan signal, and a first transmission signal may be supplied, and the supply of the first scan signal and the second transmission signal may be stopped.

[0022] In this embodiment, the start time of the third time period may be after the end time of the second time period; and during the third time period, the first scan signal and the second scan signal may be supplied, and the supply of the third scan signal, the first transmission signal and the second transmission signal may be stopped.

[0023] In an embodiment, the third node and the fourth node can be configured to receive a first data voltage corresponding to the first sub-pixel during a third time period.

[0024] In this embodiment, the start time of the fourth time period may be after the end time of the third time period; and during the fourth time period, the first scan signal may be supplied, and the supply of the second scan signal, the third scan signal, the first transmission signal, and the second transmission signal may be stopped.

[0025] In an embodiment, the fourth node can be configured to receive a second data voltage corresponding to the second sub-pixel during a fourth time period.

[0026] In this embodiment, the start time of the fifth time period may be after the end time of the fourth time period; and during the fifth time period, the second scanning signal and the second transmission signal may be supplied, while the supply of the first scanning signal, the third scanning signal and the first transmission signal may be stopped.

[0027] In this embodiment, after the fifth time period, the supply of the first scan signal, the second scan signal, and the third scan signal may be stopped, while the first transmission signal and the second transmission signal may be supplied.

[0028] According to some embodiments of this disclosure, the display device may supply a data voltage corresponding to each sub-pixel without using or including a separate demultiplexer.

[0029] According to one or more embodiments of this disclosure, an electronic device includes: a processor for providing input image data; and a display device for displaying an image based on the input image data. The display device includes: a first sub-pixel and a second sub-pixel connected to a first scan line, a second scan line, and a j-th data line, where j is an integer greater than 1; the first scan line is configured to receive a first scan signal, and the second scan line is configured to receive a second scan signal. The first sub-pixel is located in the i-th pixel row and the j-th pixel column, where i is an integer greater than 0, and the first sub-pixel includes: a first transistor connected between a first node and a second node, and including a gate electrode connected to a third node; the first node being configured to receive a first driving power supplied from a first power line; a second transistor connected between a third node and a fourth node, and configured to conduct when a second scan signal is supplied to the second scan line; a first capacitor connected between the second node and the third node; and a first light-emitting element connected between the second node and a second power line configured to receive the second driving power. The second sub-pixel is located in the i-th pixel row and the (j-1)-th pixel column, and includes: a third transistor connected between the fifth node and the sixth node, and including a gate electrode connected to the fourth node, the fifth node being configured to receive a first driving power supplied from the first power line; a fourth transistor connected between the j-th data line and the fourth node, and configured to be turned on when the first scan signal is supplied to the first scan line; a second capacitor connected between the fourth node and the sixth node; and a second light-emitting element connected between the sixth node and the second power line.

[0030] However, this disclosure is not limited to the foregoing aspects and features, and the foregoing and additional aspects and features will be set forth in part in the following detailed description with reference to the accompanying drawings, and will be apparent in part from thereto, or may be learned by practice of one or more of the embodiments presented in this disclosure. Attached Figure Description

[0031] The above and other aspects and features of this disclosure will be more clearly understood from the following detailed description of illustrative, non-limiting embodiments with reference to the accompanying drawings.

[0032] Figure 1 The figure illustrates a transistor according to an embodiment of the present disclosure.

[0033] Figure 2 This is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0034] Figure 3 The figure illustrates an embodiment according to the present disclosure. Figure 2 The block diagram shown depicts the scan driver, pixel unit, and emitter driver.

[0035] Figure 4 The figure illustrates an embodiment according to the present disclosure. Figure 2 The circuit diagram of the sub-pixel is shown.

[0036] Figure 5 The figure illustrates an embodiment according to the present disclosure. Figure 4 The waveform diagram of the sub-pixel driving method is shown in the figure.

[0037] Figures 6 to 8 It shows the basis Figure 5 The circuit diagram shown in the figure illustrates the pixel operation process of the signal.

[0038] Figure 9 The figure illustrates an embodiment according to the present disclosure. Figure 2 The circuit diagram of the sub-pixel is shown in the figure.

[0039] Figure 10 The figure illustrates an embodiment according to the present disclosure. Figure 9 The waveform diagram of the sub-pixel driving method is shown in the figure.

[0040] Figure 11 The figure illustrates an embodiment according to the present disclosure. Figure 2 The circuit diagram of the sub-pixel is shown.

[0041] Figure 12 The figure illustrates an embodiment according to the present disclosure. Figure 11 The waveform diagram of the sub-pixel driving method is shown in the figure.

[0042] Figures 13 to 18 The diagram shows that it depends on Figure 12 The circuit diagram shown in the figure illustrates the pixel operation process of the signal.

[0043] Figure 19 This is a block diagram illustrating an electronic device according to an embodiment of the present disclosure.

[0044] Figure 20 It is shown in the figure. Figure 19 A schematic diagram illustrating an example of an electronic device implemented as a smartphone.

[0045] Figure 21 It is shown in the figure. Figure 19 The electronic device is a schematic diagram of an example of a tablet computer. Detailed Implementation

[0046] In the following description, embodiments will be illustrated in more detail with reference to the accompanying drawings, in which the same reference numerals refer to the same elements throughout. However, this disclosure may be embodied in various different forms and should not be construed as being limited to the embodiments illustrated herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey the aspects and features of this disclosure to those skilled in the art. Accordingly, processes, elements, and techniques that are not essential for a person of ordinary skill in the art to fully understand the aspects and features of this disclosure may not be described. Unless otherwise stated, the same reference numerals indicate the same elements throughout the accompanying drawings and the written description, and therefore, redundant descriptions thereof are not required.

[0047] When an embodiment can be implemented differently, the specific order of processing may differ from the order described. For example, two consecutively described processes may be executed simultaneously or substantially simultaneously, or they may be executed in the reverse order of the described process.

[0048] Furthermore, as those skilled in the art will understand, given the overall content of this disclosure, each suitable feature of the various embodiments of this disclosure may be combined or integrated with each other in part or in whole, and may be technically interlocked and operated in various suitable ways, and each embodiment may be implemented independently of each other or in combination with each other in any suitable way, unless otherwise stated or implied.

[0049] In the accompanying drawings, for clarity, the relative dimensions, thicknesses, and proportions of elements, layers, and regions may be exaggerated and / or simplified. For ease of interpretation, spatially related terms such as “below,” “under,” “down,” “below,” “above,” and “on” are used herein to describe the relationship between one element or feature illustrated in the figures and one or more other elements or features. It will be understood that, in addition to the orientations depicted in the figures, spatially related terms are intended to cover different orientations of the device in use or operation. For example, if the device in the figures is flipped, an element described as “below” or “under” or “below” other elements or features will be oriented “above” other elements or features. Thus, the example terms “below” and “below” can cover both above and below orientations. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatially related descriptors used herein should be interpreted accordingly.

[0050] Furthermore, it should be anticipated that the shapes shown in the figures may vary in practice depending on, for example, tolerances and / or manufacturing techniques. Accordingly, the embodiments of this disclosure should not be construed as limited to the specific shapes shown in the figures, and should be interpreted in light of variations in shape that may occur, for example, due to manufacturing processes. Thus, the shapes shown in the figures may not depict the actual shape of an area of ​​the device, and this disclosure is not limited thereto.

[0051] In the diagram, the x-axis, y-axis, and z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular or substantially perpendicular to each other, or they can represent different directions that are not perpendicular to each other.

[0052] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, the first element, component, area, layer, or part described below may be referred to as the second element, component, area, layer, or part without departing from the spirit and scope of this disclosure.

[0053] It will be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it can be directly on, directly connected to, or coupled to that other element or layer, or there may be one or more intervening elements or layers. Similarly, when a layer, region, or element is referred to as being "electrically connected" to another layer, region, or element, it can be directly electrically connected to that other layer, region, or element, and / or can be indirectly electrically connected to that other layer, region, or element, with one or more intervening layers, regions, or elements between them. Furthermore, it will be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or there may be one or more intervening elements or layers.

[0054] The terminology used herein is for the purpose of describing particular embodiments and is not intended to limit this disclosure. As used herein, the singular forms “a” and “an” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that, when used in this specification, the terms “comprising,” “including,” “comprise,” “including,” “having,” “containing,” and “having” specify the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, the expression “A and / or B” means A, B, or A and B. When expressions such as “at least one of…” follow a list of elements, they modify the entire list of elements and do not modify the individual elements in the list. For example, the expressions “at least one of a, b and c” and “at least one of the group consisting of a, b and c” mean only a, only b, only c, both a and b, both a and c, both b and c, all a, b and c, or variations thereof.

[0055] As used herein, the terms “approximately,” “about,” and similar terms are used as terms of approximation and not as terms of degree, and are intended to describe inherent biases in measurements or calculations that will be recognized by one of ordinary skill in the art. Furthermore, when describing embodiments of this disclosure, the word “may” means “one or more embodiments of this disclosure.” As used herein, the terms “use,” “utilized,” and “used” can be considered synonymous with the terms “exploited,” “utilized,” and “exploited,” respectively.

[0056] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms (such as those defined in common dictionaries) shall be interpreted as having a meaning consistent with their meaning in the relevant field and / or the context of this specification, and shall not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0057] Figure 1 The figure illustrates a transistor according to an embodiment of the present disclosure.

[0058] refer to Figure 1According to embodiments of the present disclosure, transistor 1 may include a first electrode 2, a second electrode 4, a gate electrode 6, and a body electrode 8. For example, transistor 1 may be a metal-oxide-semiconductor field-effect transistor (MOSFET). Because transistor 1 (e.g., a MOSFET) including body electrode 8 can have a smaller mounting area, it can be suitable for implementing high-resolution pixels.

[0059] Transistor 1 can be formed on a silicon wafer. For example, a panel can be realized by stacking transistor layers, light-emitting layers, and capping layers on a silicon wafer. However, this disclosure is not limited thereto, and transistor 1 can be formed on various suitable substrates (e.g., glass substrates) known to those skilled in the art.

[0060] The first electrode 2 of transistor 1 can be the drain electrode (or source electrode), and the second electrode 4 of transistor 1 can be the source electrode (or drain electrode). When transistor 1 includes a body electrode 8, the threshold voltage of transistor 1 may be altered due to the body effect. The body effect refers to the change in the threshold voltage of transistor 1 due to the voltage difference between the body electrode 8 and the source electrode (e.g., the second electrode 4) of transistor 1.

[0061] For example, when the voltage level of the source electrode 4 is higher than the voltage level of the body electrode 8, the threshold voltage may increase. When the threshold voltage of transistor 1 changes, the magnitude of the current flowing from the drain electrode 2 of transistor 1 to the source electrode 4 may change.

[0062] According to some embodiments of this disclosure, threshold voltage compensation is possible while using transistor 1 as a driving transistor.

[0063] Figure 2 This is a block diagram illustrating a display device according to an embodiment of the present disclosure. Figure 3 The figure illustrates an embodiment according to the present disclosure. Figure 2 The block diagram shown depicts the scan driver, pixel unit, and emitter driver.

[0064] refer to Figure 2 The display device 100 according to embodiments of the present disclosure includes pixel units 110 (e.g., a pixel panel), a timing controller 120, a scan driver 130, a data driver 140, a power supply 150, and a transmit driver 160. Some of these components may be implemented as separate integrated circuits, and two or more of these components may be integrated and implemented as a single integrated circuit. In some embodiments, the scan driver 130 and / or the transmit driver 160 may be formed in the pixel unit 110.

[0065] Pixel unit 110 may include sub-pixels SP connected to first scan lines SL11 to SL1n, second scan lines SL21 to SL2n, data lines DL1 to DLm, transmit control lines EL1 to ELo, and power lines PL1, PL2, and PL3, wherein n, m, and o are integers greater than zero.

[0066] exist Figure 2 In the diagram, the sub-pixel SP is shown connected to the first scan lines SL11 to SL1n, the second scan lines SL21 to SL2n, the data lines DL1 to DLm, the transmit control lines EL1 to ELo, and the power lines PL1, PL2, and PL3. However, this disclosure is not limited thereto, and in some embodiments, the sub-pixel SP may be further connected to the third scan line, the fourth scan line, and the fourth power line.

[0067] Each of the subpixels SP can include at least one light-emitting element to generate light. Accordingly, each of the subpixels SP can generate light of a desired color (e.g., a specific or predetermined color), such as red, green, blue, cyan, magenta, or yellow. Two or more subpixels SP can constitute a pixel PXL. For example, as... Figure 2 As shown, three sub-pixels SP can form a pixel PXL.

[0068] The sub-pixel SPij is set at the i-th horizontal line (e.g., the i-th pixel row) and the j-th vertical line (e.g., the j-th pixel column). (See also: [link to relevant documentation]) Figure 4 The data lines EL1, EL2, ELk, and DLj can be connected to the first scan line SL1i, the second scan line SL2i, the k-th transmit control line ELk, and the j-th data line DLj, where i is an integer less than or equal to n, j is an integer less than or equal to m, and k is an integer less than or equal to 0. For example, k can be a number equal to or less than i. As an example, when each of the transmit control lines EL1 to ELo is connected to a sub-pixel SP set on a single horizontal line, k can be the same number as i. As another example, when each of the transmit control lines EL1 to ELo is connected to a sub-pixel SP set on two or more horizontal lines, k can be a number less than i.

[0069] When a first scan signal is supplied to each of the first scan lines SL11 to SL1n, subpixels SP can be selected on a horizontal line basis (e.g., subpixels SP connected to the same scan line can be grouped into a horizontal line or a pixel row). The subpixel SP selected by the first scan signal can receive data signals from the data lines connected to the subpixel SP (e.g., any corresponding line from DL1 to DLm). The subpixel SP receiving the data signal can generate light with a desired brightness (e.g., a specific or predetermined brightness) in response to the voltage of the data signal.

[0070] Although some of the accompanying drawings illustrate that the subpixel SP is connected to the first scan line SL1i and the second scan line SL2i, the kth emission control line ELk and the jth data line DLj, this disclosure is not limited thereto, and the subpixel SP may be connected to two or more scan lines and two or more emission control lines.

[0071] The timing controller 120 can receive input data Din and control signals CS from the host system via an interface. For example, the timing controller 120 can receive input data Din and control signals CS from at least one of a graphics processing unit (GPU), a central processing unit (CPU), and an application processor (AP) included in the host system. The control signals CS can include various suitable signals including a clock signal.

[0072] The timing controller 120 can generate a scan drive signal SCS, a data drive signal DCS, and a transmit drive signal ECS based on the control signal CS. The scan drive signal SCS, the data drive signal DCS, and the transmit drive signal ECS can be supplied to the scan driver 130, the data driver 140, and the transmit driver 160, respectively.

[0073] The timing controller 120 can arrange or rearrange the input data Din to match the specifications of the display device 100. Furthermore, the timing controller 120 can correct the input data Din to generate output data Dout, and can supply the output data Dout to the data driver 140. In some embodiments, the timing controller 120 can correct the input data Din in response to optical measurements taken during processing.

[0074] The scan driver 130 may receive a scan drive signal SCS from the timing controller 120. The scan drive signal SCS may include at least one scan start signal for driving the scan driver 130 and / or may further include at least one clock signal for driving the scan driver 130. The scan driver 130 may generate a first scan signal and a second scan signal while shifting the scan start signal in response to the clock signal.

[0075] Thus, the scan driver 130 may include a first scan driver 132 and a second scan driver 134, such as Figure 3 As shown in the image.

[0076] The first scan driver 132 can receive a first scan start signal FLM1 and can generate a first scan signal while shifting the first scan start signal FLM1 in response to a clock signal. The first scan driver 132 can sequentially supply the first scan signal to the first scan lines SL11 to SL1n.

[0077] The second scan driver 134 can receive a second scan start signal FLM2 and can generate a second scan signal while shifting the second scan start signal FLM2 in response to a clock signal. The second scan driver 134 can sequentially supply the second scan signal to the second scan lines SL21 to SL2n. The first scan signal and the second scan signal can have (for example, can be set to) a gate on-voltage such that the transistor included in the pixel PXL can be turned on.

[0078] For example, a first scan signal and a second scan signal at a low level can be supplied to a P-type transistor, and a first scan signal and a second scan signal at a high level can be supplied to an N-type transistor. The transistor receiving the first scan signal or the second scan signal can be turned on in response to the first scan signal or the second scan signal. As used herein, supplying the first scan signal and the second scan signal can mean that a gate-on voltage is supplied to the first scan line SL1i and the second scan line SL2i. Furthermore, as used herein, stopping the supply of the first scan signal and the second scan signal can mean that a gate-off voltage is supplied to the first scan line SL1i and the second scan line SL2i.

[0079] although Figure 3 A first scan driver 132 connected to first scan lines SL11 to SL1n and a second scan driver 134 connected to second scan lines SL21 to SL2n are shown, but this disclosure is not limited thereto. For example, the first scan lines SL11 to SL1n and the second scan lines SL21 to SL2n can be driven by a single scan driver.

[0080] Data driver 140 can receive output data Dout and data drive signal DCS from timing controller 120. Data drive signal DCS may include sampling signals and / or timing signals for driving data driver 140.

[0081] The data driver 140 can generate a data signal based on the data drive signal DCS and the output data Dout. For example, the data driver 140 can generate an analog data signal based on the grayscale (e.g., gray level) of the output data Dout.

[0082] The data driver 140 can apply a constant or substantially constant voltage to the data lines DL1 to DLm based on the generated analog data signal. For example, refer to... Figure 5 The data driver 140 can supply the voltage of the data signal Vdata to the data lines DL1 to DLm during a horizontal time period 1H.

[0083] In some embodiments, the display device 100 may include a demultiplexer for supplying a voltage to a data signal Vdata corresponding to each of the sub-pixels SP. The demultiplexer may supply the voltage applied to each of the data lines DL1 to DLm to the corresponding sub-pixel SP. For example, a first voltage applied to the first data line DL1 may be supplied to the first sub-pixel, and a second voltage applied to the first data line DL1 may be supplied to the second sub-pixel. Since the demultiplexer is powered, it may be desirable to omit it.

[0084] Power supply 150 can generate various appropriate electrical powers (e.g., voltages) to drive display device 100. For example, power supply 150 can generate a first driving power VDD, a second driving power VSS, and an initialization power Vint.

[0085] The first driving power VDD can be the power that supplies driving current to the sub-pixel SP. The second driving power VSS can be the power that receives driving current from the sub-pixel SP. During the period when the sub-pixel SP emits light, the first driving power VDD can have a higher voltage than the second driving power VSS.

[0086] The initial power Vint can be the light-emitting elements LD1 and LD2 that will be included in the sub-pixel SP (see, for example, see...). Figure 4 The initialization power Vint is the voltage value that, when supplied to the first electrode (e.g., the anode electrode) of the light-emitting element, causes the light-emitting element (e.g., LD1 and / or LD2) to turn off.

[0087] The first driving power VDD generated by power supply 150 can be supplied to the first power line PL1, the second driving power VSS can be supplied to the second power line PL2, and the initialization power Vint can be supplied to the third power line PL3. The first power line PL1, the second power line PL2, and the third power line PL3 can be connected together to the sub-pixel SP, but this disclosure is not limited thereto.

[0088] In some embodiments, power supply 150 may generate a reference power VRF having a voltage level greater than the initial power Vint (e.g., see...). Figure 11 Power supply 150 can be supplied via the fourth power line PL4 (see, for example, see...). Figure 11 The reference power VRF will be supplied to the sub-pixel SP.

[0089] In some embodiments, the first power line PL1 may consist of multiple power lines, and these multiple power lines may be connected to different sub-pixels SP.

[0090] In some embodiments, the second power line PL2 may consist of multiple power lines, and these multiple power lines may be connected to different sub-pixels SP.

[0091] In some embodiments, the third power line PL3 may consist of multiple power lines, and these multiple power lines may be connected to different sub-pixels SP. In some embodiments, the sub-pixel SP may be connected to one of the first power lines PL1, one of the second power lines PL2, and one of the third power lines PL3.

[0092] The transmit driver 160 can receive a transmit drive signal ECS from the timing controller 120. The transmit drive signal ECS may include a transmit start signal EFLM for driving the transmit driver 160 and at least one clock signal. The transmit driver 160 can generate a transmit signal while shifting the transmit start signal in response to the clock signal. The transmit driver 160 can sequentially supply the transmit signals to the transmit control lines EL1 to ELo. The transmit signals may have (e.g., may be set to) a gate on-voltage such that transistors included in the sub-pixel SP can be turned on.

[0093] As used herein, supplying a transmit signal can mean that the gate on voltage is supplied to the transmit control lines EL1 through ELo. As used herein, stopping the supply of a transmit signal can mean that the gate off voltage is supplied to the transmit control lines EL1 through ELo.

[0094] Figure 4 The figure illustrates an embodiment according to the present disclosure. Figure 2 The circuit diagram of the sub-pixel is shown. Figure 4 It is shown Figure 2 A diagram of one embodiment of the pixel PXL shown.

[0095] refer to Figure 4 The figure shows a first sub-pixel SPij located on the i-th horizontal line and the j-th vertical line, and a second sub-pixel SPi(j-1) located on the i-th horizontal line and the (j-1)-th vertical line, where i can be an integer greater than 0 and j can be an integer greater than 1.

[0096] Each of the first sub-pixel SPij and the second sub-pixel SPi(j-1) can be connected to a corresponding signal line. For example, the first sub-pixel SPij can be connected to the first scan line SL1i, the second scan line SL2i, and the j-th data line DLj. The second sub-pixel SPi(j-1) can be connected to the first scan line SL1i, the second scan line SL2i, and the j-th data line DLj. In some embodiments, each of the first sub-pixel SPij and the second sub-pixel SPi(j-1) can be further connected to the first power line PL1, the second power line PL2, and the third power line PL3.

[0097] In other words, the first sub-pixel SPij and the second sub-pixel SPi(j-1) can be connected to the same signal lines (e.g., the first scan line SL1i, the second scan line SL2i, and the j-th data line DLj). The second sub-pixel SPi(j-1) can be located in the same pixel row as the first sub-pixel SPij, and can also be located in a pixel column adjacent to the first sub-pixel SPij. (See reference) Figure 2 The first sub-pixel SPij and the second sub-pixel SPi(j-1) can be included in a single pixel PXL.

[0098] According to embodiments of this disclosure, a first sub-pixel SPij may include a first light-emitting element LD1 and a pixel circuit for controlling the amount of current supplied to the first light-emitting element LD1. A second sub-pixel SPi(j-1) may include a second light-emitting element LD2 and a pixel circuit for controlling the amount of current supplied to the second light-emitting element LD2.

[0099] The pixel circuit of the first sub-pixel SPij may include a first transistor M1_1, a second transistor M2_1, a third transistor M3_1, and a first capacitor C1_1.

[0100] The first transistor M1_1, the second transistor M2_1, and the third transistor M3_1 can be transistors including body electrodes. For example, each of the first transistor M1_1, the second transistor M2_1, and the third transistor M3_1 can be a metal-oxide-semiconductor field-effect transistor (MOSFET). In this case, the first transistor M1_1, the second transistor M2_1, and the third transistor M3_1 can be mounted in a smaller area, and therefore, the sub-pixel SP can be applied to a high-resolution panel. The body electrodes of the first transistor M1_1, the second transistor M2_1, and the third transistor M3_1 can receive a ground voltage. The ground voltage can have a level higher than the voltage level of the second drive power VSS.

[0101] In some embodiments, the second drive power VSS can be provided as a ground voltage. For example, the body electrodes of the first transistor M1_1, the second transistor M2_1, and the third transistor M3_1 can be electrically connected to the second power line PL2.

[0102] In some embodiments, each of the first transistor M1_1, the second transistor M2_1, and the third transistor M3_1 may be formed as an N-type transistor. However, this disclosure is not limited thereto, and at least one of the first transistor M1_1, the second transistor M2_1, and the third transistor M3_1 may be formed as a P-type transistor.

[0103] The first electrode of the first transistor M1_1 can be connected to the first node N1_1, and its second electrode can be connected to the second node N2_1. As used herein, the term "connected" includes being electrically connected. The gate electrode of the first transistor M1_1 can be connected to the third node N3_1. The first node N1_1 can refer to the node electrically connected to the first power line PL1, and the second node N2_1 can refer to the node to which the first electrode of the first light-emitting element LD1 is connected. The first transistor M1_1 can control the amount of current supplied from the first driving power VDD to the second driving power VSS via the first light-emitting element LD1 in response to the voltage at the third node N3_1.

[0104] The second transistor M2_1 can be connected between the third node N3_1 and the third node N3_2 of the second sub-pixel SPi(j-1). Furthermore, the gate electrode of the second transistor M2_1 can be electrically connected to the second scan line SL2i. The second transistor M2_1 can be turned on when the second scan signal GI is supplied to the second scan line SL2i to electrically connect the third nodes N3_1 and N3_2 to each other.

[0105] The first electrode of the third transistor M3_1 can be connected to the second node N2_1, and its second electrode can be electrically connected to the third power line PL3. Furthermore, the gate electrode of the third transistor M3_1 can be electrically connected to the first scan line SL1i. The third transistor M3_1 can be turned on when the first scan signal GW is supplied to the first scan line SL1i, thereby electrically connecting the second node N2_1 and the third power line PL3 to each other.

[0106] The first capacitor C1_1 can be connected between the second node N2_1 and the third node N3_1. The first capacitor C1_1 can store and maintain a voltage value that depends on the voltage difference applied to its opposite electrodes (e.g., the two electrodes).

[0107] In some embodiments, the first capacitor C1_1 may be a metal oxide metal (MOM) capacitor or a metal insulator metal (MIM) capacitor.

[0108] The pixel circuit of the second sub-pixel SPi(j-1) may include a first transistor M1_2, a second transistor M2_2, a third transistor M3_2, and a first capacitor C1_2.

[0109] The first transistor M1_2, the second transistor M2_2, the third transistor M3_2, and the first capacitor C1_2 of the second sub-pixel SPi(j-1) can be the same as or substantially the same as (or similar to) the first transistor M1_1, the second transistor M2_1, the third transistor M3_1, and the first capacitor C1_1 of the first sub-pixel SPij, respectively, and therefore, redundant descriptions of them need not be repeated.

[0110] The first electrode of the first transistor M1_2 can be connected to the first node N1_2, and its second electrode can be connected to the second node N2_2. The gate electrode of the first transistor M1_2 can be connected to the third node N3_2. The first node N1_2 can refer to the node electrically connected to the first power line PL1, and the second node N2_2 can refer to the node to which the first electrode of the second light-emitting element LD2 is connected. The first transistor M1_2 can control the amount of current supplied from the first driving power VDD to the second driving power VSS via the second light-emitting element LD2 in response to the voltage of the third node N3_2.

[0111] The second transistor M2_2 can be connected between the data line DLj and the third node N3_2. Furthermore, the gate electrode of the second transistor M2_2 can be electrically connected to the first scan line SL1i. The second transistor M2_2 can be turned on when the first scan signal GW is supplied to the first scan line SL1i, thereby electrically connecting the data line DLj and the third node N3_2 to each other.

[0112] The first electrode of the third transistor M3_2 can be connected to the second node N2_2, and its second electrode can be electrically connected to the third power line PL3. Furthermore, the gate electrode of the third transistor M3_2 can be electrically connected to the first scan line SL1i. The third transistor M3_2 can be turned on when the first scan signal GW is supplied to the first scan line SL1i, thereby electrically connecting the second node N2_2 and the third power line PL3 to each other.

[0113] The first capacitor C1_2 can be connected between the second node N2_2 and the third node N3_2. The first capacitor C1_2 can store and maintain a voltage value that depends on the voltage difference applied to its opposite electrodes (e.g., the two electrodes).

[0114] like Figure 4As shown, when the first scan signal GW is supplied to the second transistor M2_2 and the second scan signal GI is supplied to the second transistor M2_1, the first sub-pixel SPij can receive the data signal supplied from the data line DLj through the second transistors M2_1 and M2_2.

[0115] When the first scan signal GW is supplied to the second transistor M2_2, the second sub-pixel SPi(j-1) can receive the data signal from the data line DLj through the second transistor M2_2.

[0116] In other words, since one electrode of the second transistor M2_2 is connected to one electrode of the second transistor M2_1, the voltage of the data signal corresponding to the first sub-pixel SPij and the second sub-pixel SPi(j-1) can be supplied by controlling the first scan signal GW and the second scan signal GI.

[0117] Accordingly, the display device can supply voltage to the data signal corresponding to each of the sub-pixels SP without using or including a separate demultiplexer, thereby reducing the power consumption of the display device.

[0118] Figure 5 The figure illustrates an embodiment according to the present disclosure. Figure 4 The waveform diagram of the sub-pixel driving method is shown in the figure.

[0119] refer to Figure 2 , Figure 4 and Figure 5 During which the data signal Vdata is supplied to the first sub-pixel SPij and the second sub-pixel SPi(j-1), the horizontal time period 1H (e.g., a specific or predetermined horizontal time period) can be divided into a first time period T1, a second time period T2, and a third time period T3. The start time of the second time period T2 may be after the end time of the first time period T1. The start time of the third time period T3 may be after the end time of the second time period T2.

[0120] The data driver 140 can supply a data signal Vdata to the data line DLj during a first time period T1 to a third time period T3. In some embodiments, the voltage of the data signal Vdata may include a first data voltage D1 and a second data voltage D2. The first data voltage D1 may correspond to the data voltage of the first sub-pixel SPij, and the second data voltage D2 may correspond to the data voltage of the second sub-pixel SPi(j-1). In other words, the first sub-pixel SPij may emit light based on the first data voltage D1, and the second sub-pixel SPi(j-1) may emit light based on the second data voltage D2.

[0121] The scan driver 130 (e.g., the first scan driver 132) can supply the first scan signal GW to the first scan line SL1i during the second time period T2 and the third time period T3.

[0122] The scan driver 130 (e.g., the second scan driver 134) can supply the second scan signal GI to the second scan line SL2i during the first time period T1 and the second time period T2.

[0123] Since the first scan signal GW is not supplied and the second scan signal GI is supplied during the first time period T1, the third nodes N3_1 and N3_2 can be connected to each other. Accordingly, the voltage of the third node N3_1 of the first transistor M1_1 and the voltage of the third node N3_2 of the first transistor M1_2 can be the same or substantially the same as each other. For example, as shown in Equation 1, the voltage of each of the third nodes N3_1 and N3_2 can be half the sum of the voltage of the data signal of the first sub-pixel SPij in the previous frame and the voltage of the data signal of the second sub-pixel SPi(j-1) in the previous frame.

[0124] Equation 1:

[0125]

[0126] Referring to Equation 1, VN3 can represent the voltage of each of the third nodes N3_1 and N3_2. The first preliminary data voltage Vdata1 pre It can be the voltage of the data signal supplied to the first sub-pixel SPij in the previous frame, and the second preliminary data voltage Vdata2. pre It can be the voltage of the data signal supplied to the second sub-pixel SPi(j-1) in the previous frame.

[0127] However, according to some embodiments, the first time period T1 can be omitted as needed or desired. This will be referred to below. Figure 10 To describe in more detail.

[0128] The second time period T2 can be the period during which the first data voltage D1 of the data signal Vdata is supplied to the third nodes N3_1 and N3_2 and the initialization power Vint is supplied to the second nodes N2_1 and N2_2. Since the first scan signal GW and the second scan signal GI are supplied during the second time period T2, the voltage corresponding to the difference between the voltage of the first data voltage D1 and the voltage of the initialization power Vint can be stored in the first capacitors C1_1 and C1_2.

[0129] The third time period T3 can be the period during which the second data voltage D2 of the data signal Vdata is supplied to the third node N3_2 and the initialization power Vint is supplied to the second nodes N2_1 and N2_2. Since the first scan signal GW is supplied and the second scan signal GI is not supplied during the third time period T3, the voltage corresponding to the difference between the voltage of the second data voltage D2 and the voltage of the initialization power Vint can be stored in the first capacitor C1_2, and the first capacitor C1_2 can maintain or substantially maintain the voltage stored during the second time period T2.

[0130] like Figure 5 As shown, during a horizontal time period 1H, the supply stop time of the second scan signal GI can be earlier than the supply stop time of the first scan signal GW. For example, the supply stop time of the second scan signal GI can be the end time of the second time period T2. The supply stop time of the first scan signal GW can be the end time of the third time period T3.

[0131] Accordingly, by controlling the first scan signal GW and the second scan signal GI, data voltages D1 and D2 of the data signal Vdata corresponding to the first sub-pixel SPij and the second sub-pixel SPi(j-1) can be supplied.

[0132] Figures 6 to 8 It shows the basis Figure 5 The circuit diagram shown in the figure illustrates the pixel operation process of the signal. Figures 6 to 8 The first sub-pixel SPij and the second sub-pixel SPi(j-1) shown in the figure can correspond to the above reference. Figure 5 The first sub-pixel SPij and the second sub-pixel SPi(j-1) are described.

[0133] refer to Figure 5 and Figure 6 During the first time period T1, the second scan signal GI can be supplied to the second scan line SL2i, and the first scan signal GW can be de-supplied to the first scan line SL1i. Correspondingly, the second transistor M2_2 and the third transistors M3_1 and M3_2 of the second sub-pixel SPi(j-1) can be in the off state, and the second transistor M2_1 of the first sub-pixel SPij can be in the on state. When the second transistor M2_1 of the first sub-pixel SPij is on, the third node N3_1 and the third node N3_2 can be connected to each other.

[0134] refer to Figure 5 and Figure 7During the second time period T2, the second scan signal GI can be supplied to the second scan line SL2i, and the first scan signal GW can be supplied to the first scan line SL1i. Accordingly, the second transistors M2_1 and M2_2 and the third transistors M3_1 and M3_2 can be in the on state.

[0135] When the second transistor M2_2 of the second sub-pixel SPi(j-1) is turned on, the voltage of the data signal Vdata can be supplied from the data line DLj to the third node N3_2. When the second transistor M2_1 of the first sub-pixel SPij is turned on, the third nodes N3_1 and N3_2 can be connected to each other. Accordingly, the data signal Vdata can be supplied from the data line DLj to the third node N3_1. Figure 5 As shown, the first data voltage D1 of the data signal Vdata can be supplied to the third nodes N3_1 and N3_2.

[0136] refer to Figure 5 and Figure 8 During the third time period T3, the first scan signal GW can be supplied to the first scan line SL1i, and the second scan signal GI can be de-supplied to the second scan line SL2i. Accordingly, the second transistor M2_2 and the third transistors M3_1 and M3_2 of the second sub-pixel SPi(j-1) can remain in the on state, and the second transistor M2_1 of the first sub-pixel SPij can be in the off state.

[0137] When the second transistor M2_2 of the second sub-pixel SPi(j-1) is turned on, the data signal Vdata can be supplied from the data line DLj to the third node N3_2. For example... Figure 5 As shown, the second data voltage D2 of the data signal Vdata can be supplied to the third node N3_2.

[0138] When the second transistor M2_1 of the first sub-pixel SPij is turned off, the data signal Vdata may not be supplied from the data line DLj to the third node N3_1. Accordingly, the first capacitor C1_1 may maintain or substantially maintain the voltage stored during the second time period T2.

[0139] Figure 9 The figure illustrates an embodiment according to the present disclosure. Figure 2 The circuit diagram of the sub-pixel is shown in the image. (Reference) Figure 9 The first sub-pixel SPij and the second sub-pixel SPi(j-1) are shown.

[0140] Because the first sub-pixel SPij and the second sub-pixel SPi(j-1) can be compared with the above reference Figure 4The first sub-pixel SPij and the second sub-pixel SPi(j-1) are described as being the same or substantially the same (or similar), so there is no need to repeat their redundant description.

[0141] The first sub-pixel SPij may include a first transistor M1_1, a second transistor M2_1, a third transistor M3_1, a first capacitor C1_1, and a second capacitor C2. The second capacitor C2 may be connected between the first power line PL1 and the third node N3_1. Since the first sub-pixel SPij includes the second capacitor C2, the possibility of brightness differences between the first sub-pixel SPij and the second sub-pixel SPi(j-1) can be reduced.

[0142] refer to Figure 9 The first sub-pixel SPij is shown as including a second capacitor C2, but this disclosure is not limited thereto, and the second sub-pixel SPi(j-1) may include the second capacitor C2. In this case, the second capacitor C2 may be connected between the first power line PL1 and the third node N3_2.

[0143] Figure 10 The figure illustrates an embodiment according to the present disclosure. Figure 9 The waveform diagram of the sub-pixel driving method is shown in the figure.

[0144] refer to Figure 2 , Figure 9 and Figure 10 The data signal Vdata is supplied to the first sub-pixel SPij and the second sub-pixel SPi(j-1). The horizontal time period 1H (e.g., a specific or predetermined horizontal time period) can be divided into a first time period T1 and a second time period T2. The start time of the second time period T2 can be after the end time of the first time period T1.

[0145] Figure 10 The first time period T1 and the second time period T2 shown in the figure can be compared with the above reference. Figure 5 The second time period T2 and the third time period T3 are described as being the same or substantially the same (or similar). In other words, Figure 10 It can be illustrated in the diagram. Figure 5 The waveform diagram of the embodiment where the first time period T1 is omitted.

[0146] The first time period T1 can be the period during which the first data voltage D1 of the data signal Vdata is supplied to the third nodes N3_1 and N3_2 and the initialization power Vint is supplied to the second nodes N2_1 and N2_2. Since the first scan signal GW and the second scan signal GI are supplied during the first time period T1, the voltage corresponding to the difference between the voltage of the first data voltage D1 and the voltage of the initialization power Vint can be stored in the first capacitors C1_1 and C1_2.

[0147] The second time period T2 can be the period during which the second data voltage D2 of the data signal Vdata is supplied to the third node N3_2 and the initialization power Vint is supplied to the second nodes N2_1 and N2_2. Since the first scan signal GW is supplied and the second scan signal GI is not supplied during the second time period T2, the voltage corresponding to the difference between the voltage of the second data voltage D2 and the voltage of the initialization power Vint can be stored in the first capacitor C1_2, and the first capacitor C1_2 can maintain or substantially maintain the voltage stored during the first time period T1.

[0148] In this case, by controlling the first scan signal GW and the second scan signal GI, data voltages D1 and D2 corresponding to the data signal Vdata corresponding to the first sub-pixel SPij and the second sub-pixel SPi(j-1) can be supplied.

[0149] Figure 11 The figure illustrates an embodiment according to the present disclosure. Figure 2 The circuit diagram of the sub-pixel is shown.

[0150] refer to Figure 11 , showing the first sub-pixel SPij set on the i-th horizontal line and the j-th vertical line and the second sub-pixel SPi(j-1) set on the i-th horizontal line and the (j-1)-th vertical line, where i can be an integer greater than 0 and j can be an integer greater than 1.

[0151] Each of the first sub-pixel SPij and the second sub-pixel SPi(j-1) can be connected to a corresponding signal line. For example, the first sub-pixel SPij can be connected to the first scan line SL1i, the second scan line SL2i, the third scan line SL3i, the first transmit control line ELk, the second transmit control line ELBk, and the j-th data line DLj. The second sub-pixel SPi(j-1) can be connected to the first scan line SL1i, the second scan line SL2i, the third scan line SL3i, the first transmit control line ELk, the second transmit control line ELBk, and the j-th data line DLj. In some embodiments, each of the first sub-pixel SPij and the second sub-pixel SPi(j-1) can be further connected to the first power line PL1, the second power line PL2, the third power line PL3, and the fourth power line PL4.

[0152] In other words, the first sub-pixel SPij and the second sub-pixel SPi(j-1) can be connected to the same signal lines as each other (e.g., the first scan line SL1i, the second scan line SL2i, the third scan line SL3i, the first transmit control line ELk, the second transmit control line ELBk, and the j-th data line DLj). The second sub-pixel SPi(j-1) can be located in the same pixel row as the first sub-pixel SPij, and can also be located in a pixel column adjacent to the pixel column of the first sub-pixel SPij. (See reference) Figure 2 The first sub-pixel SPij and the second sub-pixel SPi(j-1) can be included in a single pixel PXL.

[0153] According to embodiments of this disclosure, a first sub-pixel SPij may include a first light-emitting element LD1 and a pixel circuit for controlling the amount of current supplied to the first light-emitting element LD1. A second sub-pixel SPi(j-1) may include a second light-emitting element LD2 and a pixel circuit for controlling the amount of current supplied to the second light-emitting element LD2.

[0154] Figure 11 The first light-emitting element LD1 and the second light-emitting element LD2 shown in the figure can be compared with the above reference. Figure 4 The first light-emitting element LD1 and the second light-emitting element LD2 described are the same or substantially the same (or similar). Accordingly, redundant descriptions of them need not be repeated.

[0155] The pixel circuit of the first sub-pixel SPij may include a first transistor M1_1, a second transistor M2_1, a third transistor M3_1, a fourth transistor M4_1, a fifth transistor M5_1, a sixth transistor M6_1, a first capacitor C1_1, and a second capacitor C2_1.

[0156] The first transistor M1_1, the second transistor M2_1, the third transistor M3_1, the fourth transistor M4_1, the fifth transistor M5_1, and the sixth transistor M6_1 can be transistors including a body electrode. For example, each of the first transistor M1_1, the second transistor M2_1, the third transistor M3_1, the fourth transistor M4_1, the fifth transistor M5_1, and the sixth transistor M6_1 can be a metal-oxide-semiconductor field-effect transistor (MOSFET). In this case, the first transistor M1_1, the second transistor M2_1, the third transistor M3_1, the fourth transistor M4_1, the fifth transistor M5_1, and the sixth transistor M6_1 can be mounted in a smaller area, and therefore, sub-pixels SP can be applied to a high-resolution panel. The body electrodes of the first transistor M1_1, the second transistor M2_1, the third transistor M3_1, the fourth transistor M4_1, the fifth transistor M5_1, and the sixth transistor M6_1 can receive a ground voltage.

[0157] In some embodiments, each of the first transistor M1_1, the second transistor M2_1, the third transistor M3_1, the fourth transistor M4_1, the fifth transistor M5_1, and the sixth transistor M6_1 may be formed as an N-type transistor. However, this disclosure is not limited thereto, and at least one of the first transistor M1_1, the second transistor M2_1, the third transistor M3_1, the fourth transistor M4_1, the fifth transistor M5_1, and the sixth transistor M6_1 may be formed as a P-type transistor.

[0158] The first electrode of the first transistor M1_1 can be connected to the first node N1_1, and its second electrode can be connected to the second node N2_1. The gate electrode of the first transistor M1_1 can be connected to the third node N3_1.

[0159] The second transistor M2_1 can be connected between the third node N3_1 and the third node N3_2 of the second sub-pixel SPi(j-1). Furthermore, the gate electrode of the second transistor M2_1 can be electrically connected to the second scan line SL2i. The second transistor M2_1 can be turned on when the second scan signal GI is supplied to the second scan line SL2i to electrically connect the third nodes N3_1 and N3_2 to each other.

[0160] The first electrode of the third transistor M3_1 can be connected to the fourth node N4_1, and its second electrode can be electrically connected to the third power line PL3. Furthermore, the gate electrode of the third transistor M3_1 can be electrically connected to the second scan line SL2i. The third transistor M3_1 can be turned on when the second scan signal GI is supplied to the second scan line SL2i, thereby electrically connecting the fourth node N4_1 and the third power line PL3 to each other.

[0161] The first electrode of the fourth transistor M4_1 can be electrically connected to the first power line PL1, and its second electrode can be connected to the first node N1_1. Furthermore, the gate electrode of the fourth transistor M4_1 can be electrically connected to the first transmit control line ELk. The fourth transistor M4_1 can be turned on when the first transmit signal EM is supplied to the first transmit control line ELk, thereby electrically connecting the first power line PL1 and the first node N1_1 to each other.

[0162] The first electrode of the fifth transistor M5_1 can be connected to the second node N2_1, and its second electrode can be connected to the fourth node N4_1. Furthermore, the gate electrode of the fifth transistor M5_1 can be electrically connected to the second transmit control line ELBk. The fifth transistor M5_1 can be turned on when the second transmit signal EMB is supplied to the second transmit control line ELBk, thereby electrically connecting the second node N2_1 and the fourth node N4_1 to each other.

[0163] The first electrode of the sixth transistor M6_1 can be connected to the third node N3_1, and its second electrode can be electrically connected to the fourth power line PL4. Furthermore, the gate electrode of the sixth transistor M6_1 can be electrically connected to the third scan line SL3i. The sixth transistor M6_1 can be turned on when the third scan signal GR is supplied to the third scan line SL3i, thereby electrically connecting the third node N3_1 and the fourth power line PL4 to each other.

[0164] A first capacitor C1_1 can be connected between a second node N2_1 and a third node N3_1. The first capacitor C1_1 can transmit the voltage change value of the second node N2_1 to the third node N3_1. Furthermore, the first capacitor C1_1 can store and maintain a voltage value that depends on the voltage difference applied to its opposite electrodes (e.g., the two electrodes).

[0165] One end of the second capacitor C2_1 can be electrically connected to the first power line PL1, and the other end (e.g., the opposite end) can be connected to the second node N2_1. In some embodiments, the other end of the second capacitor C2_1 can be connected to the body electrode of the first transistor M1_1.

[0166] In some embodiments, the first capacitor C1_1 and the second capacitor C2_1 may be metal oxide metal (MOM) capacitors or metal insulator metal (MIM) capacitors.

[0167] The pixel circuit of the second sub-pixel SPi(j-1) may include a first transistor M1_2, a second transistor M2_2, a third transistor M3_2, a fourth transistor M4_2, a fifth transistor M5_2, a sixth transistor M6_2, a first capacitor C1_2, and a second capacitor C2_2.

[0168] The first transistor M1_2, the second transistor M2_2, the third transistor M3_2, the fourth transistor M4_2, the fifth transistor M5_2, and the sixth transistor M6_2, the first capacitor C1_2, and the second capacitor C2_2 of the second sub-pixel SPi(j-1) can be the same as or substantially the same as (or similar to) the first transistor M1_1, the second transistor M2_1, the third transistor M3_1, the fourth transistor M4_1, the fifth transistor M5_1, the sixth transistor M6_1, the first capacitor C1_1, and the second capacitor C2_1 of the first sub-pixel SPij described above, and therefore, redundant descriptions of them need not be repeated.

[0169] The first electrode of the first transistor M1_2 can be connected to the first node N1_2, and its second electrode can be connected to the second node N2_2. The gate electrode of the first transistor M1_2 can be connected to the third node N3_2. The first node N1_2 can refer to the node electrically connected to the first power line PL1, and the second node N2_2 can refer to the node to which the first electrode of the second light-emitting element LD2 is connected. The first transistor M1_2 can control the amount of current supplied from the first driving power VDD to the second driving power VSS via the second light-emitting element LD2 in response to the voltage of the third node N3_2.

[0170] The second transistor M2_2 can be connected between the data line DLj and the third node N3_2. Furthermore, the gate electrode of the second transistor M2_2 can be electrically connected to the first scan line SL1i. The second transistor M2_2 can be turned on when the first scan signal GW is supplied to the first scan line SL1i, thereby electrically connecting the data line DLj and the third node N3_2 to each other.

[0171] The first electrode of the third transistor M3_2 can be connected to the fourth node N4_2, and its second electrode can be electrically connected to the third power line PL3. Furthermore, the gate electrode of the third transistor M3_2 can be electrically connected to the second scan line SL2i. The third transistor M3_2 can be turned on when the second scan signal GI is supplied to the second scan line SL2i, thereby electrically connecting the fourth node N4_2 and the third power line PL3 to each other.

[0172] The first electrode of the fourth transistor M4_2 can be electrically connected to the first power line PL1, and its second electrode can be connected to the first node N1_2. Furthermore, the gate electrode of the fourth transistor M4_2 can be electrically connected to the first transmit control line ELk. The fourth transistor M4_2 can be turned on when the first transmit signal EM is supplied to the first transmit control line ELk, thereby electrically connecting the first power line PL1 and the first node N1_2 to each other.

[0173] The first electrode of the fifth transistor M5_2 can be connected to the second node N2_2, and its second electrode can be electrically connected to the fourth node N4_2. Furthermore, the gate electrode of the fifth transistor M5_2 can be electrically connected to the second transmit control line ELBk. The fifth transistor M5_2 can be turned on when the second transmit signal EMB is supplied to the second transmit control line ELBk, thereby electrically connecting the second node N2_2 and the fourth node N4_2 to each other.

[0174] The first electrode of the sixth transistor M6_2 can be connected to the third node N3_2, and its second electrode can be electrically connected to the fourth power line PL4. Furthermore, the gate electrode of the sixth transistor M6_2 can be electrically connected to the third scan line SL3i. The sixth transistor M6_2 can be turned on when the third scan signal GR is supplied to the third scan line SL3i, thereby electrically connecting the third node N3_2 and the fourth power line PL4 to each other.

[0175] A first capacitor C1_2 can be connected between a second node N2_2 and a third node N3_2. The first capacitor C1_2 can transmit the voltage change value of the second node N2_2 to the third node N3_2. Furthermore, the first capacitor C1_2 can store and maintain a voltage value that depends on the voltage difference applied to its opposite electrodes (e.g., the two electrodes).

[0176] One end of the second capacitor C2_2 can be electrically connected to the first power line PL1, and the other end (e.g., the opposite end) can be connected to the second node N2_2. In some embodiments, the other end of the second capacitor C2_2 can be connected to the body electrode of the first transistor M1_2.

[0177] like Figure 11 As shown, when the first scan signal GW is supplied to the second transistor M2_2 and the second scan signal GI is supplied to the second transistor M2_1, the first sub-pixel SPij can receive the data signal supplied from the data line DLj through the second transistors M2_1 and M2_2.

[0178] When the first scan signal GW is supplied to the second transistor M2_2, the second sub-pixel SPi(j-1) can receive the data signal from the data line DLj through the second transistor M2_2.

[0179] In other words, since one electrode of the second transistor M2_2 is connected to one electrode of the second transistor M2_1, the voltage of the data signal corresponding to the first sub-pixel SPij and the second sub-pixel SPi(j-1) can be supplied by controlling the first scan signal GW and the second scan signal GI.

[0180] Accordingly, the display device can supply voltage to the data signal corresponding to each of the sub-pixels SP without using or including a separate demultiplexer, thereby reducing the power consumption of the display device.

[0181] Figure 12 The figure illustrates an embodiment according to the present disclosure. Figure 11 The waveform diagram of the sub-pixel driving method is shown in the figure.

[0182] refer to Figure 2 , Figure 11 and Figure 12 During which data signals are supplied to the first sub-pixel SPij and the second sub-pixel SPi(j-1), a horizontal time period 1H (e.g., a specific or predetermined horizontal time period) can be divided into a first time period T1, a second time period T2, a third time period T3, a fourth time period T4, and a fifth time period T5. The start time of the second time period T2 may be after the end time of the first time period T1. The start time of the third time period T3 may be after the end time of the second time period T2. The start time of the fourth time period T4 may be after the end time of the third time period T3. The start time of the fifth time period T5 may be after the end time of the fourth time period T4.

[0183] After the horizontal period 1H, the sixth period T6, in which light-emitting elements LD1 and LD2 emit light, can begin. The start time of the sixth period T6 can be after the end time of the fifth period T5.

[0184] In some embodiments, a margin period may exist between the first time period T1 and the sixth time period T6. The margin period may be a period that takes signal delay into account.

[0185] The data driver 140 can supply the voltage of the data signal to the data line DLj during the first time period T1 to the fifth time period T5.

[0186] The scan driver 130 (e.g., the first scan driver 132) can supply the first scan signal GW to the first scan line SL1i during the third time period T3 and the fourth time period T4.

[0187] The scan driver 130 (e.g., the second scan driver 134) can supply the second scan signal GI to the second scan line SL2i during the first time period T1 to the third time period T3 and the fifth time period T5.

[0188] The scan driver 130 (e.g., the third scan driver) can supply the third scan signal GR to the third scan line SL3i during the first time period T1 and the second time period T2.

[0189] The transmit driver 160 can supply the first transmit signal EM to the first transmit control line ELk during the second time period T2 and the sixth time period T6.

[0190] The transmit driver 160 can supply the second transmit signal EMB to the second transmit control line ELBk during the first time period T1, the fifth time period T5, and the sixth time period T6.

[0191] The first time period T1 can be the period during which the voltage of the reference power VRF is supplied to the third nodes N3_1 and N3_2, and the voltage of the initialization power Vint is supplied to the second nodes N2_1 and N2_2 and the fourth nodes N4_1 and N4_2. During the first time period T1, the anode electrodes of the light-emitting elements LD1 and LD2 can be initialized. Furthermore, during the first time period T1, the first capacitors C1_1 and C1_2 can store the voltage of the reference power VRF supplied to the third nodes N3_1 and N3_2. The first time period T1 can be referred to as the initialization period.

[0192] The second time period T2 can be the period during which the voltage of the reference power VRF is supplied to the third nodes N3_1 and N3_2, the voltage of the initialization power Vint is supplied to the fourth nodes N4_1 and N4_2, and the voltage of the first driving power VDD is supplied to the first nodes N1_1 and N1_2. During the second time period T2, the voltages corresponding to the threshold voltages of the first transistors M1_1 and M1_2 can be stored in the first capacitors C1_1 and C1_2, respectively. The second time period T2 can be referred to as the threshold voltage compensation period.

[0193] The third time period T3 can be the period during which data signals are supplied to the third nodes N3_1 and N3_2 and initialization power Vint is supplied to the fourth nodes N4_1 and N4_2. Since the first scan signal GW and the second scan signal GI are supplied during the third time period T3, the voltage corresponding to the data signals supplied during the third time period T3 can be stored in the first capacitors C1_1 and C1_2.

[0194] The fourth time period T4 can be the period during which the data signal is supplied to the third node N3_2. Since the first scan signal GW is supplied and the second scan signal GI is not supplied during the fourth time period T4, the voltage corresponding to the data signal supplied during the fourth time period T4 can be stored in the first capacitor C1_2.

[0195] In this case, by controlling the first scan signal GW and the second scan signal GI, the voltage of the data signal corresponding to each of the first sub-pixel SPij and the second sub-pixel SPi(j-1) can be supplied.

[0196] The fifth time period T5 can be the period in which the second nodes N2_1 and N2_2 are connected to the fourth nodes N4_1 and N4_2 when the fifth transistors M5_1 and M5_2 are turned on. The second electrodes of the first transistors M1_1 and M1_2 and the anode electrodes of the light-emitting elements LD1 and LD2 can have the same or substantially the same voltage as each other. Accordingly, when the light-emitting elements LD1 and LD2 emit light in the sixth time period T6 after the fifth time period T5, the accuracy of the grayscale level can be improved.

[0197] During the sixth time period T6, the first transistors M1_1 and M1_2 can control the amount of current flowing from the first driving power VDD through the light-emitting elements LD1 and LD2 to the second driving power VSS in response to the voltages of the third nodes N3_1 and N3_2. In this case, during the sixth time period T6, the light-emitting elements LD1 and LD2 can emit light with a brightness corresponding to the amount of current supplied from the first transistors M1_1 and M1_2.

[0198] like Figure 12 As shown, during a horizontal time period 1H, the supply stop time of the second scan signal GI can be earlier than the supply stop time of the first scan signal GW. The supply stop time of the second scan signal GI can refer to the moment when the supply first stops.

[0199] For example, the supply stop time of the second scan signal GI can be the end time of the third time period T3. The supply stop time of the first scan signal GW can be the end time of the fourth time period T4.

[0200] Accordingly, by controlling the first scan signal GW and the second scan signal GI, voltages for data signals corresponding to the first sub-pixel SPij and the second sub-pixel SPi(j-1) can be supplied.

[0201] Figures 13 to 18 The diagram shows that it depends on Figure 12 The circuit diagram shown in the figure illustrates the pixel operation process of the signal.

[0202] refer to Figure 12 and Figure 13 During the first time period T1, the second scan signal GI can be supplied to the second scan line SL2i, the third scan signal GR can be supplied to the third scan line SL3i, and the second transmit signal EMB can be supplied to the second transmit control line ELBk. Furthermore, during the first time period T1, the first scan signal GW may not be supplied to the first scan line SL1i, and the first transmit signal EM may not be supplied to the first transmit control line ELk.

[0203] Accordingly, the second transistor M2_1, the third transistors M3_1 and M3_2, the fifth transistors M5_1 and M5_2, and the sixth transistors M6_1 and M6_2 can be turned on, and the second transistor M2_2 and the fourth transistors M4_1 and M4_2 can be turned off.

[0204] When the third transistors M3_1 and M3_2 and the fifth transistors M5_1 and M5_2 are turned on, the voltage of the initialization power Vint can be supplied to the second nodes N2_1 and N2_2. When the sixth transistors M6_1 and M6_2 are turned on, the voltage of the reference power VRF can be supplied to the third nodes N3_1 and N3_2.

[0205] In this scenario, the first capacitors C1_1 and C1_2 can be initialized using the voltage of the reference power VRF and the voltage of the initial power Vint. For example, the first capacitors C1_1 and C1_2 can be charged with the voltage of the reference power VRF and the voltage of the initial power Vint during the first time period T1, regardless of the voltage charged in previous time periods (e.g., previous frame periods).

[0206] During the first time period T1, the current supplied from the first transistors M1_1 and M1_2 in response to the voltages of the third nodes N3_1 and N3_2 can be supplied to the initialization power Vint via the third transistors M3_1 and M3_2 and the fifth transistors M5_1 and M5_2. Accordingly, the light-emitting elements LD1 and LD2 can remain or substantially remain in a non-emitting state during the first time period T1. The first time period T1 can be referred to as the initialization period.

[0207] refer to Figure 12 and Figure 14 During the second time period T2, the second scan signal GI can be supplied to the second scan line SL2i, the third scan signal GR can be supplied to the third scan line SL3i, and the first transmit signal EM can be supplied to the first transmit control line ELk. Furthermore, during the second time period T2, the first scan signal GW may not be supplied to the first scan line SL1i, and the second transmit signal EMB may not be supplied to the second transmit control line ELBk.

[0208] Accordingly, the second transistor M2_1, the third transistors M3_1 and M3_2, and the sixth transistors M6_1 and M6_2 can remain or substantially remain in the on state, and the fourth transistors M4_1 and M4_2 can be in the on state. In addition, the second transistor M2_2 can remain or substantially remain in the off state, and the fifth transistors M5_1 and M5_2 can be in the off state.

[0209] Because the fourth transistors M4_1 and M4_2 can be in the on state during the second time period T2, the voltage of the first driving power VDD can be supplied to the first nodes N1_1 and N1_2. Because the fifth transistors M5_1 and M5_2 can be in the off state, the voltage of the initialization power Vint can be excluded from supplying the voltage to the second nodes N2_1 and N2_2.

[0210] In this scenario, the voltages of the second nodes N2_1 and N2_2 can be reduced from the initial voltage of the power Vint to a voltage equal to the reference power VRF voltage minus the absolute threshold voltages of the first transistors M1_1 and M1_2 (e.g., VRF-Vth). Accordingly, during the second time period T2, the first capacitors C1_1 and C1_2 can store the threshold voltages of the first transistors M1_1 and M1_2, respectively. The second time period T2 can be referred to as the threshold voltage compensation period.

[0211] Because the third transistors M3_1 and M3_2 can be in the on state during the second time period T2, the current supplied to the fourth nodes N4_1 and N4_2 can be supplied to the initialization power Vint via the third transistors M3_1 and M3_2. Accordingly, the light-emitting elements LD1 and LD2 can remain or substantially remain in a non-emitting state during the second time period T2.

[0212] refer to Figure 12 and Figure 15 During the third time period T3, the first scan signal GW can be supplied to the first scan line SL1i, and the second scan signal GI can be supplied to the second scan line SL2i. Furthermore, during the third time period T3, the third scan signal GR may not be supplied to the third scan line SL3i, the first transmit signal EM may not be supplied to the first transmit control line ELk, and the second transmit signal EMB may not be supplied to the second transmit control line ELBk.

[0213] Accordingly, the second transistor M2_1 and the third transistors M3_1 and M3_2 can maintain or substantially maintain the on state, and the second transistor M2_2 can be in the on state. In addition, the fifth transistors M5_1 and M5_2 can maintain or substantially maintain the off state, and the fourth transistors M4_1 and M4_2 and the sixth transistors M6_1 and M6_2 can be in the off state.

[0214] Since the second transistors M2_1 and M2_2 are in the ON state, data signals can be supplied from the data line DLj. In this case, the voltage of each of the second nodes N2_1 and N2_2 can be defined by Equation 2.

[0215] Equation 2:

[0216]

[0217] Referring to Equation 2, VN21 can represent the voltage of the second node N2_1 of the first sub-pixel SPij. The second node N2_2 of the second sub-pixel SPi(j-1) can have the same or substantially the same voltage as the second node N2_1 of the first sub-pixel SPij. The first data voltage D1 can be the voltage of the data signal supplied to the data line DLj during the third time period T3. C11 can be the capacitance of the first capacitor C1_1. C12 can be the capacitance of the second capacitor C2_1.

[0218] Since the first scan signal GW and the second scan signal GI are supplied during the third time period T3, the first data voltage D1 can be provided to the third nodes N3_1 and N3_2.

[0219] Accordingly, the voltage values ​​that depend on the voltage difference between the third nodes N3_1 and N3_2 and the second nodes N2_1 and N2_2 can be stored in the first capacitors C1_1 and C1_2. In other words, the voltage reflecting the first data voltage D1 supplied during the third time period T3 can be stored in the first capacitors C1_1 and C1_2.

[0220] refer to Figure 12 and Figure 16 The first scan signal GW can be supplied to the first scan line SL1i during the fourth time period T4. Furthermore, during the fourth time period T4, the second scan signal GI can be withheld from the second scan line SL2i, the third scan signal GR can be withheld from the third scan line SL3i, the first transmit signal EM can be withheld from the first transmit control line ELk, and the second transmit signal EMB can be withheld from the second transmit control line ELBk.

[0221] Accordingly, the second transistor M2_2 can remain or substantially remain in the on state. Then, the second transistor M2_1 and the third transistors M3_1 and M3_2 can be in the off state, and the fourth transistors M4_1 and M4_2, the fifth transistors M5_1 and M5_2 and the sixth transistors M6_1 and M6_2 can remain or substantially remain in the off state.

[0222] Since the second transistor M2_1 is in the off state, the data signal cannot be supplied to the third node N3_1 from the data line DLj, and the data signal can only be supplied to the third node N3_2 from the data line DLj. In this case, the voltage of the second node N2_2 can be limited by Equation 3.

[0223] Equation 3:

[0224]

[0225] Referring to Equation 3, VN22 can represent the voltage of the second node N2_2 of the second sub-pixel SPi(j-1). The second data voltage D2 can be the voltage of the data signal supplied to the data line DLj during the fourth time period T4.

[0226] Since the first scan signal GW is supplied during the fourth time period T4, the second data voltage D2 can be provided to the third node N3_2. Furthermore, since the second scan signal GI is not supplied, the second data voltage D2 may not be provided to the third node N3_1.

[0227] Accordingly, the voltage value depending on the voltage difference between the third node N3_2 and the second node N2_2 can be stored in the first capacitor C1_2. In other words, the voltage reflecting the second data voltage D2 supplied during the fourth time period T4 can be stored in the first capacitor C1_2, and the voltage stored in the first capacitor C1_1 during the third time period T3 can be maintained or substantially maintained.

[0228] Thus, by controlling the first scan signal GW and the second scan signal GI, the voltage of the data signal corresponding to each of the first sub-pixel SPij and the second sub-pixel SPi(j-1) can be supplied.

[0229] Reference Figure 12 and Figure 17 During the fifth time period T5, the second scan signal GI can be supplied to the second scan line SL2i, and the second transmit signal EMB can be supplied to the second transmit control line ELBk. Furthermore, during the fifth time period T5, the first scan signal GW may not be supplied to the first scan line SL1, the third scan signal GR may not be supplied to the third scan line SL3i, and the first transmit signal EM may not be supplied to the first transmit control line ELk.

[0230] Accordingly, the second transistor M2_1, the third transistors M3_1 and M3_2, and the fifth transistors M5_1 and M5_2 can be in the on state. The second transistor M2_2 can be in the off state, and the fourth transistors M4_1 and M4_2 and the sixth transistors M6_1 and M6_2 can remain or substantially remain in the off state.

[0231] Since the third transistors M3_1 and M3_2 and the fifth transistors M5_1 and M5_2 are in the ON state, the second electrodes of the first transistors M1_1 and M1_2 and the anode electrodes of the light-emitting elements LD1 and LD2 can have the same or substantially the same voltage. Accordingly, when the light-emitting elements LD1 and LD2 emit light in the sixth time period T6 after the fifth time period T5, the accuracy of the grayscale level can be improved. (Refer to...) Figure 12 and Figure 17 Since the third transistors M3_1 and M3_2 and the fifth transistors M5_1 and M5_2 are in the on state, the second node N2_1 and the fourth node N4_1 can have the same voltage, and the second node N2_2 and the fourth node N4_2 can have the same voltage.

[0232] In some embodiments, the current supplied to the second nodes N2_1 and N2_2 can be supplied to the initialization power Vint. Accordingly, during the fifth time period T5, the light-emitting elements LD1 and LD2 can be in a non-emitting state, thereby accurately representing the grayscale level of the display device 100. For example, the voltage of the second nodes N2_1 and N2_2 may increase to a voltage higher than the desired voltage during the third time period T3 and the fourth time period T4. Accordingly, unexpected current may be supplied to the light-emitting elements LD1 and LD2. For example, even if a black grayscale level is achieved in the pixel PXL, the light-emitting elements LD1 and LD2 may emit light briefly. According to embodiments of this disclosure, the current supplied from the first transistors M1_1 and M1_2 can be supplied to the initialization power Vint during the fifth time period T5, and therefore, the light-emitting elements LD1 and LD2 can be prevented from emitting unexpected light, and the grayscale level accuracy of the light-emitting elements LD1 and LD2 can be improved during the sixth time period T6.

[0233] refer to Figure 12 and Figure 18 During the sixth time period T6, the supply of the first scan signal GW to the first scan line SL1i can be stopped, the supply of the second scan signal GI to the second scan line SL2i can be stopped, and the supply of the third scan signal GR to the third scan line SL3i can be stopped. Then, during the sixth time period T6, the first transmit signal EM can be supplied to the first transmit control line ELk, and the second transmit signal EMB can be supplied to the second transmit control line ELBk.

[0234] Accordingly, the second transistor M2_1 and the third transistors M3_1 and M3_2 can be in the off state, and the second transistor M2_2 and the sixth transistors M6_1 and M6_2 can remain or substantially remain in the off state. The fourth transistors M4_1 and M4_2 can be in the on state, and the fifth transistors M5_1 and M5_2 can remain or substantially remain in the on state.

[0235] Thus, the first transistors M1_1 and M1_2 can control the amount of current supplied from the first driving power VDD to the second driving power VSS via the light-emitting elements LD1 and LD2 in response to the voltages of the third nodes N3_1 and N3_2, respectively. During the sixth time period T6, the light-emitting elements LD1 and LD2 can generate light with a brightness corresponding to the amount of driving current supplied from the first transistors M1_1 and M1_2.

[0236] Figure 19 This is a block diagram illustrating an electronic device 1000 according to an embodiment of the present disclosure. Figure 20 It is shown in the figure. Figure 19 The electronic device 1000 is a schematic diagram of an example of a smartphone. Figure 21 It is shown in the figure. Figure 19 The electronic device 1000 is a schematic diagram of an example of a tablet computer.

[0237] refer to Figures 19 to 21 The electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The display device 1060 may be... Figure 2 The display device. The electronic device 1000 may further include various ports for communicating with a graphics card, sound card, memory card, USB device, or other systems. In embodiments, such as Figure 20 As illustrated, the electronic device 1000 can be implemented as a smartphone. In an embodiment, as... Figure 21 As illustrated, the electronic device 1000 can be implemented as a tablet computer. However, the examples mentioned above are illustrative, and the electronic device 1000 is not limited to the examples mentioned above. For example, the electronic device 1000 can be implemented as a cellular phone, video phone, smartboard, smartwatch, navigation device for vehicle, computer monitor, laptop computer, and head-mounted display device, etc.

[0238] Processor 1010 can perform specific calculations or tasks. In embodiments, processor 1010 may include at least one of a central processing unit, an application processor, a graphics processing unit, a communication processor, an image signal processor, and a controller. Processor 1010 can be connected to other components via address buses, control buses, and data buses. In embodiments, processor 1010 may be connected to an expansion bus such as a peripheral component interconnect (PCI) bus. In embodiments, processor 1010 can provide input image data to display device 1060. Therefore, display device 1060 can display an image based on the input image data provided from processor 1010.

[0239] The memory device 1020 can store data required for performing operations of the electronic device 1000. The memory device 1020 can be used as working memory and / or buffer memory for the processor 1010. For example, the memory device 1020 may include one or more volatile memory devices such as dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, and mobile DRAM devices.

[0240] Storage device 1030 can store data in response to control signals or data from processor 1010. Storage device 1030 may include one or more non-volatile memories to retain data even when electronic device 1000 is powered off. In some embodiments, storage device 1030 may include a solid-state drive (SSD), hard disk drive (HDD), or CD-ROM, etc.

[0241] I / O device 1040 may include input devices such as a keyboard, keypad, touchpad, touchscreen, and mouse, as well as output devices such as speakers and printers. In an embodiment, display device 1060 may be integrated with I / O device 1040.

[0242] Power supply 1050 can supply the power required for the operation of electronic device 1000. For example, power supply 1050 may include a power management integrated circuit (PMIC). In an embodiment, power supply 1050 can supply power to display device 1060.

[0243] The display device 1060 can display an image in response to image data signals and / or control signals from the processor 1010. The display device 1060 can be connected to other components via a bus or other communication link.

[0244] The foregoing is an illustrative description of some embodiments of this disclosure and should not be construed as limiting it. Although some embodiments have been described, those skilled in the art will readily appreciate that various modifications can be made to the embodiments without departing from the spirit and scope of this disclosure. It will be understood that, unless otherwise described, the description of features or aspects within each embodiment should generally be considered as applicable to other similar features or aspects in other embodiments. Therefore, features, characteristics, and / or elements described in connection with a particular embodiment, as will be apparent to those skilled in the art, may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise specifically instructed. Therefore, it should be understood that the foregoing is an illustrative description of various exemplary embodiments and should not be construed as limiting to the specific embodiments disclosed herein, and various modifications to the disclosed embodiments and other exemplary embodiments are intended to be included within the spirit and scope of this disclosure as defined in the appended claims and their equivalents.

Claims

1. A display device, comprising: A first sub-pixel and a second sub-pixel are connected to a first scan line, a second scan line, and a j-th data line, where j is an integer greater than 1. The first scan line is configured to receive a first scan signal, and the second scan line is configured to receive a second scan signal. The first sub-pixel is located in the i-th pixel row and j-th pixel column, where i is an integer greater than 0, and the first sub-pixel includes: A first transistor is connected between a first node and a second node, and includes a gate electrode connected to a third node, wherein the first node is configured to receive a first drive power supplied from a first power line; A second transistor is connected between the third and fourth nodes and is configured to turn on when the second scan signal is supplied to the second scan line; A first capacitor is connected between the second node and the third node; and A first light-emitting element is connected between the second node and a second power line configured to receive second driving power, and The second sub-pixel is located in the i-th pixel row and the (j-1)-th pixel column, and includes: A third transistor is connected between the fifth and sixth nodes and includes a gate electrode connected to the fourth node, the fifth node being configured to receive the first drive power supplied from the first power line; A fourth transistor is connected between the j-th data line and the fourth node, and is configured to be turned on when the first scan signal is supplied to the first scan line; A second capacitor is connected between the fourth node and the sixth node; and The second light-emitting element is connected between the sixth node and the second power line.

2. The display device according to claim 1, wherein, The first sub-pixel further includes: A fifth transistor, connected between the second node and a third power line configured to receive initialization power, is configured to turn on when the first scan signal is supplied to the first scan line. The second sub-pixel further includes: A sixth transistor, connected between the sixth node and the third power line, is configured to turn on when the first scan signal is supplied to the first scan line.

3. The display device according to claim 1, wherein, During a horizontal time period, the supply of the second scan signal stops earlier than the supply of the first scan signal.

4. The display device according to claim 1, wherein, A horizontal time period includes a first time period and a second time period. The second time period begins after the end of the first time period. During the first time period, the first scan signal and the second scan signal are supplied, and The first scan signal is supplied during the second time period, and the supply of the second scan signal is stopped.

5. The display device according to claim 4, wherein, The third node and the fourth node are configured to receive a first data voltage corresponding to the first sub-pixel during the first time period, and The fourth node is configured to receive a second data voltage corresponding to the second sub-pixel during the second time period.

6. The display device according to claim 4, wherein, The aforementioned horizontal time period further includes a third time period. The start time of the first time period is after the end time of the third time period, and During the third time period, the second scan signal is supplied and the first scan signal is stopped.

7. The display device according to claim 1, wherein, The first sub-pixel further includes: A third capacitor is connected between the third node and the first power line.

8. A display device, comprising: A first sub-pixel and a second sub-pixel are connected to a first scan line, a second scan line, a j-th data line, and a transmit control line, where j is an integer greater than 1. The first scan line is configured to receive a first scan signal, and the second scan line is configured to receive a second scan signal. The first sub-pixel is located in the i-th pixel row and j-th pixel column, where i is an integer greater than 0, and the first sub-pixel includes: A first transistor is connected between a first node and a second node, and includes a gate electrode connected to a third node; A second transistor is connected between the third and fourth nodes and is configured to turn on when the second scan signal is supplied to the second scan line; A third transistor is connected between the first node and a first power line configured to receive the first drive power, and is configured to turn on when the first transmit signal is supplied to the first transmit control line in the transmit control line; A fourth transistor is connected between the second node and the fifth node and is configured to be turned on when the second transmit signal is supplied to the second transmit control line in the transmit control line; A first capacitor is connected between the second node and the third node; and A first light-emitting element is connected between the fifth node and a second power line configured to receive second driving power, and The second sub-pixel is located in the i-th pixel row and the (j-1)-th pixel column, and includes: The fifth transistor is connected between the sixth and seventh nodes and includes a gate electrode connected to the fourth node; A sixth transistor is connected between the j-th data line and the fourth node and is configured to be turned on when the first scan signal is supplied to the first scan line; A seventh transistor is connected between the sixth node and the first power line and is configured to turn on when the first transmit signal is supplied to the first transmit control line; An eighth transistor is connected between the seventh and eighth nodes and is configured to be turned on when the second transmit signal is supplied to the second transmit control line; A second capacitor is connected between the fourth node and the seventh node; and The second light-emitting element is connected between the eighth node and the second power line.

9. The display device according to claim 8, wherein, The first sub-pixel further includes: A ninth transistor, connected between the fifth node and a third power line configured to receive initialization power, is configured to turn on when the second scan signal is supplied to the second scan line. The second sub-pixel further includes: A tenth transistor, connected between the eighth node and the third power line, is configured to turn on when the second scan signal is supplied to the second scan line.

10. The display device according to claim 9, wherein, The first sub-pixel and the second sub-pixel are further connected to a third scan line configured to receive a third scan signal; The first sub-pixel further includes: An eleventh transistor, connected between the third node and a fourth power line configured to receive reference power, is configured to turn on when the third scan signal is supplied to the third scan line. The second sub-pixel further includes: A twelfth transistor, connected between the fourth node and the fourth power line, is configured to turn on when the third scan signal is supplied to the third scan line.

11. The display device according to claim 10, wherein, The voltage level of the reference power is higher than the voltage level of the initial power.

12. The display device according to claim 10, wherein, The first sub-pixel further includes: A third capacitor is connected between the second node and the first electric field line, and The second sub-pixel further includes: A fourth capacitor is connected between the seventh node and the first power line.

13. The display device according to claim 10, wherein, During a horizontal time period, the supply of the second scan signal stops earlier than the supply of the first scan signal.

14. The display device according to claim 10, wherein, A horizontal time period includes the first, second, third, fourth, and fifth time periods. The second time period begins after the end of the first time period. During the first time period, the second scan signal, the third scan signal, and the second transmit signal are supplied, and the supply of the first scan signal and the first transmit signal is stopped. During the second time period, the second scan signal, the third scan signal, and the first transmission signal are supplied, and the supply of the first scan signal and the second transmission signal is stopped.

15. The display device according to claim 14, wherein, The third time period begins after the end of the second time period, and During the third time period, the first scan signal and the second scan signal are supplied, and the supply of the third scan signal, the first transmission signal, and the second transmission signal is stopped.

16. The display device according to claim 15, wherein, The third node and the fourth node are configured to receive a first data voltage corresponding to the first sub-pixel during the third time period.

17. The display device according to claim 15, wherein, The start time of the fourth time period is after the end time of the third time period, and During the fourth time period, the first scan signal is supplied, and the supply of the second scan signal, the third scan signal, the first transmission signal, and the second transmission signal is stopped.

18. The display device according to claim 17, wherein, The fourth node is configured to receive a second data voltage corresponding to the second sub-pixel during the fourth time period. After the fifth time period, the supply of the first scan signal, the second scan signal, and the third scan signal is stopped, and the first transmission signal and the second transmission signal are supplied.

19. The display device according to claim 17, wherein, The start time of the fifth time period is after the end time of the fourth time period, and During the fifth time period, the second scan signal and the second transmit signal are supplied, and the first scan signal, the third scan signal, and the first transmit signal are stopped.

20. An electronic device comprising: A processor, used to provide input image data; as well as The display device according to any one of claims 1 to 19 is used to display an image based on the input image data.

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