Gate driving circuit and display device including the same

Abstract

The present disclosure relates to a gate driving circuit and a display device including the gate driving circuit, and more particularly, to a gate driving circuit having a reduced size and a display device including the gate driving circuit. The gate driving circuit includes a plurality of dummy stage circuits and stage circuits that provide a gate signal for each gate line and include a Q node, a QH node, and a QB node. A strobe signal output circuit included in each stage circuit may output first to j-th strobe signals based on first to j-th scan clock signals or a first low voltage according to a voltage level of a Q node or a voltage level of a QB node.

Description

[0001] This application is a divisional application of the invention patent application with application number 202211571450.7 (application date: December 8, 2022, invention name: Strobe driving circuit and display device including the same). TECHNICAL FIELD

[0002] The present disclosure relates to a strobe driving circuit and an electronic device including the same, and more particularly, to a strobe driving circuit and a display device including the same. BACKGROUND

[0003] Recently, display devices employing flat panel display panels, such as liquid crystal display devices, organic light emitting diode display devices, light emitting diode display devices, and electrophoretic display devices, have been widely used.

[0004] A display device can include a light emitting element and a pixel having a pixel circuit for driving the light emitting element. For example, the pixel circuit includes a driving transistor for controlling a driving current supplied to the light emitting element, and at least one switching transistor for controlling (or programming) a gate-source voltage of the driving transistor according to a strobe signal. The switching transistor of the pixel circuit can be switched by a strobe signal provided by a strobe driving circuit disposed on a substrate of a display panel.

[0005] A display device includes a display area displaying an image and a non-display area not displaying an image. As the size of the non-display area decreases, the size of an edge or a bezel area of the display device decreases, and the size of the display area increases. SUMMARY

[0006] In a display device, since a strobe driving circuit is disposed in a non-display area, the size of a display area can increase as the size of the strobe driving circuit decreases.

[0007] A strobe driving circuit can include a plurality of stage circuits. Each stage circuit can include a plurality of transistors for generating a strobe signal. As the number of transistors included in each stage circuit increases, the size of the stage circuit and the size of the strobe driving circuit increase. Therefore, in order to reduce the size of the strobe driving circuit and increase the size of the display area, it is desirable to reduce the number of transistors included in each stage circuit.

[0008] As the number of times the transistor included in each stage circuit is driven increases, the characteristics of the transistor, for example, the value of the threshold voltage, change. In a case where the voltage at the control node decreases as the value of the threshold voltage of the transistor changes, the transistor cannot be completely turned off. Thus, during driving of the gate drive circuit, a leakage current can be generated in each stage circuit. If the gate signal cannot be normally output due to this leakage current, the image quality of the display device can deteriorate.

[0009] Further, as the number of times the transistor included in each stage circuit is driven increases, the transistor can rapidly deteriorate, and the lifespan of the display device can be shortened.

[0010] The present disclosure provides embodiments that solve one or more of these problems.

[0011] According to embodiments of the present disclosure, a gate drive circuit having a reduced size and a display device having an increased display area size are provided by reducing the number of transistors included in the stage circuit and the number of lines connected to the transistors.

[0012] According to embodiments of the present disclosure, a gate drive circuit and a display device having improved durability and reliability are provided by reducing the voltage stress of the transistor included in the stage circuit and thereby enabling the lifespan of the transistor to be extended.

[0013] According to embodiments of the present disclosure, by changing the connection structure of the carry signal line of the stage circuit, display artifacts such as horizontal lines caused in VRR driving can be reduced or eliminated.

[0014] The problems or issues to be addressed herein are not limited to the above description, and other problems or issues to be addressed will become apparent to those skilled in the art from the following description.

[0015] According to an aspect of the present disclosure, a gate drive circuit includes a plurality of stage circuits capable of providing a gate signal to each of a plurality of gate lines and including an M node, a Q node, a QH node, and a QB node, and a plurality of virtual stage circuits configured in a previous stage of a first stage circuit among the plurality of stage circuits so as to stably output a gate signal.

[0016] In one embodiment, each of the plurality of stage circuits can include a line selector, a Q node controller, a Q node and QH node stabilization circuit, an inverter, a QB node stabilization circuit, a carry signal output circuit, and a gate signal output circuit.

[0017] The line selector can charge the M node based on the previous stage carry signal in response to an input of the line sense ready signal, and charge the Q node to the first high voltage level in response to an input of the reset signal or discharge the Q node to the third low voltage level in response to an input of the panel on signal.

[0018] The Q node controller can charge the Q node to the first high voltage level in response to an input of the start signal or the previous stage carry signal, and discharge the Q node to the third low voltage level in response to an input of the subsequent stage carry signal.

[0019] The Q node and QH node stabilization circuit can discharge the Q node and QH node to the third low voltage level when the QB node is charged to the second high voltage level.

[0020] The inverter can change a voltage level of the QB node according to a voltage level of the Q node.

[0021] The QB node stabilization circuit can discharge the QB node to the third low voltage level in response to an input of the previous stage carry signal, an input of the reset signal, and a charging voltage of the M node.

[0022] The carry signal output circuit can output a carry signal C(k) based on a voltage level of the carry clock signal CRCLK(k) according to a voltage level of the Q node or based on the third low voltage (GVSS3) level according to a voltage level of the QB node.

[0023] The gate signal output circuit can output a first gate signal to jth gate signal based on a first scan clock signal to jth scan clock signal according to a voltage level of the Q node or a voltage level of the QB node.

[0024] In one embodiment, the dummy stage circuits can be set almost simultaneously in response to a start signal, and output carry signals whose phases are sequentially delayed in synchronization with a gated shift clock.

[0025] Each dummy stage circuit can include a Q node controller, a Q node and QH node stabilization circuit, an inverter, and a carry signal output circuit, and further include an FB TFT circuit.

[0026] The FB TFT circuit is designed to have the same circuit structure as the T3 TFT, in which the same gate-source voltage Vgs as the T3 TFT is applied. In this case, when PBTS (positive bias temperature stress, in which the threshold voltage Vth of the T3 TFT is positively shifted) deterioration of the T3 TFT proceeds, the threshold voltage Vth of the FB TFT circuit becomes positively shifted, and the corresponding flowing current becomes reduced. A PGVDD voltage generation block (not shown) can sense this reduced current of the FB TFT circuit and increase the corresponding PGVDD voltage by the threshold voltage Vth.

[0027] In another aspect of the present disclosure, a display apparatus is provided, including a display panel including sub-pixels formed in an intersection region of a gate line and a data line, a gate driving circuit for providing a scan signal to each gate line, a data driving circuit for providing a data voltage to each data line, and a timing controller for controlling driving of the gate driving circuit and the data driving circuit.

[0028] In one embodiment, the gate driving circuit can include a plurality of stage circuits capable of providing a gate signal to each of a plurality of gate lines and including an M node, a Q node, a QH node, and a QB node, and a plurality of dummy stage circuits configured in a previous stage of a first stage circuit among the plurality of stage circuits so as to stably output the gate signal.

[0029] In one embodiment, each of the plurality of stage circuits can include a line selector, a Q node controller, a Q node and QH node stabilization circuit, an inverter, a QB node stabilization circuit, a carry signal output circuit, and a gate signal output circuit.

[0030] The line selector can charge the M node based on a previous stage carry signal in response to input of a line sensing preparation signal, and charge the Q node to a first high voltage level in response to input of a reset signal or discharge the Q node to a third low voltage level in response to input of a panel on signal.

[0031] The Q node controller can charge the Q node to the first high voltage level in response to input of a start signal or a previous stage carry signal, and discharge the Q node to the third low voltage level in response to input of a subsequent stage carry signal.

[0032] The Q node and QH node stabilization circuit can discharge the Q node and the QH node to the third low voltage level when the QB node is charged to a second high voltage level.

[0033] The inverter can change a voltage level of the QB node according to a voltage level of the Q node.

[0034] The QB node stabilization circuit can discharge the QB node to a third low voltage level in response to an input of a previous stage carry signal, an input of a reset signal, and a charging voltage of the M node.

[0035] The carry signal output circuit can output a carry signal C(k) based on a voltage level of the carry clock signal CRCLK(k) according to a voltage level of the Q node or based on a third low voltage (GVSS3) level according to a voltage level of the QB node.

[0036] The gate signal output circuit can output first to jth gate signals based on first to jth scan clock signals according to a voltage level of the Q node or a voltage level of the QB node.

[0037] In one embodiment, the dummy stage circuits can be set almost simultaneously in response to a start signal, and output carry signals whose phases are sequentially delayed in synchronization with a gated shift clock.

[0038] Each dummy stage circuit can include a Q node controller, a Q node and QH node stabilization circuit, an inverter, and a carry signal output circuit, and further include an FB TFT circuit.

[0039] The FB TFT circuit is designed to have the same circuit structure as the T3 TFT, in which the same gate-source voltage Vgs as the T3 TFT is applied. In this case, when PBTS (positive bias temperature stress, a threshold voltage Vth of the T3 TFT is positively shifted) deterioration of the T3 TFT proceeds, the threshold voltage Vth of the FB TFT circuit becomes positively shifted, and a current flowing becomes reduced. A PGVDD voltage generation block (not shown) can sense this reduced current of the FB TFT circuit and increase a corresponding PGVDD voltage by a threshold voltage Vth.

[0040] According to embodiments of the present disclosure, the number of transistors included in a stage circuit of a gate drive circuit and the number of lines connected to the transistors can be reduced, and the gate drive circuit can be stably driven. If the number of transistors included in each stage circuit is reduced, the size of the gate drive circuit can be reduced, and the reduction in the size of the stage circuit can enable an increase in the size of a display area of a display device. Further, the reduction in the number of transistors included in the stage circuit can provide an advantage that enables the stage circuit to be more simply configured and designed.

[0041] Further, according to embodiments of the present disclosure, the voltage level input to the transistor included in the stage circuit can be adjusted in accordance with the driving time of the display device. Thereby, the voltage stress of the transistor can be reduced, and the lifespan of the transistor can be prolonged. Further, the durability of the gate drive circuit and the display device can be improved, and the driving reliability of the gate drive circuit and the display device can be improved.

[0042] Further, according to embodiments of the present disclosure, by changing the connection structure of the carry signal line of the stage circuit, the horizontal line artifact caused during the VRR driving can be solved, and the image display quality of the display device can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0043] The accompanying drawings, which are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this disclosure, illustrate various aspects of the present disclosure and together with the description serve to explain the principles of the present disclosure. In the drawings:

[0044] Figure 1 A display device according to aspects of the present disclosure is schematically illustrated;

[0045] Figure 2 An example sub-pixel array included in a display panel of a display device according to aspects of the present disclosure is illustrated;

[0046] Figure 3 An example circuit configuration of a sub-pixel in a display device according to aspects of the present disclosure, and example connection structures between a timing controller, a data drive circuit, and the sub-pixel are illustrated;

[0047] Figure 4 An example configuration of a plurality of stage circuits included in a gate drive circuit according to aspects of the present disclosure is illustrated;

[0048] Figure 5 An example circuit diagram of a stage circuit included in a gate drive circuit according to aspects of the present disclosure is illustrated;

[0049] Figure 6 An example circuit diagram of a virtual stage circuit included in a gate drive circuit according to aspects of the present disclosure is illustrated;

[0050] Figure 7 A circuit diagram of another virtual stage circuit included in a gate drive circuit according to aspects of the present disclosure is illustrated;

[0051] Figure 8 A first carry signal line connection diagram of a stage circuit included in a gate drive circuit according to aspects of the present disclosure is illustrated;

[0052] Figure 9 A second carry signal line connection diagram of a stage circuit included in a gate drive circuit according to aspects of the present disclosure is illustrated;

[0053] Figure 10 is a drive timing chart of a stage circuit in a first connection configuration of Figure 8

[0054] Figure 11 is a drive timing chart of a stage circuit in a second connection configuration of Figure 9

[0055] Figure 12 is a waveform chart of an input signal and an output signal when a stage circuit of a gate drive circuit according to aspects of the present disclosure outputs a gate signal for image display; Figure 5

[0056] Figure 13 is a graph showing a change in amplitude of a second high voltage according to a driving time of a gate drive circuit in a display device according to aspects of the present disclosure; and

[0057] Figure 14 is a graph showing a change in threshold voltage amplitude of a transistor of a gate drive circuit in a display device according to aspects of the present disclosure. DETAILED DESCRIPTION

[0058] The advantages and features of the present disclosure and methods of accomplishing the same can be understood more readily by reference to the following detailed description of embodiments of the present disclosure and the accompanying drawings. The following embodiments described below are described in the context of particular embodiments, and are provided only to completely disclose the present disclosure and to fully inform those skilled in the art to which the embodiments of the present disclosure pertain. It will be understood, however, that these embodiments can be implemented in various different forms, and, further, that many changes, modifications, additions, and improvements can be made thereto without departing from the scope of the present disclosure. Therefore, the scope of the present disclosure is not limited to the following described embodiments, but is defined by the scope of the claims.

[0059] Further, shapes, sizes, proportions, angles, numbers, and the like illustrated in the drawings for describing the exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout the specification, like drawing reference numerals generally refer to like elements. Further, in the following description of the present disclosure, detailed descriptions of known functions and configurations incorporated herein can be omitted when it is determined that such detailed description can make the subject matter of some embodiments of the present disclosure unnecessarily unclear. Terms such as “include,” “have,” “comprise,” “comprising,” and “consist of” used herein are generally intended to allow addition of other components, unless the terms are used with the term “only.” The singular forms used herein are intended to include the plural forms unless the context clearly indicates otherwise.

[0060] ​​​When interpreting any element or feature of the embodiments of the present disclosure, any dimension and relative size of layers, regions, and areas should be interpreted to include a tolerance or error range, even if not specifically described.

[0061] Spatially relative terms such as "on", "above", "top", "bottom", "under", "below", "down", "up", "near", "close", "far", and the like, can be used herein to describe one element's or feature's relationship to another element or feature as illustrated in the drawings, and should be interpreted in accordance with the one or more elements or features that can be "interposed" between the elements, unless the terms are used in a manner that is clear to the person of ordinary skill in the art.

[0062] Temporal relative terms such as "after", "subsequent to", "followed by", "before", "preceded by", and the like, used herein to describe a temporal relationship between events, operations, etc., are generally intended to include events, situations, circumstances, operations, etc. that occur discontinuously, unless terms such as "directly", "immediately", etc. are used.

[0063] When, for example, embodiments related to a signal flow are discussed, an embodiment in which a signal is transmitted from a node A to a node B can include an embodiment in which the signal is transmitted from the node A to the node B through another node, unless "directly" or "directly" is used.

[0064] When terms such as "first", "second", etc. are used herein to describe various elements or components, it should be understood that the elements or components are not limited thereto. These terms are used herein only to distinguish one element from another. Accordingly, in the technical idea of the present disclosure, the first element mentioned below can be the second element.

[0065] The elements or features of the various exemplary embodiments of the present disclosure can be partially or entirely combined or combined with each other, and can be interlocked and operated in various technical ways that can be sufficiently understood by those of ordinary skill in the art, and the various exemplary embodiments can be executed independently or in association with each other.

[0066] According to embodiments of the present disclosure, the sub-pixel circuit and the gate drive circuit provided on the substrate of the display panel can be implemented using a transistor having an n-type MOSFET structure. However, embodiments of the present disclosure are not limited thereto; for example, the transistor employed in the sub-pixel circuit and the gate drive circuit can be a p-type MOSFET. The transistor can include a gate, a source, and a drain. In the transistor, a carrier can flow from the source to the drain. In the case of an n-type transistor, the source voltage is lower than the drain voltage, and an electron can move from the source to the drain because the carrier is an electron. In the n-type transistor, current can flow from the drain to the source due to the movement of the electron from the source to the drain. In the case of a p-type transistor, the source voltage is higher than the drain voltage, and a hole can move from the source to the drain because the carrier is a hole. In the p-type transistor, current can flow from the source to the drain due to the movement of the hole from the source to the drain. In the transistor having the MOSFET structure, the source and the drain are not fixed, and thus can be interchanged according to an applied voltage. Therefore, it should be noted that, herein, any one of the source and the drain is referred to as a first source / drain electrode, and the other of the source and the drain is referred to as a second source / drain electrode.

[0067] Hereinafter, exemplary examples of a gate drive circuit and a display device including the gate drive circuit according to aspects of the present disclosure will be described in detail with reference to the accompanying drawings. Even when shown in different drawings, the same elements, substantially the same elements, or nearly the same elements can have the same reference numeral. Since the elements in the drawings are exemplified for the convenience of description, and can have different proportions in the gate drive circuit, the display device, and the electronic device, the drawings are regarded as essentially illustrative rather than limiting.

[0068] Figure 1 A display device according to aspects of the present disclosure is schematically exemplified. Figure 2 An example sub-pixel array included in a display panel of a display device according to aspects of the present disclosure is exemplified.

[0069] Referring to Figure 1 and Figure 2 A display device 1 according to aspects of the present disclosure can include a display panel 10, a data drive circuit 12, a gate drive circuit 13, and a timing controller 11.

[0070] A plurality of data lines 14 and a plurality of gate lines 15 can be provided to cross each other in the display panel 10. A plurality of sub-pixels SP can be arranged in a matrix form at each intersection of the data lines 14 and the gate lines 15.

[0071] Data lines 14 may include m (m is a positive integer) data voltage supply lines (14A_1 to 14A_m) and m sense voltage readout lines (14B_1 to 14B_m). Gating lines 15 may include n (n is a positive integer) first gating lines (15A_1 to 15A_n) and n second gating lines (15B_1 to 15B_n).

[0072] Each subpixel SP can be connected to any one of the data voltage supply lines (14A_1 to 14A_m), any one of the sense voltage readout lines (14B_1 to 14B_m), and any one of the first gating lines (15A_1 to 15A_n) and the second gating line (15B_1 to 15B_n). Each subpixel SP can represent a predefined color, and a predefined number of subpixels SP can be included in a pixel P.

[0073] Each sub-pixel SP can receive data voltage through the data voltage supply line, receive a first gating signal through the first gating line, receive a second gating signal through the second gating line, and output a sensing voltage through the sensing voltage readout line.

[0074] In other words, Figure 2 In the illustrated subpixel array, subpixels SP can operate sequentially on a horizontal line basis in response to a first gating signal provided from a first gating line (15A_1 to 15A_n) based on a horizontal line (L#1 to L#n) and a second gating signal provided from a second gating line (15B_1 to 15B_n) based on a horizontal line. Subpixels SP driven for sensing operations on the same horizontal line can receive data voltage for threshold voltage sensing from data voltage supply lines (14A_1 to 14A_m) and output the sensed voltage to sense voltage readout lines (14B_1 to 14B_m). Each of the first and second gating signals can be a gating signal for sensing a threshold voltage or a gating signal for displaying an image. However, embodiments of this disclosure are not limited thereto.

[0075] Each sub-pixel SP can receive at least one high voltage EVDD and at least one low voltage EVSS from the power management circuit 16. The sub-pixel SP may include an OLED, a driving transistor, a first switching transistor, a second switching transistor, and a storage capacitor. In some embodiments, a light source other than the OLED may be included in the sub-pixel SP.

[0076] The transistors included in the sub-pixel SP can be p-type or n-type transistors. The semiconductor layer of the transistors included in the sub-pixel SP can be amorphous silicon, polycrystalline silicon, or oxide.

[0077] During the image display operation, the data drive circuit 12 can convert the compensated image data MDATA input from the timing controller 11 into data voltages for image display in accordance with the data control signal DDC, and supply the converted data voltages to the data voltage supply lines (14A_1 to 14A_m).

[0078] During the sensing operation for sensing the threshold voltage of the drive transistor, the data drive circuit 12 can supply data voltages for threshold voltage sensing to the sub-pixels SP in accordance with the first gate signal for threshold voltage sensing supplied on a horizontal line basis, convert the sensing voltage sensed by the sensing voltage readout lines (14B_1 to 14B_m) input from the display panel 10 into digital values, and supply the converted sensing values to the timing controller 11.

[0079] The gate drive circuit 13 can generate gate signals based on the gate control signal GDC. The gate signals can include a first threshold voltage sensing gate signal, a second threshold voltage sensing gate signal, a first image display gate signal, and a second image display gate signal.

[0080] During the sensing operation, the gate drive circuit 13 can supply the first threshold voltage sensing gate signal to the first gate lines (15A_1 to 15A_n) on a horizontal line basis, and supply the second threshold voltage sensing gate signal to the second gate lines (15B_1 to 15B_n) on a horizontal line basis. During the image display operation, the gate drive circuit 13 can supply the first image display gate signal to the first gate lines (15A_1 to 15A_n) on a horizontal line basis, and supply the second image display gate signal to the second gate lines (15B_1 to 15B_n) on a horizontal line basis. In one embodiment, the gate drive circuit 13 can be provided in the display panel 10 in a gate-in-panel (GIP) type.

[0081] The timing controller 11 can generate the data control signal DDC for controlling the operation timing of the data drive circuit 12 and the gate control signal GDC for controlling the operation timing of the gate drive circuit 13 based on the timing signals such as the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the dot clock signal DCLK, the data enable signal DE, etc. supplied from the host system 2. The timing controller 11 can compensate the image data DATA supplied from the host system 2 using the sensing values supplied from the data drive circuit 12, thereby generating the compensated image data MDATA for compensating the threshold voltage difference of the drive transistor, and supplying the compensated image data MDATA to the data drive circuit 12.

[0082] The power management circuit 16 can generate and supply a plurality of types of voltages required to drive the display device 1 based on a power supply provided from the host system 2. In one embodiment, the power management circuit 16 can generate at least one drive voltage EVDD and at least one base voltage (EVSS) for driving each sub-pixel SP based on an input voltage Vin provided from the host system 2, and supply the generated drive voltage EVDD and base voltage (EVSS) to the display panel 10. As another embodiment, the power management circuit 16 can generate at least one gate drive voltage GVDD and at least one gate base voltage GVSS for driving the gate drive circuit 13, and supply the generated gate drive voltage GVDD and gate base voltage GVSS to the gate drive circuit 13.

[0083] Figure 3 An example circuit configuration of a sub-pixel in a display device according to aspects of the present disclosure, and example connection structures between a timing controller, a data drive circuit, and a sub-pixel are illustrated.

[0084] Referring to Figure 3 The sub-pixel SP can include an OLED, a drive transistor DT, a storage capacitor Cst, a first switch transistor ST1, and a second switch transistor ST2.

[0085] The OLED can include an anode electrode connected to the second node N2, a cathode electrode connected to a terminal of a low-voltage supply line or a low power supply for supplying a low-level drive voltage EVSS, and an organic compound layer positioned between the anode electrode and the cathode electrode.

[0086] The drive transistor DT can turn on in accordance with a gate-source voltage Vgs and control an amount of current Ioled flowing through the OLED. The drive transistor DT can include a gate electrode connected to the first node N1, a drain electrode connected to a terminal of a high-voltage supply line or a high power supply for supplying a high-level drive voltage EVDD, and a source electrode connected to the second node N2.

[0087] The storage capacitor Cst can be connected between the first node N1 and the second node N2.

[0088] During a sensing operation, the first switch transistor ST1 can apply a data voltage Vdata for threshold voltage sensing, which is loaded on the data voltage supply line 14A, to the first node N1 in response to a first threshold voltage sensing signal SCAN.

[0089] During the image display operation, the first switching transistor ST1 can apply a data voltage Vdata for image display loaded on the data voltage supply line 14A to the first node N1 in response to a first image display gate signal SCAN. The first switching transistor ST1 can include a gate electrode connected to the first gate line 15A, a drain electrode connected to the data voltage supply line 14A, and a source electrode connected to the first node N1.

[0090] During the sensing operation, the second switching transistor ST2 can control a current flow between the second node N2 and the sensing voltage readout line 14B in response to a second threshold voltage sensing gate signal SEN, thereby enabling the source voltage of the second node N2 to be varied by following the gate voltage at the first node N1 to be stored in the sensing capacitor Cx of the sensing voltage readout line 14B.

[0091] During the image display operation, the second switching transistor ST2 can control a current flow between the second node N2 and the sensing voltage readout line 14B in response to a second image display gate signal SEN, thereby enabling the source voltage of the driving transistor DT to be reset to the initialization voltage Vpre. The gate electrode, the drain electrode, and the source electrode of the second switching transistor ST2 can be connected to the second gate line 15B, the second node N2, and the sensing voltage readout line 14B, respectively.

[0092] The data driving circuit 12 can be connected to the sub-pixel SP through the data voltage supply line 14A and the sensing voltage readout line 14B. The sensing capacitor Cx for storing the source voltage at the second node N2 as the sensing voltage Vsen can be connected to the sensing voltage readout line 14B. The data driving circuit 12 can include a digital-to-analog converter (DAC), an analog-to-digital converter (ADC), an initialization switch SW1, and a sampling switch SW2.

[0093] In the first and second periods in the sensing period, the DAC can generate a data voltage Vdata for threshold voltage sensing having the same level or different levels by control of the timing controller 11 and output the generated threshold voltage sensing data voltage Vdata to the data voltage supply line 14A. During the image display period, the DAC can convert the compensated image data MDATA into a data voltage Vdata for image display and output the converted data voltage to the data voltage supply line 14A.

[0094] The initialization switch SW1 can control the current flow between a terminal of an initialization voltage supply line or an initialization power supply for supplying an initialization voltage Vpre and the sensing voltage readout line 14B. The sampling switch SW2 can control the current flow between the sensing voltage readout line 14B and the ADC. The ADC can convert the analog sensing voltage Vsen stored in the sensing capacitor Cx into a digital sensing value, and supply the converted sensing value to the timing controller 11.

[0095] The sensing operation performed by the control of the timing controller 11 is as follows. When the threshold voltage sensing first and second gate signals SCAN and SEN having an ON level Lon are applied to the sub-pixel SP, the first and second switch transistors ST1 and ST2 can be turned on. At this time, the initialization switch SW1 of the data driving circuit 12 can also be turned on.

[0096] When the first switch transistor ST1 is turned on, the data voltage Vdata for threshold voltage sensing can be supplied to the first node N1. When the initialization switch SW1 and the second switch transistor ST2 are turned on, the initialization voltage Vpre can be supplied to the second node N2. At this time, as the gate-source voltage Vgs of the drive transistor DT becomes greater than its threshold voltage Vth, the current Ioled can flow between the drain and source of the drive transistor DT. The source voltage VN2 of the drive transistor DT charged at the second node N2 by such current Ioled gradually increases, and thus, the source voltage VN2 of the drive transistor DT follows the gate voltage VN1 of the drive transistor DT until the gate-source voltage Vgs of the drive transistor DT reaches the threshold voltage Vth.

[0097] The source voltage VN2 of the drive transistor DT increased at the second node N2 can be stored as a sensing voltage Vsen to the sensing capacitor Cx formed on the sensing voltage readout line 14B via the second switch transistor ST2. When the sampling switch SW2 in the data driving circuit 12 is turned on for a sensing period in which the second threshold voltage sensing gate signal SEN is maintained at the ON level, the sensing voltage Vsen can be detected and supplied to the ADC.

[0098] The ADC can convert the analog sensing voltage Vsen stored in the sensing capacitor Cx into a digital sensing value, and supply the converted sensing value to the timing controller 11.

[0099] In one embodiment, the timing controller 11 can control the data drive circuit 12 and the gate drive circuit 13 so that the sensing operation for one horizontal line can be performed in a period (i.e., a blanking period) between a period in which one frame of image data is displayed by an image display operation (i.e., an image display period) and a subsequent period in which a subsequent frame of image display is displayed.

[0100] The timing controller 11 can compensate the image data based on the sensing value obtained by the data drive circuit 12, and generate compensated image data MDATA resulting from the compensation. As the compensated image data MDATA is supplied to the data drive circuit 12, an image based on the compensated image data MDATA can be displayed on the display panel 10.

[0101] Figure 4 An example configuration of a plurality of stage circuits included in the gate drive circuit according to aspects of the present disclosure is illustrated.

[0102] Referring to Figure 4 , the gate drive circuit 13 according to aspects of the present disclosure can include first to kth stage circuits ST(1) to ST(k) (k is a positive integer), a gate drive voltage line 131, a clock signal line 132, a line sensing preparation signal line 133, and a reset signal line 134. Further, the gate drive circuit 13 can include one or more previous dummy stage circuits (DST1, DST2) disposed at one or more previous stages of the first stage circuit ST(1) and at least one subsequent dummy stage circuit DST3 disposed at at least one subsequent stage of the kth stage circuit ST(k). However, the structure of the gate drive circuit is not limited thereto. For example, the at least one subsequent dummy stage circuit DST3 can be omitted. For another example, the number of previous dummy stage circuits is not limited to Figure 4 the number shown.

[0103] The gate drive voltage line 131 can supply at least one high voltage GVDD and at least one low voltage GVSS provided from a power source (not shown) to the first to kth stage circuits ST(1) to ST(k), the previous dummy stage circuits (DST1, DST2), and the subsequent dummy stage circuit DST3.

[0104] In one embodiment, the gate drive voltage line 131 can include a plurality of high voltage lines that supply respective high voltages different from each other, and a plurality of low voltage lines that supply respective low voltages different from each other.

[0105] For example, the gating drive voltage line 131 may include three high-voltage lines for providing a first high voltage GVDD1, a second high voltage GVDD2, and a third high voltage GVDD3, each having a different voltage level from the other, and three low-voltage lines for providing a first low voltage GVSS1, a second low voltage GVSS2, and a third low voltage GVSS3, each having a different voltage level from the other. However, this is only an example, and the number of lines included in the gating drive voltage line 131 may vary depending on the implementation.

[0106] Clock signal line 132 can provide clock signals CLK, such as carry clock signal CRCLK, scan clock signal SCCLK, etc., provided from timing controller 11 to first-level circuit to k-level circuit (ST(1) to ST(k)), previous virtual level circuit (DST1, DST2) and subsequent virtual level circuit DST3.

[0107] Line sensing preparation signal line 133 can provide the line sensing preparation signal LSP provided from the timing controller 11 to the first-level circuitry through the k-th-level circuitry (ST(1) through ST(k)). Alternatively, line sensing preparation signal line 133 can be connected to the previous virtual stage circuitry (DST1, DST2).

[0108] The reset signal line 134 can provide the reset signal RESET provided from the timing controller 11 to the first stage circuit to the k-th stage circuit (ST(1) to ST(k)), the previous virtual stage circuit (DST1, DST2) and the subsequent virtual stage circuit DST3.

[0109] The panel open signal line 135 can provide the panel open signal POS provided by the timing controller 11 to the first stage circuit to the k-th stage circuit (ST(1) to ST(k)), the previous virtual stage circuit (DST1, DST2) and the subsequent virtual stage circuit DST3.

[0110] Although not shown, but except Figure 4 The lines (131, 132, 133, and 134) shown, used to provide different signals, can be further connected to the first-level circuit to the k-th-level circuit (ST(1) to ST(k)), the previous virtual stage circuit (DST1, DST2), and the subsequent virtual stage circuit DST3. For example, the line used to provide the start signal VST to the previous virtual stage circuit (DST1, DST2) can be additionally connected to the previous virtual stage circuit (DST1, DST2).

[0111] In response to an input of a start signal VST provided from the timing controller 124, the preceding dummy stage circuit (DST1, DST2) can output a preceding stage carry signal C. The preceding stage carry signal C can be provided to any one of the first to kth stage circuits (ST(1) to ST(k)). The preceding stage carry signal C can be provided to a next dummy stage circuit (e.g., DST2) of the preceding dummy stage circuit (DST1, DST2).

[0112] The subsequent dummy stage circuit DST3 can output a subsequent stage carry signal C. The subsequent stage carry signal C can be provided to any one of the first to kth stage circuits (ST(1) to ST(k)).

[0113] The first to kth stage circuits (ST(1) to ST(k)) can be connected to each other in a ladder or cascade manner, and can be connected to the dummy stage circuits (DST1 to DST3) in a ladder or cascade manner.

[0114] In one embodiment, each of the first to kth stage circuits (ST(1) to ST(k)) can output j (j is a positive integer) strobe signals SCOUT and one carry signal C. That is, any one of the first to kth stage circuits (ST(1) to ST(k)) can output first to jth strobe signals SCOUT and one carry signal C.

[0115] For example, in the embodiment shown in FIG. 1, each of the first to kth stage circuits can output four strobe signals SCOUT and one carry signal C. For example, the first stage circuit ST(1) can output a first strobe signal SCOUT(1), a second strobe signal SCOUT(2), a third strobe signal SCOUT(3), a fourth strobe signal SCOUT(4), and a first carry signal C(1), and the second stage circuit ST(2) can output a fifth strobe signal SCOUT(5), a sixth strobe signal SCOUT(6), a seventh strobe signal SCOUT(7), an eighth strobe signal SCOUT(8), and a second carry signal C(2). Thus, in the embodiment shown in FIG. 1, j is equal to 4. Figure 4

[0116] The number of the strobe signals output from the first to kth stage circuits (ST(1) to ST(k)) can be equal to the number n of the strobe lines 15 provided in the display panel 10. As described above, each of the stage circuits can output j strobe signals. Thus, the relationship of j x k = n holds.

[0117] For example, since j = 4 in the embodiment shown in FIG. 1, the number k of the stage circuits is equal to 1 / 4 of the number n of the strobe lines 15. That is, in the embodiment shown in FIG. 1, the number k of the stage circuits is equal to 1 / 4 of the number n of the strobe lines 15. Figure 4 Figure 4 For example, since j = 4 in the embodiment shown in FIG. 1, the number k of the stage circuits is equal to 1 / 4 of the number n of the strobe lines 15. That is, in the embodiment shown in FIG. 1, the number k of the stage circuits is equal to 1 / 4 of the number n of the strobe lines 15.​​Figure 4 In an embodiment, k = n / 4.

[0118] However, the number of the strobe signals output by each stage circuit according to embodiments of the present disclosure is not limited thereto. That is, in some embodiments, each stage circuit can output one, two, or three strobe signals, or can output five or more strobe signals. The number of the stage circuits can vary depending on the number of the strobe signals output by each stage circuit.

[0119] In the following description, an embodiment in which each stage circuit outputs 4 strobe signals SCOUT and 1 carry signal C is discussed; however, embodiments of the present disclosure are not limited thereto.

[0120] The strobe signals SCOUT output from the first stage circuit to the kth stage circuit (ST(1) to ST(k)) can be strobe signals for threshold voltage sensing or strobe signals for image display. The carry signals C output from the first stage circuit to the kth stage circuit (ST(1) to ST(k)) can be provided to stage circuits different from each other. Herein, the carry signal provided from a previous stage circuit to any stage circuit is referred to as a previous stage carry signal, and the carry signal provided from a subsequent stage circuit to a stage circuit is referred to as a subsequent stage carry signal.

[0121] Figure 5 is an example circuit diagram of a stage circuit included in a strobe driving circuit according to aspects of the present disclosure.

[0122] Figure 5 The stage circuit shown is Figure 4 any one of the first stage circuit to the kth stage circuit (ST(1) to ST(k)) shown.

[0123] Referring to Figure 5 In one embodiment, the stage circuit can include an M node, a Q node, a QB node, and a QH node. In one embodiment, the stage circuit can include a line selector 502, a Q node controller 504, a Q node and QH node stabilization circuit 506, an inverter 508, a QB node stabilization circuit 510, a carry signal output circuit 512, and a strobe signal output circuit 514.

[0124] The line selector 502 can charge the M node based on the previous stage carry signal C(k-2) in response to an input of a line sensing preparation signal LSP. In response to an input of a reset signal RESET, the line selector 502 can charge the Q node to a first high voltage (GVDD1) level based on a voltage of the charge at the M node. The line selector 502 can discharge or reset the Q node to a third low voltage (GVSS3) level in response to an input of a panel on signal POS.

[0125] The line selector 502 can include first through seventh transistors T11 through T17 and a pre-charge capacitor CA.

[0126] The first transistor T11 and the second transistor T12 can be connected between the M node and a previous stage carry signal C(k-2) line for transferring a previous stage carry signal C(k-2). The first transistor T11 and the second transistor T12 can be connected in series with each other.

[0127] The first transistor T11 can output the previous stage carry signal C(k-2) to a first connection node NC1 in response to input of a line sensing preparation signal LSP. The second transistor T12 can electrically connect the first connection node NC1 to the M node in response to input of the line sensing preparation signal LSP. For example, when the line sensing preparation signal LSP having a high voltage is input to the first transistor T11 and the second transistor T12, the first transistor T11 and the second transistor T12 can be simultaneously turned on, thereby enabling the M node to be charged to a first high voltage (GVDD1) level.

[0128] The third transistor T13 can be turned on when a voltage level of the M node is at a high level and provide the first high voltage GVDD1 to the first connection node NC1. When the first high voltage GVDD1 is provided to the first connection node NC1, a voltage difference between a gate voltage of the first transistor T11 and a voltage of the first connection node NC1 can increase. Thereafter, when the line sensing preparation signal LSP having a low level is input to the gate of the first transistor T11 and the first transistor T11 is thereby turned off, the first transistor T11 can be completely maintained in an off state due to the voltage difference between the gate voltage of the first transistor T11 and the voltage of the first connection node NC1. Accordingly, current leakage of the first transistor T11 and a voltage drop of the M node caused by the current leakage of the first transistor T11 can be prevented, which enables the voltage of the M node to be stably maintained.

[0129] The pre-charge capacitor CA can be connected between a first high voltage line for transmitting the first high voltage GVDD1 and the M node and store a voltage difference between the first high voltage GVDD1 and a voltage charged in the M node. The pre-charge capacitor CA can store a high voltage of the previous stage carry signal C(k-2) when the first transistor T11, the second transistor T12, and the third transistor T13 are turned on. The pre-charge capacitor CA can maintain the voltage of the M node at the stored voltage for a predetermined time when the first transistor T11, the second transistor T12, and the third transistor T13 are turned off.

[0130] The fourth transistor T14 and the fifth transistor T15 can be connected between the first high voltage line for transmitting the first high voltage GVDD1 and the Q node. The fourth transistor T14 and the fifth transistor T15 can be connected in series with each other.

[0131] The fourth transistor T14 and the fifth transistor T15 can charge the Q node to the first high voltage GVDD1 in response to the voltage of the M node and the input of the reset signal RESET. The fourth transistor T14 can be turned on when the voltage of the M node is at a high level, and transmit the first high voltage GVDD1 to a shared node of the fourth transistor T14 and the fifth transistor T15. The fifth transistor T15 can be turned on by the reset signal RESET having a high level, and provide the voltage of the shared node to the Q node. Accordingly, when the fourth transistor T14 and the fifth transistor T15 are simultaneously turned on, the Q node can be charged to the first high voltage GVDD1.

[0132] The sixth transistor T16 and the seventh transistor T17 can be connected between the Q node and a third low voltage line for transmitting a third low voltage GVSS3. The sixth transistor T16 and the seventh transistor T17 can be connected in series to each other.

[0133] In response to the input of the panel on signal POS, the sixth transistor T16 and the seventh transistor T17 can discharge the Q node to the third low voltage GVSS3. The discharge of the Q node to the third low voltage GVSS3 can also be expressed as the reset of the Q node. The seventh transistor T17 can be turned on by the input of the panel on signal POS having a high level and provide the third low voltage GVSS3 to the QH node. The sixth transistor T16 can be turned on by the input of the panel on signal POS having a high level and electrically connect the Q node and the QH node. Accordingly, when the sixth transistor T16 and the seventh transistor T17 are simultaneously turned on, the Q node can be discharged or reset to the third low voltage GVSS3.

[0134] The Q node controller 504 can charge the Q node to the first high voltage (GVDD1) level in response to the input of the previous stage carry signal C(k-2), and discharge the Q node to the third low voltage GVSS3 in response to the input of the subsequent stage carry signal C(k+2).

[0135] The Q node controller 504 can include a first transistor T21 to an eighth transistor T28.

[0136] The first transistor T21 and the second transistor T22 can be connected between a first high voltage line for transmitting a first high voltage GVDD1 and the Q node. The first transistor T21 and the second transistor T22 can be connected in series to each other.

[0137] The first transistor T21 and the second transistor T22 can charge the Q node to the first high voltage (GVDD1) level in response to an input of the previous stage carry signal C(k-2). The first transistor T21 can be turned on by the input of the previous stage carry signal C(k-2) and provide the first high voltage GVDD1 to the second connection node NC2. The second transistor T22 can be turned on by the input of the previous stage carry signal C(k-2) and electrically connect the second connection node NC2 with the Q node. Accordingly, when the first transistor T21 and the second transistor T22 are simultaneously turned on, the first high voltage GVDD1 can be provided to the Q node.

[0138] The fifth transistor T25 and the sixth transistor T26 can be connected to a third high voltage line for transmitting a third high voltage GVDD3. The fifth transistor T25 and the sixth transistor T26 can provide the third high voltage GVDD3 to the second connection node NC2 in response to the third high voltage GVDD3.

[0139] Since the fifth transistor T25 and the sixth transistor T26 can be simultaneously turned on by the third high voltage GVDD3, a voltage difference between the gate voltage of the first transistor T21 and the voltage of the second connection node NC2 can be increased by enabling the third high voltage GVDD3 to be constantly provided to the second connection node NC2. Accordingly, when the previous stage carry signal C(k-2) having a low level is input to the gate of the first transistor T21 and thereby the first transistor T21 is turned off, the first transistor T21 can be completely maintained in the off state due to the voltage difference between the gate voltage of the first transistor T21 and the voltage of the second connection node NC2. Accordingly, current leakage of the first transistor T21 and a voltage drop of the Q node caused by the current leakage of the first transistor T21 can be prevented, which enables the voltage of the Q node to be stably maintained.

[0140] For example, when the threshold voltage of the first transistor T21 is negative (-), the gate-source voltage Vgs of the first transistor T21 can be maintained to be negative (-) by the third high voltage GVDD3 provided to the drain electrode thereof. Accordingly, when the previous stage carry signal C(k-2) having a low level is input to the gate of the first transistor T21, thereby the first transistor T21 is turned off, the first transistor T21 can be completely maintained in the off state and occurrence of a corresponding drain current can be prevented.

[0141] In one embodiment, the third high voltage GVDD3 can be set to a voltage level lower than the first high voltage GVDD1.

[0142] The third transistor T23 and the fourth transistor T24 can be connected between the Q node and a third low voltage line for transmitting a third low voltage GVSS3. The third transistor T23 and the fourth transistor T24 can be connected in series with each other.

[0143] The third transistor T23 and the fourth transistor T24 can discharge the Q node and the QH node to the third low voltage GVSS3 in response to input of the subsequent stage carry signal C(k+2). The fourth transistor T24 can be turned on by input of the subsequent stage carry signal C(k+2) and discharge the QH node to the third low voltage GVSS3. The third transistor T23 can be turned on by input of the subsequent stage carry signal C(k+2) and electrically connect the Q node and the QH node. Accordingly, when the third transistor T23 and the fourth transistor T24 are simultaneously turned on, the Q node and the QH node can be discharged or reset to the third low voltage GVSS3.

[0144] The seventh transistor T27 and the eighth transistor T28 can be connected between a first high voltage line for transmitting a first high voltage GVDD1 and the Q node and between the first high voltage line for transmitting the first high voltage GVDD1 and the QH node. The seventh transistor T27 and the eighth transistor T28 can be connected in series with each other.

[0145] The seventh transistor T27 and the eighth transistor T28 can provide the first high voltage GVDD1 to the QH node in response to a voltage of the Q node. The seventh transistor T27 can be turned on when the voltage of the Q node is at a high level and provide the first high voltage GVDD1 to a shared node of the seventh transistor T27 and the eighth transistor T28. The eighth transistor T28 can be turned on when the voltage of the Q node is at the high level and electrically connect the shared node and the QH node. Accordingly, when the voltage of the Q node is at the high level, the seventh transistor T27 and the eighth transistor T28 can be simultaneously turned on and provide the first high voltage GVDD1 to the QH node.

[0146] When the first high voltage GVDD1 is provided to the QH node, a voltage difference between the gate of the third transistor T23 and the QH node can increase. Accordingly, the subsequent stage carry signal C(k+2) having a low level is input to the gate of the third transistor T23, whereby the third transistor T23 is turned off, and the third transistor T23 can be completely maintained in the off state due to the voltage difference between the gate voltage of the third transistor T23 and the voltage of the QH node. Accordingly, current leakage of the third transistor T23 and a voltage drop of the Q node caused by the current leakage of the third transistor T23 can be prevented, which enables the voltage of the Q node to be stably maintained.

[0147] The Q node and QH node stabilization circuit 506 can discharge the Q node and the QH node to a third low voltage (GVSS3) level in response to a voltage of the QB node.

[0148] The Q node and QH node stabilization circuit 506 can include a first transistor T31 and a second transistor T32. The first transistor T31 and the second transistor T32 can be connected between the Q node and a third low voltage line for transmitting the third low voltage GVSS3. The first transistor T31 and the second transistor T32 can be connected in series with each other.

[0149] The first transistor T31 and the second transistor T32 can discharge the Q node and the QH node to the third low voltage GVSS3 in response to a voltage of the QB node. The second transistor T32 can be turned on when the voltage of the QB node is at a high level, and provide the third low voltage GVSS3 to a shared node of the first transistor T31 and the second transistor T32. The first transistor T31 can be turned on when the voltage of the QB node is at the high level, and electrically connect the Q node with the QH node. Accordingly, when the first transistor T31 and the second transistor T32 are simultaneously turned on by the voltage of the QB node, the Q node and the QH node can be discharged or reset to the third low voltage GVSS3.

[0150] The inverter 508 can change a voltage level of the QB node according to a voltage level of the Q node.

[0151] The inverter 508 can include a first transistor T41 to a fifth transistor T45.

[0152] The second transistor T42 and the third transistor T43 can be connected between a second high voltage line for transmitting a second high voltage GVDD2 and a third connection node NC3. The second transistor T42 and the third transistor T43 can be connected in series with each other.

[0153] The second transistor T42 and the third transistor T43 can provide the second high voltage GVDD2 to the third connection node NC3 in response to the second high voltage GVDD2. The second transistor T42 can be turned on by the second high voltage GVDD2, and provide the second high voltage GVDD2 to a shared node of the second transistor T42 and the third transistor T43. The third transistor T43 can be turned on by the second high voltage GVDD2, and electrically connect the shared node of the second transistor T42 and the third transistor T43 with the third connection node NC3. Accordingly, when the second transistor T42 and the third transistor T43 are simultaneously turned on by the second high voltage GVDD2, the third connection node NC3 can be charged to a second high voltage (GVDD2) level.

[0154] The fourth transistor T44 can be connected between the third connection node NC3 and a second low voltage line for transmitting a second low voltage GVSS2.

[0155] The fourth transistor T44 can provide the second low voltage GVSS2 to the third connection node NC3 in response to the voltage of the Q node. The fourth transistor T44 can be turned on when the voltage of the Q node is at a high level, and discharge or reset the third connection node NC3 to the second low voltage GVSS2.

[0156] The first transistor T41 can be connected between a second high voltage line for transmitting a second high voltage GVDD2 and the QB node.

[0157] The first transistor T41 can provide the second high voltage GVDD2 to the QB node in response to the voltage of the third connection node NC3. The first transistor T41 can be turned on when the voltage of the third connection node NC3 is at a high level, and charge the QB node to the second high voltage (GVDD2) level.

[0158] The fifth transistor T45 can be connected between the QB node and a third low voltage line for transmitting a third low voltage GVSS3.

[0159] The fifth transistor T45 can provide the third low voltage GVSS3 to the QB node in response to the voltage of the Q node. The fifth transistor T45 can be turned on when the voltage of the Q node is at a high level, and discharge or reset the QB node to the third low voltage GVSS3 level.

[0160] The QB node stabilization circuit 510 can discharge the QB node to the third low voltage GVSS3 in response to an input of the previous stage carry signal C(k-2), an input of the reset signal, and a charging voltage of the M node.

[0161] The QB node stabilization circuit 510 can include a first transistor T51 to a third transistor T53.

[0162] The first transistor T51 can be connected between the QB node and a third low voltage line for transmitting a third low voltage GVSS3.

[0163] The first transistor T51 can provide the third low voltage GVSS3 to the QB node in response to an input of the previous stage carry signal C(k-2). The first transistor T51 can provide the third low voltage GVSS3 to the QB node when the previous stage carry signal C(k-2) having a high level is input to a gate of the first transistor T51.

[0164] The second transistor T52 and the third transistor T53 can be connected between the QB node and a third low voltage line for transmitting a third low voltage GVSS3. The second transistor T52 and the third transistor T53 can be connected in series with each other.

[0165] The second transistor T52 and the third transistor T53 can discharge the QB node to a third low voltage GVSS3 level in response to an input of a reset signal and a charging voltage of the M node. The third transistor T53 can be turned on when a voltage of the M node is at a high level, and provide the third low voltage GVSS3 to a shared node of the second transistor T52 and the third transistor T53. The second transistor T52 can be turned on by an input of the reset signal RESET, and electrically connect the shared node of the second transistor T52 and the third transistor T53 with the QB node. Accordingly, when the reset signal RESET is input as a high level of the voltage of the M node, the second transistor T52 and the third transistor T53 can be simultaneously turned on, and enable the QB node to be discharged or reset to the third low voltage GVSS3.

[0166] The carry signal output circuit 512 can output the carry signal C(k) based on a voltage level of the carry clock signal CRCLK(k) according to a voltage level of the Q node or based on a third low voltage (GVSS3) level according to a voltage level of the QB node.

[0167] The carry signal output circuit 512 can include a first transistor T61, a second transistor T62, and a boost capacitor CC.

[0168] The first transistor T61 can be connected between a clock signal line for transmitting the carry clock signal CRCLK(k) and a first output node NO1. The boost capacitor CC can be connected between a gate and a source of the first transistor T61.

[0169] The first transistor T61 can output the carry signal C(k) having a high voltage through the first output node NO1 based on the carry clock signal CRCLK(k) in response to a voltage of the Q node. The first transistor T61 can be turned on when a voltage of the Q node is at a high level, and provide the carry clock signal CRCLK(k) having a high voltage to the first output node NO1. Accordingly, the carry signal C(k) having a high voltage can be output.

[0170] The boost capacitor CC can bootstrap the voltage of the Q node in synchronization with the carry clock signal CRCLK(k) having a high voltage level until a boosted voltage level greater than the first high voltage GVDD1 is reached when the carry signal C(k) is output. The carry clock signal CRCLK(k) having a high voltage level can be output as the carry signal C(k) quickly and without distortion when the voltage of the Q node is bootstrapped.

[0171] The second transistor T62 can be connected between the first output node NO1 and a third low voltage line for transmitting a third low voltage GVSS3.

[0172] The second transistor T62 can output a carry signal C(k) having a low voltage through the first output node NO1 based on the third low voltage GVSS3 in response to the voltage of the QB node. The second transistor T62 can be turned on when the voltage of the QB node is at a high level, and supply the third low voltage GVSS3 to the first output node NO1. Accordingly, the carry signal C(k) having a low voltage can be output.

[0173] The gate signal output circuit 512 can output a plurality of gate signals (GATE(i), GATE(i+1), GATE(i+2), GATE(i+3)) based on the voltage level of the plurality of scan clock signals (SCCLK(i), SCCLK(i+1), SCCLK(i+2), SCCLK(i+3)) or the voltage level of the first low voltage GVSS1 according to the voltage level of the Q node or the voltage level of the QB, where i is a positive integer.

[0174] The gate signal output circuit 512 can include first to eighth transistors T71 to T78 and boost capacitors (CS1, CS2, CS3, CS4).

[0175] The first to eighth transistors T71 to T78 can be connected to the clock signal lines for transmitting the scan clock signals (SCCLK(i), SCCLK(i+1), SCCLK(i+2), SCCLK(i+3)) and the second to fifth output nodes NO2 to NO5, respectively. The boost capacitors (CS1, CS2, CS3, CS4) can be connected between the gates and the sources of the first to eighth transistors T71 to T78, respectively.

[0176] The first transistor T71, the third transistor T73, the fifth transistor T75, and the seventh transistor T77 can output the gate voltage of the Q node to the second output node NO2, the third output node NO3, the fourth output node NO4, and the fifth output node NO5, respectively, based on the scan clock signal (SCCLK(i), SCCLK(i+1), SCCLK(i+2), SCCLK(i+3)). The first transistor T71, the third transistor T73, the fifth transistor T75, and the seventh transistor T77 can be turned on when the voltage of the Q node is at a high level, and can provide the scan clock signal (SCCLK(i), SCCLK(i+1), SCCLK(i+2), SCCLK(i+3)) having a high voltage to the second output node NO2, the third output node NO3, the fourth output node NO4, and the fifth output node NO5, respectively. Accordingly, the gate voltage of the Q node can be output to the second output node NO2, the third output node NO3, the fourth output node NO4, and the fifth output node NO5.

[0177] When the gate voltage of the Q node is boosted, the scan clock signal (SCCLK(i), SCCLK(i+1), SCCLK(i+2), SCCLK(i+3)) having a high voltage level can be quickly and distortionlessly output as the gate voltage of the Q node.

[0178] The second transistor T72, the fourth transistor T74, the sixth transistor T76, and the eighth transistor T78 can output the strobe signals (SCOUT(i), SCOUT(i+1), SCOUT(i+2), SCOUT(i+3)) having low voltages through the second output node NO2, the third output node NO3, the fourth output node NO4, and the fifth output node NO5 based on the first low voltage GVSS1 in response to the voltage of the QB node. The second transistor T72, the fourth transistor T74, the sixth transistor T76, and the eighth transistor T78 can be turned on when the voltage of the Q node is at a high level, and provide the first low voltage GVSS1 to the second output node NO2, the third output node NO3, the fourth output node NO4, and the fifth output node NO5, respectively. Accordingly, the strobe signals (SCOUT(i), SCOUT(i+1), SCOUT(i+2), SCOUT(i+3)) having low voltages can be output.

[0179] In Figure 5 In the embodiment illustrated, three high voltages (GVDD1, GVDD2, GVDD3) having different levels from each other and three low voltages (GVSS1, GVSS2, GVSS3) having different levels from each other can be provided to each stage circuit. For example, the first high voltage GVDD1, the second high voltage GVDD2, and the third high voltage GVDD3 can be set to 20 V, 16 V, and 14 V, respectively, and the first low voltage GVSS1, the second low voltage GVSS2, and the third low voltage GVSS3 can be set to -6 V, -10 V, and -12 V, respectively. However, these numbers are only examples, and the levels of the high voltages and the low voltages can be set differently according to embodiments.

[0180] Figure 6 is an example circuit diagram of a virtual stage circuit included in a strobe driving circuit according to aspects of the present disclosure.

[0181] Figure 6 The virtual stage circuit illustrated is Figure 4 is a circuit diagram of the previous virtual stage circuit DST1 illustrated.

[0182] Referring to Figure 6 In one embodiment, the previous virtual stage circuit DST1 can include a Q node, a QB node, and a QH node. In one embodiment, the previous virtual stage circuit DST1 can include a Q node controller 504, a Q node and QH node stabilization circuit 506, an inverter 508, and a carry signal output circuit 512.

[0183] The Q-node controller 504 can charge the Q-node to the first high voltage (GVDD1) level in response to an input of a start signal Vst for initialization of the RT sensing line, and discharge the Q-node to the third low voltage GVSS3 in response to an input of a subsequent carry signal C(k+2).

[0184] The Q-node controller 504 can include a first transistor T21 to an eighth transistor T28.

[0185] The first transistor T21 and the second transistor T22 can be connected between a first high voltage line for transmitting the first high voltage GVDD1 and the Q-node. The first transistor T21 and the second transistor T22 can be connected in series with each other.

[0186] The first transistor T21 and the second transistor T22 can charge the Q-node to the first high voltage (GVDD1) level in response to an input of a previous carry signal C(k-2). The first transistor T21 can be turned on by the input of the previous carry signal C(k-2), and provide the first high voltage GVDD1 to a second connection node NC2. The second transistor T22 can be turned on by the input of the previous carry signal C(k-2), and electrically connect the second connection node NC2 with the Q-node. Accordingly, when the first transistor T21 and the second transistor T22 are simultaneously turned on, the first high voltage GVDD1 can be provided to the Q-node.

[0187] The fifth transistor T25 and the sixth transistor T26 can be connected to a third high voltage line for transmitting a third high voltage GVDD3. The fifth transistor T25 and the sixth transistor T26 can provide the third high voltage GVDD3 to the second connection node NC2 in response to the third high voltage GVDD3.

[0188] Since the fifth transistor T25 and the sixth transistor T26 can be simultaneously turned on by the third high voltage GVDD3, a voltage difference between a gate voltage of the first transistor T21 and a voltage of the second connection node NC2 can be increased by enabling the third high voltage GVDD3 to be constantly provided to the second connection node NC2. Accordingly, when the previous carry signal C(k-2) having a low level is input to the gate of the first transistor T21 and the first transistor T21 is thereby turned off, the first transistor T21 can be completely maintained in an off state due to the voltage difference between the gate voltage of the first transistor T21 and the voltage of the second connection node NC2. Accordingly, current leakage of the first transistor T21 and a voltage drop of the Q-node caused by the current leakage of the first transistor T21 can be prevented, which enables the voltage of the Q-node to be stably maintained.

[0189] For example, when the threshold voltage of the first transistor T21 is negative (-), the gate-source voltage Vgs of the first transistor T21 can be maintained as negative (-) by the third high voltage GVDD3 supplied to the drain electrode thereof. Accordingly, the previous stage carry signal C(k-2) having a low level is input to the gate of the first transistor T21, whereby the first transistor T21 is turned off, the first transistor T21 can be completely maintained in an off state and occurrence of a corresponding drain current can be prevented.

[0190] In one embodiment, the third high voltage GVDD3 can be set to a voltage level lower than the first high voltage GVDD1.

[0191] The third transistor T23 and the fourth transistor T24 can be connected between the Q node and a third low voltage line for transmitting a third low voltage GVSS3. The third transistor T23 and the fourth transistor T24 can be connected in series to each other.

[0192] The third transistor T23 and the fourth transistor T24 can discharge the Q node and the QH node to the third low voltage GVSS3 in response to input of the subsequent stage carry signal C(k+2). The fourth transistor T24 can be turned on by input of the subsequent stage carry signal C(k+2) and discharge the QH node to the third low voltage GVSS3. The third transistor T23 can be turned on by input of the subsequent stage carry signal C(k+2) and electrically connect the Q node and the QH node. Accordingly, when the third transistor T23 and the fourth transistor T24 are simultaneously turned on, the Q node and the QH node can be discharged or reset to the third low voltage GVSS3.

[0193] The seventh transistor T27 and the eighth transistor T28 can be connected between a first high voltage line for transmitting the first high voltage GVDD1 and the Q node and between the first high voltage line for transmitting the first high voltage GVDD1 and the QH node. The seventh transistor T27 and the eighth transistor T28 can be connected in series to each other.

[0194] The seventh transistor T27 and the eighth transistor T28 can supply the first high voltage GVDD1 to the QH node in response to a voltage of the Q node. The seventh transistor T27 can be turned on when the voltage of the Q node is at a high level and supply the first high voltage GVDD1 to a shared node of the seventh transistor T27 and the eighth transistor T28. The eighth transistor T28 can be turned on when the voltage of the Q node is at a high level and electrically connect the shared node and the QH node. Accordingly, when the voltage of the Q node is at a high level, the seventh transistor T27 and the eighth transistor T28 can be simultaneously turned on and supply the first high voltage GVDD1 to the QH node.

[0195] When the first high voltage GVDD1 is supplied to the QH node, the voltage difference between the gate of the third transistor T23 and the QH node increases. Accordingly, the subsequent stage carry signal C(k+2) having a low level is input to the gate of the third transistor T23, whereby the third transistor T23 is turned off, and the third transistor T23 can be completely maintained in the off state due to the voltage difference between the gate voltage of the third transistor T23 and the voltage of the QH node. Accordingly, current leakage of the third transistor T23 and a voltage drop of the Q node caused by the current leakage of the third transistor T23 can be prevented, which enables the voltage of the Q node to be stably maintained.

[0196] The Q node and QH node stabilization circuit 506 can discharge the Q node and the QH node to a third low voltage (GVSS3) level in response to the voltage of the QB node.

[0197] The Q node and QH node stabilization circuit 506 can include a first transistor T31 and a second transistor T32. The first transistor T31 and the second transistor T32 can be connected between the Q node and a third low voltage line for transmitting the third low voltage GVSS3. The first transistor T31 and the second transistor T32 can be connected in series with each other.

[0198] The first transistor T31 and the second transistor T32 can discharge the Q node and the QH node to the third low voltage GVSS3 in response to the voltage of the QB node. The second transistor T32 can be turned on when the voltage of the QB node is at a high level, and supply the third low voltage GVSS3 to a shared node of the first transistor T31 and the second transistor T32. The first transistor T31 can be turned on when the voltage of the QB node is at a high level, and electrically connect the Q node and the QH node. Accordingly, when the first transistor T31 and the second transistor T32 are simultaneously turned on by the voltage of the QB node, the Q node and the QH node can be discharged or reset to the third low voltage GVSS3.

[0199] The inverter 508 can change the voltage level of the QB node according to the voltage level of the Q node.

[0200] The inverter 508 can include a first transistor T41 to a fifth transistor T45.

[0201] The second transistor T42 and the third transistor T43 can be connected between a second high voltage line for transmitting a second high voltage GVDD2 and a third connection node NC3. The second transistor T42 and the third transistor T43 can be connected in series with each other.

[0202] The second transistor T42 and the third transistor T43 can provide the second high voltage GVDD2 to the third connection node NC3 in response to the second high voltage GVDD2. The second transistor T42 can be turned on by the second high voltage GVDD2 and provide the second high voltage GVDD2 to a shared node of the second transistor T42 and the third transistor T43. The third transistor T43 can be turned on by the second high voltage GVDD2 and electrically connect the shared node of the second transistor T42 and the third transistor T43 with the third connection node NC3. Accordingly, when the second transistor T42 and the third transistor T43 are turned on at the same time by the second high voltage GVDD2, the third connection node NC3 can be charged to the second high voltage (GVDD2) level.

[0203] The fourth transistor T44 can be connected between the third connection node NC3 and a second low voltage line for transmitting the second low voltage GVSS2.

[0204] The fourth transistor T44 can provide the second low voltage GVSS2 to the third connection node NC3 in response to a voltage of the Q node. The fourth transistor T44 can be turned on when the voltage of the Q node is at a high level and discharge or reset the third connection node NC3 to the second low voltage GVSS2.

[0205] The first transistor T41 can be connected between a second high voltage line for transmitting the second high voltage GVDD2 and the QB node.

[0206] The first transistor T41 can provide the second high voltage GVDD2 to the QB node in response to a voltage of the third connection node NC3. When the voltage of the third connection node NC3 is at a high level, the first transistor T41 can be turned on and charge the QB node to the second high voltage (GVDD2) level.

[0207] The fifth transistor T45 can be connected between the QB node and a third low voltage line for transmitting the third low voltage GVSS3.

[0208] The fifth transistor T45 can provide the third low voltage GVSS3 to the QB node in response to a voltage of the Q node. The fifth transistor T45 can be turned on when the voltage of the Q node is at a high level and discharge or reset the QB node to the third low voltage GVSS3 level.

[0209] The carry signal output circuit 512 can output the carry signal C(k) based on a voltage level of the carry clock signal CRCLK(k) according to a voltage level of the Q node or based on the third low voltage (GVSS3) level according to a voltage level of the QB node.

[0210] The carry signal output circuit 512 can include a first transistor T61, a second transistor T62, and a boost capacitor CC.

[0211] The first transistor T61 can be connected between a clock signal line for transmitting a carry clock signal CRCLK(k) and a first output node NO1. The boost capacitor CC can be connected between the gate and the source of the first transistor T61.

[0212] The first transistor T61 can output a carry signal C(k) having a high voltage through the first output node NO1 based on the carry clock signal CRCLK(k) in response to the voltage of the Q node. The first transistor T61 can be turned on when the voltage of the Q node is at a high level and provide the carry clock signal CRCLK(k) having a high voltage to the first output node NO1. Accordingly, the carry signal C(k) having a high voltage can be output.

[0213] The boost capacitor CC can bootstrap the voltage of the Q node in synchronization with the carry clock signal CRCLK(k) having a high voltage level until a boosted voltage level greater than the first high voltage GVDD1 is reached when the carry signal C(k) is output. The carry clock signal CRCLK(k) having a high voltage level can be output as the carry signal C(k) quickly and without distortion when the voltage of the Q node is bootstrapped.

[0214] The second transistor T62 can be connected between the first output node NO1 and a third low voltage line for transmitting a third low voltage GVSS3.

[0215] The second transistor T62 can output a carry signal C(k) having a low voltage through the first output node NO1 based on the third low voltage GVSS3 in response to the voltage of the QB node. The second transistor T62 can be turned on when the voltage of the QB node is at a high level and provide the third low voltage GVSS3 to the first output node NO1. Accordingly, the carry signal C(k) having a low voltage can be output.

[0216] Figure 7 is a circuit diagram of another dummy stage circuit included in a strobe driving circuit according to aspects of the present disclosure.

[0217] Figure 7 The dummy stage circuit shown is Figure 4 is a circuit diagram of the previous dummy stage circuit DST2 shown.

[0218] Reference is made to Figure 7In one embodiment, the previous virtual stage circuit DST2 can include a Q node, a QB node, and a QH node. In one embodiment, the previous virtual stage circuit DST2 can include a Q node controller 504, a Q node and QH node stabilization circuit 506, an inverter 508, a carry signal output circuit 512, and a FB TFT circuit 516.

[0219] The Q node controller 504, the Q node and QH node stabilization circuit 506, the inverter 508, and the carry signal output circuit 512 are the same as the Q node controller 504, the Q node and QH node stabilization circuit 506, the inverter 508, and the carry signal output circuit 512 in the circuit diagram of Figure 6 With this in mind, the discussion of these elements is omitted and the discussion related to the circuit diagram of Figure 6 is incorporated for this embodiment. Figure 7

[0220] In one embodiment, the FB TFT circuit 516 of the previous virtual stage circuit DST2 is designed to have the same circuit structure as the T3 TFT (e.g., the first transistor T31 and the second transistor T32) with the same gate-source voltage Vgs applied as the T3 TFT. In this case, when the PBTS (positive bias temperature stress, the threshold voltage Vth of the T3 TFT is positively shifted) of the T3 TFT degrades, the threshold voltage Vth of the FB TFT circuit is also positively shifted, and the flowing current is reduced. The PGVDD voltage generation block (not shown) can sense this reduced current of the FB TFT circuit and increase the corresponding PGVDD voltage by the threshold voltage Vth.

[0221] ​The FB TFT circuit 516 can include first to sixth transistors T81 to T86. The first transistor T81 and the second transistor T82 can be connected between a feedback voltage line for transmitting a feedback voltage GVDD_FB and a third low voltage line for transmitting a third low voltage GVSS3. The first transistor T81 and the second transistor T82 can discharge the QH node to the third low voltage GVSS3 in response to a voltage of the QB node. The second transistor T82 can be turned on when the voltage of the QB node is at a high level, and provide the third low voltage GVSS3 to a shared node of the first transistor T81 and the second transistor T82. The first transistor T81 can be turned on when the voltage of the QB node is at a high level, and provide the feedback voltage GVDD_FB to the QH node. Accordingly, when the first transistor T31 and the second transistor T32 are simultaneously turned on by the voltage of the QB node, the Q node and the QH node can be discharged or reset to the third low voltage GVSS3. The third transistor T83 and the fourth transistor T84 and the fifth transistor T85 and the sixth transistor T86 have the same functions and operations as the first transistor T81 and the second transistor T82, and thus a description of these elements will be omitted for convenience of description. In addition, the number of transistors included in the FB TFT circuit 516 is not limited to the number shown. For example, the FB TFT circuit 516 can include one or more pairs of two transistors connected in series between the feedback voltage line and the third low voltage line for transmitting the third low voltage, and a gate electrode of each of the one or more pairs of two transistors can be commonly connected to the QB node, and a connection node between the first transistor and the second transistor can be commonly connected to the QH node. Figure 7

[0222] Figure 8 is a first carry signal line connection diagram of a stage circuit described herein, and Figure 9 is a second carry signal line connection diagram of a stage circuit described herein.

[0223] Referring to Figure 8 ​In one embodiment, the carry signal lines between the stage circuits can be connected such that the carry signal line is connected from a first one of the previous virtual stage circuits DST1, DST2 to the first stage circuit ST(1), and the carry signal line is connected from a second one of the previous virtual stage circuits DST1, DST2 to the second stage circuit ST(2). The stage circuits in the first carry signal line connection diagram can be executed such that the start signal Vst is input to the first previous virtual stage circuit DST1 and the second previous virtual stage circuit DST2 simultaneously for RT sensing line initialization, whereby the first previous virtual stage circuit DST1 and the second previous virtual stage circuit DST2 are activated, a previous stage carry signal C is generated, and the generated previous stage carry signal C is output to the first stage circuit ST(1) and the second stage circuit ST(2), respectively.

[0224] However, when the first carry signal line connection diagram of the stage circuits based on Figure 8 is executed for variable refresh rate (VRR) driving, the first previous virtual stage circuit DST1 and the second previous virtual stage circuit DST2 can be activated, and the FB TFT circuit 156 of the second previous virtual stage circuit DST2 is turned off and the corresponding PGVDD voltage is raised, which causes display artifacts such as horizontal lines to occur due to voltage difference.

[0225] To solve this horizontal line that occurs in VRR driving for the first carry signal line connection diagram of the stage circuits based on Figure 8 , a second carry signal line connection diagram of the stage circuits as shown in Figure 9 is developed.

[0226] In VRR driving, if the stage circuits are driven by the second carry signal line connection diagram as shown in Figure 9 , the occurrence of display artifacts such as horizontal lines can be solved. The relevant discussion is given below with reference to Figure 6 , Figure 7 and Figure 9 :

[0227] i. The start signal Vst is input to the first previous virtual stage circuit DST1 for RT sensing line initialization; ii. Then, the first previous virtual stage circuit DST1 can be activated, a previous stage carry signal C is generated, and the generated previous stage carry signal C is output to the second previous virtual stage circuit DST2 and the first stage circuit ST(1); and iii. Thereafter, when the previous stage carry signal C from the first previous virtual stage circuit DST1 is input, the second previous virtual stage circuit DST2 can be activated, a previous stage carry signal C is generated, and the generated previous stage carry signal C is output to the second stage circuit ST(2).

[0228] In this way, in the second carry signal line connection diagram, since the start signal Vst can be input only to the first previous virtual stage circuit DST1, and the previous stage carry signal C from the first previous virtual stage circuit DST1 is input to the second previous virtual stage circuit DST2, the Q node of the second previous virtual stage circuit DST2 is not activated, thus, the QB node can be maintained in the on state, and the FB TFT circuit 156 can normally operate.

[0229] When the FB TFT circuit 156 of the second previous virtual stage circuit DST2 normally operates, since the corresponding PGVDD voltage does not change, no voltage difference is caused, and the occurrence of horizontal lines caused by the first carry signal line connection diagram of the stage circuit can be prevented.

[0230] Figure 10 is a drive timing diagram of the stage circuit in the VRR driving according to the first connection diagram. Figure 8 In the Figure 10 , it can be seen that the FB TFT circuit 156 of the second previous virtual stage circuit DST2 is turned off, and the increase of the corresponding PGVDD voltage is maintained until the next frame starts.

[0231] Figure 11 is a drive timing diagram of the stage circuit in the VRR driving according to the second connection diagram. Figure 9 In the Figure 9 , it can be seen that the FB TFT circuit 156 of the second previous virtual stage circuit DST2 is turned on, and the corresponding PGVDD voltage is normally maintained until the next frame starts.

[0232] As described above, with reference to Figure 6 , Figure 7 , Figure 10 and Figure 11 , when performing VRR driving, since the stage circuit according to the embodiments of the present disclosure is driven according to the second connection diagram of the carry signal line, display artifacts such as horizontal lines can be solved and the image display quality can be improved.

[0233] Figure 12 The waveforms of the input signal and the output signal when the stage circuit outputs a gate signal for image display in the gate driving circuit according to aspects of the present disclosure are illustrated. Figure 5

[0234] ​In the period (from P1 to P2), when the previous stage carry signal C(k-2) having a high level is input, the first transistor T21 and the second transistor T22 of the Q node controller 504 can be turned on. Accordingly, the Q node can be charged to a first high voltage (GVDD1) level. Since the first transistor T51 of the QB node stabilization circuit 510 is turned on by the previous stage carry signal C(k-2) having a high level, the QB node can be discharged to a third low voltage GVSS3.

[0235] In the period (from P2 to P3), when the scan clock signal SCCLK(i) having a high level is input, the voltage of the Q node is boosted to a first boosted voltage (BL1) level higher than the first high voltage GVDD1 by the boost capacitor CS1. Accordingly, in the period (from P2 to P3), the strobe signal SCOUT(i) can be output from the second output node NO2.

[0236] In the period (from P3 to P4), when the scan clock signal SCCLK(i+1) having a high level is input together with the scan clock signal SCCLK(i) having a high level, the voltage of the Q node can be boosted to a second boosted voltage (BL2) level higher than the first boosted voltage (BL1) level by the boost capacitors (CS1, CS2). Accordingly, in the period (from P3 to P4), the strobe signal SCOUT(i+1) can be output from the third output node NO3.

[0237] In the period (from P4 to P5), when the scan clock signal SCCLK(i+2) having a high level is input together with the scan clock signal SCCLK(i+1) having a high level, the voltage of the Q node can be maintained at the second boosted voltage (BL2) level higher than the first boosted voltage (BL1) level by the boost capacitors (CS2, CS3). Accordingly, in the period (from P4 to P5), the strobe signal SCOUT(i+2) can be output from the fourth output node NO4.

[0238] In the period (from P5 to P6), when the scan clock signal SCCLK(i+3) having a high level is input together with the scan clock signal SCCLK(i+2) having a high level, the voltage of the Q node can be maintained at the second boosted voltage (BL2) level higher than the first boosted voltage (BL1) level by the boost capacitors (CS3, CS4). Accordingly, in the period (from P5 to P6), the strobe signal SCOUT(i+3) can be output from the fifth output node NO5.

[0239] In the period (from P6 to P7), since only the scan clock signal SCCLK(i+3) having a high level is input, the voltage of the Q node can be lowered to the level of the first boosted voltage BL1 through the boost capacitor CS4.

[0240] Further, in the period (from P6 to P7), when the carry clock signal CRCLK(k) having a high level is input, the carry signal C(k) can be output from the first output node NO1 through the first transistor T61 turned on by the voltage charged in the Q node.

[0241] In the period (from P7 to P8), since no scan clock signal is input, the voltage of the Q node can be charged to the first high voltage (GVDD1) level again. In addition, in the period (from P7 to P8), when the subsequent stage carry signal C(k+2) having a high level is input, the third transistor T23 and the fourth transistor T24 of the Q node controller 504 can be turned on. Thus, at the time point of P8, the Q node can be discharged to the third low voltage GVSS3. When the Q node is discharged to the third low voltage GVSS3, since the fourth transistor T44 included in the inverter 508 is cut off and the second high voltage GVDD2 is applied to the gate of the first transistor T41, the first transistor T41 can be turned on. When the first transistor T41 is turned on, the QB node can be charged to the second high voltage (GVDD2) level.

[0242] Figure 4 and Figure 5 The stage circuits of the gate drive circuit 13 illustrated in FIG. 6 do not share the QB node. Thus, the QB node can be turned on or off every frame. Accordingly, the transistors (T31, T32, T62, T72, T74, T76, T78) connected to the QB node can be turned on or off every frame.

[0243] In this way, if the transistors (T31, T32, T62, T72, T74, T76, T78) connected to the QB node are turned on or off every frame, the transistors (T31, T32, T62, T72, T74, T76, T78) can be rapidly deteriorated due to voltage stress applied to the transistors (T31, T32, T62, T72, T74, T76, and T78). The deterioration of the transistors due to the voltage stress applied to the transistors can cause an increase in threshold voltage of the transistors, which in turn can cause performance deterioration and a lifespan reduction of the display device 1.

[0244] Accordingly, to reduce the deterioration rate of the transistors (T31, T32, T62, T72, T74, T76, T78) connected to the QB node, the gate drive circuit 13 according to aspects of the present disclosure can adjust the magnitude of the voltage charged to the QB node, the second high voltage GVDD2.

[0245] Figure 13 is a graph showing a change in the amplitude of the second high voltage according to the driving time of the gate drive circuit in the display device according to aspects of the present disclosure. In Figure 13 , the horizontal axis represents the driving time of the gate drive circuit 13, and the vertical axis represents the amplitude of the second high voltage GVDD2 shown in Figure 13 .

[0246] In one embodiment, the amplitude of the second high voltage GVDD2 provided to the QB node shown in Figure 13 may be adjusted according to the driving time of the gate drive circuit 13.

[0247] For example, as shown in Figure 13 , the amplitude of the second high voltage GVDD2 can increase as the driving time of the gate drive circuit 13 increases. That is, as shown in Figure 13 , the amplitude of the second high voltage GVDD2 can increase stepwise to GV1, GV2, GV3, GV4, and GV5 each time the driving time of the gate drive circuit 13 increases to AT1, AT2, AT3, AT4, or AT5. At this time, the amplitude of the second high voltage GVDD2 (GV1, GV2, GV3, GV4, GV5) of each stage can be a value greater than or equal to the threshold voltage of the transistor (T31, T32, T62, T72, T74, T76, T78) connected to the QB node at each driving time (AT1, AT2, AT3, AT4, AT5) and determined through experiments.

[0248] Figure 13 An embodiment in which the amplitude of the second high voltage GVDD2 increases stepwise as the driving time of the gate drive circuit 13 increases is shown. However, in another embodiment, the amplitude of the second high voltage GVDD2 can increase linearly or nonlinearly in proportion to the driving time of the gate drive circuit 13.

[0249] In addition, Figure 13 AT1, AT2, AT3, AT4, AT5, GV1, GV2, GV3, GV4, and GV5 shown in

[0250] In addition, Figure 13The intervals between AT1, AT2, AT3, AT4, and AT5, and the intervals between GV1, GV2, GV3, GV4, and GV5, can be the same or different. For example, the difference between AT2 and AT1 can be set to be the same as or different from the difference between AT5 and AT4. As another example, the difference between GV3 and GV2 can be set to be the same as or different from the difference between GV5 and GV4.

[0251] like Figure 13 As shown, by increasing the amplitude of the second high voltage GVDD2 proportionally to the driving time of the gating drive circuit 13, the gating drive circuit 13 can be driven normally, and the voltage stress applied to the transistors (T31, T32, T62, T72, T74, T76, and T78) connected to the QB node can be minimized. Therefore, the lifespan of the display device 1 can be extended.

[0252] Figure 14 It is a graph showing the change in the threshold voltage amplitude of the transistor in the display device according to the aspects of the present disclosure, based on the driving time of the gating drive circuit.

[0253] exist Figure 14 In the data, 1204 indicates that when a second high voltage GVDD2 of the same amplitude is always provided... Figure 4 and Figure 5 When the QB node in the gate drive circuit 13 shown is selected, the threshold voltage amplitude of the transistor connected to the QB node changes.

[0254] In addition, data 1206 indicates that when in Figure 4 and Figure 5 In the gating drive circuit 13 shown, when the amplitude of the second high voltage GVDD2 increases according to the driving time of the gating drive circuit 13, the amplitude of the threshold voltage of the transistor connected to the QB node changes.

[0255] Figure 14 Data 1204 shows that when a second high voltage GVDD2 with the same amplitude is always supplied... Figure 4 and Figure 5 When the QB node in the shown gate drive circuit 13 is activated, the threshold voltage of the transistor connected to the QB node increases sharply. Therefore, the transistor connected to the QB node degrades rapidly, and the lifespan of the display device 1 is shortened.

[0256] However, from Figure 14 Data 1206 shows that when... Figure 4 and Figure 5The increase rate of the threshold voltage amplitude of the transistor connected to the QB node is significantly reduced compared to the case where the amplitude of the second high voltage GVDD2 always has the same amplitude when adjusting the amplitude of the second high voltage GVDD2 according to the driving time of the gate drive circuit 13 in the illustrated gate drive circuit 13. Therefore, it is possible to further prolong the life of the display device 1.

[0257] The above description has been presented to enable any person skilled in the art to make and use the disclosure, and the context in which it is provided has been provided in the specific application and its requirements. Various modifications, additions and substitutions to the described embodiments will be apparent to those skilled in the art and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of the disclosure. Although the exemplary embodiments have been described for illustrative purposes, those skilled in the art will recognize that various modifications and applications can be made without departing from the essential characteristics of the disclosure. For example, various modifications can be made to the specific components of the exemplary embodiments. The above description and drawings provide examples of the technical idea of the disclosure for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical idea of the disclosure. Therefore, the scope of the disclosure is not limited to the illustrated embodiments, but is intended to conform to the widest range consistent with the claims. The scope of protection of the disclosure should be interpreted according to the claims, and all technical ideas within the scope of the claims should be interpreted as being included in the scope of the disclosure.

[0258] Cross Reference to Related Applications

[0259] This application claims the priority benefit of Korean Patent Application No. 10-2021-0194274, filed December 31, 2021, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

Claims

1. A gating driving circuit, the gating driving circuit comprising: The first virtual stage circuit and the second virtual stage circuit, each of which can provide a carry signal and each includes a Q node, a QH node and a QB node; as well as Multiple stages of circuitry, each capable of providing a gating signal to each gating line, and each including the Q node, the QH node, and the QB node. Each of the plurality of stage circuits provides a corresponding gating signal to a corresponding gating line among the plurality of gating lines based on at least one of a plurality of carry signals from the first virtual stage circuit and the second virtual stage circuit, one or more preceding stage circuits among the plurality of stage circuits, and one or more subsequent stage circuits among the plurality of stage circuits. Wherein, the first virtual stage circuit and the second virtual stage circuit operate such that: Only the first virtual level circuit, which is one of the first virtual level circuits and the second virtual level circuit, is input with a start signal to activate the first virtual level circuit; and A carry signal from the first virtual level circuit is input to the second virtual level circuit so that the second virtual level circuit can be activated without the start signal.

2. The gating drive circuit according to claim 1, wherein, The Q-node controller included in the second virtual level circuit controls the charging or discharging of the Q-node based on the carry signal from the first virtual level circuit.

3. The gating drive circuit according to claim 2, wherein, When the start signal is input to the first virtual level circuit and the carry signal from the first virtual level circuit is input to the second virtual level circuit, the Q node controller of the second virtual level circuit deactivates the Q node in the second virtual level circuit and puts the QB node on.

4. The gating drive circuit according to claim 1, wherein, The second virtual stage circuit also includes a feedback circuit.

5. The gating drive circuit according to claim 4, wherein, The feedback circuit is connected between the feedback voltage line for transmitting the feedback voltage and the low voltage line for transmitting the low voltage, and is configured to discharge or reset at least one of the Q node and the QH node to a low voltage level in response to the voltage of the QB node.

6. The gating drive circuit according to claim 5, wherein, The feedback circuit includes one or more pairs of transistors, each pair of transistors including a first transistor and a second transistor connected in series between the feedback voltage line and the low voltage line, the gate electrodes of the first transistor and the second transistor being connected together to the QB node of the second virtual level circuit, and the connection node between the first transistor and the second transistor being connected together to the QH node of the second virtual level circuit.

7. The gating drive circuit according to claim 1, wherein, Each of the first virtual level circuit and the second virtual level circuit includes: A Q-node controller is configured to charge the Q-node to a first high voltage level and discharge the Q-node to a third low voltage level. Q-node and QH-node stabilization circuits are used to discharge the Q-node and QH-node to the third low voltage level when the QB-node is charged to the second high voltage level. An inverter, the inverter being used to change the voltage level of the QB node according to the voltage level of the Q node; A carry signal output circuit is used to output a carry signal based on the voltage level of the Q node and the voltage level of the carry clock signal, or based on the voltage level of the QB node and the third low voltage level.

8. The gating drive circuit according to claim 7, wherein, The respective Q-node controllers of the first virtual stage circuit and the second virtual stage circuit charge the Q-node to the first high voltage level in response to a start signal and a carry signal from the first virtual stage circuit, and discharge the Q-node to the third low voltage level in response to a subsequent carry signal.

9. The gating drive circuit according to claim 1, wherein, Each of the stage circuits includes: A line selector is configured to charge the M-node based on a previous carry signal in response to an input line sensing readiness signal, and to charge the Q-node to a first high voltage level in response to an input reset signal or to discharge the Q-node to a third low voltage level in response to an input panel open signal. A Q-node controller is configured to charge the Q-node to the first high voltage level in response to an input of a previous stage carry signal, and to discharge the Q-node to the third low voltage level in response to an input of a subsequent stage carry signal. Q-node and QH-node stabilization circuits are used to discharge the Q-node and QH-node to the third low voltage level when the QB-node is charged to the second high voltage level. An inverter, the inverter being used to change the voltage level of the QB node according to the voltage level of the Q node; QB node stabilization circuit, the QB node stabilization circuit being used to discharge the QB node to the third low voltage level in response to the input of the previous stage carry signal, the input of the reset signal and the charging voltage of the M node; A carry signal output circuit, wherein the carry signal output circuit is configured to output a carry signal based on the voltage level of the Q node based on the voltage level of the carry clock signal or based on the voltage level of the QB node based on the third low voltage level; and A gating signal output circuit is configured to output a first gating signal to a j-th gating signal based on the voltage level of the Q node or the voltage level of the QB node, according to a first scan clock signal to a j-th scan clock signal or a first low voltage.

10. The gating drive circuit according to claim 9, wherein, The first high voltage level and the second high voltage level are different from each other.

11. The gating drive circuit according to claim 9, wherein, The line selector includes a first transistor and a second transistor connected between the M node and a previous stage carry signal line for providing the previous stage carry signal, and a third transistor connected between a connection node and a first high voltage line for providing the first high voltage level, the connection node being located between the first transistor and the second transistor. The first transistor and the second transistor are controlled by the line sensing preparation signal, and the third transistor is controlled by the voltage of the M node.

12. The gating drive circuit according to claim 9, wherein, When the voltage level of the Q node is at a high voltage level, the strobe signal output circuit outputs the first strobe signal to the j-th strobe signal sequentially based on the first scan clock signal to the j-th scan clock signal.

13. The gating drive circuit according to claim 9, wherein, The gating signal output circuit includes: A pull-up transistor, which is turned on when the voltage level of the Q node is high and is capable of providing the first scan clock signal to the j-th scan clock signal to the output node; A pull-down transistor that turns on when the voltage level of the QB node is high and is capable of providing the first low voltage to the output node; and A boost capacitor is connected between the gate and source of the pull-up transistor.

14. The gating drive circuit according to claim 13, wherein, The pull-down transistor is turned on when the voltage level of the QB node is charged to the second high voltage level.

15. The gating drive circuit according to claim 9, wherein, The Q-node and QH-node stabilization circuits include a first transistor and a second transistor, which are turned on when the QB-node is charged to the second high voltage level.

16. The gating drive circuit according to claim 9, wherein, The amplitude of the second high voltage level is adjusted according to the driving time of the gating drive circuit.

17. The gating drive circuit according to claim 9, wherein, The amplitude of the second high voltage level increases with the increase of the driving time of the gating drive circuit.

18. The gating drive circuit according to claim 9, wherein, The carry signal output circuit includes a pull-up transistor and a boost capacitor connected between the gate and source of the pull-up transistor.

19. The gating drive circuit according to claim 9, wherein, j is a positive integer greater than or equal to 2.

20. The gating drive circuit according to claim 1, wherein, The carry signal line of the first virtual stage circuit is connected to the second virtual stage circuit and the first stage circuit in the plurality of stage circuits, and the carry signal line of the second virtual stage circuit is connected to the second stage circuit in the plurality of stage circuits.

21. The gating drive circuit according to claim 1, wherein, The gating drive circuit is executed with a variable refresh rate drive.

22. A gating driving circuit, the gating driving circuit comprising: The first virtual stage circuit and the second virtual stage circuit, each of which can provide a carry signal and each includes a Q node, a QH node and a QB node; as well as Multiple stages of circuitry, each capable of providing a gating signal to each gating line, and each including the Q node, the QH node, and the QB node. Each of the plurality of stage circuits provides a corresponding gating signal to a corresponding gating line among the plurality of gating lines based on at least one of a plurality of carry signals from the first virtual stage circuit and the second virtual stage circuit, one or more preceding stage circuits among the plurality of stage circuits, and one or more subsequent stage circuits among the plurality of stage circuits. The first virtual stage circuit is activated by an input start signal, generates a first previous stage carry signal, and outputs the first previous stage carry signal to the second virtual stage circuit and the first stage circuit among the plurality of stage circuits. The second virtual stage circuit is activated by a first previous stage carry signal that is different from the start signal from the first virtual stage circuit, generates a second previous stage carry signal, and outputs the second previous stage carry signal to a second stage circuit that is adjacent to and different from the first stage circuit among the plurality of stage circuits.

23. The gating drive circuit according to claim 22, wherein, The second virtual stage circuit also includes a feedback circuit connected between a feedback voltage line for transmitting a feedback voltage and a low voltage line for transmitting a low voltage, and configured to discharge or reset at least one of the Q node and the QH node to a low voltage level in response to the voltage of the QB node.

24. A gating driving circuit, the gating driving circuit comprising: The first virtual stage circuit and the second virtual stage circuit, each of which can provide a carry signal and each includes a Q node, a QH node and a QB node; as well as Multiple stages of circuitry, each capable of providing a gating signal to each gating line, and each including the Q node, the QH node, and the QB node. The second virtual stage circuit includes a feedback circuit connected between a feedback voltage line for transmitting feedback voltage and a low voltage line for transmitting low voltage. The start signal is input only to the first virtual stage circuit in the first virtual stage circuit and the second virtual stage circuit. The previous stage carry signal line of the first virtual stage circuit is applied to the second virtual stage circuit and the first stage circuit in the plurality of stage circuits. The previous stage carry signal line of the second virtual stage circuit is connected to the second stage circuit in the plurality of stage circuits.

25. A display device, the display device comprising: The display panel includes sub-pixels formed in the intersection area of ​​the gate lines and the data lines; The gating drive circuit according to any one of claims 1 to 24, wherein the gating drive circuit is configured to provide a scan signal to each of the gating lines; A data driving circuit, wherein the data driving circuit is used to provide a data voltage to each of the data lines; as well as A timing controller is used to control the driving of the gating drive circuit and the data drive circuit.

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