Semiconductor device manufacturing method
By creating grooves in the second metal layer of the semiconductor device near the wire bonding area of the package, lateral stress is blocked, the problem of dielectric layer fracture is solved, and the reliability and production efficiency of the device are improved.
Patent Information
- Application Number
- CN202511042012.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-28
- Publication Date
- 2025-11-04
AI Technical Summary
In the CUP design process of semiconductor devices, the dielectric layer below the top metal layer is prone to fracture under vertical and horizontal stress, leading to crack formation, affecting device reliability and potentially causing leakage paths or short circuits.
A groove is made in the second metal layer near the packaging wire bonding area. By forming a horizontal break, the transverse stress during packaging wire bonding is blocked, thus preventing the dielectric layer from breaking.
It effectively avoids dielectric layer fracture, improves the reliability and productivity of semiconductor devices, and prevents premature failure.
Smart Images
Figure CN120895478A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to a semiconductor device, in particular to a semiconductor device manufacturing method. BACKGROUND
[0002] The description in this part only provides background information related to the present application disclosure, and does not constitute prior art.
[0003] At present, when designing CUP (Chip Under Pad), it is generally necessary to apply vertical force to the metal layer located on the top layer during packaging wire bonding or testing pinning, such as Figure 1 As shown in the above stress application, vertical stress and horizontal stress will be generated between layers, specifically, under the effect of the above two stresses, the toughness of the dielectric layer below the top metal layer is poor, and the fracture may occur, resulting in cracks, which may cause early failure (reliability risk) of the semiconductor device, causing additional leakage path, and even short circuit in severe cases.
[0004] It should be noted that the above introduction to the technical background is only to facilitate the clear and complete description of the technical scheme of the present application, and to facilitate the understanding of those skilled in the art. The above technical scheme cannot be considered as known to those skilled in the art only because it is described in the background section of the present application. SUMMARY
[0005] The purpose of the present application is to provide a semiconductor device manufacturing method, which can avoid the fracture of the second dielectric layer by opening a groove near the packaging wire bonding area of the second metal layer, so as to break the horizontal stress transmitted transversely during packaging wire bonding.
[0006] In order to achieve the above purpose, the present application discloses a semiconductor device manufacturing method, which comprises:
[0007] forming a substrate layer;
[0008] forming source metal, drain metal and gate metal on the top surface of the substrate layer;
[0009] forming a first dielectric layer on the top surface of the source metal, the drain metal and the gate metal;
[0010] forming a first metal layer on the top surface of the first dielectric layer, and electrically connecting the first metal layer with the corresponding source metal, drain metal or gate metal in ohmic contact;
[0011] forming a second dielectric layer on the top surface of the first metal layer;
[0012] forming a second metal layer on the top surface of the second dielectric layer, and electrically connecting the second metal layer with the corresponding first metal layer via a metal via;
[0013] determining a packaging wire region, and forming a groove in the second metal layer adjacent to the packaging wire region, the groove being used to block stress transferred from the packaging wire region during a packaging wire process.
[0014] As a further description of the above technical solution, in the step of "determining a packaging wire region, and forming a groove in the second metal layer adjacent to the packaging wire region", the step successively includes the steps of gluing, developing, exposing, and etching.
[0015] As a further description of the above technical solution, the groove extends in a direction perpendicular to the second metal layer.
[0016] As a further description of the above technical solution, the groove is arranged in a direction penetrating the second metal layer.
[0017] As a further description of the above technical solution, in the step of "determining a packaging wire region, and forming a groove in the second metal layer adjacent to the packaging wire region", the packaging wire region has a first width, and the groove is arranged at a position away from the packaging wire region by a second width, wherein the first width is greater than the second width.
[0018] As a further description of the above technical solution, the first width is set to 50 um, and the second width is set to 10-20 um.
[0019] As a further description of the above technical solution, the number of grooves is set to be multiple, and the multiple grooves are arranged at intervals on the second metal layer.
[0020] The application further discloses a semiconductor device, wherein the semiconductor device is prepared by the above semiconductor device manufacturing method, and the semiconductor device comprises a base layer of a bottom layer, a source metal, a drain metal, and a gate metal formed above the base layer, a first dielectric layer formed above the source metal, the drain metal, and the gate metal, a second metal layer formed above the first dielectric layer, and a groove arranged adjacent to a packaging wire region on the second metal layer.
[0021] By means of the above technical solution, the application has the following beneficial effects:
[0022] The semiconductor device manufacturing method of the present application can form a groove in the second metal layer near the packaging wire bonding area, the groove can form a fault in a certain position of the second metal layer in the horizontal direction, so as to break the horizontal stress transmitted in the transverse direction during packaging wire bonding, and the propagation of the horizontal stress in the horizontal direction of the second metal layer is broken at the position of the groove, thereby avoiding the further pulling of the second dielectric layer in the horizontal direction caused by the second metal layer, so as to avoid the fracture of the second dielectric layer with poor toughness, thereby avoiding the generation of cracks in the prior art, avoiding the problem that the semiconductor device may be early failure (there is a risk of reliability), and indirectly improving the production capacity.
[0023] In order to enable a person skilled in the art to further understand the features and technical contents of the present application, please refer to the following detailed description and drawings of the present application. However, the drawings provided are only used for reference and illustration, and are not used to limit the present application. BRIEF DESCRIPTION OF DRAWINGS
[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiment or prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art without creative labor.
[0025] Figure 1 is a schematic diagram of the fracture of the second dielectric layer caused by the packaging wire bonding of the prior art;
[0026] Figure 2 is a stress schematic diagram of a semiconductor device manufacturing method provided by the present application;
[0027] Figure 3 is a cross-sectional schematic diagram of a semiconductor device manufacturing method provided by the present application;
[0028] Figures 4-9 is a step schematic diagram of a semiconductor device manufacturing method provided by the present application.
[0029] In the drawings:
[0030] 1, base layer;
[0031] 2, source metal;
[0032] 3, drain metal;
[0033] 4, gate metal;
[0034] 5, first metal layer;
[0035] 6, second dielectric layer;
[0036] 7. Second metal layer; 71. Package wire bonding area; 72. Groove. DETAILED DESCRIPTION
[0037] In order to make the person skilled in the art better understand the technical solutions in the specification, the technical solutions in the specification will be described clearly and completely in the following with reference to the drawings in the specification. Obviously, the described embodiments are only part of the embodiments of the specification, not all. Based on the embodiments in the specification, all other embodiments obtained by the person skilled in the art without creative labor should belong to the protection scope of the specification.
[0038] The following is to illustrate the embodiments of the present application by specific embodiments, and the person skilled in the art can understand the advantages and effects of the present application from the disclosure of the specification. The present application can be implemented or applied by other different specific embodiments, and each detail in the specification can be modified and changed in various ways based on different views and applications without departing from the concept of the present application. In addition, the drawings of the present application are only simple schematic illustrations, not the depiction according to the actual size, and the prior declaration. The following embodiments will further illustrate the related technical content of the present application in detail, but the disclosed content is not used to limit the protection scope of the present application.
[0039] It should be understood that although the terms "first", "second", "third" and the like may be used herein to describe various components or signals, these components or signals should not be limited by these terms. These terms are mainly used to distinguish one component from another component, or one signal from another signal. In addition, the term "or" used herein may include any one or more combinations of the associated listed items.
[0040] Please refer to Figures 2-3 A semiconductor device manufacturing method is provided in the embodiment, wherein the semiconductor device manufacturing method comprises:
[0041] Forming a substrate layer 1;
[0042] Forming a source metal 2, a drain metal 3 and a gate metal 4 on the top surface of the substrate layer 1;
[0043] Forming a first dielectric layer on the top surface of the source metal 2, the drain metal 3 and the gate metal 4;
[0044] Forming a first metal layer 5 on the top surface of the first dielectric layer, and electrically connecting the first metal layer 5 with the corresponding source metal 2, drain metal 3 or gate metal 4 in ohmic contact;
[0045] A second dielectric layer 6 is formed on the top surface of the first metal layer 5;
[0046] A second metal layer 7 is formed on the top surface of the second dielectric layer 6, and the second metal layer 7 is electrically connected with the corresponding first metal layer 5 through a metal via hole;
[0047] A wire-bonding area 71 is determined on the second metal layer 7, and a groove 72 is formed on the second metal layer 7 near the wire-bonding area 71, which is used to block the stress transmitted from the wire-bonding area 71 during the wire-bonding process.
[0048] In the actual operation, the substrate layer 1 is first formed by the above method, wherein the substrate layer 1 is composed of Si, SiC, GaN and other substrate materials, and is formed by metal organic chemical vapor deposition or photolithography, and is used for connecting the source metal 2, the drain metal 3 and the gate metal 4. The source metal 2, the drain metal 3 and the gate metal 4 are formed on the substrate layer 1, wherein the source metal 2, the drain metal 3 and the gate metal 4 are connected to the first dielectric layer, also called IMD layer (Inter-Metal Dielectric Layer), and the first metal layer 5 is formed on the dielectric layer. The first dielectric layer mainly plays the role of effectively electrically and thermally isolating the source metal 2, the drain metal 3, the gate metal 4 and the first metal layer 5, and provides effective mechanical support. The first dielectric layer can be formed by chemical vapor deposition. Similarly, the second dielectric layer 6 is laid on the first metal layer 5 and covers the first metal layer 5 and the first dielectric layer, which has a similar function to the first dielectric layer. When the first dielectric layer is formed, ohmic contacts for connecting the source metal 2, the drain metal 3, the gate metal 4 and the first metal layer 5 are made at the corresponding positions. Similarly, when the second dielectric layer 6 is formed, a corresponding number of metal via holes for connecting the first metal layer 5 and the second metal layer 7 are made at the corresponding positions. Then, after the second metal layer 7 is laid, the wire-bonding area 71 is determined on the second metal layer 7, and the groove 72 is formed near the wire-bonding area 71. The second metal layer 7 needs to be patterned to form a corresponding groove 72 line, and the position of the groove 72 is determined according to the position of the corresponding wire-bonding area 71. The groove 72 is arranged adjacent to the wire-bonding area 71 and matched one by one.
[0049] In the above method, the corresponding groove 72 is arranged at the wire-bonding area 71, so that the groove 72 can form a fault at a certain position of the second metal layer 7 in the horizontal direction, such as Figure 2As shown, so that the encapsulation wire breakage of the horizontal stress is broken, the horizontal stress is broken at the position where the groove 72 is located, and the further horizontal pulling of the second dielectric layer 6 is avoided, so that the second dielectric layer 6 with poor toughness is broken, and the crack in the prior art is avoided, and the production capacity is indirectly improved. Specifically, as shown in Figure 1 As shown, in the prior art, the same semiconductor device without the groove 72 is encapsulated and wired, and the encapsulation and wiring area 71 first receives the force in the vertical direction, and the second metal layer 7 is deformed under the action of the force, and the bottom second dielectric layer 6 is deformed, and the horizontal deformation of the second metal layer 7 occurs in the vertical deformation process, so that the second metal layer 7 is displaced in the horizontal direction, and the bottom second dielectric layer 6 is displaced in the horizontal direction. Because the toughness of the second dielectric layer 6 is significantly weaker than that of the metal second metal layer 7, the second dielectric layer 6 is broken, and the above situation is limited due to the setting of the groove 72 in the present application, and the breakage is avoided.
[0050] Further, the encapsulation and wiring area 71 is determined on the second metal layer 7, and the groove 72 is opened near the encapsulation and wiring area 71 of the second metal layer 7, which includes the steps of gluing, developing, exposing and etching in sequence. Among them, the glue is uniformly coated on the surface of the second metal layer 7. This step ensures that the pattern information can be accurately transmitted in the subsequent process, and protects the area that does not need to be etched from being eroded. After gluing, pre-baking is performed to improve the stability and adhesion of the photoresist. Then the pattern is transferred (mainly the pattern of the linear groove 72) by exposure, and then the unexposed photoresist is removed by developing. The photoresist after exposure plays a protective role for the second metal layer 7 in the etching process. In the etching process, the unprotected second metal layer 7 is dissolved by chemical etching process, and the shape of the groove 72 is etched.
[0051] Further, as shown in Figure 2 In this embodiment, the groove 72 extends in a direction perpendicular to the second metal layer 7. That is, in this embodiment, the groove is set as a vertical rectangular body, which can maximize the propagation of the horizontal stress. Of course, it is also relatively easy to achieve by chemical etching, and the production cost is relatively low. Specifically, the groove 72 is arranged in the direction of the second metal layer 7, and can completely block the propagation of the horizontal stress at the encapsulation and wiring area 71.
[0052] Further, the packaging wire region 71 is determined on the second metal layer 7, and the recess 72 is opened at a position adjacent to the packaging wire region 71 on the second metal layer 7, wherein the packaging wire region 71 has a first width, and the recess 72 is arranged at a position with a second width away from the packaging wire region 71, and the first width is greater than the second width. Specifically, after the packaging wire is formed, the packaging wire region 71 can form a similar arc-shaped surface as shown in Figure 2 The width of the arc-shaped surface can be regarded as the first width, and the second width refers to the width of the recess 72 in the horizontal direction. The second width of the recess 72 is smaller than the first width of the packaging wire region 71 because the recess 72 can achieve the effect of hindering the wave transmission of force as long as it exists, and the structural stability can be improved. Specifically, in one of the embodiments, the first width is set to 50um, and the second width is set to 10-20um. That is, the width of the recess 72 is less than half of the width of the packaging wire region 71, and has better stability.
[0053] Further, the number of recesses 72 is set to be multiple, and the multiple recesses 72 are arranged at intervals on the second metal layer 7. The specific number of recesses 72 can be determined according to the number of packaging wire regions 71. For example, one recess 72 can be arranged on each side of the packaging wire region 71, or one recess 72 can be arranged on one side.
[0054] Specifically, in Figure 1 and Figure 2 , the dark gray arrows in the structure can be regarded as a schematic of the direction of force transmission, and not the specific structure.
[0055] Please refer to Figures 4-9 , the following is a step-by-step description of a semiconductor device manufacturing method provided by an embodiment of the present specification:
[0056] As shown in Figure 4 , first, a planar base layer 1 is formed; then, as shown in Figure 5 , a source metal 2, a drain metal 3, and a gate metal 4 are formed at a predetermined position on the base layer 1; as shown in Figure 6 , a first dielectric layer is formed on the top surface of the source metal 2, the drain metal 3, and the gate metal 4, so that the source metal 2, the drain metal 3, and the gate metal 4 are covered in the top direction; as shown in Figure 7 , a first metal layer 5 is formed on the top surface of the first dielectric layer, and the first metal layer 5 is in ohmic contact with the corresponding source metal 2, drain metal 3, or gate metal 4; then, as shown in Figure 8 , a second dielectric layer is formed on the top surface of the first metal layer 5, so that the first metal layer 5 is covered in the top direction; as shown in Figure 9As shown, the second metal layer 7 is formed on the top surface of the second dielectric layer 6, and the second metal layer 7 is electrically connected with the corresponding first metal layer 5 through a metal via, and a packaging wire region 71 is determined, and a groove 72 is opened near the packaging wire region 71 on the second metal layer 7, and the groove 72 is used to block the stress transferred from the packaging wire region 71 in the process of packaging wire.
[0057] The above disclosed content is only the preferred feasible embodiment of the present application, and does not limit the patent application scope of the present application, so any equivalent technical change made by referring to the content of the present application and the drawings is included in the patent application scope of the present application.
[0058] The various embodiments in the specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to each other, and each embodiment mainly explains the difference from other embodiments.
[0059] Although the present application is described through the embodiments, those skilled in the art know that there are many modifications and changes of the present application without departing from the spirit of the present application, and it is expected that the attached embodiments include these modifications and changes without departing from the present application.
Claims
1. A method for fabricating a semiconductor device, characterized in that, The semiconductor device fabrication method includes: Forming the basal layer; Source metal, drain metal, and gate metal are formed on the top surface of the substrate layer; A first dielectric layer is formed on the top surface of the source metal, the drain metal, and the gate metal; A first metal layer is formed on the top surface of the first dielectric layer, and the first metal layer is electrically connected to the corresponding source metal, drain metal or gate metal ohmic contact. A second dielectric layer is formed on the top surface of the first metal layer; A second metal layer is formed on the top surface of the second dielectric layer, and the second metal layer is electrically connected to the corresponding metal via of the first metal layer; A packaging wire bonding area is defined, and a groove is formed in the second metal layer near the packaging wire bonding area. The groove is used to block the stress transmitted from the packaging wire bonding area during the packaging wire bonding process.
2. The semiconductor device fabrication method according to claim 1, characterized in that: The step "determine the packaging wire bonding area and create a groove in the second metal layer near the packaging wire bonding area" includes the steps of applying adhesive, developing, exposing, and etching in sequence.
3. The semiconductor device fabrication method according to claim 1, characterized in that: The groove extends in a direction perpendicular to the second metal layer.
4. The semiconductor device fabrication method according to claim 3, characterized in that: The groove is positioned to penetrate the second metal layer.
5. The semiconductor device fabrication method according to claim 1, characterized in that: In the step "determine the encapsulation wire bonding area and create a groove in the second metal layer near the encapsulation wire bonding area", the encapsulation wire bonding area has a first width, and the groove is located at a position far from the second width of the encapsulation wire bonding area, wherein the first width is greater than the second width.
6. The method for fabricating a semiconductor device according to claim 1, characterized in that: The first width is set to 50um, and the second width is set to 10~20um.
7. The method for fabricating a semiconductor device according to claim 1, characterized in that: The number of grooves is set to multiple, and the multiple grooves are spaced apart on the second metal layer.
8. A semiconductor device, characterized in that, The semiconductor device is fabricated using the semiconductor device fabrication method according to claim 1. The semiconductor device includes a bottom substrate layer, a source metal, a drain metal, and a gate metal formed above the substrate layer, a first dielectric layer formed above the source metal, drain metal, and gate metal, and a second metal layer formed above the first dielectric layer. A groove is provided on the second metal layer near the packaging wire bonding area.