Semiconductor packaging method, semiconductor assembly and electronic equipment

Abstract

The invention relates to a semiconductor packaging method, a semiconductor assembly and electronic equipment. The method comprises the following steps: providing at least one first welding structure; the first welding structure comprises a semiconductor device with a first alignment welding part and a first substrate with a second alignment welding part, and the first alignment welding part and the second alignment welding part are welded in an alignment manner; one of the first alignment welding part and the second alignment welding part is an alignment welding ball, and the other one is an alignment welding pad; and introducing a reducing gas between the semiconductor device and the first substrate, heating the alignment solder ball to a molten state, and cooling to obtain a second welding structure. Reducing gas is used as the soldering flux, so that the alignment solder balls are prevented from being oxidized in the heating process to change the tension characteristics of the alignment solder balls, the influence of the liquid soldering flux on the self-alignment precision is eliminated, the self-alignment force of the alignment solder balls in the molten state is fully utilized, the semiconductor device is further dragged to the target position, and the self-alignment precision of the semiconductor device is further improved through two times of self-alignment. And the self-alignment precision of the semiconductor device is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor packaging method, a semiconductor assembly and an electronic device. BACKGROUND

[0002] Chip self-alignment wafer-level fan-out packaging is to use a low-precision chip mounter to mount a semiconductor device on a substrate, and to use the self-alignment characteristics of solder melting to pull the semiconductor device from a mounting position to a target position, thereby effectively reducing the equipment investment cost of the chip recombination process. However, in the recombination process, internal gas expansion, liquid flux volatilization, activation and thermal decomposition, and other phenomena occur when the solder melts, which generate additional forces and affect the self-alignment of the semiconductor device. At the same time, the friction between the flux and the semiconductor device hinders the self-alignment movement of the semiconductor device, thereby reducing the self-alignment accuracy of the semiconductor device. SUMMARY

[0003] To solve the above technical problems, the present application provides a semiconductor packaging method, a semiconductor assembly and an electronic device.

[0004] The present application provides a semiconductor packaging method, comprising:

[0005] providing at least one first solder structure; the first solder structure comprises a semiconductor device with a first alignment solder part and a first substrate with a second alignment solder part, the first alignment solder part and the second alignment solder part are aligned and soldered; wherein one of the first alignment solder part and the second alignment solder part is an alignment solder ball, and the other is an alignment solder pad;

[0006] passing a reducing gas between the semiconductor device and the first substrate, and heating the alignment solder ball to a molten state and then cooling to obtain a second solder structure.

[0007] Optionally, before the reducing gas is passed between the semiconductor device and the first substrate, the semiconductor packaging method further comprises:

[0008] placing the first solder structure on a vacuum platform, and the semiconductor device is located on the side of the first substrate away from the vacuum platform;

[0009] wherein the direction of the vacuum platform pointing to the first solder structure is the same as the direction of gravity.

[0010] Optionally, passing a reducing gas between the semiconductor device and the first substrate, and heating the alignment solder ball to a molten state and then cooling to obtain a second solder structure, comprises:

[0011] A reducing gas is introduced between the semiconductor device and the first substrate, and the alignment solder ball is heated to a molten state;

[0012] A planar structure is provided on a side of the semiconductor device facing away from the first substrate;

[0013] The planar structure is used to apply pressure to the semiconductor device while the alignment solder ball in the molten state is cooled to obtain the second solder structure.

[0014] Optionally, the semiconductor packaging method further comprises:

[0015] A second substrate is provided, and the second solder structure is fixed to the second substrate, with the semiconductor device facing the second substrate;

[0016] The first substrate is removed;

[0017] A plastic encapsulation layer is formed, covering the semiconductor device and a surface of the second substrate not occupied by the semiconductor device;

[0018] The second substrate is removed.

[0019] Optionally, a side of the second substrate comprises an adhesive layer;

[0020] The fixing of the second solder structure to the second substrate comprises:

[0021] The semiconductor device faces the adhesive layer, and the second solder structure is fixed to the second substrate through the adhesive layer;

[0022] The removal of the second substrate comprises:

[0023] The second substrate and the adhesive layer are removed by heating or light irradiation.

[0024] Optionally, the first alignment solder part is located on a passive side of the semiconductor device; the semiconductor packaging method further comprises:

[0025] The plastic encapsulation layer is thinned;

[0026] A connection device is formed on an active side of the semiconductor device.

[0027] Optionally, the active side of the semiconductor device comprises a connection pad and a connection bump, the connection bump is located on a side of the connection pad facing away from the semiconductor device, and the first alignment solder part is located on a side of the connection bump facing away from the connection pad; the semiconductor packaging method further comprises:

[0028] The plastic sealing layer is thinned until the connecting bump is exposed.

[0029] Optionally, the reducing gas comprises at least one of formic acid gas, acetic acid gas and hydrogen.

[0030] The application further provides a semiconductor assembly packaged based on any of the semiconductor packaging methods.

[0031] The application further provides an electronic device comprising the semiconductor assembly.

[0032] Compared with the prior art, the technical scheme provided by the application has the following advantages:

[0033] The semiconductor packaging method, semiconductor assembly and electronic device provided by the application, the semiconductor packaging method comprises the following steps: providing at least one first solder structure; the first solder structure comprises a semiconductor device with a first alignment solder part and a first substrate with a second alignment solder part, the first alignment solder part and the second alignment solder part are aligned and soldered; wherein one of the first alignment solder part and the second alignment solder part is an alignment solder ball, and the other is an alignment solder pad; the alignment solder ball is heated to a molten state and then cooled in an atmosphere containing a reducing gas to obtain a second solder structure. Thus, the alignment solder ball of the first solder structure which has been preliminarily self-aligned is heated to a molten state in an atmosphere containing a reducing gas, and the reducing gas is used as a flux in this process, which not only prevents the alignment solder ball from being oxidized and changing its tension characteristics during the heating process, but also eliminates the influence of the liquid flux on the self-alignment accuracy, fully utilizes the self-alignment force of the alignment solder ball in the molten state, and further drags the semiconductor device to the target position, thereby improving the self-alignment accuracy of the semiconductor device through twice self-alignment. BRIEF DESCRIPTION OF DRAWINGS

[0034] The accompanying drawings, which are incorporated into and form a part of the specification, illustrate one embodiment consistent with the application and, together with the description, serve to explain the principles of the application.

[0035] In order to more clearly illustrate the technical scheme in the embodiments of the application or the prior art, the accompanying drawings required to be used in the embodiments or prior art description will be briefly introduced. Obviously, for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0036] Figure 1 A structure diagram of self-alignment of a semiconductor device in a related technology is provided for the embodiments of the application.

[0037] Figure 2 A flowchart of a semiconductor packaging method is provided for the embodiments of the application.

[0038] Figures 3-4 This is a schematic diagram of a semiconductor packaging method provided in an embodiment of this application;

[0039] Figure 5 A schematic flowchart illustrating another semiconductor packaging method provided in an embodiment of this application;

[0040] Figures 6-7 This is a schematic diagram of another semiconductor packaging method provided in an embodiment of this application;

[0041] Figure 8 for Figure 2 A detailed flowchart of S120 in the semiconductor packaging method shown;

[0042] Figures 9-10 To and Figure 8 The diagram shows the structure corresponding to the semiconductor packaging method shown.

[0043] Figure 11 A schematic flowchart illustrating another semiconductor packaging method provided in this application embodiment;

[0044] Figures 12-16 To and Figure 11 The diagram shows a structural schematic corresponding to a semiconductor packaging method.

[0045] Figures 17-21 To and Figure 11 The diagram shows another structural schematic corresponding to the semiconductor packaging method shown.

[0046] Among them, 1' Semiconductor device; 2' Substrate; 3' Vacuum platform; 4' Liquid flux; 5' Alignment solder ball; 6' Bubble; 1. Semiconductor device; 11. Active surface; 12. Passive surface; 2. First substrate; 3. Vacuum platform; 4. Alignment pad; 5. Alignment solder ball; 6. Planar structure; 7. Second substrate; 71. Adhesive layer; 8. Molding layer. Detailed Implementation

[0047] To better understand the above-mentioned objectives, features, and advantages of this application, the solution of this application will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be combined with each other.

[0048] Many specific details are set forth in the following description in order to provide a full understanding of this application, but this application may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some embodiments of this application, and not all embodiments.

[0049] In related technologies, such as Figure 1As shown, the semiconductor device 1' is attached to the substrate 2' by surface mounting process, the semiconductor device 1' is connected with the substrate 2' through the aligned solder ball 5' and the aligned solder pad, and the liquid flux 4' is filled between the semiconductor device 1' and the substrate 2'. In the recombination process, the liquid flux 4' generates the bubble 6' in the preheating and activation stage, the breaking of the bubble 6' generates unpredictable thrust, and the semi-solid liquid flux 4' has large viscosity, the friction between the liquid flux 4' and the semiconductor device 1' limits the movement of the semiconductor device 1', and these factors cause the self-alignment accuracy of the semiconductor device 1' to decrease.

[0050] To solve the above technical problems, the semiconductor packaging method, the semiconductor assembly and the electronic device provided by the embodiments of the present application include: providing at least one first welding structure; the first welding structure includes a semiconductor device with a first alignment welding part and a first substrate with a second alignment welding part, the first alignment welding part and the second alignment welding part are aligned and welded; one of the first alignment welding part and the second alignment welding part is an alignment solder ball, and the other is an alignment solder pad; reducing gas is introduced between the semiconductor device and the first substrate, and the alignment solder ball is heated to a molten state and then cooled to obtain a second welding structure. Thus, in an atmosphere containing reducing gas, the alignment solder ball of the first welding structure which has been preliminarily self-aligned is heated to a molten state, and in this process, the reducing gas is used as a flux, which prevents the alignment solder ball from being oxidized and changing its tension characteristics during the heating process, eliminates the influence of the liquid flux on the self-alignment accuracy, fully utilizes the self-alignment force of the alignment solder ball in the molten state to further drag the semiconductor device to the target position, and improves the self-alignment accuracy of the semiconductor device through twice self-alignment.

[0051] The semiconductor packaging method, the semiconductor assembly and the electronic device provided by the embodiments of the present application will be described exemplarily in combination with the drawings.

[0052] Figure 2 A flowchart of a semiconductor packaging method provided by the embodiments of the present application is shown.

[0053] Referring to Figure 2 As shown, the semiconductor packaging method includes the following steps:

[0054] S110, providing at least one first welding structure.

[0055] In combination with Figure 3The first welding structure includes a semiconductor device 1 having a first alignment welding portion and a first substrate 2 having a second alignment welding portion, wherein the first alignment welding portion and the second alignment welding portion are aligned and welded; wherein, one of the first alignment welding portion and the second alignment welding portion is an alignment solder ball 5, and the other is an alignment pad 4. If the first alignment welding portion of the semiconductor device 1 is an alignment solder ball 5, then the second alignment welding portion of the first substrate 2 is an alignment pad 4; if the first alignment welding portion of the semiconductor device 1 is an alignment pad 4, then the second alignment welding portion of the first substrate 2 is an alignment solder ball 5.

[0056] Semiconductor device 1 includes, but is not limited to, wafers, dies, and chips, and also includes all types of semiconductor devices known to those skilled in the art, which are not limited herein. Semiconductor device 1 includes a passive surface and an active surface disposed opposite to each other. The first alignment bonding portion may be located on the passive surface and is used only for self-alignment of semiconductor device 1; the first alignment bonding portion may also be located on the active surface and has both self-alignment and electrical connection functions.

[0057] The embodiments of this application do not limit the type of the first substrate 2, and all types of carriers known to those skilled in the art can be used, such as wafer carriers, silicon-based carriers, glass carriers, or metal carriers.

[0058] S120. A reducing gas is introduced between the semiconductor device and the first substrate, and the alignment solder balls are heated to a molten state and then cooled to obtain a second solder structure.

[0059] The reducing gas has strong reducing properties. By introducing the reducing gas between the semiconductor device 1 and the first substrate 2, the alignment solder balls 5 are heated, remelted, and cooled in the atmosphere of the reducing gas, preventing the alignment solder balls 5 from being oxidized during the remelting process and thus changing their tension characteristics. The reducing gas includes at least one of formic acid gas, acetic acid gas, and hydrogen gas. In other embodiments, nitrogen gas can also be introduced between the semiconductor device 1 and the first substrate 2. Utilizing the inertness of nitrogen, nitrogen is used to remove oxygen and protect the alignment solder balls 5 from oxidation. All processes known to those skilled in the art can be used to melt the alignment solder balls, such as reflow soldering, and are not limited here.

[0060] In this step, combined Figure 4 The first welded structure is placed in a reducing gas atmosphere, and the alignment solder balls 5 are remelted. Since there is no liquid flux present, the influence of liquid flux on self-alignment accuracy is eliminated. Under the action of surface tension, the molten alignment solder balls 5 further drag the semiconductor device 1 to the target position. Through two self-alignments, the alignment accuracy of the semiconductor device 1 is improved. The first welded structure after the above operation is cooled to obtain the second welded structure.

[0061] The semiconductor packaging method provided by the embodiments of the present application comprises the following steps: providing at least one first solder structure; the first solder structure comprises a semiconductor device with a first alignment solder part and a first substrate with a second alignment solder part, the first alignment solder part is aligned with the second alignment solder part; one of the first alignment solder part and the second alignment solder part is an alignment solder ball, and the other is an alignment solder pad; reducing gas is introduced between the semiconductor device and the first substrate, and the alignment solder ball is heated to a molten state and then cooled to obtain a second solder structure. Thus, in the atmosphere containing reducing gas, the alignment solder ball of the first solder structure which has been preliminarily self-aligned is heated to a molten state, and in this process, the reducing gas is used as a flux, which prevents the alignment solder ball from being oxidized in the heating process to change its tension characteristics, eliminates the influence of the liquid flux on the self-alignment accuracy, and fully utilizes the self-alignment force of the alignment solder ball in the molten state to further pull the semiconductor device to the target position, thereby improving the self-alignment accuracy of the semiconductor device through twice self-alignment.

[0062] In some embodiments, as shown in FIG. 1, before the step of "providing at least one first solder structure", the semiconductor packaging method further comprises the following steps: Figure 5

[0063] S210, providing a semiconductor device with a first alignment solder part and a first substrate with a second alignment solder part.

[0064] S220, coating a liquid flux on the surfaces of the first alignment solder part and the second alignment solder part.

[0065] The liquid flux is selected from all types of fluxes known to those skilled in the art, such as inorganic fluxes, organic fluxes or resin fluxes, which are not limited herein. The coating method of the flux is not limited in the present application, and all coating methods known to those skilled in the art can be used, such as spraying, brushing or dipping.

[0066] S230, substantially aligning the first alignment solder part with the second alignment solder part, and welding the first alignment solder part with the second alignment solder part by using a reflow soldering process.

[0067] ​In this step, the first and second alignment soldering parts are basically aligned, meaning they are in contact with each other but not precisely aligned in the direction perpendicular to the plane of the first substrate 2. During the soldering process, one of the first and second alignment soldering parts, acting as alignment solder balls, melts or partially melts and wets the other, acting as alignment pads. Based on the principle of minimum surface energy, the molten or partially molten alignment solder balls tend to deform and move to bring the first and second alignment soldering parts closer to alignment, thereby moving the lighter semiconductor device 1 to the target position. After the alignment solder balls cool, the semiconductor device 1 is fixed in the target position, achieving high-strength mechanical fixation of the semiconductor device 1 (up to the kilogram-force level), effectively improving the yield of subsequent processes. Since the position of the second alignment soldering part on the first substrate 2 is fixed, by controlling the relative position of the semiconductor device 1 and the second alignment soldering part, the semiconductor device 1 is more accurately fixed in the target position on the first substrate 2.

[0068] The welded structure obtained in this step is as follows: Figure 1 As shown, due to the use of flux, the technical problems described in the background section are unavoidable.

[0069] S240. Remove the flux to obtain the first welded structure.

[0070] This step uses all methods known to those skilled in the art to remove the flux filling the space between the semiconductor device and the first substrate, such as water washing or acid washing, which are not limited herein.

[0071] The first welded structure obtained in this step is as follows: Figure 3 As shown.

[0072] S250, Provide at least one first welded structure.

[0073] S260. A reducing gas is introduced between the semiconductor device and the first substrate, and the alignment solder balls are heated to a molten state and then cooled to obtain a second solder structure.

[0074] In this embodiment, steps S250 to S260 are the same as steps S110 to S120, and can be found in the explanation of steps S110 to S120, which will not be repeated here.

[0075] In some embodiments, prior to "introducing a reducing gas between the semiconductor device and the first substrate", the semiconductor packaging method further includes the following steps:

[0076] The first welding structure is placed on a vacuum platform, and the semiconductor device is located on the side of the first substrate away from the vacuum platform;

[0077] Among them, combined Figure 6 orFigure 7 The direction in which the vacuum platform 3 points to the first solder structure is the same as the direction of gravity G.

[0078] In this embodiment, the force analysis of the molten self-alignment solder ball is carried out by a mechanical model, which is as follows:

[0079] F = 2πγDsinθ(x / h);

[0080] N = mg;

[0081] F 张力 = γ2πd;

[0082] Wherein, F represents the self-alignment force; D represents the diameter of the self-alignment solder ball 5; θ represents the contact angle; γ represents the surface tension coefficient of the self-alignment solder ball 5, which is between 0.4-0.5 N / m; h represents the distance between the semiconductor device 1 and the first substrate 2; x represents the offset; d represents the diameter of the self-alignment pad 4; N represents the gravity of the self-alignment solder ball 5, and m represents the weight of the self-alignment solder ball 5; g represents the gravity coefficient; F 张力 represents the surface tension.

[0083] The self-alignment force F is positively correlated with the offset x, and the smaller the offset x, that is, the closer the offset position to the center of gravity of the self-alignment solder ball 5, the smaller the self-alignment force F. The surface tension F 张力 makes the self-alignment solder ball 5 tend to be spherical, and the surface tension F 张力 is related to the radius of curvature. The self-alignment solder ball is affected by the gravity N, which causes the shape of the self-alignment solder ball 5 to deviate from the spherical shape. The contact angle θ of the self-alignment solder ball 5 with the first substrate 2 (or the semiconductor device 1) is determined by the surface tension F 张力 and wettability.

[0084] When the semiconductor device 1 is located above the first substrate 2, the horizontal component F g,h of the gravity is opposite to the direction of the surface tension F 张力 , and the force acting on the self-alignment solder ball 5 is as follows:

[0085] F = F 张力 - F g,h = γxsinθ - F g,h ;

[0086] When the semiconductor device 1 is located below the first substrate 2, the horizontal component F g,h of the gravity is consistent with the direction of the surface tension F 张力 , and the force acting on the self-alignment solder ball 5 is as follows:

[0087] F = F 张力 - F g,h = γxsinθ + F g,h ;

[0088] Thus, when the semiconductor device 1 is located below the first substrate 2, the alignment solder ball 5 has a higher self-alignment force F, which promotes the alignment solder ball to return to the center position.

[0089] In this embodiment, as shown in Figure 6 , the first solder structure is inverted by the vacuum platform 3, i.e., the first solder structure is located below the vacuum platform 3, and the semiconductor device 1 is located below the first substrate 2; then, as shown in Figure 7 , the alignment solder ball 5 is heated to a molten state, and the self-gravity of the semiconductor device 1 enhances the wettability of the alignment solder ball, reduces the contact angle θ, and increases the surface tension F 张力 In the horizontal direction, the horizontal component of the gravity of the alignment solder ball 5 is consistent with the direction of the surface tension F 张力 , and under the joint action of the gravity of the semiconductor device 1 and the surface tension of the alignment solder ball, the alignment solder ball is promoted to return to the center position, and the semiconductor device 1 is dragged to the target position.

[0090] In some embodiments, as shown in Figure 8 , the step of "after the reducing gas is introduced between the semiconductor device and the first substrate, and the alignment solder ball is heated to a molten state and then cooled, a second solder structure is obtained" includes the following steps:

[0091] S321, a reducing gas is introduced between the semiconductor device and the first substrate, and the alignment solder ball is heated to a molten state.

[0092] This step can refer to the explanation of the reducing gas and the heating process at S120, which will not be repeated here.

[0093] S322, a planar structure is provided, and the planar structure is located on the side of the semiconductor device away from the first substrate.

[0094] In this step, as shown in Figure 9 , a planar structure 6 is provided, and the planar structure 6 is located on the side of the semiconductor device 1 away from the first substrate 2; as shown in Figure 10 , after the alignment solder ball in the molten state completes the second self-alignment, the planar structure 6 contacts the semiconductor device 1. The side surface of the planar structure 6 facing the semiconductor device has a higher flatness.

[0095] S323, a pressure is applied to the semiconductor device by the planar structure, and the alignment solder ball in the molten state is cooled to obtain a second solder structure.

[0096] In this step, as shown in Figure 10 ​As shown, by applying pressure to the semiconductor device 1 through the planar structure 6, the semiconductor device 1 is pressed towards the first substrate 2, while the alignment solder balls are cooled. By controlling the semiconductor device 1 at the same height through the planar structure 6, the height difference of the semiconductor device 1 due to process error of the previous process is reduced, which is more conducive to the smooth and effective performance of the subsequent process.

[0097] In some embodiments, as shown, the semiconductor packaging method comprises the following steps: Figure 11

[0098] S410, providing at least one first solder structure.

[0099] S420, passing a reducing gas between the semiconductor device and the first substrate, and heating the alignment solder balls to a molten state and then cooling to obtain a second solder structure.

[0100] In this embodiment, steps S410-S420 are the same as steps S110-S120, and can be referred to the explanation of steps S110-S120, which will not be repeated here.

[0101] S430, providing a second substrate, fixing the second solder structure on the second substrate, and the semiconductor device faces the second substrate.

[0102] As shown in Figure 12 or Figure 17 The side of the semiconductor device 1 of the second solder structure faces the second substrate 7, and the second solder structure is fixed on the second substrate 7.

[0103] S440, removing the first substrate.

[0104] This step can remove the first substrate in all ways known to those skilled in the art, such as heating, etching or grinding, which is not limited here.

[0105] Exemplarily, as shown in Figure 13 or Figure 18 The first substrate 2 is disconnected from the alignment solder balls 5 by heating, so that the first substrate 2 is removed.

[0106] S450, forming a plastic encapsulation layer; the plastic encapsulation layer covers the semiconductor device and the surface of the second substrate not occupied by the semiconductor device.

[0107] As shown in Figure 14 or Figure 19 ​As shown, the plastic encapsulation can be performed by injection molding, compression molding or printing, and the plastic encapsulation layer 8 is made of a molding compound of resin material (e.g. epoxy resin). The plastic encapsulation layer 8 is on the same side of the second substrate 7 as the semiconductor device 1, and covers the upper surface and side surface of the semiconductor device 1, and also covers the surface of the second substrate 7 not occupied by the semiconductor device 1.

[0108] S460, removing the second substrate.

[0109] As shown in Figure 15 or Figure 20 The second substrate 7 can be removed in any manner known to those skilled in the art, such as by heating, ultraviolet light, laser, etching or grinding, and is not limited herein.

[0110] In some embodiments, as shown in Figure 12 or Figure 17 One side of the second substrate 7 includes an adhesive layer 71; and the step of "fixing the second solder structure to the second substrate" includes the following steps:

[0111] fixing the semiconductor device towards the adhesive layer, and fixing the second solder structure to the second substrate through the adhesive layer;

[0112] The adhesive layer 71 has adhesion, and can stably fix the second solder structure to the second substrate 7. In some embodiments, the adhesive layer 71 includes a temporary bonding layer, such as a thermal adhesive or an optical adhesive.

[0113] The step of "removing the second substrate" includes the following steps:

[0114] The second substrate and the adhesive layer are removed by heating or light.

[0115] In this step, if the adhesive layer 71 includes a thermal adhesive, heating is used; if the adhesive layer 71 includes an optical adhesive, ultraviolet light or laser light is used to weaken the adhesion of the adhesive layer 71, so as to remove the second substrate 7 and the adhesive layer 71. This removal method does not damage the structure of the second substrate 7, and the second substrate 7 can be reused, which is conducive to reducing the packaging cost.

[0116] In some embodiments, as shown in Figures 12-16 The first alignment solder portion is located on the passive surface 12 of the semiconductor device 1; and the semiconductor packaging method further includes the following steps:

[0117] Thinning the plastic encapsulation layer;

[0118] Forming a connector on the active surface of the semiconductor device.

[0119] In this embodiment, as shown in Figure 16As shown, the plastic encapsulation layer 8 is thinned by grinding from the side of the active surface 11 of the semiconductor device 1, which is conducive to reducing the thickness of the package. Then, a connection device is formed on the side of the active surface 11 of the semiconductor device 1, and the connection device is used to electrically connect external devices. The connection device includes at least one of a redistribution layer, a connection pad, a connection bump, and a connection solder ball.

[0120] In some embodiments, as shown in Figures 17-21 As shown, the active surface 11 of the semiconductor device 1 includes a connection pad and a connection bump (not shown in the figure), the connection bump is located on the side of the connection pad away from the semiconductor device 1, and the first alignment solder joint is located on the side of the connection bump away from the connection pad; the semiconductor packaging method further includes the following steps:

[0121] The plastic encapsulation layer is thinned until the connection bump is exposed.

[0122] In some embodiments, as shown in

[0123] In some embodiments, as shown in Figure 21 As shown, the plastic encapsulation layer 8 is thinned by grinding from the side of the active surface 11 of the semiconductor device 1, which is conducive to reducing the thickness of the package. Then, a connection device is formed on the side of the active surface 11 of the semiconductor device 1, and the connection device is used to electrically connect external devices. The connection device includes at least one of a redistribution layer, a connection pad, a connection bump, and a connection solder ball.

[0124] The semiconductor packaging method provided by the embodiments of the present application first solves the interference of liquid flux on self-alignment in the process by effectively combining the reducing gas soldering technology and the chip self-alignment technology; secondly, the self-alignment of the alignment solder ball is realized by using the more advantageous mechanical model formed by the gravitational force of the semiconductor device and the surface tension; finally, the two technical requirements of self-alignment and height calibration are effectively optimized by combining the planar structure to calibrate the height of the semiconductor device, which improves the stability and reliability of the method, provides a feasible scheme for the low-precision placement machine to complete the chip reorganization, greatly reduces the cost of advanced packaging placement machine equipment, thereby greatly reducing the investment cost of advanced packaging, and is conducive to the upgrading of traditional packaging to advanced packaging.

[0125] On the basis of the above-mentioned embodiments, the application further provides a semiconductor assembly packaged based on any of the above-mentioned semiconductor packaging methods, which has the corresponding beneficial effects. To avoid repeated description, details are not described here.

[0126] On the basis of the above-mentioned embodiments, the application further provides an electronic device comprising the above-mentioned semiconductor assembly, which has the corresponding beneficial effects. To avoid repeated description, details are not described here.

[0127] It should be noted that, in this document, relational terms such as“first” and“second”, and the like, are used solely to distinguish one entity or action from another entity or action, without necessarily requiring or implying any actual relationship or order between such entities or actions. Moreover, the terms“comprises”,“comprising”, or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by“comprises a...” does not, without more constraints, foreclose the existence of additional identical elements in the process, method, article, or apparatus that comprises the stated elements.

[0128] The above description is merely that of specific embodiments of the application, making it possible for those skilled in the art to understand or implement the application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other embodiments without departing from the spirit or scope of the application. Therefore, the application is not intended to be limited to the embodiments described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A semiconductor packaging method, characterized in that, include: Provide at least one first welded structure; The first welding structure includes a semiconductor device having a first alignment welding portion and a first substrate having a second alignment welding portion, wherein the first alignment welding portion and the second alignment welding portion are aligned and welded; wherein, one of the first alignment welding portion and the second alignment welding portion is an alignment solder ball and the other is an alignment solder pad; A reducing gas is introduced between the semiconductor device and the first substrate, and the alignment solder balls are heated to a molten state and then cooled to obtain a second solder structure.

2. The semiconductor packaging method according to claim 1, characterized in that, Before introducing a reducing gas between the semiconductor device and the first substrate, the semiconductor packaging method further includes: The first welding structure is placed on a vacuum platform, and the semiconductor device is located on the side of the first substrate away from the vacuum platform; The direction in which the vacuum platform points toward the first welded structure is the same as the direction of gravity.

3. The semiconductor packaging method according to claim 2, characterized in that, The process involves introducing a reducing gas between the semiconductor device and the first substrate, heating the alignment solder balls to a molten state, and then cooling them to obtain a second solder structure, comprising: A reducing gas is introduced between the semiconductor device and the first substrate, and the alignment solder balls are heated to a molten state. A planar structure is provided, the planar structure being located on the side of the semiconductor device opposite to the first substrate; Pressure is applied to the semiconductor device using the planar structure, while the molten alignment solder balls are cooled to obtain the second solder structure.

4. The semiconductor packaging method according to any one of claims 1-3, characterized in that, Also includes: A second substrate is provided, and the second welding structure is fixed to the second substrate, with the semiconductor device facing the second substrate; Remove the first substrate; Forming a molding seal; The molding layer covers the semiconductor device and the surface of the second substrate not occupied by the semiconductor device; Remove the second substrate.

5. The semiconductor packaging method according to claim 4, characterized in that, One side of the second substrate includes an adhesive layer; The step of fixing the second welding structure to the second substrate includes: The semiconductor device is oriented toward the adhesive layer, and the second welding structure is fixed to the second substrate through the adhesive layer; The removal of the second substrate includes: The second substrate and the adhesive layer are removed by heating or light.

6. The semiconductor packaging method according to claim 4, characterized in that, The first alignment and welding portion is located on the passive surface of the semiconductor device; The semiconductor packaging method further includes: The molding layer is thinned. A connection device is formed on the active surface of the semiconductor device.

7. The semiconductor packaging method according to claim 4, characterized in that, The active surface of the semiconductor device includes a connection pad and a connection bump, the connection bump being located on the side of the connection pad away from the semiconductor device, and the first alignment soldering portion being located on the side of the connection bump away from the connection pad. The semiconductor packaging method further includes: The molding layer is thinned until the connecting bumps are exposed.

8. The semiconductor packaging method according to claim 1, characterized in that, The reducing gas includes at least one of formic acid gas, acetic acid gas, and hydrogen gas.

9. A semiconductor component, characterized in that, The semiconductor component is packaged based on the semiconductor packaging method according to any one of claims 1 to 8.

10. An electronic device, characterized in that, include: The semiconductor component as described in claim 9.

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