Crystal rapid oscillation starting circuit based on dual-mode current control

Abstract

The invention provides a crystal rapid oscillation starting circuit based on dual-mode current control, and relates to the technical field of integrated circuits, working stages of the crystal rapid oscillation starting circuit sequentially comprise an oscillation starting stage and a maintaining stage, and the crystal rapid oscillation starting circuit comprises a bias current source module which is used for responding to an enable signal to work in the oscillation starting stage, the maximum bias current is output according to the first bias control signal and the power supply voltage signal; in the maintaining stage, a second bias control signal is received, maintaining bias current is output according to the second bias control signal and the power supply voltage signal, and the maintaining bias current is smaller than the maximum bias current; the transconductance amplification module is connected with the output end of the bias current source module; and the unity gain amplification module and the transconductance amplification module form a negative feedback structure. According to the crystal rapid oscillation starting circuit, low power consumption can be realized while oscillation starting of the crystal oscillator within the specified time is ensured.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a crystal fast start-up circuit based on dual-mode current control. Background Technology

[0002] With the booming development of emerging application areas such as the Internet of Things and portable medical devices, clock chips, as the core module providing time references, directly affect the battery life and operational reliability of devices through their power consumption performance. Current typical application scenarios demand nanoamp-level current consumption from real-time clocks. Among various types of clock chips, crystal oscillators stand out due to their highly stable oscillation frequency, which is less affected by external environmental factors (such as temperature and humidity). Furthermore, their frequency accuracy can typically reach the ppm level or even higher, making them an ideal choice for high-precision clock sources.

[0003] In crystal oscillator applications, the power consumption of traditional crystal oscillator circuits is insufficient for applications highly sensitive to power consumption, such as the Internet of Things (IoT), wearable devices, and portable medical devices. For example, in remote sensor nodes, to ensure stable operation over extended periods and enable real-time data acquisition and transmission, the crystal oscillator circuit must be optimized for low power consumption. However, current traditional oscillator circuits suffer from incompatibility between rapid crystal oscillation startup and stable oscillation maintenance with low power consumption, as well as excessively large circuit area. Summary of the Invention

[0004] In view of this, this application proposes a crystal fast start-up circuit based on dual-mode current control.

[0005] The technical solution of this application is implemented as follows: a crystal fast oscillation circuit based on dual-mode current control, wherein the working stages of the crystal fast oscillation circuit sequentially include an oscillation stage and a maintenance stage; the crystal fast oscillation circuit includes: A bias current source module is configured to operate in response to an enable signal during the oscillation start-up phase, and output a maximum bias current based on a first bias control signal and a power supply voltage signal; during the sustaining phase, it receives a second bias control signal and outputs a sustaining bias current based on the second bias control signal and the power supply voltage signal, wherein the sustaining bias current is less than the maximum bias current. A transconductance amplification module, connected to the output terminal of the bias current source module, is used to provide an equivalent oscillation negative resistance value based on the maximum bias current during the oscillation start-up phase; and to provide an equivalent maintenance negative resistance value based on the maintenance bias current during the maintenance phase; wherein the equivalent maintenance negative resistance value is less than the equivalent oscillation negative resistance value. A unity-gain amplifier module, which together with the transconductance amplifier module form a negative feedback structure, is used to respond to the enable signal to operate such that the output voltage signal of the transconductance amplifier module is equal to the output voltage signal of the unity-gain amplifier module after oscillation is completed.

[0006] In one embodiment, the bias current source module includes: a reference unit and a plurality of current mirror units; The reference unit is used to operate in response to the enable signal and provides a uniform gate bias voltage to the mirror transistors of each current mirror unit based on the reference current source. During the oscillation start-up phase, each current mirror unit turns on in response to the corresponding first bias control signal and outputs a bias current based on the received power supply voltage signal, so that the bias current source module outputs the maximum bias current. During the maintenance phase, some of the current mirror units turn on in response to the corresponding second bias control signal, while the remaining current mirror units turn off in response to the corresponding second bias control signal, so that the bias current source module outputs the maintenance bias current.

[0007] In one embodiment, the reference unit includes: a first MOS transistor and a second MOS transistor; The first terminal of the first MOS transistor is used to receive the power supply voltage signal, the gate of the first MOS transistor is used to receive the enable signal, and the second terminal of the first MOS transistor is connected to the first terminal of the second MOS transistor. The second terminal of the second MOS transistor is connected to the reference current source, and the gate of the second MOS transistor is connected to the second terminal of the second MOS transistor and the gate of the mirror transistor of each current mirror unit.

[0008] In one embodiment, the current mirror unit includes: a control transistor and a mirror transistor; The first terminal of the control transistor is used to receive the power supply voltage signal, the gate of the control transistor is used to receive the bias control signal, and the second terminal of the control transistor is connected to the first terminal of the mirror transistor. The bias control signal is the first bias control signal during the oscillation stage and the bias control signal is the second bias control signal during the maintenance stage. The second electrode of the mirror transistor is connected to the transconductance amplification module, and the gate of the mirror transistor is used to receive the gate bias voltage provided by the reference unit.

[0009] In one embodiment, the number of current mirror units is four, namely a first current mirror unit, a second current mirror unit, a third current mirror unit, and a fourth current mirror unit; The ratio of the dimensions of the mirror tubes in the first current mirror unit, the second current mirror unit, the third current mirror unit, and the fourth current mirror unit is 8:4:2:1.

[0010] In one embodiment, during the maintenance phase, the first current mirror unit, the second current mirror unit, and the third current mirror unit are disconnected sequentially.

[0011] In one embodiment, the transconductance amplification module includes: a first PMOS transistor and a first NMOS transistor; The first terminal of the first PMOS transistor is connected to the output terminal of the bias current source module, the gate of the first PMOS transistor is connected to the output terminal of the unity gain amplifier module, and the second terminal of the first PMOS transistor is connected to the unity gain amplifier module and serves as the output terminal of the crystal fast start-up circuit. The first terminal of the first NMOS transistor is connected to the second terminal of the first PMOS transistor, the gate of the first NMOS transistor is connected to the gate of the first PMOS transistor, and the second terminal of the first NMOS transistor is grounded.

[0012] In one embodiment, the unity-gain amplifier module includes: an enable control circuit and a unity-gain amplifier circuit; The enable control circuit is used to control the operating state of the unity-gain amplifier circuit in response to the enable signal; The unity-gain amplifier circuit and the transconductance amplifier module form a negative feedback structure. The unity-gain amplifier circuit is used to make the output voltage signal of the transconductance amplifier module equal to the output voltage of the unity-gain amplifier module through the negative feedback mechanism.

[0013] In one embodiment, the enable control circuit includes: a second PMOS transistor, a third PMOS transistor, a second NMOS transistor, and a third NMOS transistor; The first terminal of the second PMOS transistor is used to receive the power supply voltage signal, and the second terminal of the second PMOS transistor is connected to the gate of the third PMOS transistor, the first terminal of the second NMOS transistor, and the gate of the third NMOS transistor, respectively. The gate of the second PMOS transistor is used to receive the enable signal. The first terminal of the third PMOS transistor is used to receive the power supply voltage signal, and the second terminal of the third PMOS transistor is connected to the first terminal of the third NMOS transistor and the unity gain amplifier circuit, respectively. The second terminal of the second NMOS transistor is grounded, and the gate of the second NMOS transistor is used to receive the enable signal; The second terminal of the third NMOS transistor is connected to the unity-gain amplifier circuit.

[0014] In one embodiment, the unity-gain amplifier circuit includes: a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor; The first terminal of the fourth PMOS transistor is used to receive the power supply voltage signal, the second terminal of the fourth PMOS transistor is connected to the first terminal of the fifth PMOS transistor, and the gate of the fourth PMOS transistor is used to receive the enable signal. The second terminal of the fifth PMOS transistor is connected to the first terminal of the sixth PMOS transistor and the first terminal of the seventh PMOS transistor, respectively, and the gate of the fifth PMOS transistor is connected to the reference current source. The second terminal of the sixth PMOS transistor is connected to the second terminal of the third NMOS transistor and the first terminal of the fourth NMOS transistor, respectively, and is connected to the transconductance amplification module as the output terminal of the unity-gain amplification module. The gate of the sixth PMOS transistor is connected to the second terminal of the third PMOS transistor. The second terminal of the seventh PMOS transistor is connected to the first terminal of the fifth NMOS transistor, and the gate of the seventh PMOS transistor is connected to the output terminal of the transconductance amplifier. The second terminal of the fourth NMOS transistor is grounded, and the gate of the fourth NMOS transistor is connected to the first terminal of the fourth NMOS transistor and the gate of the fifth NMOS transistor, respectively. The second terminal of the fifth NMOS transistor is grounded.

[0015] The crystal fast start-up circuit based on dual-mode current control proposed in this application has the following advantages over related technologies: 1. The crystal fast start-up circuit of this application, during the start-up phase, outputs a maximum bias current to the transconductance amplification module through the bias current source module, enabling the transconductance amplification module to provide an equivalent negative resistance value for start-up based on the maximum bias current, thus achieving rapid start-up. During the sustaining phase, the bias current source module outputs a sustaining bias current to the transconductance amplification module, enabling the transconductance amplification module to provide an equivalent negative sustaining resistance value based on the sustaining bias current. Since the sustaining bias current is less than the maximum bias current, stable oscillation is maintained with a lower current during the sustaining phase, thereby reducing power consumption. Therefore, the crystal fast start-up circuit of this application can achieve low power consumption while ensuring that the crystal oscillator starts oscillating within a specified time.

[0016] 2. A negative feedback structure is formed by combining a unity-gain amplifier module and a transconductance amplifier module. The unity-gain amplifier module operates in response to the enable signal, ensuring that the output voltage signals of the transconductance amplifier module and the unity-gain amplifier module are equal after oscillation begins. This replaces the traditional bias resistor with a unity-gain amplifier module, avoiding the effects of resistor temperature drift and providing a more precise bias for the transconductance amplifier module. Furthermore, it significantly reduces the area of ​​the oscillation circuit compared to traditional bias resistors. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of a crystal fast start-up circuit based on dual-mode current control in one embodiment of this application; Figure 2 This is a schematic diagram comparing the maximum bias current and the sustaining bias current in one embodiment of this application; Figure 3 This is a schematic diagram of a crystal fast start-up circuit based on dual-mode current control in another embodiment of this application.

[0019] Explanation of reference numerals in the attached figures: 1-Bias current source module, 11-Reference unit, 12-Current mirror unit, 2-Transconductance amplifier module, 3-Unity gain amplifier module, 31-Enable control circuit, 32-Unity gain amplifier circuit. Detailed Implementation

[0020] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the embodiments of this application. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0021] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0022] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0023] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0024] As described in the background section, with the booming development of emerging application areas such as the Internet of Things (IoT) and portable medical devices, clock chips, as the core module providing time references, directly affect the power consumption performance of devices and their operational reliability. Current typical application scenarios demand nanoamp-level current consumption from real-time clocks. Among various types of clock chips, crystal oscillators are ideal choices for high-precision clock sources due to their highly stable oscillation frequency, which is less affected by external environmental factors (such as temperature and humidity). Furthermore, their frequency accuracy can typically reach the ppm level or even higher.

[0025] In crystal oscillator applications, the power consumption of traditional crystal oscillator circuits is insufficient for applications highly sensitive to power consumption, such as the Internet of Things (IoT), wearable devices, and portable medical devices. For example, in remote sensor nodes, to ensure stable operation over extended periods and enable real-time data acquisition and transmission, the crystal oscillator circuit must be optimized for low power consumption. However, current traditional oscillator circuits suffer from incompatibility between rapid crystal oscillation startup and stable oscillation maintenance with low power consumption, as well as excessively large circuit area.

[0026] Based on this, in some embodiments, such as Figure 1 As shown, this application provides a crystal fast start-up circuit based on dual-mode current control. The working stages of the crystal fast start-up circuit include an oscillation stage and a maintenance stage. The crystal fast start-up circuit includes: a bias current source module 1, a transconductance amplifier module 2, and a unity-gain amplifier module 3.

[0027] like Figure 2 As shown, the bias current source module 1 is used to operate in response to the enable signal EN during the oscillation start-up phase, according to the first bias control signal I. C1 The power supply voltage signal VDD outputs the maximum bias current I1; during the sustaining phase, it receives the second bias control signal I. C2 According to the second bias control signal I C2 The power supply voltage signal VDD outputs a bias current I2, wherein the bias current I2 is less than the maximum bias current I1.

[0028] The transconductance amplifier module 2 is connected to the output terminal of the bias current source module 1, and is used to provide an equivalent negative resistance value for oscillation based on the maximum bias current I1 during the oscillation stage; and to provide an equivalent negative resistance value for maintenance based on the maintenance bias current I2 during the maintenance stage; wherein the equivalent negative resistance value for maintenance is less than the equivalent negative resistance value for oscillation.

[0029] The unity-gain amplifier module 3 and the transconductance amplifier module 2 form a negative feedback structure. The unity-gain amplifier module 3 is used to respond to the enable signal EN, so that the output voltage signal of the transconductance amplifier module 2 and the output voltage signal of the unity-gain amplifier module 3 are equal after the oscillation is completed.

[0030] It is understandable that during the start-up phase, when the system enable signal EN (e.g., EN low level) triggers its operation, the first bias control signal I... C1This will drive the internal circuits of the current mirror and switching transistors to a fully configured state. For example, by maximizing the conduction of the control transistor M1 through a fully open parallel current branch, combined with the power supply voltage signal VDD, the maximum bias current I1 is output to the transconductance amplifier module 2. After receiving the maximum bias current I1, the transconductance amplifier module 2 can have extremely high transconductance (transconductance is positively correlated with bias current) to generate a sufficiently large negative resistance to overcome the loss of the crystal's equivalent series resistance, driving the oscillation to quickly establish itself from the noise background (satisfying the oscillation condition of "loop gain > 1"). The negative resistance provided by the transconductance amplifier module 2 largely determines the length of the oscillation start-up time. Therefore, by outputting the maximum bias current I1 to the transconductance amplifier module 2 during the oscillation start-up stage, the bias current source module 1 can shorten the oscillation start-up time and ensure that the crystal oscillator starts oscillating within the specified time.

[0031] After entering the maintenance phase, the second bias control signal I C2 The module's operating mode will be adjusted (such as turning off part of the current mirror and reducing the control voltage to reduce the conduction current), so that the output holding bias current I2 is significantly reduced (less than the maximum bias current I1). At this time, the transconductance of the transconductance amplifier falls back to the critical value, which not only accurately offsets the crystal loss through negative resistance to maintain the balance of oscillation energy, but also greatly reduces the circuit power consumption due to the reduction of current. At the same time, it avoids the distortion of the oscillation waveform or the amplitude attenuation caused by excessive bias, and finally achieves dynamic optimization of "fast start-up + stable low power consumption".

[0032] Unity-gain amplifier module 3 (characterized by high input impedance and low output impedance) and transconductance amplifier module 2 form a negative feedback closed loop. When the enable signal EN is triggered, the unity-gain module starts working. During the oscillation start-up phase, the output voltages of both modules gradually converge as the signal establishes. Once oscillation is complete and the system enters a stable state (the maintenance phase), the dynamic adjustment mechanism of the negative feedback (if a voltage difference exists, the feedback signal will drive the circuitry within the loop to correct the deviation) forces the output voltage of transconductance amplifier module 2 to be equal to the output voltage of unity-gain amplifier module 3. This design replaces the voltage divider function of traditional bias resistors. On the one hand, it eliminates the interference of resistor temperature drift on the bias through active feedback; on the other hand, it reduces the chip area through integrated circuitry and locks the transconductance amplifier at a precise DC operating point, ensuring energy balance and waveform stability during the oscillation maintenance phase.

[0033] In the aforementioned crystal fast start-up circuit, during the start-up phase, the bias current source module 1 outputs a maximum bias current I1 to the transconductance amplification module 2, enabling the transconductance amplification module 2 to provide an equivalent negative resistance value based on the maximum bias current I1, thus achieving rapid start-up. During the sustaining phase, the bias current source module 1 outputs a sustaining bias current I2 to the transconductance amplification module 2, enabling the transconductance amplification module 2 to provide an equivalent negative sustaining resistance value based on the sustaining bias current I2. Since the sustaining bias current I2 is less than the maximum bias current I1, stable oscillation is maintained with a lower current during the sustaining phase, thereby reducing power consumption. Therefore, the crystal fast start-up circuit of this application can achieve low power consumption while ensuring the crystal oscillator starts up within a specified time. Furthermore, by replacing the traditional bias resistor with a unity-gain amplification module 3, the influence of resistor temperature drift is avoided, and a more precise bias is provided for the transconductance amplification module 2, significantly reducing the area of ​​the start-up circuit compared to the traditional bias resistor.

[0034] In some embodiments, such as Figure 3 As shown, the bias current source module 1 includes a reference unit 11 and multiple current mirror units 12.

[0035] Reference unit 11 is used to operate in response to the enable signal EN, and provides a uniform gate bias voltage to the mirror transistors M2 of each current mirror unit 12 based on the reference current source. Reference unit 11 starts working after the enable signal EN is activated, and provides a uniform gate bias voltage to the mirror transistors M2 of each current mirror unit 12 through the reference current source, ensuring that the gate-source voltage (VGS) of all mirror transistors M2 is consistent.

[0036] During the start-up phase, each current mirror unit 12 responds to the corresponding first bias control signal I. C1 When turned on, a bias current is output based on the received power supply voltage signal VDD, so that the bias current source module 1 outputs the maximum bias current I1.

[0037] During the maintenance phase, some current mirror units 12 respond to the corresponding second bias control signal I. C2 When the residual current mirror unit 12 is turned on, it responds to the corresponding second bias control signal I. C2 Disconnect to allow the bias current source module 1 to output a sustained bias current I2.

[0038] It is understandable that during the start-up phase, all current mirror units 12 respond to the first bias control signal I. C1 (Such as a low-level conduction signal) is simultaneously turned on, and the bias current is superimposed through the parallel mirror branch based on the power supply voltage signal VDD to achieve the maximum bias current I1 output, providing sufficient energy for the transconductance amplifier to overcome the loss of the crystal resonator and meet the oscillation conditions.

[0039] After entering the maintenance phase, the second bias control signal I received by part of the current mirror unit 12 C2 The high-level signal is the second bias control signal I received by the residual current mirror unit 12. C2 The current mirror unit 12 is at a low level, therefore, part of the current mirror unit 12 responds to the corresponding second bias control signal I. C2 When the residual current mirror unit 12 is turned on, it responds to the corresponding second bias control signal I. C2 Disconnecting the current mirror unit 12 will selectively disconnect some of the current mirror units 12, leaving only the necessary mirror branches conducting, causing the output current to drop back to the minimum value required to maintain oscillation. This reduces the overall circuit operating current and effectively reduces power consumption while ensuring the crystal maintains oscillation.

[0040] In some embodiments, such as Figure 3 As shown, the reference unit 11 includes: a first MOS transistor T1 and a second MOS transistor T2.

[0041] The first terminal of the first MOSFET T1 is used to receive the power supply voltage signal VDD, the gate of the first MOSFET T1 is used to receive the enable signal EN, and the second terminal of the first MOSFET T1 is connected to the first terminal of the second MOSFET T2.

[0042] The second terminal of the second MOS transistor T2 is connected to the reference current source, and the gate of the second MOS transistor T2 is connected to the second terminal of the second MOS transistor T2 and the gate of the mirror transistor M2 of each current mirror unit 12.

[0043] In this application, the first MOSFET T1 and the second MOSFET T2 can both be PMOS transistors. The source and drain of the MOSFETs can be interchangeable; therefore, the first terminal in this application can be either the source or the drain. When the first terminal is the source, the second terminal is the drain; when the first terminal is the drain, the second terminal is the source.

[0044] It can be understood that the first terminal of the first MOSFET T1 is connected to the power supply voltage signal VDD, and its gate receives the enable signal EN. When the enable signal EN is valid (e.g., the gate of the PMOS is connected to a low level), the first MOSFET T1 is turned on, and the power supply voltage is transmitted sequentially through the first and second terminals of the first MOSFET T1 to the first terminal of the second MOSFET T2. Since the second terminal of the second MOSFET T2 is connected to the reference current source, which is grounded, and the gate of the second MOSFET T2 is connected to the second terminal of the second MOSFET T2 and the gate of the mirror transistor M2 of each current mirror unit 12, when the reference current source flows through the second MOSFET T2, a stable gate-source voltage (Vgs) will be generated between its gate and source. Since the gate is connected to the gate of each mirror transistor M2, this Vgs will be applied as a uniform bias voltage to the gate of all mirror transistors M2, ensuring that the Vgs of the mirror transistor M2 is completely consistent with that of the second MOSFET T2.

[0045] This design makes the second MOSFET T2 the "reference transistor" of the reference unit 11. Through its own current-voltage characteristics, it converts the reference current into a stable gate bias, providing a precise bias reference for the mirror transistors M2 of each current mirror unit 12. This ensures the replication accuracy of the mirror current (determined by the MOSFET size ratio). During the start-up phase, in conjunction with the enable signal EN, all current mirror branches are turned on to output the maximum bias current I1. During the maintenance phase, in conjunction with the control signal, branches are selectively turned on to output the maintenance bias current I2, ultimately achieving dynamic control and high-precision output of the bias current. When the enable signal EN is invalid, the first MOSFET T1 is turned off, cutting off the power supply path to reduce static power consumption.

[0046] In some embodiments, such as Figure 3 As shown, the current mirror unit 12 includes a control transistor M1 and a mirror transistor M2.

[0047] The first terminal of control transistor M1 is used to receive the power supply voltage signal VDD, and the gate of control transistor M1 is used to receive the bias control signal. The second terminal of control transistor M1 is connected to the first terminal of mirror transistor M2. The bias control signal is the first bias control signal I during the oscillation start-up phase. C1 The bias control signal during the maintenance phase is the second bias control signal I. C2 .

[0048] The second terminal of the mirror transistor M2 is connected to the transconductance amplifier module 2, and the gate of the mirror transistor M2 is used to receive the gate bias voltage provided by the reference unit 11.

[0049] It can be understood that the first terminal of the control transistor M1 is connected to the power supply voltage signal VDD, and the gate of the control transistor M1 receives the bias control signal (such as the aforementioned first bias control signal I). C1 Or the second bias control signal I C2 The second electrode is connected to the first electrode of the mirror transistor M2. Therefore, the conduction state of the control transistor M1 is determined by the bias control signal. During the start-up phase, the control transistor M1 responds to the first bias control signal I. C1 When the circuit is turned on, the power supply voltage is transmitted to the first terminal of the mirror transistor M2 via the first and second terminals of the control transistor M1. Since the gate of the mirror transistor M2 receives the uniform gate bias voltage output from the reference unit 11, and the second terminal of the mirror transistor M2 is connected to the transconductance amplifier module 2, the second terminal of the mirror transistor M2 can directly output bias current to the transconductance amplifier module 2. During the oscillation phase, all control transistors M1 are connected to the first bias control signal I. C1 When the current mirror unit 12 is turned on, all the mirror tubes M2 work synchronously. During the oscillation stage, the bias current output by each current mirror unit 12 is superimposed to output the maximum bias current I1 to the transconductance amplification module 2, thereby meeting the high transconductance requirement of the transconductance amplification module 2.

[0050] During the maintenance phase, part of the control transistor M1 responds to the corresponding second bias control signal I. C2 When the high-level signal is turned off, the power supply path to the corresponding mirror transistor M2 is cut off. During the sustaining phase, only a portion of the control transistor M1 is turned on, and the corresponding mirror transistor M2 outputs a sustaining bias current I2. Therefore, during the sustaining phase, only a portion of the current mirror unit 12 outputs bias current, and the bias current output by the bias current source module 1 is less than the maximum bias current I1 output during the start-up phase. Thus, the overall circuit operating current is reduced during the sustaining phase, effectively reducing power consumption while ensuring the crystal maintains oscillation. Through the above circuit design, dynamic control of the bias current can be achieved through the selective switching of the control transistor M1 and the precise current replication of the mirror transistor M2, supporting the entire process of the oscillation circuit from start-up to stability, achieving rapid start-up while maintaining low power consumption.

[0051] It should be noted that the mirror transistors M2 of each current mirror unit 12 can use the same gate length to reduce the error caused by the lateral diffusion of the source and drain.

[0052] In some embodiments, such as Figure 3 As shown, there are four current mirror units 12, namely the first current mirror unit 121, the second current mirror unit 122, the third current mirror unit 123 and the fourth current mirror unit 124.

[0053] The size ratio of the mirror tube M2 in the first current mirror unit 121, the second current mirror unit 122, the third current mirror unit 123, and the fourth current mirror unit 124 is 8:4:2:1.

[0054] It is understandable that, since the mirror current of a MOSFET is proportional to its size, when the size ratio of the mirror transistors M2 in the four current mirror units 12 is 8:4:2:1, the ratio of the bias currents output by the four current mirror units 12 is also 8:4:2:1. During the oscillation start-up phase, all four current mirror units are turned on in response to the first bias control signal IC1, and the total output bias current is the sum of the currents of the four units, i.e., the maximum bias current I1, which meets the high transconductance requirement for the transconductance amplifier module 2 to start up. During the maintenance phase, the second bias control signal IC2 selectively turns on some current mirror units 12, and the total output current is the sum of the currents of the turned-on units, i.e., the maintenance bias current I2. Through this flexible adjustment of the proportional combination, the oscillation stability during the maintenance phase can be guaranteed, power consumption can be significantly reduced, and precise quantitative adjustment of the bias current can be achieved using a fixed ratio to adapt to the current requirements in different scenarios.

[0055] In some embodiments, during the maintenance phase, the first current mirror unit 121, the second current mirror unit 122, and the third current mirror unit 123 are sequentially disconnected. Figure 1That is, after the crystal has completed its oscillation and stabilized, I CTRL3、 I CTRL2、 I CTRL1 Connect the high-level signal sequentially.

[0056] It is understandable that during the maintenance phase, the first current mirror unit 121, the second current mirror unit 122, and the third current mirror unit 123 are disconnected sequentially. Since the size ratio of the mirror transistor M2 in the first current mirror unit 121, the second current mirror unit 122, the third current mirror unit 123, and the fourth current mirror unit 124 is 8:4:2:1, the mirror current of the MOSFET is proportional to its size. Therefore, this process essentially achieves a gradual reduction in the bias current by step-wise shutting down a large proportion of the current branches. Initially, only the first current mirror unit 121 is disconnected, while the remaining second, third, and fourth current mirror units are turned on, ensuring that the total current is still higher than the final maintenance value and that the oscillation energy is not interrupted by a sudden drop in current. Subsequently, the second current mirror unit 122 is disconnected, while the remaining third and fourth current mirror units are turned on, and the total bias current further approaches the critical current for maintaining oscillation. Finally, the third current mirror unit 123 is disconnected, leaving only the fourth current mirror unit 124 working, and the total current stabilizes at the minimum maintenance current. The minimum holding current just meets the requirement that the absolute value of the negative resistance of the transconductance amplifier module 2 is equal to the equivalent series resistance (ESR) of the crystal. This sequential design of "large proportion turning off first, small proportion turning off later" avoids the impact of sudden current changes on the oscillation phase and amplitude (preventing oscillation stoppage or waveform distortion), and achieves a smooth transition from "excess energy injection" to "energy balance" by gradually reducing the current (corresponding to a gradual decrease in transconductance and a gradual increase in negative resistance). At the same time, it maximizes the reduction of power consumption during the holding phase, perfectly adapting to the dynamic characteristics requirements of the crystal oscillator circuit from start-up to stability.

[0057] In some embodiments, such as Figure 3 As shown, the transconductance amplification module 2 includes: a first PMOS transistor P1 and a first NMOS transistor N1.

[0058] The first terminal of the first PMOS transistor P1 is connected to the output terminal of the bias current source module 1, the gate of the first PMOS transistor P1 is connected to the output terminal of the unity gain amplifier module 3, and the second terminal of the first PMOS transistor P1 is connected to the unity gain amplifier module 3 and serves as the output terminal of the crystal fast start-up circuit.

[0059] The first terminal of the first NMOS transistor N1 is connected to the second terminal of the first PMOS transistor P1, the gate of the first NMOS transistor N1 is connected to the gate of the first PMOS transistor P1, and the second terminal of the first NMOS transistor N1 is grounded.

[0060] It can be understood that the first PMOS transistor P1 and the first NMOS transistor N1 form an inverter structure, and the transconductance amplification module 2 is an inverting amplifier. The first terminal of the first PMOS transistor P1 is connected to the output terminal of the bias current source module 1, receiving a dynamically adjustable bias current (maximum current during the oscillation stage to provide high transconductance, and minimum current during the sustain stage to reduce power consumption). The gate of the first PMOS transistor P1 and the gate of the first NMOS transistor N1 are connected to the output terminal of the unity-gain amplification module 3, receiving the feedback voltage signal XI. The second terminal of the first PMOS transistor P1 not only serves as the output terminal of the crystal fast oscillation circuit, outputting the voltage signal XO, but also connects in reverse to the input terminal of the unity-gain amplification module 3, forming a closed-loop negative feedback structure. The first terminal of the first NMOS transistor N1 is connected to the drain of the first PMOS transistor P1, and its gate is connected to XI along with the gate of the PMOS transistor. The second terminal is directly grounded, forming a typical CMOS inverter topology. When the input voltage XI changes, the PMOS transistor and the NMOS transistor exhibit complementary conduction characteristics. When XI increases, the NMOS transistor conducts more strongly, pulling down the output voltage XO. When XI decreases, the PMOS transistor conducts more strongly, pulling up the output voltage XO. This characteristic makes the inverter equivalent to a voltage-controlled current source, and its transconductance Gm is determined by the bias current. During the oscillation start-up phase, the bias current source provides the maximum current, causing Gm to reach its peak value. At this time, the negative resistance generated by the inverter is significantly less than the equivalent series resistance of the crystal resonator, satisfying the oscillation start-up condition (loop gain > 1). After entering the maintenance phase, the bias current decreases, Gm falls back to the critical value, and the negative resistance and ESR are dynamically balanced (-1 / Gm = ESR), maintaining stable oscillation operation.

[0061] Furthermore, the unity-gain amplifier module 3 forces the voltages of XI and XO to be equal through negative feedback, ensuring the stability of the inverter's operating point and eliminating the temperature drift effect of traditional bias resistors. Simultaneously, the symmetrical structure of the PMOS and NMOS transistors effectively suppresses common-mode noise and improves the purity of the oscillation signal. This design cleverly combines the high transconductance characteristics of the inverter with the stability of closed-loop feedback, achieving rapid start-up, low power consumption maintenance, and high-precision frequency control of the crystal oscillator circuit.

[0062] In some embodiments, such as Figure 3 As shown, the unity-gain amplifier module 3 includes an enable control circuit 31 and a unity-gain amplifier circuit 32.

[0063] The enable control circuit 31 is used to control the operating state of the unity gain amplifier circuit 32 in response to the enable signal EN.

[0064] The unity-gain amplifier circuit 32 and the transconductance amplifier module 2 form a negative feedback structure. The unity-gain amplifier circuit 32 is used to make the output voltage signal of the transconductance amplifier module 2 equal to the output voltage of the unity-gain amplifier module 3 through the negative feedback mechanism.

[0065] It can be understood that the enable control circuit 31 responds to the external enable signal EN (such as EN being active low) by turning on or off the power supply path to control the switching on and off of the unity-gain amplifier circuit 32. When EN is active, the enable control circuit 31 provides power to the unity-gain amplifier circuit 32, enabling it to enter the working state; when EN is inactive, it cuts off the power supply to reduce static power consumption.

[0066] The unity-gain amplifier circuit 32 and the transconductance amplifier module 2 form a closed-loop negative feedback system. The unity-gain amplifier circuit 32 uses a negative feedback mechanism to make the output voltage signal of the transconductance amplifier module 2 equal to the output voltage of the unity-gain amplifier module 3, achieving voltage following. By replacing the traditional bias resistor with the unity-gain amplifier circuit 32, the influence of resistor temperature drift is avoided, while providing a more precise bias for the transconductance amplifier module 2, and significantly reducing the area of ​​the oscillation circuit compared to the traditional bias resistor.

[0067] In some embodiments, such as Figure 3 As shown, the enable control circuit 31 includes: a second PMOS transistor P2, a third PMOS transistor P3, a second NMOS transistor N2, and a third NMOS transistor N3.

[0068] The first terminal of the second PMOS transistor P2 is used to receive the power supply voltage signal VDD. The second terminal of the second PMOS transistor P2 is connected to the gate of the third PMOS transistor P3, the first terminal of the second NMOS transistor N2, and the gate of the third NMOS transistor N3, respectively. The gate of the second PMOS transistor P2 is used to receive the enable signal EN.

[0069] The first terminal of the third PMOS transistor P3 is used to receive the power supply voltage signal VDD. The second terminal of the third PMOS transistor P3 is connected to the first terminal of the third NMOS transistor N3 and the unity gain amplifier circuit 32.

[0070] The second terminal of the second NMOS transistor N2 is grounded, and the gate of the second NMOS transistor N2 is used to receive the enable signal EN.

[0071] The second terminal of the third NMOS transistor N3 is connected to the unity-gain amplifier circuit 32.

[0072] It can be understood that when the enable signal EN is low, the second PMOS transistor P2 turns on in response to the enable signal EN, transmitting the power supply voltage to the gate of the third PMOS transistor P3, the first terminal of the second NMOS transistor N2, and the gate of the third NMOS transistor N3. Simultaneously, the gate of the second NMOS transistor N2 receives the enable signal EN, its gate voltage is low, and N2 turns off. At this time, the gate voltage of the third PMOS transistor P3 is pulled high (close to the power supply voltage VDD), causing P3 to turn off. The gate voltage of the third NMOS transistor N3 is also high, turning it on. The first and second terminals of the third NMOS transistor N3 respectively provide low-level signals to the unity-gain amplifier circuit 32, enabling the unity-gain amplifier circuit 32 to operate normally. When EN is high, the gate voltage of the second PMOS transistor P2 is high, turning it off and cutting off the power supply path. Simultaneously, the gate voltage of the second NMOS transistor N2 is high, turning it on and pulling the gate voltage of the third PMOS transistor P3 low (close to ground), causing P3 to turn on. Meanwhile, the gate voltage of the third NMOS transistor N3 is low, turning it off. At this time, the first terminal of the third PMOS transistor P3 outputs a high-level signal to the unity-gain amplifier circuit 32. No current flows through part of the unity-gain amplifier circuit 32, entering a low-power standby state. This circuit design uses a complementary switch to invert the logic of the enable signal EN, ensuring that the circuit operates when EN is active (low level) and is turned off when EN is inactive (high level). It also avoids the leakage problems that may exist in a single-switch structure, further reducing standby power consumption.

[0073] In the crystal oscillator circuit, the enable control circuit 31 works in conjunction with the unity gain amplifier circuit 32 to ensure that the circuit is activated only when oscillation is needed (such as when the system wakes up), effectively reducing the overall power consumption. At the same time, the oscillation is quickly established and shut down by responding quickly to the enable signal EN, meeting the application requirements of low power consumption and high performance.

[0074] In some embodiments, such as Figure 3 As shown, the unity-gain amplifier circuit 32 includes: a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh PMOS transistor P7, a fourth NMOS transistor N4, and a fifth NMOS transistor N5.

[0075] The first terminal of the fourth PMOS transistor P4 is used to receive the power supply voltage signal VDD. The second terminal of the fourth PMOS transistor is connected to the first terminal of the fifth PMOS transistor P5. The gate of the fourth PMOS transistor P4 is used to receive the enable signal EN.

[0076] The second terminal of the fifth PMOS transistor P5 is connected to the first terminal of the sixth PMOS transistor P6 and the first terminal of the seventh PMOS transistor P7, respectively. The gate of the fifth PMOS transistor P5 is connected to the reference current source.

[0077] The second terminal of the sixth PMOS transistor P6 is connected to the second terminal of the third NMOS transistor N3 and the first terminal of the fourth NMOS transistor N4, respectively, and is connected to the transconductance amplifier module 2 as the output terminal of the unity gain amplifier module 3. The gate of the sixth PMOS transistor P6 is connected to the second terminal of the third PMOS transistor P3.

[0078] The second terminal of the seventh PMOS transistor P7 is connected to the first terminal of the fifth NMOS transistor N5, and the gate of the seventh PMOS transistor P7 is connected to the output terminal of the transconductance amplifier.

[0079] The second terminal of the fourth NMOS transistor N4 is grounded, and the gate of the fourth NMOS transistor N4 is connected to the first terminal of the fourth NMOS transistor N4 and the gate of the fifth NMOS transistor N5, respectively.

[0080] The second terminal of the fifth NMOS transistor N5 is grounded.

[0081] It can be understood that the fourth PMOS transistor P4 acts as a power switch. The first terminal of the fourth PMOS transistor P4 is connected to the power supply voltage signal VDD, and the gate of the fourth PMOS transistor P4 is connected to the enable signal EN. When EN is low, the fourth PMOS transistor P4 is turned on, and the power supply voltage signal VDD is transmitted to the fifth PMOS transistor P5. The fifth PMOS transistor P5 is connected to the reference current source, and the gate of the fifth PMOS transistor P5 receives the bias voltage generated by the reference current (the uniform gate bias voltage provided by the reference unit 11). The second terminal of the fifth PMOS transistor P5 is connected to the first terminal of the fifth PMOS transistor P5 and the first terminal of the sixth PMOS transistor P6, respectively. Therefore, during the oscillation stage and the sustaining stage, an electrical bias current is output to the fifth PMOS transistor P5 and the sixth PMOS transistor P6.

[0082] The gate of the sixth PMOS transistor P6 is connected to the second terminal of the third PMOS transistor P3. Referring to the previous embodiment, when the enable signal EN is low, the gate voltage of the sixth PMOS transistor P6 is low, and the sixth PMOS transistor P6 is turned on. Since the second terminal of the sixth PMOS transistor P6 is connected to the second terminal of the third NMOS transistor N3 and the first terminal of the fourth NMOS transistor N4, and serves as the output terminal of the unity-gain amplifier module 3 connected to the transconductance amplifier module 2, the voltage signal output from the second terminal of the sixth PMOS transistor P6 is transmitted to the second terminal of the third NMOS transistor N3, the first terminal of the fourth NMOS transistor N4, and the transconductance amplifier module 2, i.e., XI.

[0083] When EN is active, if the XI voltage is higher than XO, the seventh PMOS transistor P7 conducts more strongly, and the current of the fifth NMOS transistor N5 increases, pulling XI low through a negative feedback mechanism. Conversely, if XI is lower than XO, the sixth PMOS transistor P6 conducts more strongly, and the current of the fourth NMOS transistor N4 increases, pulling XI high, ultimately forcing XI to equal XO, achieving unity-gain characteristics. This circuit achieves high input impedance and low output impedance voltage following functionality through current mirror bias, differential pair input, and cascode output structure. Simultaneously, it utilizes an enable control signal to quickly switch operating states, meeting the bias stability and power consumption requirements of the crystal oscillator circuit at different stages.

[0084] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this application can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this application. In particular, the features described in the various embodiments and / or claims of this application can be combined and / or combined in various ways without departing from the spirit and teachings of this application. All such combinations and / or combinations fall within the scope of this application. Therefore, the scope of this application should not be limited to the above embodiments, but should be defined not only by the appended claims, but also by their equivalents. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A crystal fast oscillation circuit based on dual-mode current control, characterized in that, The operation of the crystal fast oscillation circuit includes, in sequence, an oscillation start-up stage and a maintenance stage; the crystal fast oscillation circuit includes: A bias current source module is configured to operate in response to an enable signal during the oscillation start-up phase, and output a maximum bias current based on a first bias control signal and a power supply voltage signal; during the sustaining phase, it receives a second bias control signal and outputs a sustaining bias current based on the second bias control signal and the power supply voltage signal, wherein the sustaining bias current is less than the maximum bias current. A transconductance amplification module, connected to the output terminal of the bias current source module, is used to provide an equivalent oscillation negative resistance value based on the maximum bias current during the oscillation start-up phase; and to provide an equivalent maintenance negative resistance value based on the maintenance bias current during the maintenance phase; wherein the equivalent maintenance negative resistance value is less than the equivalent oscillation negative resistance value. A unity-gain amplifier module, which together with the transconductance amplifier module form a negative feedback structure, is used to respond to the enable signal to operate such that the output voltage signal of the transconductance amplifier module is equal to the output voltage signal of the unity-gain amplifier module after oscillation is completed.

2. The crystal fast start-up circuit based on dual-mode current control as described in claim 1, characterized in that, The bias current source module includes: a reference unit and multiple current mirror units; The reference unit is used to operate in response to the enable signal and provides a uniform gate bias voltage to the mirror transistors of each current mirror unit based on the reference current source. During the oscillation start-up phase, each current mirror unit turns on in response to the corresponding first bias control signal and outputs a bias current based on the received power supply voltage signal, so that the bias current source module outputs the maximum bias current. During the maintenance phase, some of the current mirror units turn on in response to the corresponding second bias control signal, while the remaining current mirror units turn off in response to the corresponding second bias control signal, so that the bias current source module outputs the maintenance bias current.

3. The crystal fast start-up circuit based on dual-mode current control as described in claim 2, characterized in that, The reference unit includes: a first MOS transistor and a second MOS transistor; The first terminal of the first MOS transistor is used to receive the power supply voltage signal, the gate of the first MOS transistor is used to receive the enable signal, and the second terminal of the first MOS transistor is connected to the first terminal of the second MOS transistor. The second terminal of the second MOS transistor is connected to the reference current source, and the gate of the second MOS transistor is connected to the second terminal of the second MOS transistor and the gate of the mirror transistor of each current mirror unit.

4. The crystal fast start-up circuit based on dual-mode current control as described in claim 2, characterized in that, The current mirror unit includes: a control transistor and a mirror transistor; The first terminal of the control transistor is used to receive the power supply voltage signal, the gate of the control transistor is used to receive the bias control signal, and the second terminal of the control transistor is connected to the first terminal of the mirror transistor. The bias control signal is the first bias control signal during the oscillation stage and the bias control signal is the second bias control signal during the maintenance stage. The second electrode of the mirror transistor is connected to the transconductance amplification module, and the gate of the mirror transistor is used to receive the gate bias voltage provided by the reference unit.

5. The crystal fast start-up circuit based on dual-mode current control as described in claim 4, characterized in that, The number of current mirror units is four, namely, the first current mirror unit, the second current mirror unit, the third current mirror unit, and the fourth current mirror unit. The ratio of the dimensions of the mirror tubes in the first current mirror unit, the second current mirror unit, the third current mirror unit, and the fourth current mirror unit is 8:4:2:

1.

6. The crystal fast start-up circuit based on dual-mode current control as described in claim 5, characterized in that, During the maintenance phase, the first current mirror unit, the second current mirror unit, and the third current mirror unit are disconnected in sequence.

7. The crystal fast start-up circuit based on dual-mode current control as described in claim 1, characterized in that, The transconductance amplification module includes: a first PMOS transistor and a first NMOS transistor; The first terminal of the first PMOS transistor is connected to the output terminal of the bias current source module, the gate of the first PMOS transistor is connected to the output terminal of the unity gain amplifier module, and the second terminal of the first PMOS transistor is connected to the unity gain amplifier module and serves as the output terminal of the crystal fast start-up circuit. The first terminal of the first NMOS transistor is connected to the second terminal of the first PMOS transistor, the gate of the first NMOS transistor is connected to the gate of the first PMOS transistor, and the second terminal of the first NMOS transistor is grounded.

8. The crystal fast start-up circuit based on dual-mode current control as described in claim 1, characterized in that, The unity-gain amplifier module includes: an enable control circuit and a unity-gain amplifier circuit; The enable control circuit is used to control the operating state of the unity-gain amplifier circuit in response to the enable signal; The unity-gain amplifier circuit and the transconductance amplifier module form a negative feedback structure. The unity-gain amplifier circuit is used to make the output voltage signal of the transconductance amplifier module equal to the output voltage of the unity-gain amplifier module through the negative feedback mechanism.

9. The crystal fast start-up circuit based on dual-mode current control as described in claim 8, characterized in that, The enable control circuit includes: a second PMOS transistor, a third PMOS transistor, a second NMOS transistor, and a third NMOS transistor; The first terminal of the second PMOS transistor is used to receive the power supply voltage signal, and the second terminal of the second PMOS transistor is connected to the gate of the third PMOS transistor, the first terminal of the second NMOS transistor, and the gate of the third NMOS transistor, respectively. The gate of the second PMOS transistor is used to receive the enable signal. The first terminal of the third PMOS transistor is used to receive the power supply voltage signal, and the second terminal of the third PMOS transistor is connected to the first terminal of the third NMOS transistor and the unity gain amplifier circuit, respectively. The second terminal of the second NMOS transistor is grounded, and the gate of the second NMOS transistor is used to receive the enable signal; The second terminal of the third NMOS transistor is connected to the unity-gain amplifier circuit.

10. The crystal fast start-up circuit based on dual-mode current control as described in claim 9, characterized in that, The unity-gain amplifier circuit includes: a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor; The first terminal of the fourth PMOS transistor is used to receive the power supply voltage signal, the second terminal of the fourth PMOS transistor is connected to the first terminal of the fifth PMOS transistor, and the gate of the fourth PMOS transistor is used to receive the enable signal. The second terminal of the fifth PMOS transistor is connected to the first terminal of the sixth PMOS transistor and the first terminal of the seventh PMOS transistor, respectively, and the gate of the fifth PMOS transistor is connected to the reference current source. The second terminal of the sixth PMOS transistor is connected to the second terminal of the third NMOS transistor and the first terminal of the fourth NMOS transistor, respectively, and is connected to the transconductance amplification module as the output terminal of the unity-gain amplification module. The gate of the sixth PMOS transistor is connected to the second terminal of the third PMOS transistor. The second terminal of the seventh PMOS transistor is connected to the first terminal of the fifth NMOS transistor, and the gate of the seventh PMOS transistor is connected to the output terminal of the transconductance amplifier. The second terminal of the fourth NMOS transistor is grounded, and the gate of the fourth NMOS transistor is connected to the first terminal of the fourth NMOS transistor and the gate of the fifth NMOS transistor, respectively. The second terminal of the fifth NMOS transistor is grounded.

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