A design method of a TIADC system mismatch error correction circuit

Abstract

The application discloses a design method of a TIADC system mismatch error correction circuit. Firstly, aiming at the digital correction circuit of the TIADC system mismatch error, the bit width of the correction coefficient in the multiplier is determined according to the distribution law of each order coefficient of the correction filter; the bit width of the correction sampling value in the multiplier is determined in combination with the dynamic performance index of the single-chip ADC and the noise requirement of the TIADC system, the approximate compression tree structure of the multiplier is designed, and the truncation bit width in the step-by-step summation process of the multiplier output is determined; the to-be-summed items in each channel of the correction filter are step-by-step compressed by the compressor, and the final summation is completed through the adder to obtain the correction result of the current sampling point, and the correction of the TIADC system mismatch error is completed. By using the method, the scale of the digital correction circuit can be reduced, and the purpose of reducing the resource consumption of the digital correction circuit under the premise of ensuring the correction accuracy is achieved.

Description

Technical Field

[0001] This invention relates to the field of digital integrated circuit design technology, and in particular to a design method for a mismatch error correction circuit in a TIADC (Time-Interleaved Analog-to-Digital Converter) system. Background Technology

[0002] High-speed, high-precision analog-to-digital conversion technology has important and wide applications in high-energy physics experiments, digital storage oscilloscopes, communications, radar, and other fields. Although the sampling rate performance of a single ADC (Analog-to-Digital Converter) has been greatly improved with the advancement of semiconductor technology and integrated circuit design, the ever-evolving application requirements mean that a single ADC still cannot meet the needs of many scenarios, especially in situations requiring both high speed and high precision. An effective approach is to employ a multi-channel time-interleaved structure, using M ADC chips and parallel alternating sampling technology to increase the system sampling rate to M times that of a single ADC.

[0003] However, due to differences in signal delay and variations in chip manufacturing processes, mismatches inevitably exist between channels, such as bias mismatch, gain mismatch, and sampling clock phase mismatch. These mismatches lead to deviations in the sampling results, which manifest as spurious signals at corresponding frequency points in the spectrum, thus degrading the dynamic performance of the TIADC (Time-Interleaved Analog-to-Digital Converter) system. Therefore, it is necessary to correct the various mismatch errors of the TIADC. In recent years, digital correction algorithms based on perfect reconstruction theory and machine learning have been widely used to address the digital correction problem of mismatch errors in TIADCs, achieving good correction results. However, these methods still have the following limitations at the hardware implementation level, especially in the specific implementation of the underlying digital correction circuit: they rely on a large number of DSP (Digital Signal Processor) resources inside high-end FPGAs (Field Programmable Gate Arrays), resulting in high system power consumption and cost, making it difficult to meet the actual deployment requirements of low-power or low-cost systems. Therefore, it is necessary to study the digital correction circuit for TIADC mismatch error, and reduce the resource consumption of the correction circuit while ensuring the system correction accuracy. Summary of the Invention

[0004] The purpose of this invention is to provide a design method for a mismatch error correction circuit in a TIADC system. This method can reduce the size of the digital correction circuit, thereby reducing the resource consumption of the digital correction circuit while ensuring correction accuracy.

[0005] The objective of this invention is achieved through the following technical solution:

[0006] A design method for a mismatch error correction circuit in a TIADC system, the method comprising:

[0007] Step 1: For the mismatch error correction circuit of the Time-Interleaved Analog-to-Digital Converter (TIADC) system, determine the bit width of the correction coefficients in the multiplier according to the distribution law of the coefficients of each order of the correction filter; wherein, the digital correction circuit consists of Z parallel correction filters, each correction filter consists of K multipliers and summing circuits, forming a K-order filtering process for the original sampling result.

[0008] Step 2: Based on the dynamic performance indicators of the single-chip analog-to-digital converter (ADC) and the noise requirements of the TIADC system, determine the bit width of the correction sampling value in the multiplier, design the approximate compressed tree structure of the multiplier, and determine the truncation bit width in the step-by-step summation process of the multiplier output.

[0009] Step 3: Use a compressor to compress the terms to be summed in each channel of the correction filter step by step, and use an adder to complete the final summation to obtain the correction result of the current sampling point, thus completing the correction of the mismatch error of the TIADC system.

[0010] As can be seen from the technical solution provided by the present invention, this method can reduce the size of the digital correction circuit, thereby reducing the resource consumption of the digital correction circuit while ensuring the correction accuracy. It has good effectiveness, practicality and scalability, and is easy to integrate into hardware, with obvious advantages in hardware overhead. Attached Figure Description

[0011] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic flowchart of the design method for the mismatch error correction circuit of the TIADC system provided in an embodiment of the present invention;

[0013] Figure 2 This is a schematic diagram of the TIADC system as exemplified in this invention;

[0014] Figure 3 This is a schematic diagram of the TIADC mismatch error digital correction circuit as exemplified in this invention;

[0015] Figure 4 This is a schematic diagram showing the average value of each correction coefficient in the examples given in this invention;

[0016] Figure 5 This is a schematic diagram of the standard deviation of each correction coefficient in the examples given in this invention;

[0017] Figure 6 This is a schematic diagram of the overall architecture of the digital correction circuit provided in an embodiment of the present invention;

[0018] Figure 7 This is a schematic diagram of an approximate compressed tree for an 8-bit × 8-bit multiplier as described in the present invention.

[0019] Figure 8 This is a schematic diagram of an approximate compressed tree for the 10-bit × 10-bit multiplier exemplified in this invention;

[0020] Figure 9 This is a schematic diagram of an approximate compressed tree for the 12-bit × 16-bit multiplier exemplified in this invention;

[0021] Figure 10 This is a schematic diagram of the signal-to-noise ratio (SNR) versus input signal frequency before and after correction, provided in an embodiment of the present invention. Detailed Implementation

[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments, and do not constitute a limitation of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present invention.

[0023] like Figure 1 The diagram shows a flowchart of a TIADC system mismatch error correction method provided in an embodiment of the present invention. The method includes:

[0024] Step 1: For the digital correction circuit of the mismatch error in the time-interleaved analog-to-digital converter (TIADC) system, determine the bit width of the correction coefficients in the multiplier based on the distribution law of the coefficients of each order of the correction filter;

[0025] The digital correction circuit consists of Z parallel correction filters, each composed of K multipliers and a summing circuit, forming a K-order filter for the original sampling result. The specific filtering process of the digital correction circuit is expressed as follows:

[0026] (1)

[0027] in, Indicates after the first The corrected sampling result output by each correction filter; Indicates the first The correction filter is the first One original sampling result; Indicates the first The correction filter is the first One correction factor; Indicates the first The result of bias error correction for each correction filter; K is the order of the correction filter.

[0028] The process of determining the bit width of the correction coefficients in the multiplier based on the distribution pattern of the coefficients of each order of the correction filter is as follows:

[0029] The range of mismatch error variation of the TIADC system under multiple frequency points was determined by experimental measurement and literature review.

[0030] The gain mismatch error, bias mismatch error, and sampling clock phase mismatch error of the analog-to-digital converter are randomly selected multiple times within the range of variation to generate multiple sets of mismatch error parameters, and the corresponding sampling waveform data containing mismatch error at multiple frequency points are simulated.

[0031] The TIADC mismatch error correction algorithm is used to correct multiple sets of sampled waveform data containing mismatch errors, and multiple sets of correction coefficients are obtained. Among them, the TIADC mismatch error correction algorithm includes a perfect reconstruction algorithm or a machine learning algorithm.

[0032] The average value and standard deviation of each correction coefficient are calculated. For the correction coefficient corresponding to the sampling point whose average value is close to 1, 1 is subtracted from the correction coefficient and the difference is used to replace the original correction coefficient.

[0033] The lower bits of the correction coefficients are truncated based on the standard deviation of each correction coefficient, while the sign bit is retained, to determine the input bit width of the correction coefficients in the multiplier.

[0034] In the specific implementation process, the mismatch error of the TIADC system includes: , and ; This represents the gain error of the m-th ADC channel under a sinusoidal input with frequency f; This represents the sampling clock phase error of the m-th ADC channel under a sinusoidal input with frequency f; This represents the bias error of the m-th ADC channel under a sinusoidal input with frequency f;

[0035] bias error It is a fixed value, and and It changes with the frequency of the input signal;

[0036] Gain error The range of variation is Sampling clock phase error The range of variation is Bias error The range of variation is ;in, This represents the minimum gain error under a sinusoidal input with frequency f; This represents the maximum gain error under a sinusoidal input with frequency f; This represents the minimum value of the sampling clock phase error under a sinusoidal input with frequency f; This represents the maximum value of the sampling clock phase error under a sinusoidal input with frequency f; This represents the minimum value of the bias error; This represents the maximum value of the bias error.

[0037] The generated sets of mismatch errors are randomly selected independently, and the sampled waveform data containing the mismatch errors are represented as follows:

[0038] (2)

[0039] in, , and These represent the amplitude, angular frequency, and phase of the input sine wave, respectively. This represents the sampling time of the i-th sampling point; This represents the gain error of the m-th ADC channel under a sinusoidal input of frequency f, obtained by randomly sampling the j-th mismatch error. This represents the sampling clock phase error of the m-th ADC channel under a sinusoidal input of frequency f, obtained by randomly sampling the j-th mismatch error. This represents the bias error of the m-th ADC channel under random sampling of the j-th mismatch error; This represents the i-th sampled data of the m-th channel under a sinusoidal input of frequency f, obtained by random sampling of the j-th mismatch error.

[0040] The process of truncating the lower bits of the correction coefficients based on the standard deviation of each order of correction coefficients while retaining the sign bit to determine the input bit width of the correction coefficients in the multiplier is as follows:

[0041] When the correction factor is not truncated, the correction factor Represented by N being a fraction smaller than a specific point, the format is as follows:

[0042] C[C0C1C2……C N-1 ]

[0043] Where C0 is the sign bit and C1 has a weight of 2. 0 The C2 weight is 2. -1 And so on, C N-1 Weight 2 2-N When the correction coefficient is not truncated, its range is [-2: 2-2]. 2-N ];

[0044] After truncating the original N-bit correction coefficient by T bits (lower bits), the truncated correction coefficient C' is obtained, represented in the following format:

[0045] C'[C0C N-T+1 C N-T+2 ...C N-1 ]

[0046] Where C0 is the sign bit, C N-T+1 Weight 2 T-N C N-T+2 Weight 2 T-N-1 The rest follow the same pattern; the range of the truncated correction coefficient C' is [-2]. 1+T-N :2 1+T-N -2 2-N ];

[0047] The selection of the truncation digit T should ensure that the range of the truncated correction coefficient C' covers at least 6 times the standard deviation of the correction coefficient, in order to avoid overflow of the correction coefficient and loss of correction accuracy.

[0048] Step 2: Based on the dynamic performance indicators of the single-chip analog-to-digital converter (ADC) and the noise requirements of the TIADC system, determine the bit width of the correction sampling value in the multiplier, design the approximate compressed tree structure of the multiplier, and determine the truncation bit width in the step-by-step summation process of the multiplier output.

[0049] In this step, the specific dynamic performance indicators of a single ADC (such as signal-to-noise ratio) are considered. ), and the range of dynamic performance loss (such as reduced confidence-to-satisfaction ratio) allowed by the correction calculation error of the TIADC system. The upper limit of the allowable calculation error during the correction process is calculated. ;

[0050] Raw sampling results of the multiplier input By truncating the high-order bits and reducing the multiplier's bit width, the error caused by the multiplier's limited bit width can be calculated. ;in, Indicates the first The correction filter is the first One original sampling result;

[0051] When compressing the partial product in the multiplier, an approximate compressed tree is designed instead of an exact compressed tree, and the error generated by the approximate compressed tree of the multiplier is calculated. ;

[0052] During the summation of the outputs of each channel multiplier, the output bit width of the multiplier is reduced, and the error caused by the high-order bit truncation during the step-by-step summation process is calculated. ;

[0053] Calculate the upper limit of error Assigned to three independent errors , and Based on the error allocation results and error analysis, the bit width of the corrected sample value in the multiplier is determined, the design of the approximate compressed tree of the multiplier is completed, and the truncation bit width of each stage in the step-by-step summation process is determined.

[0054] In practice, the upper limit of the allowable calculation error during the correction process. The calculation method is as follows:

[0055] (3)

[0056] in, To calculate the upper limit of error The mean square value; This indicates the loss of signal-to-noise ratio in the TIADC system due to calculation errors during the calibration process; This indicates the signal-to-noise ratio of a single-chip ADC; The energy of the sinusoidal signal;

[0057] Errors caused by the finite bit width of the multiplier The calculation process is as follows:

[0058] Original sampling results A P-bit unsigned number is represented as follows:

[0059] ;

[0060] Where S0 is the most significant bit of the sampling result, S1 is the second most significant bit of the sampling result, and so on. P-1 It is the least significant bit of the sampling result; the original sampling result The range of the expression is [0:1-2]. -P ];

[0061] For the original sampling results The most significant L bits are truncated to obtain the truncated sampling result. , is represented as:

[0062] ;

[0063] Among them, S L-1 It is the least significant bit of the truncated sampling result; truncated sampling result The range of the expression is [0:1-2]. -L ];

[0064] By truncating the original sampling results and correction coefficients, the operation bit width of the multiplier is reduced from the original P bits × N bits to L bits × T bits; where P is the bit width of the original sampling result; N is the bit width of the correction coefficient before truncation; L is the bit width of the sampling result after truncation; and T is the bit width of the correction coefficient after truncation.

[0065] Errors caused by the finite bit width of the multiplier average with mean square value The expression is:

[0066] (4)

[0067] (5).

[0068] An approximate compressed tree is designed to replace the exact compressed tree. Specifically, the partial products generated during the multiplier calculation are plotted as a partial product array. Some of the least significant bits in the partial product array are discarded, forming a simplified partial product array. The error generated by the approximate compressed tree of the multiplier is thus reduced. It increases with the number of bits discarded;

[0069] Error caused by high-order truncation during successive summation average with mean square value The expression is:

[0070] (6)

[0071] (7)

[0072] Where W is the output bit width of the multiplier;

[0073] , and These three errors are independent of each other, so the total calculation error is... mean square value The sum of the mean square values ​​of all errors is calculated using the following formula:

[0074] (8)

[0075] in, This represents the computational error caused by the truncation of the operand width in the i-th multiplier; This indicates the computational error of the i-th multiplier caused by using an approximate compressed tree; This represents the calculation error caused by truncation of the output bit width of the i-th multiplier; K is the order of the correction filter.

[0076] By calculating the upper limit of error mean square value The error is allocated among three factors to determine the circuit architecture, while simultaneously satisfying the total calculation error. Not exceeding the upper limit of calculation error .

[0077] Step 3: Use a compressor to compress the terms to be summed in each channel of the correction filter step by step, and use an adder to complete the final summation to obtain the correction result of the current sampling point, thus completing the correction of the mismatch error of the TIADC system.

[0078] In this step, the terms to be summed in each channel of the correction filter include: the summation correction results of the outputs of K approximate multipliers. and carry correction results DC bias error correction item and the original sampling results of the current sampling point ;

[0079] The compressor includes 2-2 compressors, 3-2 compressors, and 4-2 compressors, used to compress multiple terms to be summed into a sum result and a carry result;

[0080] The final corrected output result for the current sampling point is obtained by summing the output of the compressor and the carry result using a binary adder. The expression is:

[0081] (9)

[0082] in, This is the summation result output by the compressor; This is the carry result output by the compressor.

[0083] It is worth noting that the contents not described in detail in the embodiments of the present invention belong to the prior art known to those skilled in the art.

[0084] The method described in this invention will be explained in detail below with a specific example. This example involves the optimized design of a digital correction circuit for mismatch error in a four-channel 16Gsps 12-bit TIADC system, such as... Figure 2The diagram shows the schematic of the TIADC system, an example of this invention. The core of this TIADC system consists of four 4 Gsps 12-bit ADC chips. The sampling clocks of the four ADCs are 90° out of phase, and the sampling rate of a single ADC is one-quarter of the system's equivalent sampling rate. During operation, the input signal is simultaneously input to all four ADCs for sampling, and then the outputs of the four ADCs are concatenated according to the sampling order. In actual circuits, due to differences in the delay before the input signal enters the ADC, the inability to strictly guarantee a 90° phase difference between the four sampling clocks, and the inevitable differences in the gain and bias of the four ADCs, the concatenated signal is distorted. For example... Figure 3 The diagram shown is a schematic of the TIADC mismatch error digital correction circuit, an example of the present invention. It consists of 60 parallel-operating filters, each of which includes 80 multipliers and summing circuits, forming an 80th-order filter.

[0085] The method for correcting mismatch errors in the TIADC system described in this embodiment of the invention optimizes the resources of the digital correction circuit, including the following steps:

[0086] Step 1: Through actual measurement, literature review, and device datasheet consultation, determine the variation range of the actual mismatch error at multiple frequency points within a reasonable range. The gain error variation range is as follows: The sampling clock phase error variation range is The bias error varies within the range of .

[0087] In this embodiment, the gain error range is [0.96 : 1.04], the sampling clock phase error range is [-20 ps : 20 ps], and the bias error range is [-0.05 : 0.05].

[0088] Step 2: Randomly select multiple values ​​for the mismatch error within the above-mentioned mismatch error range to generate multiple sets of mismatch errors, and simulate to generate corresponding multi-frequency sampling waveform data containing mismatch errors;

[0089] In this embodiment, 100 sets of mismatch error parameters are generated through simulation, and corresponding sampling waveform data containing mismatch error at multiple frequency points are produced.

[0090] Step 3: Correct multiple sets of sampled waveform data containing mismatch errors using the perfect reconstruction algorithm, machine learning algorithm, or other TIADC mismatch error correction algorithms to obtain multiple sets of theoretical values ​​of correction coefficients;

[0091] In this embodiment, based on the 100 sets of waveform data containing mismatch errors obtained in step 1, the theoretical values ​​of 100 sets of correction coefficients are calculated using the TIADC mismatch error correction algorithm based on machine learning methods.

[0092] Step 4: Calculate the mean and standard deviation of each correction coefficient;

[0093] In this embodiment, the analysis results are as follows: Figure 4 and Figure 5 As shown, Figure 4 This is a schematic diagram showing the average values ​​of the correction coefficients in the examples given in this invention. Figure 5 This is a schematic diagram of the standard deviation of each correction coefficient in the example given in this invention.

[0094] Step 5: For the correction coefficient corresponding to the current sampling point whose average value approaches 1, subtract 1 from it and use the difference to replace the original correction coefficient;

[0095] In this embodiment, the 41st order coefficient is the correction coefficient corresponding to the current sampling point, and its average value is close to 1.

[0096] Step 6: Truncate the lower bits of the correction coefficients according to the standard deviation of each order, while retaining the sign bit, to determine the input bit width of the correction coefficients in each multiplier;

[0097] In this embodiment, the correction coefficients from order 0 to order 27 are truncated to 8 bits, the correction coefficients from order 28 to order 35 are truncated to 10 bits, the correction coefficients from order 36 to order 43 are truncated to 16 bits, the correction coefficients from order 44 to order 51 are truncated to 10 bits, and the correction coefficients from order 52 to order 79 are truncated to 8 bits.

[0098] Step 7: Based on the dynamic performance indicators of a single ADC (such as signal-to-noise ratio) ), and the range of dynamic performance loss (such as reduced confidence-to-satisfaction ratio) allowed by the correction calculation error of the TIADC system. The upper limit of the allowable calculation error during the correction process is calculated. ;

[0099] In this embodiment, the SINAD of the ADC is 62 dB across the entire frequency range of the input signal; the allowable correction calculation error results in a SINAD loss of 0.3 dB.

[0100] By normalizing the ADC range to [0:1] and setting the input signal amplitude to -1 dBFS, the upper limit of the allowable calculation error during the calibration process can be calculated. The mean square value is 4.48 × 10⁻⁶. -9 .

[0101] Step 8: Three methods are used to reduce the resource consumption of the correction calculation process: raw sampling results of the multiplier input. Perform high-level truncation on the correction coefficients. Low-order truncation is performed to reduce the multiplier bit width; when partial product is performed in the compressed multiplier, an approximate compressed tree is designed instead of an exact compressed tree to reduce the number of compressors; during the summation of the outputs of each channel multiplier, the output bit width is reduced step by step to reduce the size of the summation circuit.

[0102] The correction error terms for the three methods described above are calculated: the error caused by the finite bit width of the multiplier. Errors generated by multiplier approximation of compressed tree Errors caused by high-order truncation during the successive summation process Clarify the expressions for the changes in each error term and circuit structure parameters;

[0103] Upper limit of allowable calculation error The allocation is made among the three error terms mentioned above;

[0104] Based on the error allocation results and error analysis, the bit width of the corrected sample value in the multiplier was finally determined, the design of the approximate compressed tree of the multiplier was completed, and the truncation bit width of each stage in the stepwise summation process was determined.

[0105] In this embodiment, the upper limit of the calculation error will be... Divide equally among the three error terms, namely:

[0106]

[0107] like Figure 6 The diagram shown is a schematic diagram of the overall architecture of the digital correction circuit provided in an embodiment of the present invention.

[0108] The 0th to 27th order correction sampling points are truncated to 8 bits, the 28th to 35th order correction sampling points are truncated to 10 bits, the 36th to 43rd order correction sampling points are truncated to 12 bits, the 44th to 51st order correction sampling points are truncated to 10 bits, and the 52nd to 79th order correction sampling points are truncated to 8 bits.

[0109] The correction filter consists of 56 8-bit × 8-bit multipliers, 16 10-bit × 10-bit multipliers, 8 12-bit × 16-bit multipliers, and a summing circuit.

[0110] The multiplier uses a radix-4 Booth multiplier and an optimization method with sign bit extension to reduce the number of compressors required;

[0111] like Figure 7The diagram shown is an approximate compressed tree diagram of an 8-bit × 8-bit multiplier according to an example of the present invention, ignoring some product symbols within the dashed boxes from the 0th to the 6th least significant bits in the product array diagram;

[0112] like Figure 8 The diagram shown is an approximate compressed tree diagram of the 10-bit × 10-bit multiplier of the present invention, ignoring some product symbols within the dashed boxes from the 0th to the 8th least significant bits in the product array diagram;

[0113] like Figure 9 The diagram shown is an approximate compressed tree diagram of the 12-bit × 16-bit multiplier of the present invention, ignoring some product symbols within the dashed boxes from the 0th to the 12th least significant bits in the product array diagram;

[0114] The output width of an 8-bit × 8-bit multiplier is 9 bits; the output width of a 10-bit × 10-bit multiplier is 11 bits; and the output width of a 12-bit × 16-bit multiplier is 14 bits.

[0115] Step 9: Use a compressor to compress the terms to be summed in each channel of the filter step by step, and use an adder to complete the final summation to obtain the correction result of the current sampling point;

[0116] In this example, the term to be summed includes: the summation and correction results of the outputs of K approximate multipliers. and carry correction results DC bias error correction item and the original sampling results of the current sampling point ;

[0117] Design a compression tree using 2-2, 3-2, and 4-2 compressors to compress the multiple terms to be summed into a single summation result and a carry result.

[0118] The final corrected output result of the current sampling point is obtained by summing the output of the compressor and the carry result using a hybrid carry adder.

[0119] This example synthesizes the filter circuit. According to the synthesis results, compared with the original circuit, the area of ​​the optimized correction circuit is reduced by 80.3% and the power consumption is reduced by 81.0%.

[0120] This example selects a sine wave ranging from 250 MHz to 7450 MHz as the input signal test frequency. The aforementioned 16-Gsps 12-bit TIADC system is used to perform parallel alternating sampling of the sine wave at multiple frequency points. The output data from each channel is interleaved and spliced ​​before being passed through an 80th-order filter. The filter coefficients are those obtained after training and stabilization. The waveform data output by the filter is the corrected waveform data. Spectral analysis is performed on the waveform data from the single-chip ADC, the waveform data before correction, the waveform data obtained by correcting the original sampling results using high-precision floating-point correction coefficients, and the correction result obtained using the optimized correction filter of this method. The signal-to-noise ratio (SNR) versus input signal frequency curve is obtained, as shown below. Figure 10 The diagram shows the signal-to-noise ratio (SNR) versus input signal frequency before and after correction according to an embodiment of the present invention. The SNR of the single-chip ADC is 62 dB. The average SNR of the correction result using floating-point correction coefficients is 61.84 dB. The average SNR of the correction result using the resource-optimized filter is 61.60 dB, with a SNR loss of 0.24 dB, which is in line with expectations. Figure 10 As can be seen, after calibration, the dynamic performance of the TIADC system is significantly improved compared to before calibration, and the accuracy loss caused by resource optimization is within an acceptable range.

[0121] In summary, the embodiments of the present invention reduce the bit width of the multipliers in the filter and design an approximate compressed tree structure, separating the current sampling point from the correction result, thereby reducing the size of the digital correction circuit. This achieves the goal of reducing the resource consumption of the digital correction circuit while ensuring correction accuracy. It has good effectiveness, practicality and scalability, and is easy to integrate into hardware, with obvious advantages in hardware overhead.

[0122] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims. The information disclosed in the background section is intended only to enhance the understanding of the overall background technology of the present invention and should not be construed as an admission or implication in any way that such information constitutes prior art known to those skilled in the art.

Claims

1. A design method for a mismatch error correction circuit in a TIADC system, characterized in that, The method includes: Step 1: For the mismatch error correction circuit of the Time-Interleaved Analog-to-Digital Converter (TIADC) system, determine the bit width of the correction coefficients in the multiplier according to the distribution law of the coefficients of each order of the correction filter; wherein, the digital correction circuit consists of Z parallel correction filters, each correction filter consists of K multipliers and summing circuits, forming a K-order filtering process for the original sampling result. Step 2: Based on the dynamic performance indicators of the single-chip analog-to-digital converter (ADC) and the noise requirements of the TIADC system, determine the bit width of the correction sampling value in the multiplier, design the approximate compressed tree structure of the multiplier, and determine the truncation bit width in the step-by-step summation process of the multiplier output. Step 3: Use a compressor to compress the terms to be summed in each channel of the correction filter step by step, and use an adder to complete the final summation to obtain the correction result of the current sampling point, thus completing the correction of the mismatch error of the TIADC system.

2. The design method of the mismatch error correction circuit for the TIADC system according to claim 1, characterized in that, In step 1, the specific filtering process of the digital correction circuit is as follows: （1） in, Indicates after the first The corrected sampling result output by each correction filter; Indicates the first The correction filter is the first One original sampling result; Indicates the first The correction filter is the first One correction factor; Indicates the first The bias error correction result of the correction filter; K is the order of the correction filter; The process of determining the bit width of the correction coefficients in the multiplier based on the distribution pattern of the coefficients of each order of the correction filter is as follows: The range of mismatch error variation of the TIADC system under multiple frequency points was determined by experimental measurement and literature review. The gain mismatch error, bias mismatch error, and sampling clock phase mismatch error of the analog-to-digital converter are randomly selected multiple times within the range of variation to generate multiple sets of mismatch errors, and the corresponding sampling waveform data containing mismatch errors at multiple frequency points are simulated. The TIADC mismatch error correction algorithm is used to correct multiple sets of sampled waveform data containing mismatch errors, and multiple sets of correction coefficients are obtained. Among them, the TIADC mismatch error correction algorithm includes a perfect reconstruction algorithm or a machine learning algorithm. The average value and standard deviation of each correction coefficient are calculated. For the correction coefficient corresponding to the sampling point whose average value is close to 1, 1 is subtracted from the correction coefficient and the difference is used to replace the original correction coefficient. The lower bits of the correction coefficients are truncated based on the standard deviation of each correction coefficient, while the sign bit is retained, to determine the input bit width of the correction coefficients in the multiplier.

3. The design method of the TIADC system mismatch error correction circuit according to claim 2, characterized in that, The mismatch error of the TIADC system includes: , and ; This represents the gain error of the m-th ADC channel under a sinusoidal input with frequency f; This represents the sampling clock phase error of the m-th ADC channel under a sinusoidal input with frequency f; This represents the bias error of the m-th ADC channel under a sinusoidal input with frequency f; bias error It is a fixed value, and and It changes with the frequency of the input signal; Gain error The range of variation is Sampling clock phase error The range of variation is Bias error The range of variation is ;in, This represents the minimum gain error under a sinusoidal input with frequency f; This represents the maximum gain error under a sinusoidal input with frequency f; This represents the minimum value of the sampling clock phase error under a sinusoidal input with frequency f; This represents the maximum value of the sampling clock phase error under a sinusoidal input with frequency f; This represents the minimum value of the bias error; This represents the maximum value of the bias error.

4. The design method of the TIADC system mismatch error correction circuit according to claim 2, characterized in that, The generated sets of mismatch errors are randomly selected independently, and the sampled waveform data containing the mismatch errors are represented as follows: （2） in, , and These represent the amplitude, angular frequency, and phase of the input sine wave, respectively. This represents the sampling time of the i-th sampling point; This represents the gain error of the m-th ADC channel under a sinusoidal input of frequency f, obtained by randomly sampling the j-th mismatch error. This represents the sampling clock phase error of the m-th ADC channel under a sinusoidal input of frequency f, obtained by randomly sampling the j-th mismatch error. This represents the bias error of the m-th ADC channel under random sampling of the j-th mismatch error; This represents the i-th sampled data of the m-th channel under a sinusoidal input of frequency f, obtained by random sampling of the j-th mismatch error.

5. The design method of the mismatch error correction circuit for the TIADC system according to claim 2, characterized in that, The process of truncating the lower bits of the correction coefficients based on the standard deviation of each order of correction coefficients while retaining the sign bit to determine the input bit width of the correction coefficients in the multiplier is as follows: When the correction factor is not truncated, the correction factor Represented by N being a fraction smaller than a specific point, the format is as follows: C[C0C1C2……C N-1 ] Where C0 is the sign bit and C1 has a weight of 2. 0 The C2 weight is 2. -1 And so on, C N-1 Weight 2 2-N When the correction coefficient is not truncated, its range is [-2: 2-2]. 2-N ]; After truncating the original N-bit correction coefficient by T bits (lower bits), the truncated correction coefficient C' is obtained, represented in the following format: C’[C0C N-T+1 C N-T+2 ……C N-1 ] Where C0 is the sign bit, C N-T+1 Weight 2 T-N C N-T+2 Weight 2 T-N-1 The rest follow the same pattern; the range of the truncated correction coefficient C' is [-2]. 1+T-N :2 1+T-N -2 2-N ]; The number of truncation points T should be selected such that the range of the truncated correction coefficient C' covers at least 6 times the standard deviation of the correction coefficient.

6. The design method of the mismatch error correction circuit for the TIADC system according to claim 1, characterized in that, The process of step 2 is as follows: Based on the dynamic performance specifications of a single ADC and the range of dynamic performance loss due to the allowable correction calculation error of the TIADC system, the upper limit of the allowable calculation error during the correction process is calculated. ; Raw sampling results of the multiplier input By truncating the high-order bits and reducing the multiplier's bit width, the error caused by the multiplier's limited bit width can be calculated. ;in, Indicates the first The correction filter is the first One original sampling result; When compressing the partial product in the multiplier, an approximate compressed tree is designed instead of an exact compressed tree, and the error generated by the approximate compressed tree of the multiplier is calculated. ; During the summation of the outputs of each channel multiplier, the output bit width of the multiplier is reduced, and the error caused by the high-order bit truncation during the step-by-step summation process is calculated. ; Calculate the upper limit of error Assigned to three independent errors , and Based on the error allocation results and error analysis, the bit width of the corrected sample value in the multiplier is determined, the design of the approximate compressed tree of the multiplier is completed, and the truncation bit width of each stage in the step-by-step summation process is determined.

7. The design method of the mismatch error correction circuit for the TIADC system according to claim 6, characterized in that, Upper limit of allowable calculation error during the calibration process The calculation method is as follows: （3） in, To calculate the upper limit of error The mean square value; This indicates the loss of signal-to-noise ratio in the TIADC system due to calculation errors during the calibration process; This indicates the signal-to-noise ratio of a single-chip ADC; This represents the energy of a sinusoidal signal.

8. The design method of the mismatch error correction circuit for the TIADC system according to claim 7, characterized in that, Errors caused by the finite bit width of the multiplier The calculation process is as follows: Original sampling results A P-bit unsigned number is represented as follows: ； Where S0 is the most significant bit of the sampling result, S1 is the second most significant bit of the sampling result, and so on. P-1 It is the least significant bit of the sampling result; the original sampling result The range of the expression is [0:1-2]. -P ]; For the original sampling results The most significant L bits are truncated to obtain the truncated sampling result. , is represented as: ； Among them, S L-1 It is the least significant bit of the truncated sampling result; truncated sampling result The range of the expression is [0:1-2]. -L ]; By truncating the original sampling results and correction coefficients, the operation bit width of the multiplier is reduced from the original P bits × N bits to L bits × T bits; where P is the bit width of the original sampling result; N is the bit width of the correction coefficient before truncation; L is the bit width of the sampling result after truncation; and T is the bit width of the correction coefficient after truncation. Errors caused by the finite bit width of the multiplier average with mean square value The expression is: （4） （5）。 9. The design method of the mismatch error correction circuit for the TIADC system according to claim 8, characterized in that, An approximate compressed tree is designed to replace the exact compressed tree. Specifically, the partial products generated during the multiplier calculation are plotted as a partial product array. Some of the least significant bits in the partial product array are discarded, forming a simplified partial product array. The error generated by the approximate compressed tree of the multiplier is thus reduced. It increases with the number of bits discarded; Error caused by high-order truncation during successive summation average with mean square value The expression is: （6） （7） Where W is the output bit width of the multiplier; , and These three errors are independent of each other, so the total calculation error is... mean square value The sum of the mean square values ​​of all errors is calculated using the following formula: （8） in, This represents the computational error caused by the truncation of the operand width in the i-th multiplier; This indicates the computational error of the i-th multiplier caused by using an approximate compressed tree; This represents the calculation error caused by truncation of the output bit width of the i-th multiplier; K is the order of the correction filter. By calculating the upper limit of error mean square value The error is allocated among three factors to determine the circuit architecture, while simultaneously satisfying the total calculation error. Not exceeding the upper limit of calculation error .

10. The design method of the mismatch error correction circuit for the TIADC system according to claim 1, characterized in that, In step 3, the terms to be summed in each channel of the correction filter include: the summation correction results of the outputs of K approximate multipliers. and carry correction results DC bias error correction item and the original sampling results of the current sampling point ; The compressor includes 2-2 compressors, 3-2 compressors, and 4-2 compressors, used to compress multiple terms to be summed into a sum result and a carry result; The final corrected output result for the current sampling point is obtained by summing the output of the compressor and the carry result using a binary adder. The expression is: （9） in, This is the summation result output by the compressor; This is the carry result output by the compressor.

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