Intelligent test method based on AFDX bus module

Abstract

The invention provides an intelligent test method based on an AFDX (avionics full duplex switched Ethernet) bus module, which belongs to the technical field of avionics network communication and comprises the following steps: automatically generating and inserting configurable frame counting parameters through a frame counting management module; generating a high-precision time scale based on a programmable clock source and resolution through a frame time scale management module; based on a BAG and GAP cooperation mechanism, cyclic transmission of data frames of multiple sub-ports under the same virtual link is realized. According to the testing method, a plurality of sub-port data frames can be sent in the same BAG period through a GAP mechanism, the bandwidth utilization rate is improved by 300%-400%, and compared with a traditional frame counting and time mark parameter manual configuration method, the accuracy of frame counting and time mark counting is improved, and errors caused by manual configuration are reduced.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of avionics network communication, and particularly relates to an intelligent testing method based on an AFDX bus module. BACKGROUND

[0002] In an avionics system, the ARINC664-P7 protocol is widely used for data transmission between end systems (ES), and determines communication through a virtual link (VL). In a traditional scheme, the bandwidth allocation of each virtual link is controlled through a bandwidth allocation interval (BAG), but the following problems exist: Low transmission efficiency: multiple sub-ports under the same virtual link need to occupy multiple BAG cycles to complete data frame transmission, resulting in insufficient bandwidth utilization.

[0003] Poor flexibility: frame counting and time scale management rely on manual configuration, making it difficult to support automatic adjustment in a dynamic network environment.

[0004] Lack of intelligent error injection: the traditional scheme cannot flexibly simulate various communication errors (such as SN number errors, IP check errors, etc.), limiting the comprehensiveness of system testing. SUMMARY

[0005] The purpose of the present application is to solve the problems existing in the prior art, and to provide a technical scheme supporting automatic data frame addition, automatic cyclic transmission and efficient flow control.

[0006] In order to achieve the above purpose, the present application provides the following technical scheme, an intelligent testing method based on an AFDX bus module, comprising: A frame counting management module automatically generates and inserts configurable frame counting parameters; A frame time scale management module generates high-precision time scales based on programmable clock sources and resolutions; Based on the BAG and GAP cooperative mechanism, the cyclic transmission of data frames of multiple sub-ports under the same virtual link is realized.

[0007] The intelligent testing method based on the AFDX bus module provided by the present application also has the following technical features, the frame counting management module automatically generates and inserts configurable frame counting parameters, comprising: The user sends data according to the data queue generated by the host ICD, and the data includes frame counting bits, and the data is sorted according to the data frame size; The frame counting management module generates data frames according to the software dynamic configuration of frame counting feature types in the data and inserts them into the data; The data is arranged according to the frame counting to finally form a data queue.

[0008] The AFDX bus module intelligent test method provided by the application further has the technical features that the high-precision time mark is generated based on the programmable clock source and resolution by the frame time mark management module, and the high-precision time mark includes: The user generates a data queue according to the host ICD, and the data includes a time mark bit; The frame time mark management module adds the high-precision time mark to the time mark data bit corresponding to the data frame through the clock source according to the time mark data bit in the data; The data is arranged according to the frame count to finally form a data queue with a time mark, a data bit and a frame count.

[0009] The AFDX bus module intelligent test method provided by the application further has the technical features that the frame count management module supports eight independently configured frame counts.

[0010] The AFDX bus module intelligent test method provided by the application further has the technical features that the value range of the GAP is within 260 ms.

[0011] The AFDX bus module intelligent test method provided by the application further has the technical features that the value range of the BAG is 1 ms-4000 ms.

[0012] Beneficial effects: The test method provided by the application can send multiple sub-port data frames in the same BAG cycle through the GAP mechanism, and the bandwidth utilization rate is improved by 300%-400%. Compared with the traditional manual configuration method of frame count and time mark parameters, the method improves the accuracy of the frame count and the time mark count, and reduces the error caused by manual configuration. The technical solution provided by the application designs a high-efficiency and high-precision clock module through the design method of BAG and GAP, which is used to provide accurate clock technology for each virtual link and ensure the accurate control of the output traffic. The technical support is provided for the cyclic transmission of each virtual link. Compared with simple data cyclic transmission, the problem of insufficient bandwidth utilization is avoided. BRIEF DESCRIPTION OF DRAWINGS

[0013] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings needed in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor.

[0014] Figure 1 It is the maximum bandwidth data packet stream in the VL embodiment of the application; Figure 2 It is the non-maximum bandwidth data packet stream in the VL embodiment of the application; Figure 3 Figure 1 is a Sub-VLFIFO queue diagram in an embodiment of the present application; Figure 4 Figure 2 is a traffic data diagram on a VL in an embodiment of the present application. DETAILED DESCRIPTION

[0015] The present application will be further described below in conjunction with the accompanying drawings and embodiments, but it should be noted that these embodiments are not a limitation on the present application, and equivalent transformations or substitutions of function, method, or structure made by those of ordinary skill in the art based on these embodiments are within the scope of the present application.

[0016] In the description of the embodiments of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0017] In addition, the terms "first", "second", "third", and the like are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined with "first", "second", and the like can explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise stated, the meaning of "a plurality of" is two or more.

[0018] The terms "mounting", "connection", and "connection" should be broadly understood, for example, it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, or it can be a communication between two elements inside. For those of ordinary skill in the art, the specific meaning of the above terms in the present application can be understood through specific circumstances.

[0019] As shown in FIG. 1, an embodiment of the present application provides a method for intelligent testing of an AFDX bus module, comprising: Figures 1-4 generating and inserting configurable frame count parameters automatically through a frame count management module; generating high-precision time stamps based on programmable clock sources and resolutions through a frame time stamp management module; Based on the BAG and GAP cooperative mechanism, the cyclic transmission of data frames of multiple sub-ports under the same virtual link is realized. ​

[0020] In some embodiments, the configurable frame count parameter is automatically generated and inserted by the frame count management module, including: The user sends data in order according to the data frame size of the data queue generated by the host ICD, and the data includes frame count bits; The frame count management module generates and inserts data frames according to the software dynamically configured frame count feature type in the data; The data is arranged according to the frame count to finally form a data queue.

[0021] In some embodiments, the high-precision timestamp is generated by the frame timestamp management module based on a programmable clock source and resolution, including: The user sends data in order according to the data queue generated by the host ICD, and the data includes timestamp bits; The frame timestamp management module adds high-precision timestamps to the timestamp data bits of the data frame through the clock source according to the timestamp data bits in the data; The data is arranged according to the frame count to finally form a data queue with timestamp, data bits, and frame count.

[0022] In some embodiments, the frame count management module supports 8 independently configured frame counts, including size end, length (0-2 bytes), resolution (1-32768), and initial value. The frame count is dynamically configured by software in the data message to configure the frame count marker bit or frame count feature data type, to automatically generate and insert the frame count in the sent data.

[0023] In some embodiments, the frame timestamp clock management module provides 3 clock sources (1 μs, 5 μs, 50 μs) and programmable resolution (1-32768), combined with special address area management, to automatically add high-precision timestamps (48 bits) to data frames and reduce FPGA resource consumption.

[0024] In some embodiments, the GAP (port transmission interval) defines the transmission interval of adjacent sub-port frames in the same VL within 260 ms, to achieve the cyclic transmission of all sub-port data frames in the same VL within a single BAG cycle.

[0025] In some embodiments, the BAG (bandwidth allocation interval) defines the starting time interval of the same port frame in the same virtual link (VL), with a value range of 1 ms-4000 ms.

[0026] In some embodiments: If a VL contains 4 sub-ports (addresses 1000-1003), BAG=50 ms, and GAP=10 ms, the transmission sequence is: Within the BAG0 cycle, sub-ports 1000 (0ms), 1001 (10ms), 1002 (20ms), and 1003 (30ms) are sent sequentially; The next cycle begins after BAG1 (50ms), and so on.

[0027] like Figure 1 The diagram shows the maximum bandwidth data packet stream in a VL, reflecting the minimum time interval between the starting bits of two adjacent frames of the maximum bandwidth data in the same virtual link (VL).

[0028] like Figure 2 The diagram shows a non-maximum bandwidth data packet stream in VL, reflecting the minimum time interval between the starting bits of two adjacent frames in a non-maximum bandwidth state.

[0029] like Figure 3 The diagram shown is a Sub-VL FIFO queue diagram, which reflects how each Sub-VL is read out by the main FIFO in a first-in-first-out manner based on polling (based on MAC frames).

[0030] like Figure 4 The diagram shown is a traffic data graph on VL, reflecting the data arrangement of the data stream after each data frame is polled individually.

[0031] In some embodiments, the frame counting management module and the frame timing management module support dual redundant channels (4 RJ45 interfaces), each channel includes network A / B, with 128 virtual links, and each VL supports 4 sub-virtual links. They are integrated into the FPGA and achieve low-latency access through a dedicated address area.

[0032] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention. The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the protection scope of the present invention.

Claims

1. An intelligent testing method based on an AFDX bus module, characterized in that, include: The frame count management module automatically generates and inserts configurable frame count parameters. The frame time stamp management module generates high-precision time stamps based on a programmable clock source and resolution. Based on the BAG and GAP collaborative mechanism, the cyclic transmission of data frames from multiple sub-ports under the same virtual link is realized.

2. The intelligent testing method based on the AFDX bus module according to claim 1, characterized in that, The automatic generation and insertion of configurable frame count parameters by the frame count management module includes: The user sends data according to the data queue generated by the host ICD, which includes frame count bits, and sorts the data according to the data frame size. The frame counting management module generates and inserts data frames into the data based on the frame counting feature type dynamically configured by the software in the data. The data is arranged according to the frame count to form a data queue.

3. The intelligent testing method based on the AFDX bus module according to claim 1, characterized in that, The generation of high-precision time stamps based on a programmable clock source and resolution via the frame time stamp management module includes: The user generates a data queue according to the host ICD, and the data includes time stamp bits; The frame time stamp management module adds high-precision time stamps to the corresponding time stamp data bits in the data frame using a clock source, based on the time stamp data bits in the data. The data is arranged according to the frame count to form a data queue with a timestamp, data bits, and frame count.

4. The intelligent testing method based on the AFDX bus module according to claim 1, characterized in that, The frame count management module supports eight independently configured frame counts.

5. The intelligent testing method based on the AFDX bus module according to claim 1, characterized in that, The value of GAP is within 260ms.

6. The intelligent testing method based on the AFDX bus module according to claim 1, characterized in that, The value of BAG ranges from 1ms to 4000ms.

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