Energy storage power supply and hardware communication circuit thereof

Abstract

The invention discloses an energy storage power supply and a hardware communication circuit thereof. The hardware communication circuit comprises a main control chip, a pull-up resistor, a digital potentiometer and a USB control circuit. A USB control chip is arranged in the USB control circuit; the digital potentiometer is connected to a communication bus between the main control chip and the USB control chip; the pull-up resistor is connected to a communication bus between the main control chip and the digital potentiometer; the main control chip is used for generating a communication control signal to the USB control chip; and the main control chip is also used for sending a digital signal to the digital potentiometer to adjust the resistance value of the digital potentiometer so as to dynamically adjust the resistance value of the pull-up resistor and adapt to the communication rate of the communication control signal under different load conditions. According to the hardware communication circuit, the main control chip dynamically adjusts the resistance value of the pull-up resistor by adjusting the resistance value of the digital potentiometer so as to adapt to the communication rate of the communication control signal under different load conditions, and the communication quality of the communication bus under different load conditions is enhanced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of energy storage, in particular to an energy storage power supply and a hardware communication circuit thereof BACKGROUND

[0002] At present, communication control between a main control chip (MCU) in a main control board of a portable outdoor power supply and a USB control circuit mostly adopts an Inter-Integrated Circuit (IIC) communication. The IIC communication mode has simple communication circuit resources, simple software communication timing and fast transmission speed. The IIC communication mode becomes a mainstream choice for short-distance low-speed communication in an embedded system due to its simplicity, support for multiple load devices and low hardware cost, and is particularly suitable for scenarios with limited pin resources.

[0003] However, various types of strong magnetic field interference circuits exist on and around the main control board, which is a great source of communication signal interference and can seriously interfere with the IIC communication on the main control board, increase the communication error rate and even stop the communication. Therefore, how to improve the anti-interference ability of the IIC communication between the main control chip and the USB control circuit of the main control board and the communication quality is a problem to be solved. SUMMARY

[0004] In view of this, the present application aims to at least partially solve one of the problems in the related art. To this end, the purpose of the present application is to provide an energy storage power supply and a hardware communication circuit thereof.

[0005] The present application provides a hardware communication circuit of an energy storage power supply. The hardware communication circuit comprises a main control chip, a pull-up resistor, a digital potentiometer and a USB control circuit. The USB control circuit is provided with a USB control chip; the digital potentiometer is connected to a communication bus between the main control chip and the USB control chip; the pull-up resistor is connected to the communication bus between the main control chip and the digital potentiometer; the main control chip is used to generate a communication control signal to the USB control chip; the main control chip is also used to send a digital signal to the digital potentiometer to adjust the resistance value of the digital potentiometer, so as to dynamically adjust the resistance value of the pull-up resistor and adapt the communication rate of the communication control signal under different load conditions.

[0006] The present application also provides an energy storage power supply. The energy storage power supply comprises the hardware communication circuit described in the above embodiments.

[0007] Thus, the hardware communication circuit of the energy storage power supply of the present application is increased with a digital potentiometer and a pull-up resistor, the master control chip sends a digital signal to the digital potentiometer to adjust the resistance value of the digital potentiometer, so as to dynamically adjust the resistance value of the pull-up resistor, adapt the communication rate of the communication control signal under different load conditions, enhance the communication quality of the communication bus under different load conditions, improve the communication reliability of the communication bus between the master control chip and the USB control chip in a strong electromagnetic interference environment, and improve the power supply quality of the energy storage power supply.

[0008] Additional aspects and advantages of the present application will be in part apparent and in part pointed out hereinafter. BRIEF DESCRIPTION OF DRAWINGS

[0009] The above and / or additional aspects and advantages of the present application will become apparent and be readily appreciated from the following description, including the accompanying drawings, wherein:

[0010] Figure 1 is a structural schematic diagram of the hardware communication circuit of the energy storage power supply of certain embodiments of the present application;

[0011] Figure 2 is a flowchart schematic diagram of the hardware communication circuit of the energy storage power supply of certain embodiments of the present application in operation. DETAILED DESCRIPTION

[0012] The embodiments of the present application are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar notations represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by reference to the accompanying drawings are exemplary only, and are used only for explanation of the present application, and cannot be understood as a limitation of the present application.

[0013] In the description of the present application, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance, or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0014] In the description of the present application, it should be noted that, unless explicitly specified and limited, the terms "mounting", "connecting" should be understood in a broad sense, which can mean fixed connection, or detachable connection, or integral connection; can be mechanical connection, or electrical connection or can communicate with each other; can be directly connected, or indirectly connected through an intermediate medium, or the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0015] The following disclosure provides many different embodiments or examples for implementing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeatedly refer to numbers and / or letters in different examples, and such repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed.

[0016] The embodiments of the present application are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals represent the same or similar elements or elements with the same or similar functions throughout. The embodiments described below by referring to the accompanying drawings are exemplary, only for explaining the present application, and cannot be understood as limiting the present application.

[0017] Please refer to Figure 1 The present application provides a hardware communication circuit 100 of an energy storage power supply. The hardware communication circuit 100 comprises a master control chip 10, a pull-up resistor 20, a digital potentiometer 30 and a USB control circuit 40. The USB control circuit 40 is provided with a USB control chip 41. The digital potentiometer 30 is connected to the communication bus between the master control chip 10 and the USB control chip 41. The pull-up resistor 20 is connected to the communication bus between the master control chip 10 and the digital potentiometer 30. The master control chip 10 sends a communication control signal to the USB control chip 41, and the master control chip 10 is also used to send a digital signal to the digital potentiometer 30 to adjust the resistance value of the digital potentiometer 30, so as to dynamically adjust the resistance value of the pull-up resistor 20, and adapt the communication rate of the communication control signal under different load conditions.

[0018] Specifically, the communication bus between the master control chip 10 and the USB control chip 41 can be an integrated circuit bus (Inter-Integrated Circuit, IIC).

[0019] The master control chip 10 is configured to output a communication control signal to the USB control chip 41, and the USB control chip 41 is configured to convert the communication control signal into a differential communication signal and output the differential communication signal to the USB control circuit 40. The communication control signal can include configuration instructions and read state instructions. That is, the master control chip 10 sends configuration instructions or read state instructions, such as charging protocol and read voltage or current setting instructions, to the USB control chip 41 through the IIC bus (including the SDA data line and the SCL clock line).

[0020] The USB control circuit 41 executes the control instructions corresponding to the communication control signal sent by the master control chip 10, and returns the operation result to the master control chip 10 through the communication bus.

[0021] The pull-up resistor 20 can include resistors R1 and R2 as shown in Figure 1 The digital potentiometer 30 is an electronic element that controls the resistance value through a digital signal.

[0022] The master control chip 10 is also configured to send a digital signal to the digital potentiometer 30 to adjust the resistance value of the digital potentiometer 30, so as to dynamically adjust the resistance value of the pull-up resistor 20 and adapt the communication rate of the communication control signal under different load conditions. That is, the resistance value of the pull-up resistor 20 in the communication bus of the application can be dynamically adjusted by adjusting the resistance value in the digital potentiometer 30 through the master control chip 10, and then the communication rate of the communication control signal can be controlled by dynamically adjusting the resistance value of the pull-up resistor 20. The communication rate of the communication control signal under different load conditions also changes accordingly, thereby enhancing the communication quality of the communication bus, improving the communication reliability of the communication bus between the master control chip 10 and the USB control chip 41 in a strong electromagnetic interference environment, and improving the power supply quality of the energy storage power supply.

[0023] It can be understood that the resistance value of the pull-up resistor 20 in the communication bus of the application can be dynamically adjusted according to the number of load devices (load capacitances) connected to the USB control circuit 40. When the number of load devices increases, the capacitance of the communication bus increases, which may cause the edge of the communication control signal to become slow, for example, the rising or falling time of the communication control signal is too long. Increasing the pull-up resistance can speed up the signal edge speed, indirectly support higher communication rate of the communication bus or improve response delay, and enhance the communication quality of the communication bus when the number of loads is large. In addition, when the number of load devices decreases, increasing the resistance value of the pull-up resistor can slow down the signal edge speed, indirectly support lower communication rate of the communication bus, reduce the power consumption of the energy storage power supply, and also ensure the communication quality of the communication bus when the number of loads is small.

[0024] Or, the hardware communication circuit 100 of the energy storage power supply dynamically adjusts the core purpose of the pull-up resistor 20 through the master control chip 10 to realize dynamic optimization among communication signal integrity, power consumption, and compatibility, while enhancing the adaptive ability and reliability of the communication system.

[0025] In this way, the hardware communication circuit 100 of the energy storage power supply of the present application increases the digital potentiometer 30 and the pull-up resistor 20, and the master control chip 10 sends a digital signal to the digital potentiometer 30 to adjust the resistance value of the digital potentiometer 30, so as to dynamically adjust the resistance value of the pull-up resistor 20, adapt the communication rate of the communication control signal under different load conditions, enhance the communication quality of the communication bus under different load conditions, improve the communication reliability of the communication bus between the master control chip 10 and the USB control chip 41 in a strong electromagnetic interference environment, and improve the power supply quality of the energy storage power supply.

[0026] In some embodiments, a voltage dividing resistor 50 is provided between the master control chip 10 and the digital potentiometer 30, the first end of the voltage dividing resistor 50 is connected with the digital potentiometer 30 and the master control chip 10, and the second end of the voltage dividing resistor 50 is grounded. The master control chip 10 calculates the actual resistance value of the digital potentiometer 30 by detecting the resistance value of the voltage dividing resistor 50, and adjusts the resistance value of the digital potentiometer 30 according to the difference between the actual resistance value and the target resistance value.

[0027] It can be understood that when the number of load devices connected to the USB port controlled by the USB control circuit 40 of the energy storage power supply changes, the USB control circuit 40 can feed back the real-time load device connection state to the master control chip 10, so that the master control chip 10 can calculate the target value of the pull-up resistor 20 required according to the current number of load devices and a preset algorithm, so as to obtain the target resistance value of the digital potentiometer 30 required for adjustment. The preset algorithm can be a calculation formula of the pull-up resistor meeting the IIC communication standard.

[0028] The voltage dividing resistor 50 can include Figure 1 The first end of the resistor R3 is connected with the A1 pin of the master control chip 10 and the A1 pin of the digital potentiometer 30, and the second end of the resistor R3 is grounded. The first end of the resistor R4 is connected with the A0 pin of the master control chip 10 and the A0 pin of the digital potentiometer 30, and the second end of the resistor R4 is grounded.

[0029] Before the actual resistance value of the digital potentiometer 30 needs to be adjusted to the target resistance value, the host chip 10 can first calculate the actual resistance value of the digital potentiometer 30 by detecting the resistance value of the voltage dividing resistor 50. Then, according to the difference between the actual resistance value of the digital potentiometer 30 and the target resistance value of the digital potentiometer 30, the resistance value of the digital potentiometer 30 is adjusted to the target resistance value, so as to adjust the resistance value of the pull-up resistor 20 to the corresponding target value.

[0030] In some embodiments, the hardware communication circuit 100 further comprises a filter 60. The filter 60 is connected in series on the communication bus between the digital potentiometer 30 and the USB control chip 41, and the filter 60 is used to filter the communication control signal output by the host chip 10.

[0031] Specifically, the filter 60 can be an LC filter, and specifically can include a capacitor C1, a capacitor C2, an inductor L1, a capacitor C3, a capacitor C4 and an inductor L2 as shown in the following figure. Figure 1

[0032] That is, the hardware communication circuit 100 of the present application can also be provided with a filter 60 to filter the communication control signal output by the host chip 10, which can filter out noise and other bad factors affecting communication quality in the communication control signal, further improve the communication reliability of the communication bus between the host chip 10 and the USB control chip 41 in a strong electromagnetic interference environment, and improve the power supply quality of the energy storage power supply.

[0033] In some embodiments, the USB control circuit 40 is configured to convert the communication control signal into a differential communication signal through the USB control chip 41 after the USB control chip 41 receives the communication control signal, and when the starting byte and / or the ending byte of the current frame data in the differential communication signal do not conform to the corresponding self-defined specification, the USB control circuit 40 is configured to determine that the current frame data is invalid, and mark the current frame data as invalid frame data.

[0034] Specifically, the USB control chip 41 can include a level conversion circuit and a differential drive circuit inside, and can convert the logic signal into a differential pair conforming to the USB electrical specification, so that the USB control chip 41 can convert the communication control signal into a differential communication signal.

[0035] ​When the USB control chip 41 converts the communication control signal into the differential communication signal, the USB control circuit 40 checks whether the start byte and / or the end byte of the current frame data in the differential communication signal is inconsistent with the corresponding self-defined specification, and determines that the current frame data is invalid and marks the current frame data as invalid frame data if the start byte of the current frame data in the differential communication signal is inconsistent with the corresponding self-defined start byte specification, or if the end byte of the current frame data in the differential communication signal is inconsistent with the corresponding self-defined end byte specification, or if the start byte of the current frame data in the differential communication signal is inconsistent with the corresponding self-defined start byte specification and the end byte of the current frame data in the differential communication signal is inconsistent with the corresponding self-defined end byte specification.

[0036] In this way, the USB control circuit 40 of the application can mark the wireless frame data in the differential communication signal, and after marking, the error data can be prevented from being misused, and subsequent processing errors can be avoided, thereby further improving the power supply quality of the energy storage power supply.

[0037] In some embodiments, the USB control circuit 40 is further configured to, after the USB control chip 41 receives the communication control signal, convert the communication control signal into the differential communication signal by the USB control chip 41, and terminate receiving the current frame data and trigger a timeout fault signal when the end byte of the current frame data in the differential communication signal is not detected within a preset time.

[0038] Specifically, the preset time can be 490 μs, 500 μs, 501 μs, 502 μs, 504 μs, 505 μs, 506 μs, 507 μs, 509 μs or 510 μs, without limitation.

[0039] It can be understood that if the USB control circuit 40 does not detect the end byte of the current frame data in the differential communication signal within a long time, it indicates that the communication between the current master chip 10 and the USB control chip 41 fails, and the communication control signal transmitted by the master chip 10 is missing, resulting in no end byte.

[0040] Therefore, when the end byte of the current frame data in the differential communication signal is not detected within the preset time, the USB control circuit 40 can terminate receiving the current frame data and trigger a timeout fault signal, so that the power supply of the energy storage power supply to the load device is interrupted according to the fault signal, and other protection measures are triggered, so as to avoid damaging the load device.

[0041] In some embodiments, the USB control circuit 40 is further configured to, after the USB control chip 41 receives the communication control signal, convert the communication control signal into a differential communication signal through the USB control chip 41, verify the parity bit of the address byte of the differential communication signal, and if the parity bit of the address byte of the differential communication signal fails the verification, discard the data packet corresponding to the differential communication signal and send a retransmission signal to the host chip 10.

[0042] It can be understood that if the address byte is flipped (e.g., 0 to 1 or 1 to 0) due to interference, noise or hardware failure during transmission, the parity of the actual received address byte does not match the parity of the sending end, resulting in a parity check failure when verifying the parity bit of the IIC communication signal address byte.

[0043] Therefore, the USB control circuit 40 of the present application verifies the parity bit of the IIC communication signal address byte, and if the parity check fails, the current data packet corresponding to the differential communication signal is discarded, and a retransmission signal is returned to the host chip 10 through the SCL signal in Figure 1 , informing the host chip 10 to retransmit.

[0044] In this way, the data corresponding to the parity check failure is discarded as invalid data, which can prevent subsequent data from being sent to the wrong slave device and prevent misoperation. In addition, after discarding the invalid data packet, the USB control circuit 40 does not need to parse or respond to the error frame, which can save CPU computing resources (such as interrupt processing and protocol parsing) and bus bandwidth.

[0045] In some embodiments, the USB control circuit 40 is further configured to verify the parity bit of the address byte of the differential communication signal, and if the parity bit of the address byte of the differential communication signal passes the verification, the host chip 10 performs CRC verification on the data packet corresponding to the differential communication signal, and if the result of the CRC verification is correct, the control instruction corresponding to the communication control signal is executed and the operation result is returned to the host chip 10 through the communication bus.

[0046] Specifically, for example, after the USB control circuit 40 verifies the parity bit of the address byte of the differential communication signal, if the parity bit of the address byte of the differential communication signal passes the verification, the host chip 10 can calculate the CRC8 check value of the data packet content corresponding to the differential communication signal, and if the result of the CRC verification is correct, the USB control circuit executes the control instruction corresponding to the IIC communication control signal sent by the host chip 10 and returns the operation result to the host chip 10 through the bus.

[0047] CRC8 is a preset 8-order polynomial, and the final 1-byte (8-bit) check value is obtained by performing modulo 2 division on data. For example, the preset 8-order polynomial can be CRC-8 = x 8 +x 2 +x+1.

[0048] Therefore, the USB control circuit 40 can perform CRC check on the data packet corresponding to the differential communication signal after successfully checking the parity bit of the address byte of the differential communication signal. After the double check is correct, the USB control circuit 40 will execute the corresponding control instruction to achieve the enhancement effect of the communication signal at the communication protocol layer.

[0049] In some embodiments, the master control chip 10 is provided with an error counter, and the USB control circuit 40 is further configured to verify the parity bit of the address byte of the differential communication signal. If the parity bit of the address byte of the differential communication signal is successfully checked, the master control chip 10 performs CRC check on the data packet corresponding to the differential communication signal. If the result of the CRC check is an error, the error count of the error counter is increased by one. When the continuous error count in the error counter of the master control chip 10 exceeds a first preset number of times, a preset retransmission mechanism is triggered.

[0050] Specifically, the first preset number of times can be 4, 5 or 6, which is not limited. In detail, taking the first preset number of times as 5 as an example, if the master control chip 10 performs CRC check on the data packet corresponding to the differential communication signal, the result of the CRC check is an error, the error counter is increased by one. Once the continuous error count exceeds 5, the preset retransmission mechanism is triggered, so that the master control chip 10 retransmits the communication control signal to the USB control circuit 40 according to the preset retransmission mechanism.

[0051] Therefore, the hardware communication circuit 100 can automatically trigger the master control chip 10 to retransmit the communication control signal to the USB control chip 41 when the master control chip 10 performs CRC check and the result of the check is an error, even if the USB control circuit 40 successfully checks the parity bit of the address byte of the differential communication signal but the result of the CRC check on the data packet corresponding to the differential communication signal is an error. This enhances the communication quality of the IIC bus and improves the communication reliability of the IIC bus between the master control chip 10 and the USB control circuit 40 in a strong electromagnetic interference environment.

[0052] In some embodiments, the preset retransmission mechanism is an exponential backoff algorithm for automatic retransmission. The exponential backoff algorithm is an algorithm for retransmission at exponentially spaced intervals.

[0053] Specifically, the master chip 10 adopts an exponential backoff algorithm to retransmit the communication control signal. After the first retransmission of the communication control signal to the USB control chip 41, the master chip 10 retransmits the communication control signal to the USB control chip 41 again after an interval of 1 ms. After the second retransmission of the communication control signal to the USB control chip 41, the master chip 10 retransmits the communication control signal to the USB control chip 41 again after an interval of 2 ms. After the third retransmission of the communication control signal to the USB control chip 41, the master chip 10 retransmits the communication control signal to the USB control chip 41 again after an interval of 4 ms. This can avoid congestion of the communication bus, build a communication rate adjustment logic, and dynamically adjust the communication rate, for example, to reduce the communication rate to 100 kHz.

[0054] In this way, the master chip 10 of the application adopts the exponential backoff algorithm to automatically retransmit the communication control signal to the USB control chip 41, which can adjust the communication rate between the master chip 10 and the USB control circuit 40, achieve the effect of dynamically adjusting the communication rate, and improve the communication quality between the master chip 10 and the USB control circuit 40.

[0055] In some embodiments, when the master chip 10 retransmits the communication control signal to the USB control chip 41 more than the second preset number of times using the preset retransmission mechanism, if the result of the CRC check is still incorrect, the master chip 10 triggers an alarm signal and reports an error code, and the master chip 10 controls the communication rate of the communication control signal to reduce to a first rate value. When the master chip 10 retransmits the communication control signal to the USB control chip 41 less than or equal to the second preset number of times using the preset retransmission mechanism, if the result of the CRC check is correct, the master chip 10 controls the communication rate of the communication control signal to remain at a second rate value.

[0056] Specifically, the second preset number of times can be 2, 3, or 4, which is not limited here.

[0057] The first rate value may, for example, be 100 kHz, 110 kHz, 120 kHz, 130 kHz, 140 kHz, 150 kHz, 160 kHz, 170 kHz, 180 kHz, 190 kHz, or 200 kHz, which is not limited here.

[0058] The second rate value may, for example, be 390 kHz, 400 kHz, 410 kHz, 420 kHz, 430 kHz, 440 kHz, 450 kHz, 460 kHz, 470 kHz, 480 kHz, or 490 kHz, which is not limited here.

[0059] Please refer to Figure 2For example, taking the second preset number of 3 times, the first rate value of 100 kHz, and the second rate value of 400 kHz as an example, if the master control chip 10 automatically retransmits the communication control signal to the USB control chip 41 according to the preset retransmission mechanism, if the master control chip 10 retransmits the communication control signal using the exponential backoff algorithm, and the result of the CRC check is still incorrect after retransmission 4 times, it indicates that the communication between the master control chip 10 and the USB control circuit 40 may be subject to strong electromagnetic interference. Therefore, the master control chip 10 can control the communication rate of the communication control signal to reduce to 100 kHz. Reducing the communication rate in a strong electromagnetic interference environment can effectively improve the anti-interference ability and communication reliability of the communication bus, and ensure the communication quality between the master control chip 10 and the USB control chip 41. At the same time, the master control chip 10 triggers an alarm signal and reports an error code to the control system, for example, a battery management system (BMS), so that the hardware communication circuit 100 can timely send an alarm signal, facilitating the user to timely remove the strong electromagnetic interference component.

[0060] In addition, after the master control chip 10 retransmits the communication control signal to the USB control chip 41 twice using the preset retransmission mechanism, if the result of the CRC check is correct, the master control chip 10 can also control the communication rate of the communication control signal to remain at 400 kHz. Understandably, compared to a higher frequency (such as MHz level), 400 kHz is more stable in long cable or complex electromagnetic environment, reducing signal attenuation and noise influence.

[0061] The application also provides a storage power supply. The storage power supply includes the hardware communication circuit 100 of any one of the above embodiments.

[0062] Specifically, the structure and working principle of the hardware communication circuit 100 are as described above, and will not be repeated here. The storage power supply can be an outdoor portable storage power supply or other power supply, which is not limited here.

[0063] In this way, the hardware communication circuit 100 of the storage power supply of the application adds the digital potentiometer 30 and the pull-up resistor 20. The master control chip 10 sends a digital signal to the digital potentiometer 30 to adjust the resistance value of the digital potentiometer 30, so as to dynamically adjust the resistance value of the pull-up resistor 20, adapt the communication rate of the communication control signal under different load conditions, thereby enhancing the communication quality of the communication bus under different load conditions, improving the communication reliability of the communication bus between the master control chip 10 and the USB control chip 41 in a strong electromagnetic interference environment, and improving the power supply quality of the storage power supply.

[0064] That is, the communication quality between the main control chip 10 and the USB control chip 41 is improved, the communication reliability of the IIC bus between the main control chip 10 and the USB control circuit 40 in a strong electromagnetic interference environment is improved, and the quality of the energy storage power supply is effectively improved by the combination of the internal structure optimization of the hardware communication circuit 100, the communication protocol enhancement, and the communication rate dynamic adjustment.

[0065] The above embodiments only express several embodiments of the application, and the description is more specific and detailed, but it cannot be understood as a limitation on the scope of the patent of the application. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the application, several modifications and improvements can be made, which belong to the protection scope of the application. Therefore, the protection scope of the patent of the application should be subject to the appended claims.

Claims

1. A hardware communication circuit for an energy storage power supply, characterized in that, The hardware communication circuit includes: a main control chip, a pull-up resistor, a digital potentiometer, and a USB control circuit. The USB control circuit contains a USB control chip. The digital potentiometer is connected to the communication bus between the main control chip and the USB control chip. The pull-up resistor is connected to the communication bus between the main control chip and the digital potentiometer. The main control chip is used to send communication control signals to the USB control chip; The main control chip is also used to send digital signals to the digital potentiometer to adjust the resistance value of the digital potentiometer, so as to dynamically adjust the resistance value of the pull-up resistor and adapt to the communication rate of the communication control signal under different load conditions.

2. The hardware communication circuit according to claim 1, characterized in that, A voltage divider resistor is provided between the main control chip and the digital potentiometer. The first end of the voltage divider resistor is connected to the digital potentiometer and the main control chip, and the second end of the voltage divider resistor is grounded. The main control chip calculates the actual resistance value of the digital potentiometer by detecting the resistance value of the voltage divider resistor, and adjusts the resistance value of the digital potentiometer according to the difference between the actual resistance value and the target resistance value.

3. The hardware communication circuit according to claim 1, characterized in that, The hardware communication circuit also includes a filter, which is connected in series on the communication bus between the digital potentiometer and the USB control chip. The filter is used to filter the communication control signal output by the main control chip.

4. The hardware communication circuit according to claim 1, characterized in that, The USB control circuit is used to convert the communication control signal into a differential communication signal after the USB control chip receives the communication control signal, and to determine that the current frame data is invalid and mark the current frame data as invalid frame data when the start byte and / or end byte of the current frame data in the differential communication signal does not conform to the corresponding custom specification.

5. The hardware communication circuit according to claim 1, characterized in that, The USB control circuit is also used to convert the communication control signal into a differential communication signal after the USB control chip receives the communication control signal, and terminate the reception of the current frame data and trigger a timeout fault signal when the end byte of the current frame data in the differential communication signal is not detected within a preset time.

6. The hardware communication circuit according to claim 1, characterized in that, The USB control circuit is further configured to, after the USB control chip receives the communication control signal, convert the communication control signal into a differential communication signal through the USB control chip, verify the parity check bit of the address byte of the differential communication signal, and if the parity check bit of the address byte of the differential communication signal fails to be verified, discard the data packet corresponding to the differential communication signal and send a retransmission signal to the main control chip.

7. The hardware communication circuit according to claim 6, characterized in that, The USB control circuit is also used to verify the parity check bit of the address byte of the differential communication signal. If the parity check bit of the address byte of the differential communication signal is successfully verified, the main control chip performs CRC verification on the data packet corresponding to the differential communication signal. If the result of the CRC verification is correct, the control command corresponding to the communication control signal is executed, and the operation result is returned to the main control chip through the communication bus.

8. The hardware communication circuit according to claim 7, characterized in that, The main control chip has an error counter. The USB control circuit is also used to verify the parity check bit of the address byte of the differential communication signal. If the parity check bit of the address byte of the differential communication signal is successfully verified, the main control chip performs CRC verification on the data packet corresponding to the differential communication signal. If the result of the CRC verification is an error, the error count of the error counter is incremented by one. When the continuous error count in the error counter exceeds a first preset number, the main control chip triggers a preset retransmission mechanism.

9. The hardware communication circuit according to claim 8, characterized in that, The preset retransmission mechanism is to use an exponential backoff algorithm for automatic retransmission, and the exponential backoff algorithm is an algorithm that retransmits at exponential intervals.

10. The hardware communication circuit according to claim 9, characterized in that, If the main control chip retransmits the communication control signal to the USB control chip more than a second preset number of times using the preset retransmission mechanism, and the result of the CRC check is still incorrect, the main control chip triggers an alarm signal and reports an error code, and the main control chip controls the communication rate of the communication control signal to be reduced to a first rate value. When the main control chip retransmits the communication control signal to the USB control chip using the preset retransmission mechanism for less than or equal to the second preset number of times, if the result of the CRC check is correct, the main control chip controls the communication rate of the communication control signal to remain at the second rate value.

11. An energy storage power source, characterized in that, The energy storage power supply includes the hardware communication circuit described in any one of claims 1 to 10.

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