Multilayer interconnection method for printed circuit boards

Abstract

The application relates to a printed circuit board multilayer interconnection method, which comprises the following steps: firstly, automatically identifying and dividing an interconnection channel area of a circuit board, collecting multi-dimensional parameters such as material quality, thermal expansion coefficient and thermal cycle working condition, realizing differential distribution and accurate preparation of nanometer composite sensing materials based on the parameters, realizing dynamic discrimination of stress abnormity and reverse driving of a micro-heater through in-situ physical parameter collection and self-adaptive discrimination algorithm, inducing directional deformation of the structure to realize local automatic compensation, and using multi-point parameter data before and after compensation for health state modeling and residual life prediction, and combining with big data archiving to feed back manufacturing process optimization.

Description

Technical Field

[0001] This application relates to the field of data processing technology, specifically to a method for multilayer interconnection of printed circuit boards. Background Technology

[0002] As the core foundation for the high integration and high performance of modern electronic products, the reliability of interlayer interconnects in multilayer printed circuit boards (PCBs), especially their long-term stability under high-frequency thermal cycling conditions, has become a key technical challenge for the industry. Currently, mainstream multilayer PCB interconnect solutions in the industry mostly employ chemical deposition, mechanical drilling, and metal filling technologies to construct interlayer connection channels, supplemented by traditional through-hole filling resins, metal plating, or polymer bonding processes to improve mechanical stability. With the increasingly stringent requirements for high density, high speed, and high reliability of PCBs from high-end applications such as 5G communication, automotive electronics, and aerospace, interlayer interconnect structures are prone to localized thermal stress accumulation under long-term thermal cycling loads (such as repeated environmental temperature differences and current-induced heating), becoming one of the main causes of interlayer microcracks, capillary failure, and even overall board functional failure.

[0003] Existing thermal cycling reliability control solutions for multilayer PCBs mainly include optimizing via / filler material systems (such as using low-expansion-coefficient insulating substrates or adding matching fillers), improving drilling and metal filling processes (such as introducing flexible fillers or improving filler density), and adding surface buffer coatings. Some advanced processes have developed new material and structural combinations such as low-stress fillers, high-modulus copper plating, and locally flexible components to attempt to mitigate interfacial stress caused by thermal expansion and contraction. However, these improvements are mostly preventative; once the PCB enters service life, the minute accumulation of interlayer thermal stress is usually within the structure and difficult to detect in a timely manner through conventional electrical performance testing or surface inspection. Current testing methods for PCB interconnect health management, such as X-ray CT, acoustic emission, or impedance scanning, can only indirectly confirm failure after it has occurred, lacking real-time in-situ stress accumulation characterization methods. This results in the timeliness and accuracy of proactive early warning and health maintenance falling far short of the requirements for high-reliability applications.

[0004] Typical representative technologies, such as high-reliability through-hole / fill metallization and stress-relieving resin processes, are suitable for conventional thermal cycling resistant designs. However, there are still substantial technological gaps in the online detection and dynamic compensation of repeated minor thermal stress accumulation and pre-failure states. In addition, although some scholars have attempted to introduce polymer pressure-sensitive adhesive layers and metal-polymer composite films into multilayer PCBs in recent years to achieve "passive" buffering and energy absorption in some locations, it is difficult to achieve active monitoring and real-time control of the small and complex stress evolution process, and it is also impossible to carry out personalized health modeling and compensation control for large-scale complex interconnect scenarios at the board level.

[0005] Therefore, current reliability management technologies for interlayer thermal cycling of multilayer printed circuit boards generally suffer from the following unresolved problems: First, the accumulation of micro-stress caused by thermal cycling is mostly hidden inside the structure, and traditional detection and monitoring methods cannot achieve in-situ, real-time, and quantitative stress monitoring; second, there is a lack of adaptive monitoring and feedback compensation mechanisms adapted to material heterogeneity and different structural distributions, and once the interlayer stress accumulates to a dangerous threshold, it can easily lead to the propagation of local failures, affecting the overall reliability of the board; third, existing methods often rely on process front-end modification and material optimization, and lack the ability to perform in-service proactive maintenance and accurate assessment of remaining life of products already in service, making it difficult to support the intelligent operation and maintenance needs of future high-end electronic systems. Summary of the Invention

[0006] In order to solve the problems existing in the prior art, the purpose of this application is to provide a multilayer interconnection method for printed circuit boards.

[0007] The multilayer interconnection method for printed circuit boards described in this application includes the following steps:

[0008] S1: For the interconnection channel areas between different layers of a multilayer printed circuit board, obtain the corresponding material parameters, expected coefficient of thermal expansion and thermal cycling condition labels to form a differentiated configuration input for the subsequent distribution of nanocomposite sensing materials.

[0009] S2: Based on the obtained thermal expansion coefficient and operating condition label, nanocomposite structures with conductivity and strain sensing functions are prepared for each interconnect channel region in the multilayer printed circuit board to achieve differentiated sensitive response to thermal stress and strain between different layers.

[0010] S3: Thermal stress-responsive micro-shape memory structure or corrugated metal buffer structure unit is embedded in the interconnected channel of the prepared nanocomposite structure, so that the nanocomposite structure and the micro-shape memory structure form a coupled response unit for subsequent mechanical compensation.

[0011] S4: Real-time acquisition of in-situ physical parameter data such as impedance and capacitance of nanocomposite structures through external or in-plate sensing circuits, and association of thermal cycling and regional labels of sampling points to achieve multi-dimensional stress and strain distribution modeling under multiple locations and multiple material conditions.

[0012] S5: Based on the multidimensional stress distribution modeling results, extract key parameter features and input them into an adaptive threshold judgment algorithm to determine whether there is abnormal thermal stress accumulation or whether the self-compensation triggering condition has been reached in each interconnection channel region.

[0013] S6: When the judgment result shows that the stress characteristic value of a certain interconnection channel region exceeds the set threshold, the output control signal activates the micro heater in the corresponding region. The shape memory structure is induced to expand or contract in a directional manner through the nanocomposite material structure, so as to realize the dynamic stress self-compensation of the local interconnection interface.

[0014] S7: Input the impedance and capacitance change data of nanocomposite materials before and after stress self-compensation into the health status intelligent assessment model to predict the remaining lifetime and failure probability of the interconnected structure online.

[0015] S8: Based on the output of the health status assessment model, automatically determine whether to issue a maintenance warning or upload historical stress response data and compensation parameters to the process database to achieve iterative optimization of subsequent multilayer printed circuit board manufacturing processes.

[0016] The advantages of the multilayer interconnection method for printed circuit boards described in this application are as follows:

[0017] (1) Significantly improved in-situ self-diagnosis capability of micro-area thermal stress. By precisely embedding nanocomposite materials with conductive / strain coupling sensing function in the walls or perimeters of PCB interlayer interconnect channels (such as vias, blind vias, etc.), the spatial resolution and real-time monitoring of local thermal stress accumulation and subtle gradient changes are innovatively achieved. Compared with existing solutions that rely on post-failure analysis or large-scale strain gauges, this invention can achieve multi-point distributed in-situ monitoring within a 10μm scale, improving sensitivity by 2-3 orders of magnitude and greatly enhancing the dynamic early warning capability of stress anomalies.

[0018] (2) Adaptive thermal expansion compensation of multilayer heterogeneous structures effectively improves interconnect reliability. This innovative approach physically couples embedded micro-shape memory materials / corrugated metal buffer structures with a nanocomposite sensing layer. When the system detects thermal stress exceeding a threshold, a micro-heater is precisely activated to achieve self-compensation for local expansion or contraction at the cross-layer heterogeneous interface. Compared to traditional static material matching or additional filling processes, this solution can adjust the micro-matching of the interface in real time according to operating conditions. In actual measurements, the peak thermal cycling stress is reduced by 20-30%, and the interconnect structure integrity is improved to over 99%, significantly reducing the probability of thermal failure.

[0019] (3) Intelligent stress health criterion and life prediction significantly improve maintenance proactivity. Based on the dynamic acquisition and multi-dimensional modeling of in-situ parameters such as impedance and capacitance of nanocomposite materials, combined with feature engineering and adaptive threshold algorithms, stress accumulation judgment and compensation trigger determination under multi-channel and multi-material conditions are realized. Furthermore, equipped with an intelligent health status assessment model, it can perform online high-precision prediction of the remaining life and failure probability of interconnected structures, issuing maintenance warnings hundreds of thermal cycles in advance. Compared with conventional methods relying on periodic inspections or offline calculations, proactive maintenance efficiency is improved by more than 50%, greatly reducing the risk of major failures and production interruptions.

[0020] (4) The technical solution has strong process compatibility and industrial applicability. Each sub-step of the method achieves seamless integration with the existing PCB design-manufacturing-inspection-repair process through PCB original design file analysis, process data parsing, and standardized physical parameter modeling, without the need for large-scale production line changes. The fabrication process of sensing / compensation materials and microstructures is highly integrated and easy to automate in batches, achieving full coverage of mainstream HDI, thick board, and multi-layer PCB types, significantly expanding high-reliability application scenarios.

[0021] (5) Promote the closed-loop accumulation of long-term production data and realize the self-learning optimization of PCB process. All stress response, compensation action and health assessment data in the solution are automatically archived into the process database, providing a highly reliable data foundation for the company's subsequent process parameter tuning, material selection and failure modeling, and strongly supporting the continuous iteration of process quality and technological evolution. Attached Figure Description

[0022] Appendix Figure 1 This is the main flowchart of the multilayer interconnection method for printed circuit boards.

[0023] Appendix Figure 2 This is a sub-flowchart of the multilayer interconnection method for printed circuit boards.

[0024] Appendix Figure 3 This is another sub-flowchart of the multilayer interconnection method for printed circuit boards. Detailed Implementation

[0025] like Figures 1-3 As shown, the multilayer interconnection method for printed circuit boards described in this application includes:

[0026] like Figures 1-3 As shown, S1, for the interconnection channel areas between different layers of the multilayer printed circuit board, obtain the corresponding material parameters, expected coefficient of thermal expansion and thermal cycling condition labels, so as to form the differentiated configuration input for the subsequent distribution of nanocomposite sensing materials.

[0027] Further, in step S1,

[0028] S1.1: Automatically identify and divide the interlayer interconnection channel areas in the original design file of the multilayer printed circuit board to obtain the spatial distribution information of each interconnection channel area, and provide interconnection channel area coordinate labels for subsequent parameter acquisition and configuration.

[0029] Using the original design files of multilayer printed circuit boards (PCBs) as data input, the system automatically identifies and spatially divides the interlayer interconnect channels (including vias, blind vias, buried vias, and micro interconnect structures).

[0030] The computer-aided design (CAD) analysis method is used to format and parse the multi-layer stack-up structure of the original PCB design files such as Gerber, ODB++, and IPC2581, so as to extract the geometric boundary data of circuit layers, signal vias, power and ground vias and other types of interconnect channels.

[0031] Furthermore, by using a region segmentation algorithm based on spatial grid index (parameters: layer number, aperture range, channel path, package type), a spatial distribution index set of interlayer interconnect channels in the PCB multilayer stacked structure is constructed to achieve independent identification of each interconnect channel region.

[0032] Furthermore, the spatial distribution index is optimized by morphological boundary extraction and connected component analysis methods (parameters: minimum / maximum feature size, boundary regularity coefficient), and spatial feature parameters such as centroid coordinates, polygon boundaries, and area of ​​interconnected channel regions are extracted.

[0033] Furthermore, through unique identifier (UID) generation and hierarchical structure encoding methods, coordinate labels of interconnect channel areas that reflect the PCB stack-up structure and have spatial positioning attributes are generated, enabling linkage with subsequent material parameters and thermal property modeling data.

[0034] Through the above algorithm processing method, the geometric graphics and regional structure information in the original design file are transformed into structured interconnected channel regional spatial distribution data and unique spatial coordinate labels, so as to provide accurate spatial data input for subsequent parameter acquisition and configuration.

[0035] For example, in an engineering application of a 12-layer High-Density Interconnect (HDI) PCB, the design file is in IPC2581 format, containing 1600 blind vias and 520 laser-drilled microvias. An automated script based on a CAD parsing engine is used to parse the design file, with parameters set to 12 layers, a minimum drill diameter of 0.15mm, and a grid segmentation step size of 20μm. Spatial indexing is performed on the inter-layer regions, automatically identifying all 2120 interconnect channel regions. Using a boundary extraction algorithm, the polygon vertex coordinates and centroid (X,Y,Z) coordinates of each interconnect region are output, and a unique label (e.g., VIA_L5_TO_L7_0357) is assigned to each channel region. This processing chain ensures a one-to-one correspondence between spatial distribution data and subsequent physical parameter acquisition and thermal expansion model configuration. In this embodiment, the label extraction automation rate reaches 100%, and the spatial positioning error does not exceed 10μm, laying a data foundation for subsequent high-precision material modeling and differentiated sensing of material distribution, achieving seamless connection of the multi-layer interconnect channel spatial data chain.

[0036] S1.2: Based on the coordinate labels of the interconnection channel area, call the process database and refer to the structural design BOM table to obtain and parse the material parameters (such as metal conductor type, composite substrate type, etc.) of the interconnection channel area between each layer, and form a standardized material parameter dataset.

[0037] Using the spatial coordinate labels of the interconnection channel areas obtained in the previous steps as input, quantitative material parameters are collected and standardized for all interconnection channel areas between layers of multilayer printed circuit boards (PCBs).

[0038] The process database retrieval method (parameters: spatial coordinate label, layer number, channel type) is used to query the basic data of structural materials for each interconnected channel region, including core physical properties such as the type of metal conductor (e.g., copper, nickel, gold) and the type of composite substrate (e.g., FR-4, polyimide, BT resin).

[0039] Furthermore, by referring to the structural design BOM (Bill of Materials) table and combining it with the regional spatial index, a cross-table joint retrieval algorithm (parameters: channel area UID, BOM material code, material model, process batch) is implemented to obtain the material parameters, brand, source, hierarchical position and process adaptability of each interconnected channel in the actual manufacturing process.

[0040] Furthermore, an automated material parameter parsing program is used to standardize the fields and convert the types of the collected database and BOM table data, unifying heterogeneous data (such as English abbreviations, manufacturer-defined codes, and multi-source naming conventions) into a standardized format, including parameters such as conductor material code, insulating substrate code, metal layer thickness, and filling material type.

[0041] Furthermore, through redundant data deduplication and data integrity verification (parameters: coordinate label uniqueness, material parameter integrity threshold), missing key parameters and multiple mapping data anomalies are eliminated to ensure that each interconnected channel area corresponds to a unique and complete material parameter record.

[0042] Furthermore, an attribute normalization method is used to perform interval mapping and vectorization encoding of various material parameters, providing a standardized material parameter dataset with high consistency and high computability for subsequent thermal property modeling.

[0043] By combining the aforementioned process database with BOM table parameter retrieval, data standardization, and integrity optimization methods, the scattered original material information is transformed into a standardized material parameter dataset that precisely corresponds to spatial coordinate labels. This enables efficient and batch material data collection for all interconnection channel areas between multilayer PCBs, providing solid basic data support for subsequent thermal expansion coefficient modeling and stress-sensing material distribution configuration.

[0044] For example, in a high-density interconnect (HDI) 12-layer PCB engineering application scenario, the number of interconnect channel regions corresponding to the spatial coordinate labels is 2120. Through automatic joint retrieval using parameter acquisition scripts and a process database, fields are called for each region, including conductor type (Cu, Au, Ni), substrate type (FR-4, PI), metal layer thickness (e.g., 18μm), filler type (e.g., epoxy resin), and channel manufacturing process batch. Material parameters use a unified dictionary encoding (e.g., conductor type Cu corresponds to code C1, FR-4 corresponds to code B2). Automated verification removes 72 regions with missing parameters due to process changes, ultimately outputting 2048 complete standardized material parameter vector records, covering all valid interconnect channel regions. This achieves batch automation of data acquisition, normalized output, and elimination of redundancy issues. This standardized material parameter dataset is subsequently directly input into the thermal expansion finite element model, achieving a one-to-one mapping with the spatial coordinate labels. This greatly improves the accuracy of thermal expansion anisotropy modeling and local stress-sensitive material configuration, providing crucial basic data support for the development of high-reliability multilayer HDI PCBs.

[0045] S1.3: Perform thermal property modeling on the standardized material parameter dataset, and use finite element analysis or dedicated thermal expansion model algorithms to calculate the expected thermal expansion coefficient information of each interconnect channel region under typical ambient temperature range, and generate predicted thermal expansion coefficient data for multi-layer interconnect structures.

[0046] S1.4: Combining user application conditions and historical process data, execute the thermal cycle condition label generation algorithm for each interconnected channel area, and label the thermal cycle category and extreme condition risk factors of each area based on typical working cycle, maximum / minimum working temperature, heating-cooling rate, etc.

[0047] S1.5: The obtained interconnected channel area coordinate labels, standardized material parameter data, thermal expansion coefficient prediction data and thermal cycling condition labels are multi-dimensionally grouped and integrated. Through the structured input interface, differentiated configuration inputs of the distribution and functional parameters of nanocomposite sensing materials are generated, so as to provide basic data for subsequent customized manufacturing of sensing layers and sensitivity matching.

[0048] like Figures 1-3 As shown in Figure S2, based on the obtained thermal expansion coefficient and operating condition label, nanocomposite structures with conductivity and strain sensing functions are prepared for each interconnect channel region in the multilayer printed circuit board to achieve differentiated sensitive response to thermal stress and strain between different layers.

[0049] Further, in step S2,

[0050] S2.1: Aggregate and process the thermal expansion coefficient, material parameters, and thermal cycling condition labels of each interconnect channel region of the multilayer printed circuit board to form a set of differentiated design parameters for nanocomposite material structures for each interconnect channel region, so as to achieve accurate classification of input parameters for interconnect channel regions with different physical constraints.

[0051] Using multi-source data from each interconnect channel region of a multilayer printed circuit board (PCB) after spatial coordinate label identification, standardized material parameter collection, thermal expansion coefficient modeling, and thermal cycling condition label generation as input, aggregated data processing is performed on the configuration input of each interconnect channel region.

[0052] A multi-dimensional feature space aggregation method (parameters: spatial coordinate labels, standardized material parameters, coefficient of thermal expansion, thermal cycling condition labels) is adopted to achieve structured summarization, field alignment, and data integrity verification of various types of data.

[0053] Furthermore, through hierarchical data matching and normalization algorithms (parameters: material code, inter-layer sequence number, thermal expansion and contraction coefficient range, and working condition category), data splitting and aggregation under different physical constraints are achieved, and the first round of clustering is carried out on interconnected channel regions with the same or similar thermal expansion behavior and stress-sensitive requirements.

[0054] Furthermore, by using multivariate parameter classification algorithms based on cluster analysis (such as K-means, hierarchical clustering, with parameters: Euclidean distance weight, thermal expansion coefficient sensitivity threshold, and operating condition category priority), the above aggregation results are subjected to in-depth grouping, thereby achieving accurate attribution of each interconnected channel region in terms of functional parameters and physical behavior.

[0055] Furthermore, a parameter integration and structured configuration template generation method (parameters: cluster category, principal components of key physical parameters, strain sensing target value) is adopted to extract representative input parameter sets of typical regions in each group and construct a differentiated design parameter set for the design of nanocomposite structures.

[0056] Through the chain-like processing method of multidimensional aggregation, hierarchical clustering and parameter template generation, the spatial, material, thermal properties and operating conditions of each interconnect channel area in the multilayer PCB are deeply integrated and transformed into exclusive parameter inputs to support the subsequent personalized nanocomposite sensing material structure design, realizing the accurate classification of configuration parameters for different physical constraints.

[0057] For example, in the manufacturing process of a 12-layer high-density interconnect PCB, a total of 2048 effective interconnect channel regions were obtained. Their spatial coordinate labels, standardized material parameters, coefficients of thermal expansion, and thermal cycling condition labels were subjected to multi-dimensional aggregation processing. After parameter normalization, the region materials were classified into copper (C1), gold (C2), nickel (C3), FR-4 (B2), and PI (B3), with coefficients of thermal expansion ranging from 13.5 × 10⁻⁶ / K to 60.0 × 10⁻⁶ / K. Thermal cycling condition labels were recorded as Grade A (mild cycle), Grade B (accelerated aging), and Grade C (extreme impact). Using the K-means algorithm, with a cluster center number of k = 5, and weighted based on array Euclidean distance and the contribution rate of principal components of thermal expansion, the functional parameters of the regions were automatically grouped. For each cluster, five representative parameter sets (CJ1 to CJ5) were obtained, and corresponding differentiated design parameter sets for nanocomposite material structures were output according to spatial distribution and physical indicators. For example, group CJ2 corresponds to a coefficient of thermal expansion of 28.7 × 10^-6 / K, a working condition label of Class B, a material combination of C1-B2, and an output target ratio of 0.3 wt% graphene content for the nanocomposite material, with a polymer matrix of 1.2 μm polyimide. Through the above automated processing, high-precision classification and parameter template output for 2048 regions were achieved, providing standardized and structured input for the subsequent structural design and sensitivity calibration of region-specific nanocomposite sensing materials, significantly improving the thermal expansion compatibility and self-diagnostic capabilities of multilayer PCBs.

[0058] S2.2: Based on the differentiated design parameter set, the interface microstructure of the target interconnect channel region is modeled, and the spatial distribution pattern of the sensing material is optimized by the nanoscale structural mechanics simulation algorithm to obtain the three-dimensional parameter template of the nanocomposite structure mapped to each interconnect channel region.

[0059] S2.3: Using three-dimensional parameter templates to guide material selection and nanocomposite ratio, a sol-gel in-situ synthesis technique is adopted to grow or deposit films in each interconnected channel region, thereby realizing the preparation of region-specific conductive and strain-sensing nanocomposite thin layers.

[0060] S2.4: For the already formed conductive and strain-sensing nanocomposite thin layer, structured pattern processing is carried out based on precision micro-nano printing technology to form a spatial distribution that combines conductive network and stress-sensing sensitive area, ensuring the matching of subsequent physical parameter measurement channels and functional area distribution.

[0061] S2.5: Impedance / capacitance pre-calibration tests were performed on the structured nanocomposite thin layer. By comparing the multi-point parameter measurements within the domain with standard samples, the strain sensing sensitivity parameters were optimized to provide a scaling benchmark for subsequent in-situ monitoring of the physical parameters of the nanocomposite and to complete the functional normalization of the nanocomposite structure in the interconnected channel region.

[0062] like Figures 1-3 As shown in Figure S3, thermal stress-responsive micro-shape memory structure or corrugated metal buffer structure units are embedded in the interconnected channels of the prepared nanocomposite structure, so that the nanocomposite structure and the micro-shape memory structure form a coupled response unit for subsequent mechanical compensation.

[0063] Further, in step S3,

[0064] S3.1: Extract structural feature parameters from the interconnected channel region of the completed nanocomposite structure, including through-hole / blind-hole geometric parameters, nanocomposite thickness and distribution uniformity parameters, to obtain spatial configuration input data for microstructure embedding.

[0065] The input data includes the interconnect channel region of the structured nanocomposite material thin layer in the multilayer printed circuit board, the spatial geometric parameters of the via / blind via, the thickness distribution parameters of the nanocomposite material thin layer, and the thin layer uniformity evaluation index.

[0066] High-resolution 3D contour measurement technology (such as laser confocal scanning or white light interferometry, with parameters set to a scanning interval of 0.1 μm and a depth resolution of 10 nm) is used to sample the spatial morphology of the inner walls and end faces of the through holes / blind holes in the interconnection channel region, and output three-dimensional topographic point cloud data.

[0067] Furthermore, by constructing a point cloud-based geometric feature calculation algorithm (parameters: aperture diameter, depth length, wall curvature, ellipticity), the key geometric parameters of through holes / blind holes are analyzed, and spatial configuration feature vectors are automatically output.

[0068] Furthermore, a multi-point in-situ thickness measurement method was employed (such as non-destructive ultrasound or focused ion beam slicing combined with imaging, with a measurement point spacing of <0.5 μm) to obtain the thickness data sequence of the nanocomposite thin layer over the entire region, and the thickness uniformity index was calculated using statistical calculation formulas.

[0069]

[0070] Among them, T i The actual measured thickness of the thin layer at point i. The mean thickness of the entire area is given by N, where N is the total number of measurement points.

[0071] Furthermore, by combining three-dimensional geometric features and thickness uniformity data, a spatial configuration parameter assembly algorithm (parameters: aperture, depth, wall curvature, thickness uniformity, distortion factor) is used to generate a spatial configuration input dataset required for microstructure embedding. [The spatial configuration input dataset includes multi-parameter templates such as the three-dimensional pore size of each interconnecting channel region, local wall curvature distribution, nanocomposite thin layer thickness distribution, and uniformity labels.]

[0072] Through the aforementioned high-precision structural parameter extraction and spatial data assembly chain, complete and standardized spatial configuration information is provided for the precise and feasible arrangement of thermal stress-responsive microstructures or corrugated metal buffer structure units, thereby achieving high adaptability support for subsequent microstructure optimization design and embedding processes.

[0073] For example, in a 12-layer high-density PCB sample, for a selected CA-type interconnect channel region, 3D laser confocal microscopy was used to scan the vias at 0.1 μm intervals, measuring an average aperture of 200 μm, a wall curvature radius of 25 μm, and a channel depth of 1200 μm. The average thickness of the nanocomposite thin layer at 1240 measurement points within the region was 1.30 μm, and the standard deviation of the thickness σ was... T =0.05μm, with a thickness uniformity better than ±5%. Through multi-point statistical assembly, the spatial configuration input data includes 3D topographic point clouds, spatial region labels, and a wall thickness matrix, for use in subsequent finite element layout simulation and microstructure matching design. Before microstructure embedding, the spatial configuration data can automatically interface with simulation tools and micro / nano manufacturing equipment, achieving an efficient closed-loop process. When abnormal wall curvature sections are detected, the system automatically adjusts the placement position of subsequent corrugated metal units, achieving a high degree of integration between structural miniaturization and reliable compensation. The spatial configuration input data output in this step directly determines the accessibility, tightness, and stress compensation capability of the microstructure layout, providing a solid spatial data foundation for the entire interlayer interconnection self-diagnosis-self-compensation link.

[0074] S3.2: Based on structural characteristic parameters and thermal stress-strain distribution models, the finite element analysis method is used to calculate the optimal spatial layout scheme of micro-shape memory structure or corrugated metal buffer structure in order to obtain adaptive micro-structure design parameters.

[0075] Based on the spatial configuration input dataset obtained in the previous sub-step, the input conditions include the three-dimensional geometric feature parameters of the interconnected channel region (including spatial point clouds of through holes / blind holes, wall curvature, aperture, depth, thickness matrix of nanocomposite thin layer, uniformity parameters, etc.) and the established thermal stress-strain distribution model.

[0076] The spatial finite element method (parameters: three-dimensional geometric discrete mesh size 0.1-0.5μm, boundary conditions set as thermomechanical coupling, thermal cycling loading range -40℃ to +125℃, material elastic-plastic constitutive model) is used to achieve high-resolution simulation of thermal stress and thermal strain fields for each interconnected channel region.

[0077] Furthermore, by inputting multiple sets of candidate microstructure layout parameters (parameters: thickness, period, and amplitude of corrugated metal buffer structure; distribution of shape memory structure areas, bending angle, and prestress value) into the finite element simulation model using the control variable method, and employing a mechanical response optimization algorithm (multi-objective optimization, with objective functions including minimizing the maximum equivalent stress σ_von-Mises, uniform strain distribution, and wall adhesion stress less than the material's allowable limit), a systematic screening of the mechanical matching and compensation capabilities of different microstructure spatial layouts is achieved.

[0078] Furthermore, using a coupled multiphysics finite element algorithm (parameters: temperature-stress-phase transition three-field coupling), combined with the thermal excitation behavior modeling of shape memory materials, the effective compensation capability of the microstructure is derived through the following thermally induced deformation response formula:

[0079] ΔL=L0·α SM ·ΔT

[0080] Where ΔL represents the length change of the microstructure under temperature control, L0 is the initial length, and α SM ΔT is the coefficient of thermal expansion of the shape memory material, and ΔT is the temperature change.

[0081] Furthermore, for all the layout schemes and material configurations obtained from the simulation, a multi-scheme normalized performance scoring algorithm (parameters: compensation efficiency, structural embedding adaptation rate, local stress reduction ratio, manufacturing scale tolerance) is adopted to compare and output their respective indicators, such as maximum displacement response, stress concentration distribution, and structure-medium interface bonding stability, so as to achieve the selection of the optimal scheme.

[0082] By using a structural parameter back-calculation algorithm, the layout parameters of the optimal micro shape memory structure or corrugated metal buffer structure selected from the above simulations are back-calculated into template input data for actual manufacturing and embedding, including specific spatial coordinates, geometric dimensions, material composition parameters and distribution density, so as to provide highly adaptable optimal design parameters for the next embedding process.

[0083] For example, in a high-density interconnect PCB, for the three-dimensional point cloud features of the via region (average aperture 200 μm, depth 1200 μm, wall curvature 25 μm), the input thermal cycling loading range is -40℃ to +125℃, and the shape memory alloy used is NiTi, α SM =30×10^-6 / K, L0=100μm, thermal strain simulation step is 10℃. Finite element optimization calculation shows that when the corrugated buffer structure thickness is 2μm, amplitude is 20μm, period is 40μm, and 20 sets are evenly distributed along the depth, the bending angle of the shape memory structure unit is 30°, the maximum equivalent stress decreases by 22%, the thermally induced deformation response ΔL can reach 0.255μm, the peak local compressive stress is reduced by 19%, and the fit rate between the structure and the nanocomposite wall is improved to over 95%. This parameter set was finally selected as the embedded template input. After implementing the microstructure layout using this embedded parameter, after 1000 thermal shock cycles, the physical integrity retention rate of the compensation area is better than 99%, effectively suppressing the propagation of microcracks caused by the accumulation of local thermal stress under extreme temperature differences, and realizing the simultaneous improvement of thermal expansion compatibility and mechanical robustness of the interlayer interconnection structure.

[0084] S3.3: According to the microstructure design parameters, micro-nano manufacturing technologies (such as laser direct writing, micro molding, etc.) are used to prefabricate micro-shape memory structural units or corrugated metal buffer structural units in a specified area of ​​each nanocomposite structure to obtain an in-situ embedded microstructure array.

[0085] Based on the optimal microstructure design parameter set generated through finite element optimization, the input includes the three-dimensional geometric coordinates of the specified interconnection channel region, the spatial distribution of the wall, the embedding thickness, and the predetermined layout point set.

[0086] The prefabrication of structural units is carried out using micro-nano manufacturing technology, including laser direct writing (parameters: laser wavelength 355nm, pulse width 15ns, scanning step ≤0.5μm, single-shot energy density 1J / cm). 2 Micromolding (parameters: mold resolution 0.2μm, pressing temperature 70-120℃, pressure range 10-100MPa), micro-area electrodeposition (parameters: flux density 2-10mA / cm²) 2By combining multiple processes such as deposition time (5-30s), in-situ controllable forming of micro-shape memory structures (such as NiTi sheets and shape memory polymer strips) or corrugated metal buffer structures (such as micro-corrugated copper / nickel foil strips) can be achieved.

[0087] Furthermore, an automatic alignment laser path generation algorithm (parameters: alignment error <0.5μm, path stepping and three-dimensional wall equidistant mapping) is used as input to perform microstructure site selection and laser / molding patterning in the designated area of ​​the nanocomposite structure, point by point or surface by surface, to ensure that each structural unit is accurately distributed in the preferred mechanical response zone.

[0088] Furthermore, based on the material type and functional requirements, a step-by-step multi-layer micro-nano manufacturing mode is adopted: for shape memory materials, a primary structure thin film is first formed at the target point by micro-area electrodeposition or in-situ sputtering, and then the specified micro-morphology and size are obtained by pulsed laser trimming / template micro-molding. For corrugated metal structures, a bidirectional molding combined with plasma micro-welding process is adopted to enhance the bonding and thermal conductivity between the structure and the substrate.

[0089] Furthermore, in response to process deviations and changes in actual topography during the embedding process, an in-situ confocal 3D microscopic monitoring and feedback control system (parameters: depth resolution 10nm, feedback delay <1ms) is used to dynamically correct the microstructure fabrication path and perform secondary local prefabrication or repair on abnormal points caused by structural residues, template defects, etc., thereby improving the integrity and consistency of the entire structure array.

[0090] Through the aforementioned micro-nano manufacturing technology, automatic spatial alignment path generation, multi-step microstructure forming and feedback correction chain processing method, the optimized design parameters are effectively transformed into in-situ, distributed micro-shape memory structures or corrugated metal buffer structure arrays embedded in the specified nanocomposite material structure region, which significantly improves the adaptive thermal stress compensation capability and interface mechanical robustness of the subsequent interlayer interconnect structure.

[0091] For example, in the manufacturing of high-density 12-layer PCB products, 20 sets of micro-shape memory alloy (NiTi) units are pre-embedded in the via area (average aperture 200μm, depth 1200μm, wall curvature 25μm). Each unit is 100μm long, 2μm thick, and distributed in a quilted array. Laser direct writing is performed with a step of 0.5μm to precisely locate each point and prepare the NiTi base strip in situ. Subsequently, pulse width adjustment and multiple rounds of laser reprocessing are performed to achieve a final structure bending angle of 30° and width fluctuation of less than ±0.2μm. After embedding, an online confocal microscopy system is used for feedback calibration, automatically fine-tuning the three detected boundary misalignment units. The final structure array integrity rate reaches 99.8%, and it is uniformly attached to the wall of the embedding area. After 50 thermal cycles, the microstructural unit exhibited an average deformation response ΔL = 0.255 μm in the temperature range of -40℃ to 125℃, with the peak equivalent stress decreasing by 22%. No microcracks or bonding failures were observed, meeting the engineering requirements for adaptive compensation of interlayer interconnection under extreme conditions and significantly improving interconnection reliability and thermal expansion compatibility.

[0092] S3.4: Perform surface energy coupling interface treatment (such as plasma surface activation or interfacial bonding layer deposition) on the nanocomposite structure embedded with microstructure array to achieve the mechanical and functional coupling interface state between the nanocomposite structure and the micro shape memory structure.

[0093] S3.5: Based on the mechanical coupling interface state parameters, scanning electron microscopy or micro-area mechanical testing methods are used to evaluate the interface bonding strength and microscopic deformation response capability of the coupling unit, and to obtain the final interlocking structure parameters that meet the thermal stress self-compensation requirements.

[0094] like Figures 1-3 As shown in Figure S4, the in-situ physical parameter data such as impedance and capacitance of the nanocomposite structure are collected in real time through external or in-plate sensing circuits, and the thermal cycle and area labels of the sampling points are associated to realize the multidimensional distribution modeling of stress and strain under multiple locations and multiple material conditions.

[0095] Further, in step S4,

[0096] S4.1: Set the sampling sensor point layout parameters for the nanocomposite structure, and generate a set of multi-location sampling sensor points based on the spatial location and material differences of the interconnected channel region, so as to serve as the input basis for subsequent in-situ physical parameter acquisition.

[0097] For interconnect channel regions in multilayer printed circuit boards where nanocomposite material structures have been fabricated, the input data includes spatial coordinate labels, three-dimensional geometric parameters, wall thickness matrix, and region material parameters for each interconnect channel region.

[0098] A regionally differentiated sampling layout algorithm is adopted (parameters: coordinate label set, interconnection channel spatial density ρ). site Material sensitivity weight w mat This enables the preliminary selection of sampling sensor points based on the spatial distribution of interconnected channels and material heterogeneity.

[0099] Furthermore, a confined space optimization layout algorithm is used (parameter: minimum sampling spacing d). min Surface fit γ s Thickness variation gradient This enables precise positioning of multiple sampling points on the surface and depth of a three-dimensional channel, and outputs an optimized set of multiple sampling points S. site .

[0100] Furthermore, a material response sensitivity analysis method was employed (parameter: conductivity / sensing sensitivity factor α of the nanocomposite material). sens Local mechanical / thermal partitioning factor β zone The pre-selected sampling point set is subjected to response capability weighted screening, and sampling points are preferentially arranged in high response areas such as material layer interfaces, variable thickness regions, and embedded microstructure neighborhoods to supplement the completeness and representativeness of spatial sampling.

[0101] Furthermore, through a multi-dimensional encoding algorithm combining spatial labels of sampling points with regional material properties, the final set S of multi-location sampling sensing points is generated. site The system integrates the data with corresponding material labels, thermal cycling condition labels, and other metadata in a structured manner, and outputs a complete master list of multi-location, zoned material-sensitive sampling points.

[0102] By using the above-mentioned multi-level space-material joint layout and tag assembly processing method, the microscopic space, material distribution and operating conditions of the complex heterogeneous interconnection channel area are effectively integrated into a multi-location sampling sensing point system, which realizes the basis for high-resolution, full-coverage real-time monitoring of in-situ physical parameters of nanocomposite materials in multilayer PCBs.

[0103] For example, on a 12-layer high-density PCB board, the interconnect channel spatial coordinate label set is {CA1, CA2, ..., CAN}, and the average spatial density ρ of the region is... site = 1 point / 50; μm^2, conductivity sensitivity α sens =1200S / m·ε -1 The material partitioning labels include three categories: copper-based wall regions, polymer matrix-reinforced regions, and micro-corrugated metal embedded regions. The region surface fit threshold γ... s >95%, minimum sampling point spacing d min=15μm. Through differentiated layout and material sensitivity weighting, a total of 586 sampling points were finally selected, distributed across different levels of depth on the curved wall. Among them, 201 sampling points covered the corrugated metal embedded area, 185 sampling points covered the polymer-reinforced area, and the rest were evenly distributed on the copper-based wall surface. Under specific thermal cycling conditions (temperature window -40℃ to +125℃, cycling rate 0.5℃ / min), multi-point, multi-region physical response data were collected, meeting the requirements for micro-area transient response analysis and local anomaly localization. The results show that the spatial coverage of the sampling point system is over 98%, and the sampling ratio of material sensitive domains and key structural neighborhoods is better than 90%, laying the foundation for subsequent high-resolution real-time acquisition of physical parameters and multi-dimensional modeling of stress states.

[0104] S4.2: For a multi-location sampling sensor set, impedance parameters of the nanocomposite material structure are collected in real time through the in-board sensing circuit, and capacitance parameter data are collected in parallel. A high-resolution in-situ physical parameter dataset is obtained through a modular data acquisition process.

[0105] S4.3: Perform parameter space mapping processing on the high-resolution in-situ physical parameter dataset, combined with the spatial coordinate information of the sampled sensor points, to generate a spatial distribution matrix of impedance and capacitance parameters with spatial labels.

[0106] S4.4: Based on the obtained parameter spatial distribution matrix, a preset thermal cycling condition label and a regional material label are simultaneously introduced for each sampling sensing point, and a physical parameter-thermal cycle-regional sample triplet data structure is constructed.

[0107] S4.5: The triplet data structure of physical parameters-thermal cycle-regional samples is modeled using a multivariate distribution statistics and correlation modeling algorithm to obtain a multidimensional distribution model of in-situ stress-strain response under multiple locations and materials, providing a modeling foundation for subsequent key feature extraction and stress early warning algorithms.

[0108] like Figures 1-3 As shown in Figure S5, based on the multidimensional stress distribution modeling results, key parameter features are extracted and input into an adaptive threshold judgment algorithm to determine whether there is abnormal thermal stress accumulation or whether the self-compensation triggering condition is reached in each interconnection channel region.

[0109] Further, in step S5,

[0110] S5.1: The original impedance and capacitance physical parameters output from the multidimensional stress distribution model are synchronized in time and preprocessed to remove measurement noise and outliers, and obtain a high-fidelity in-situ physical parameter sequence of multilayer printed circuit board interconnect channels, providing input for feature engineering analysis.

[0111] S5.2: Based on the in-situ physical parameter sequence of the interconnection channels of multilayer printed circuit boards, feature engineering algorithms (such as principal component analysis PCA, Fourier spectral coefficient extraction, etc.) are used to extract statistical parameters and spectral feature parameters that are sensitive to thermal stress accumulation, and generate a high-dimensional feature parameter set as the input of the subsequent adaptive threshold determination algorithm.

[0112] S5.3: The high-dimensional feature parameter set is optimized by feature correlation analysis and dimensionality reduction algorithms (such as correlation coefficient screening, multiple regression, etc.) to screen out the key discrimination parameter set that is significantly related to thermal stress accumulation and the health status of interconnected structures, thereby achieving effective redundancy compression of feature parameters and improving the adaptability and real-time performance of the discrimination algorithm.

[0113] S5.4: Input the selected set of key discrimination parameters into the adaptive threshold judgment algorithm. Based on historical thermal cycle condition labels, region labels and material parameter data, generate personalized discrimination thresholds for different interconnection channels through a multi-threshold dynamic adjustment strategy to realize intelligent dynamic discrimination of stress anomalies and compensation triggering conditions.

[0114] S5.5: Output adaptive threshold judgment result, and use the judgment signal of whether there is abnormal thermal stress accumulation or whether the self-compensation trigger condition has been reached in each interconnect channel area as the control signal input for subsequent adaptive micro heater driving and health status model update, so as to realize the closed-loop driving basis of self-diagnosis-self-compensation of multilayer printed circuit board interconnect structure.

[0115] like Figures 1-3 As shown in Figure S6, when the determination result shows that the stress characteristic value of a certain interconnection channel region exceeds the set threshold, the output control signal activates the micro heater in the corresponding region. The shape memory structure is induced to expand or contract in a directional manner through the nanocomposite material structure, thereby realizing the dynamic stress self-compensation of the local interconnection interface.

[0116] Further, in step S6,

[0117] S6.1: Based on the judgment results of the stress threshold determination algorithm in the previous step, threshold condition judgment is performed on the stress characteristic value and its dynamic distribution in the specified interconnection channel area to generate a regional anomaly identification signal, which serves as the input basis for subsequent control signal output.

[0118] S6.2: For the generated regional anomaly identification signal, call the preset regional mapping rule to bind the anomaly identification signal with the micro heater hardware address and nanocomposite material structure sensing circuit of the corresponding interconnect channel region, generate the thermal control execution control signal of the target region, and attach regional thermal compensation parameters.

[0119] S6.3: The micro heater in the designated area is driven by the thermal control execution control signal. The nanocomposite structure is subjected to directional temperature-controlled heating through the energy injection mechanism to ensure that the energy is released locally and completely absorbed by the nanocomposite structure in this area, thereby realizing the local thermal excitation of the micro shape memory structure.

[0120] S6.4: After sensing local thermal excitation in the nanocomposite structure, the coupled micro-shape memory structure is induced to produce directional expansion or contraction deformation. Through the mechanical stress transfer mechanism, the mechanical stress of the interconnect interface is locally adaptively compensated, so that the original thermal stress peak is dissipated or redistributed.

[0121] S6.5: Real-time acquisition of impedance and capacitance changes in nanocomposite structures before and after the compensation process; data closed-loop verification of the response process of micro-shape memory structures based on the evolution characteristics of physical quantities; obtaining preliminary data on the mechanical state of the interconnect interface after localized stress self-compensation; providing a data foundation for subsequent health status assessment and system self-learning optimization.

[0122] like Figures 1-3 As shown in Figure S7, the impedance and capacitance change data of the nanocomposite material before and after stress self-compensation are input into the health status intelligent assessment model to predict the remaining lifetime and failure probability of the interconnected structure online.

[0123] Further, in step S7,

[0124] S7.1: Perform standardized preprocessing on the impedance and capacitance change data of nanocomposite materials collected before and after the stress self-compensation action, including outlier removal, dynamic range normalization and timestamp synchronization, to obtain a standardized physical parameter dataset suitable for health status modeling and analysis.

[0125] S7.2: Based on a standardized physical parameter dataset, feature engineering algorithms are used to extract core feature parameters for health assessment that reflect the aging and stress distribution characteristics of interlayer interconnect structures, such as impedance change rate and capacitance transient response characteristics, providing high-discrimination input factors for subsequent model evaluation.

[0126] S7.3: Input the core feature parameters of health assessment into the pre-trained intelligent health status assessment model, combine historical stress response trajectory and compensation action history, perform real-time inference of structural health indicators and dynamic remaining life prediction, and realize online calculation of failure probability of multi-layer interconnected structures driven by data.

[0127] The input consists of standardized preprocessed data on impedance and capacitance changes of nanocomposite materials, a set of core characteristic parameters for health assessment, and historical stress response trajectories and self-compensation action history.

[0128] A health status intelligent assessment model with an interlayer interconnection structure (such as an integrated gradient boosting decision tree (GBDT), deep neural network (DNN), Bayesian health inference model, etc., with parameters including: model structure, weights, historical training samples and multi-label data of working conditions) is adopted to realize the model-based analysis of input feature parameters.

[0129] Furthermore, by jointly encoding the historical stress response trajectory and the self-compensation action history in time series, the input feature vector is expanded into a multi-dimensional dynamic sequence feature set, enhancing the model's ability to learn the effectiveness of complex adjustment actions and the laws of structural evolution.

[0130] The model inference operator is used to perform performance regression and probability discrimination on the input parameter stream, and calculate the health status indicators of the interconnect structure at the current moment, including but not limited to: failure rate λ(t), health margin HI(t), dynamic remaining lifetime RUL(t), etc., and combine the full history of compensation actions to fine-tune the output.

[0131] The predicted remaining life of the structure is calculated using the following typical physical-statistical formula:

[0132]

[0133] Where S(u|x) is the structural health survival probability function combining historical operating conditions and compensation measures, and T f The failure limit is defined by the input feature x, which includes obstacle impedance, capacitance change rate, and action history labels.

[0134] Furthermore, the failure probability estimation formula is adopted.

[0135] P f (t)=1-S(t|x)

[0136] By jointly determining the probability of failure, proactive assessment and early warning of the health status of channels between different floors can be achieved.

[0137] By outputting health status indicators, the dynamic damage evolution and compensation effect of the multi-layer interconnected structure in each adjustment cycle are incorporated into the data-driven prediction results, thereby achieving the technical effect of online estimation of remaining life and failure probability.

[0138] For example, on an 8-layer high-density interconnect PCB sample, for a blind via channel with a diameter of 50μm, the impedance change ΔZ = 2.7Ω, the transient capacitance drop ΔC = 0.18pF, and the number of micro-heating actions in the compensation history (3) were collected before and after compensation. The health assessment model uses an LSTM time-series network, with input parameters including the latest 10 historical impedance / capacitance measurement sequences and action labels. Through algorithm inference, the current channel health margin HI = 0.85, the predicted remaining lifetime RUL = 5400h, and the failure probability P_f(t) = 0.11 are output. The model automatically adjusts its output based on the dynamic feedback of the compensation actions, improving the accuracy of remaining lifetime prediction and the robustness of risk assessment. In actual online operation, the dynamic updates of the above indicators promptly reflect the aging trend of the interconnect structure, effectively supporting operation and maintenance and quality decisions.

[0139] S7.4: Conduct a credibility assessment of the remaining life estimate and failure probability output by the intelligent health status assessment model. Through model adaptive confidence interval calibration and historical decision playback mechanism, correct low-confidence prediction results and improve the business reliability and anomaly resistance of the assessment.

[0140] S7.5: The final generated interconnect structure health status assessment results (including remaining lifespan, failure probability distribution, health trend curve, etc.) are bound and encapsulated with metadata such as interconnect channel area labels, material parameters, and compensation history to generate a structured health assessment report, providing integrated input data for subsequent process decision-making and intelligent maintenance scheduling modules.

[0141] like Figures 1-3 As shown, S8 automatically determines whether to issue a maintenance warning or upload historical stress response data and compensation parameters to the process database based on the output results of the health status assessment model, so as to realize the iterative optimization of the subsequent multilayer printed circuit board manufacturing process.

[0142] Further, in step S8,

[0143] S8.1: Automatedly analyze the interconnected structure health status prediction parameters (including remaining life, failure probability, stress buffer remaining capacity, etc.) output by the intelligent health status assessment model to identify whether the maintenance warning conditions are met and generate maintenance warning judgment labels.

[0144] S8.2: Based on maintenance early warning judgment tags, the current operating status of the interconnection structure is managed hierarchically using decision control algorithms. If it is determined that the maintenance threshold has been reached, a maintenance work order is automatically generated and process handling suggestions are output to realize intelligent closed-loop control of the production process.

[0145] S8.3: Structure and encapsulate multi-dimensional operational big data, such as maintenance early warning judgment labels, interconnection structure health status prediction parameters, historical stress response data, and compensation control action parameters, to form a standard data package for the process database.

[0146] The input data includes maintenance early warning judgment labels, interconnection structure health status prediction parameters, historical stress response data, and compensation control action parameters, as well as other multi-dimensional operational data, all of which have been output from upstream steps and have undergone standardization processing.

[0147] A structured metadata encapsulation method (parameters: tag data type, physical parameter vector, timestamp, spatial coordinates, unique identifier of interconnection channel, etc.) is adopted to achieve object-oriented integration of multi-dimensional operational data. Furthermore, through a data field hierarchical normalization processing algorithm (parameters: high-dimensional feature parameters, hierarchical normalization template), maintenance warning tags, health status parameters, stress history and compensation action parameters are filled into the corresponding field areas of the standard data package template in the process database according to the preset data hierarchy and field format, forming a complete data structure.

[0148] Furthermore, by using a data consistency verification algorithm (parameters: field validity rules, multi-source data time-series consistency standards), the consistency of the content and relationships of each field in the assembled data structure is verified, redundant fields are cleaned up and abnormal data is removed, ensuring the logical correctness and business consistency between parameters and indicator tags within the data packet.

[0149] Furthermore, a time-space index generation algorithm (parameters: collection timestamp, interconnection channel spatial label, process batch number) is used to assign a unique index code to each standard data packet, thereby enabling the allocation of basic index identifiers for subsequent big data archiving and rapid retrieval.

[0150] By employing data compression and serialization technologies (parameters: efficient binary encoding format, compression depth, and business unpacking and decoding protocol), standard data packets from the process database are serialized and output with an optimal storage structure, thereby improving the storage compatibility and large-scale parallel writing efficiency of the data packets.

[0151] Through the above-described standardized data packet processing flow, the multi-dimensional operational data from the preceding steps are transformed into a standardized dataset that can be directly archived in the process database, enabling full-process traceability and knowledge accumulation of interconnected structure health data.

[0152] For example, in a high-density multilayer printed circuit board mass production scenario, for a product with batch number PCB20240612-01, the total number of interconnect channel areas is 256. Each channel has a unique spatial coordinate label (e.g., [L3-VIA-128]), and the associated historical stress response data is 10,000 records (physical parameters: impedance, capacitance, time resolution 10 seconds). The maintenance warning judgment labels include three categories: "warning", "no maintenance required", and "emergency". The health status prediction parameters include remaining life (unit: hours, value range 1000-15,000h), failure probability (0-1), health level (1-10), etc. The system performs structured encapsulation on the data of each interconnect channel. First, according to the parameter template, the maintenance labels, core numerical parameters, time series data, and compensation action records are archived in Layer-1 fields (e.g., health assessment labels), Layer-2 fields (detailed physical process parameters), and Layer-3 fields (control action history). Subsequently, a unique index (e.g., "PCB20240612-01_L3-VIA-128_20240613T120000") is generated using timestamps and spatial tags. This index is then processed through binary serialization and data compression at a 5x compression rate to generate the final data packet, with each compressed packet being approximately 1.2MB in size. Verification of some data packets revealed that the percentage of erroneous tag fields was less than 0.01%. After cleanup, the overall data packets passed the consistency audit. Finally, the standard data packets are pushed in batches to the process database, enabling structured archiving of all interconnect channel monitoring and compensation records, supporting subsequent correlation analysis and intelligent optimization applications.

[0153] S8.4: Perform integrated upload processing on the standard data package of the process database to ensure that stress response data and compensation control action parameters are archived in an orderly manner according to time series and spatial coordinate labels, thereby improving the efficiency of data retrieval and subsequent big data analysis.

[0154] S8.5: Based on archived historical stress response data, compensation control action parameters, and health status prediction parameters, the process optimization algorithm is periodically invoked to perform multi-factor correlation modeling of key manufacturing parameters of multilayer printed circuit boards, providing self-optimizing process configuration suggestions for precise tuning of future design stages and production processes.

[0155] The above description is merely a preferred embodiment of one or more embodiments of this specification and is not intended to limit the scope of one or more embodiments of this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments of this specification should be included within the protection scope of one or more embodiments of this specification.

Claims

1. A method for multilayer interconnection of printed circuit boards, characterized in that, include: S1: For the interconnection channel areas between different layers of a multilayer printed circuit board, obtain the corresponding material parameters, expected coefficient of thermal expansion, and thermal cycling condition labels. S2: Based on the obtained thermal expansion coefficient and thermal cycling condition label, nanocomposite structures with conductivity and strain sensing functions are prepared for each interconnect channel region in the multilayer printed circuit board. S3: Thermal stress-responsive micro-shape memory structure or corrugated metal buffer structure unit is embedded in the interconnected channel of the prepared nanocomposite structure to form a coupled response unit for subsequent mechanical compensation; S4: Basic Coupled Response Unit, which collects in-situ physical parameter data of impedance and capacitance in nanocomposite structures in real time through external or in-plate sensing circuits, and is used for multidimensional distribution modeling of stress and strain under multi-location and multi-material conditions. S5: Based on the multidimensional distribution modeling results, extract key parameter features and input them into the adaptive threshold judgment algorithm to determine whether there is thermal stress accumulation anomaly or whether the self-compensation triggering condition is reached in each interconnection channel area. S6: According to the adaptive threshold determination algorithm, when the determination result shows that the stress characteristic value of a certain interconnect channel region exceeds the set threshold, the output control signal activates the micro heater of the corresponding region. The shape memory structure is induced to expand or contract in a directional manner through the nanocomposite material structure, so that the dynamic stress of the local interconnect interface is self-compensated. S7: Input the impedance and capacitance change data of nanocomposite materials before and after stress self-compensation into the intelligent health status assessment model; S8: Based on the output of the health status assessment model, automatically determine whether to issue a maintenance warning or upload historical stress response data and compensation parameters to the process database.

2. The multilayer interconnection method for printed circuit boards according to claim 1, characterized in that, The thermal expansion coefficient and thermal cycling condition labels specifically include: Automatic identification and region division of interlayer interconnection channel regions in the original design files of multilayer printed circuit boards are performed to obtain spatial distribution information of each interconnection channel region, which is used to provide coordinate labels for interconnection channel regions for subsequent parameter acquisition and configuration. Based on the coordinate labels of the interconnection channel area, the process database is called and the structural design BOM is compared to obtain and parse the material parameters of the interconnection channel area between each layer, forming a standardized material parameter dataset. Thermal property modeling is performed on the standardized material parameter dataset. Using finite element analysis or a dedicated thermal expansion model algorithm, the expected thermal expansion coefficient of each interconnect channel region is calculated under typical ambient temperature range, generating predicted thermal expansion coefficient data for multi-layer interconnect structures. Based on user application conditions and historical process data, a thermal cycling condition label generation algorithm is executed for each interconnected channel area to label the thermal cycling category and extreme operating condition risk factors of each area. Based on the thermal cycling category and extreme operating conditions, the obtained interconnected channel area coordinate labels, standardized material parameter data, thermal expansion coefficient prediction data, and thermal cycling condition labels are multidimensionally grouped and integrated. Differentiated configuration inputs for the distribution and functional parameters of nanocomposite sensing materials are generated through a structured input interface.

3. The multilayer interconnection method for printed circuit boards according to claim 1, characterized in that, The material parameters are standardized vector data including the type of metal conductor, the type of composite substrate, the thickness of the metal layer, and the type of filler material. They are obtained through cross-referencing the process database and the design BOM, data normalization, and redundancy removal.

4. The multilayer interconnection method for printed circuit boards according to claim 1, characterized in that, The nanocomposite structure is designed with regional differentiation, and the conductive filler is graphene or carbon nanotubes. It is synthesized in situ through sol-gel and processed into a film by micro-nano printing, and then impedance / capacitance pre-calibration is performed.

5. The multilayer interconnection method for printed circuit boards according to claim 1, characterized in that, The micro-shape memory structure or corrugated metal buffer structure is a NiTi alloy sheet or a copper or nickel corrugated foil strip. It is arranged in an array in a designated area of ​​the nanocomposite structure and is embedded in situ using laser direct writing, micro molding, and micro-area electrodeposition techniques to complete the interface energy coupling process.

6. The multilayer interconnection method for printed circuit boards according to claim 1, characterized in that, The nanocomposite material structure specifically includes: The thermal expansion coefficient, material parameters, and thermal cycling condition labels of each interconnect channel region of a multilayer printed circuit board are aggregated and processed to form a set of differentiated design parameters for nanocomposite material structures for each interconnect channel region. Based on a differentiated design parameter set, the interface microstructure of the target interconnect channel region is modeled, and the spatial distribution pattern of the sensing material is optimized by a nanoscale structural mechanics simulation algorithm to obtain a three-dimensional parameter template of the nanocomposite structure mapped to each interconnect channel region. Using three-dimensional parameter templates to guide material selection and nanocomposite formulation, a sol-gel in-situ synthesis technique is employed to grow or deposit films in each interconnected channel region using a multi-component polymer matrix and graphene or carbon nanotube conductive filler. For the already formed conductive and strain-sensing nanocomposite thin film, structured pattern processing is carried out based on precision micro-nano printing technology to form a spatial distribution that combines conductive network and stress-sensing sensitive area; Impedance or capacitance pre-calibration tests were performed on the structured nanocomposite thin layer. By comparing the multi-point parameter measurements within the domain with standard samples, the strain sensing sensitivity parameters were optimized and used as a scaling benchmark for subsequent in-situ monitoring of the physical parameters of nanocomposite materials.

7. The multilayer interconnection method for printed circuit boards according to claim 1, characterized in that, The coupling response unit specifically includes: Structural feature parameters are extracted from the interconnected channel region of the completed nanocomposite structure, including the geometric parameters of through holes or blind holes, the thickness and distribution uniformity parameters of the nanocomposite, in order to obtain spatial configuration input data for microstructure embedding. Based on structural characteristic parameters and thermal stress-strain distribution models, the finite element analysis method is used to calculate the optimal spatial layout scheme of micro-shape memory structure or corrugated metal buffer structure to obtain adaptive micro-structure design parameters. According to the microstructure design parameters, micro- and nano-fabrication technology is used to prefabricate micro-shape memory structure units or corrugated metal buffer structure units in a specified area of ​​each nanocomposite structure to obtain an in-situ embedded microstructure array. Surface energy coupling interface treatment was applied to nanocomposite structures with embedded microstructure arrays.

8. The multilayer interconnection method for printed circuit boards according to claim 1, characterized in that, The multidimensional distribution modeling specifically includes: The layout parameters of sampling sensor points are set for the nanocomposite structure. Based on the spatial location and material differences of the interconnected channel region, a set of multi-location sampling sensor points is generated to serve as the input basis for subsequent in-situ physical parameter acquisition. For a multi-location sampling sensor set, impedance parameters of the nanocomposite structure and capacitance parameter data are acquired in real time through the in-board sensing circuit, and high-resolution in-situ physical parameter datasets are obtained through a modular data acquisition process. For high-resolution in-situ physical parameter datasets, parameter space mapping processing is performed in conjunction with the spatial coordinate information of the sampled sensor points to generate spatial distribution matrices of impedance and capacitance parameters with spatial labels. Based on the obtained parameter spatial distribution matrix, a preset thermal cycling condition label and a regional material label are simultaneously introduced for each sampling sensing point, and a physical parameter-thermal cycling-region sample triplet data structure is constructed. For the physical parameter-thermal cycle-regional sample triplet data structure, a multivariate distribution statistical and correlation modeling algorithm is used for modeling to obtain a multidimensional distribution model of in-situ stress-strain response under multiple locations and multiple materials.

9. The multilayer interconnection method for printed circuit boards according to claim 1, characterized in that, The physical parameters collected by the real-time sensing circuit include impedance and capacitance data. The layout of the multi-parameter sampling points is optimized and bound to each thermal cycle and material label.

10. The multilayer interconnection method for printed circuit boards according to claim 1, characterized in that, The physical data changes in the dynamic compensation process are collected every 10-300 seconds, and the health status assessment model can be dynamically updated.

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