Semiconductor device
By employing a multi-layer isolation structure design in semiconductor devices, the problem of deformation of the peripheral structure due to uneven stress is solved, thereby improving the stability and integration of the devices.
Patent Information
- Application Number
- CN202511036687.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-25
- Publication Date
- 2025-11-04
AI Technical Summary
Existing semiconductor devices are prone to deformation in the peripheral metal and dielectric layers due to uneven stress, which affects device reliability.
The design employs a multi-layered isolation structure, including a first isolation layer, a second isolation layer, and a third isolation layer. The material of the second isolation layer is different from the other layers, and the bottom of the letter line structure in the outer area is lower than the top of the isolation layer to increase mechanical strength and support.
This improves the stability of the peripheral structure, reduces the probability of deformation, and enhances the integration and electrical performance of the device.
Smart Images
Figure CN120897447A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor, and particularly relates to a semiconductor device. BACKGROUND
[0002] With the continuous development of semiconductor technology, the size of semiconductor devices is continuously reduced to meet the needs of high integration and high density. However, with the highly miniaturized semiconductor device size, the preparation process of the semiconductor device is more and more complex and difficult.
[0003] The semiconductor device in the prior art includes a multi-layer structure stacked in turn from bottom to top, and the lower layer of the peripheral region often adopts an insulating material such as silicon oxide. The mechanical strength of such material is low, and when a metal layer, a dielectric layer and other structures are stacked above it, the metal layer, the dielectric layer and other structures above the peripheral region are prone to insufficient support due to uneven stress, thereby causing structural deformation and even affecting the reliability of the device. SUMMARY
[0004] In view of the above problems, the embodiments of the present application provide a semiconductor device, aiming to improve the stability of the peripheral region structure.
[0005] In order to achieve the above purpose, the embodiments of the present application provide the following technical solutions:
[0006] The first aspect of the embodiments of the present application provides a semiconductor device, comprising:
[0007] A substrate having a core region and a peripheral region adjacent to the core region, wherein the substrate includes an isolation structure and an active structure defined by the isolation structure, and the isolation structure includes:
[0008] A first isolation structure located in the core region;
[0009] A second isolation structure located in the peripheral region, the second isolation structure includes a first isolation layer, a second isolation layer and a third isolation layer stacked in turn; the material of the second isolation layer is different from the material of the first isolation layer and the third isolation layer; the second isolation layer includes a first part extending along a first direction and a second part extending along the thickness direction of the substrate;
[0010] A word line structure crossing the isolation structure and the active structure along the first direction and being arranged in the core region and the peripheral region, and the bottom of the word line structure in the peripheral region is lower than the top of the first part along the thickness direction of the substrate.
[0011] In some optional embodiments, the word line structure in the peripheral region penetrates the second isolation layer along the thickness direction of the substrate.
[0012] In some embodiments, a bottom of the word line structure in the peripheral region is lower than a top of the third isolation layer and is not lower than a bottom of the third isolation layer.
[0013] In some embodiments, the word line structure comprises a gate conductive layer, a gate blocking layer covering an outer wall of the gate conductive layer, and a gate dielectric layer covering an outer wall of the gate blocking layer.
[0014] The semiconductor device further comprises a gate covering insulating layer, the gate covering insulating layer is located at a top of the word line structure and directly contacts the word line structure, and a projection of the gate covering insulating layer covers a projection of the word line structure along a thickness direction of the substrate.
[0015] In some embodiments, a bottom profile of the word line structure in the peripheral region is in a circular arc shape.
[0016] In some embodiments, a bottom profile of the word line structure in the peripheral region is in an inverted cone shape.
[0017] In some embodiments, at least the gate blocking layer has a void.
[0018] In some embodiments, a bottom of the word line structure in the peripheral region is located in the third isolation layer, and the void is located in the gate blocking layer in the third isolation layer.
[0019] In some embodiments, the void is located between the gate blocking layer and the gate conductive layer.
[0020] In some embodiments, a thickness of the gate blocking layer at a bottom of the gate conductive layer is greater than a thickness of the gate blocking layer at a sidewall of the gate conductive layer.
[0021] In some embodiments, a bottom of the gate conductive layer is located in the second isolation layer; or,
[0022] A bottom of the gate conductive layer is located in the third isolation layer.
[0023] In some embodiments, the gate conductive layer comprises a first portion, the first portion is located in the second isolation layer, a cross-sectional dimension of the first portion gradually decreases from bottom to top along a thickness direction of the substrate, so that a profile of the first portion is in an inverted cone shape.
[0024] In some embodiments, the gate conductive layer further comprises a second portion, the second portion is located below the first portion and directly contacts the first portion.
[0025] At least part of the second portion is located in the second isolation layer, and a cross-sectional dimension of the second portion in a second horizontal direction is smaller than a minimum cross-sectional dimension of the first portion.
[0026] In some optional embodiments, a bottom of the gate blocking layer is located in the third isolation layer, and a profile of the bottom of the gate blocking layer is one of a circular arc shape and an inverted taper shape.
[0027] In some optional embodiments, the bottom of the gate blocking layer includes a first blocking layer, and a cross-sectional dimension of the first blocking layer in a second horizontal direction decreases successively from bottom to top along a thickness direction of the substrate, so that a profile of the first blocking layer is an inverted taper shape.
[0028] In some optional embodiments, the bottom of the gate blocking layer further includes a second blocking layer, the second blocking layer is located below the first blocking layer and directly contacts the first blocking layer.
[0029] A profile of the second blocking layer along the thickness direction of the substrate is one of a strip shape and an inverted taper shape.
[0030] A second aspect of an embodiment of the present application provides a semiconductor device, comprising:
[0031] A substrate includes an isolation structure and an active structure defined by the isolation structure, the isolation structure includes a first isolation layer, a second isolation layer and a third isolation layer stacked successively, a material of the second isolation layer is different from materials of the first isolation layer and the third isolation layer, the second isolation layer includes a first portion extending in a first direction and a second portion extending in a thickness direction of the substrate.
[0032] A word line structure crosses the isolation structure and the active structure in the first direction, and a bottom of the word line structure located in the peripheral region is lower than a top of the first portion in the thickness direction of the substrate.
[0033] A third aspect of an embodiment of the present application provides a semiconductor device, comprising:
[0034] A substrate includes an isolation structure and an active structure defined by the isolation structure, the isolation structure includes:
[0035] A first isolation layer directly contacts the active structure.
[0036] A second isolation layer is located on the first isolation layer, the second isolation layer includes a first portion extending in a first direction and a second portion extending in a thickness direction of the substrate.
[0037] A third isolation layer is located on the second isolation layer; the material of the second isolation layer is different from the material of the first isolation layer and the third isolation layer.
[0038] A word line structure extends along a first direction and partially overlaps with the isolation structure, wherein an end surface of one end of the word line structure directly contacts an end surface of the first part of the second isolation layer along the first direction.
[0039] In some optional embodiments, the bottom of at least part of the word line structure is lower than the top of the third isolation layer and is not lower than the bottom of the third isolation layer.
[0040] In some optional embodiments, the bottom profile of at least part of the word line structure is curved along the first direction.
[0041] In one embodiment of the present application, the bottom of the word line structure in the peripheral region of the semiconductor device is lower than the top of the first part of the second isolation layer, so that more word line structures can be deposited under the peripheral region of the semiconductor device, the material used to form the word line structure has high mechanical strength, and a more stable support can be formed on the upper structure of the peripheral region, thereby overcoming the problem that the structure close to the upper layer in the peripheral region is easily deformed in the prior art. Secondly, the material of the second isolation layer in the semiconductor device is different from the material of the first isolation layer and the third isolation layer, so that the first part of the second isolation layer or the third isolation layer can be used as an etching stop layer during preparation, so that the depth of the word line structure in the isolation layer can be controlled, and it is ensured that the word line structure does not contact the active structure, and more word line structures are located in the isolation layer and do not occupy the area above the word line structure, which is beneficial to the integration of other elements and further improves the integration of the semiconductor device.
[0042] In addition to the technical problems solved by the embodiments of the present application, the technical features constituting the technical solutions and the beneficial effects brought by these technical features described above, other technical problems solved by the semiconductor device provided by the embodiments of the present application, other technical features included in the technical solutions and the beneficial effects brought by these technical features will be further described in detail in the specific embodiments. BRIEF DESCRIPTION OF DRAWINGS
[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.
[0044] Figure 1Part plan structure schematic diagram of semiconductor device provided for the embodiment of the present application;
[0045] Figure 2 For Figure 1 Cross-sectional schematic diagram at A-A in the middle;
[0046] Figure 3 For Figure 1 Cross-sectional schematic diagram at B-B in the middle;
[0047] Figure 4 For Figure 2 Structure schematic diagram of part structure in the middle;
[0048] Figure 5 For Figure 2 Another structure schematic diagram of part structure in the middle;
[0049] Figure 6 For Figure 2 Still another structure schematic diagram of part structure in the middle;
[0050] Figure 7 For Figure 2 Still another structure schematic diagram of part structure in the middle;
[0051] Figure 8 For Figure 2 Still another structure schematic diagram of part structure in the middle;
[0052] Figure 9 For Figure 2 Still another structure schematic diagram of part structure in the middle;
[0053] Figure 10 For Figure 2 Still another structure schematic diagram of part structure in the middle.
[0054] Explanation of reference signs:
[0055] 10-semiconductor device;
[0056] 100-substrate; 110-active structure;
[0057] 200-isolation structure; 210-first isolation layer; 220-second isolation layer; 221-first part;
[0058] 222-second part; 230-third isolation layer;
[0059] 300-word line structure; 310-gate conductive layer; 311-first part; 312-second part;
[0060] 320-gate blocking layer; 321-first blocking layer; 322-second blocking layer;
[0061] 330 - gate dielectric layer; 340 - polysilicon layer;
[0062] 400 - gate cover insulating layer;
[0063] 500 - void;
[0064] 600 - bit line structure; 610 - bit line lower electrode; 620 - bit line middle electrode; 630 - bit line upper electrode; 640 - bit line cover layer; 650 - bit line spacer layer; 660 - contact plug;
[0065] 700 - buffer layer. DETAILED DESCRIPTION
[0066] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the following will be combined with the accompanying drawings for the embodiments of the present application to make a clear and complete description of the technical solutions in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application. The following embodiments and features in the embodiments can be combined with each other without conflict.
[0067] Embodiment One
[0068] Please refer to Figure 1 The embodiment of the present application provides a semiconductor device 10, which includes a substrate 100 having a core region and a peripheral region adjacent to the core region, wherein the core region can be represented as COR, and the peripheral region can be represented as POR; the substrate 100 has isolation structures 200 and active structures 110 defined by the isolation structures 200, the isolation structures 200 define the active structures 110 in the core region and the peripheral region respectively, the active structures 110 are multiple, and the multiple active structures 110 can be arranged in an array.
[0069] As shown in Figure 1 The multiple active structures 110 have an included angle with the first direction (represented as D1) and the second direction (represented as D2) respectively, for example, in a planar coordinate system, the first direction D1 is, for example, an X direction in the planar coordinate system, the second direction D2 is, for example, a Y direction in the planar coordinate system, the thickness direction of the substrate 100 is represented as a third direction D3, and the extension direction of the active structure 110 is represented as a fourth direction D4, the fourth direction D4 has an inclined included angle with the first direction D1 and the second direction D2 respectively, wherein the first direction D1 and the second direction D2 both have multiple active structures 110, and the multiple active structures 110 in the first direction D2 and the second direction D2 are both arranged in parallel.
[0070] The substrate 100 can be, for example, a silicon single crystal substrate 100 or a silicon-on-insulator (SOI) substrate 100, and is not specifically limited herein. For example, the substrate 100 can include or be formed of germanium silicon, silicon-on-germanium silicon (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.
[0071] In some embodiments, the isolation structure 200 includes a first isolation structure and a second isolation structure. The first isolation structure is located in the core region and defines a plurality of active structures 110 in the core region. The second isolation structure is located in the peripheral region and defines a plurality of active structures 110 in the peripheral region.
[0072] For example, as shown in FIG. 1, the second isolation structure includes a first isolation layer 210, a second isolation layer 220, and a third isolation layer 230 stacked in the thickness direction D3 of the substrate 100. Figure 2 The material of the second isolation layer 220 is different from that of the first isolation layer 210 and the third isolation layer 230. For example, the material of the second isolation layer 220 is silicon nitride, and the materials of the first isolation layer 210 and the third isolation layer 230 are both silicon oxide. In addition, the second isolation layer 220 includes a first portion 221 extending in the first direction and a second portion 222 extending in the thickness direction of the substrate 100.
[0073] In a specific implementation, an isolation trench is formed on the substrate 100, and then an isolation material such as a silicide is sequentially deposited in the isolation trench. For example, silicon oxide is sequentially deposited in the isolation trench to form a silicon oxide layer covering the trench wall of the isolation trench, thereby forming the third isolation layer 230. Then, a silicon nitride material is deposited on the third isolation layer 230 to form a silicon nitride layer covering the surface of the third isolation layer 230, thereby forming the second isolation layer 220. Then, a silicon oxide material is deposited on the surface of the second isolation layer 220 to form a silicon oxide layer covering the second isolation layer 220 and filling the trench formed by the second isolation layer 220, thereby forming the third isolation layer 230. In this way, the first isolation layer 210, the second isolation layer 220, and the third isolation layer 230 are sequentially stacked in the thickness direction of the substrate 100 from top to bottom. The material of the second isolation layer 220 is different from that of the first isolation layer 210 and the third isolation layer 230, and the second isolation layer 220 includes a first portion 221 extending in the first direction D1 and a second portion 222 extending in the thickness direction of the substrate 100.
[0074] For example, as shown in FIG. 1, the second isolation structure includes a first isolation layer 210, a second isolation layer 220, and a third isolation layer 230 stacked in the thickness direction D3 of the substrate 100. Figure 2The semiconductor device 10 further comprises word line structures 300 extending across the isolation structures 200 and the active structures 110 in the first direction and arranged in the core region and the peripheral region, and the bottom of the word line structures 300 arranged in the peripheral region is lower than the top of the first portion 221 in the thickness direction of the substrate 100.
[0075] Specifically, the forming of the word line structures 300 comprises the following steps: first, removing the isolation structures 200 in the core region and the peripheral region, the remaining isolation structures in the core region are formed as the first isolation structures, and the remaining isolation structures in the peripheral region are formed as the second isolation structures, i.e. the first isolation layer 210, the second isolation layer 220 and the third isolation layer 230 are stacked in the thickness direction of the substrate from top to bottom in the peripheral region. Ideally, the heights of the first isolation layer 210, the second isolation layer 220 and the third isolation layer 230 are consistent, but in the actual preparation process, due to preparation errors, the heights of the remaining first isolation layer 210, the remaining second isolation layer 220 and the remaining third isolation layer 230 in the peripheral region have errors, as long as the height difference of the remaining first isolation layer 210, the remaining second isolation layer 220 and the remaining third isolation layer 230 in the peripheral region is within the error range allowed by the semiconductor device, the specific error range is not limited; then, the remaining first isolation layer 210, the remaining second isolation layer 220 and the remaining third isolation layer 230 in the peripheral region are removed separately, so that the first portion 221 of the second isolation layer 220 in the peripheral region is partially removed, and the bottom of the word line structure filled on the first portion 221 of the second isolation layer 220 is lower than the top of the first portion 221. In detail, the material of the second isolation layer 220 is different from that of the first isolation layer 210 and the third isolation layer 230, and the first portion 221 of the second isolation layer 220 can be used as an etching stop layer, so that the etching endpoint of the isolation structure 200 in the peripheral region can be controlled, and the bottom of the word line structure filled on the isolation layer is lower than the top of the first portion 221.
[0076] It should be noted that, since the material of the second isolation layer 220 is different from that of the first isolation layer 210 and the third isolation layer 230, when the first isolation layer 210 is etched by using an etching gas for etching the first isolation layer 210, the first portion 221 of the second isolation layer 220 can be used as an etching stop layer; when the second isolation layer 220 is etched by using an etching gas for etching the second isolation layer 220, the third isolation layer 230 below the second isolation layer 220 can be used as an etching stop layer, so that the etching endpoint of the isolation structure 200 in the peripheral region can be controlled.
[0077] As shown in FIG. 1, the word line structures 300 extend in the first direction, and the word line structures 300 are a plurality of word line structures 300 arranged in the second direction in sequence and at intervals. Figure 1 As shown in FIG. 1, the word line structures 300 extend in the first direction, and the word line structures 300 are a plurality of word line structures 300 arranged in the second direction in sequence and at intervals.
[0078] Please continue to refer to Figure 2 and Figure 3 As shown, the bottom of the word line structure 300 located in the peripheral region is lower than the top of the third isolation layer 230, but not lower than the bottom of the third isolation layer 230. Specifically, the material of the second isolation layer 220 is different from that of the first isolation layer 210 and the third isolation layer 230. The third isolation layer 230 can be used as an etch stop layer, thereby controlling the etch endpoint of the isolation structure 200 in the peripheral region. This ensures that the bottom of the word line structure 300 filled on the isolation layer is lower than the top of the third isolation layer 230, but not lower than the bottom of the third isolation layer 230. In this way, more word line structures 300 can be filled on the isolation structure 200 in the peripheral region. Since the word line structure 300 contains conductive material, which has better support than insulating material, it can support the components subsequently formed above the semiconductor peripheral region, reducing the probability of tilting of the components located above the peripheral region.
[0079] Please refer to Figure 2 and Figure 3 As shown, the word line structure 300 includes a gate conductive layer 310, a gate barrier layer 320 covering the outer wall of the gate conductive layer 310, and a gate dielectric layer 330 covering the outer wall of the gate barrier layer 320; the semiconductor device 10 also includes a gate covering insulating layer 400, which is located on top of the word line structure 300 and is in direct contact with the word line structure 300, and the projection of the gate covering insulating layer 400 covers the projection of the word line structure 300 along the thickness direction of the substrate 100.
[0080] The gate conductive layer 310 is made of, but is not limited to, metallic tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), or their silicides (such as tungsten silicides and titanium silicides). The gate barrier layer 320 is made of, but is not limited to, titanium nitride (TiN), and is used to prevent ion tunneling between the gate conductive layer 310 and the substrate 100. The gate dielectric layer 330 is made of, but is not limited to, silicon oxide, silicon nitride, or other silicide materials for electrical isolation. In some embodiments, the word line structure 300 may also include only the gate conductive layer 310 and the gate dielectric layer 330, where the gate conductive layer 310 may be titanium nitride (TiN).
[0081] In some embodiments, please refer to Figure 5 and Figure 6 As shown, the bottom outline of the word line structure 300 located in the peripheral area is arc-shaped; or, the bottom outline of the word line structure 300 located in the peripheral area is elliptical arc-shaped. This can optimize the electric field distribution, reduce leakage current and electron migration, thereby improving the overall performance of the semiconductor device 10.
[0082] In some embodiments, as shown in Figure 4 and Figure 7 The bottom profile of the word line structure 300 in the peripheral region is inverted conical, which can improve the compactness of the structure and the integration of the semiconductor device 10 while optimizing the electric field distribution.
[0083] In addition, as shown in Figure 5 The gate blocking layer 320 has at least a void 500, and the profile shape of the void 500 can be circular, elliptical or any other shape, which is not limited here.
[0084] In the embodiments of the present application, by providing the void 500 in the gate blocking layer 320, the stress release space can be provided, and the parasitic capacitance can be effectively reduced, thereby improving the overall performance of the semiconductor device 10.
[0085] In some embodiments, as shown in Figure 5 The bottom of the word line structure 300 in the peripheral region is located in the third isolation layer 230, and the void 500 is located in the gate blocking layer 320 in the third isolation layer 230.
[0086] For example, as shown in Figure 5 The void 500 is located between the gate blocking layer 320 and the gate conductive layer 310, i.e. the void 500 is located between the bottom of the gate conductive layer 310 and the gate blocking layer 320 and directly contacts the bottom of the gate conductive layer 310 and the gate blocking layer 320, and in Figure 5 The void 500 is elliptical, and the long axis direction of the void 500 is consistent with the thickness direction of the substrate 100, and the short axis direction is consistent with the first direction.
[0087] In some embodiments, as shown in Figure 6 The thickness of the gate blocking layer 320 at the bottom of the gate conductive layer 310 is greater than the thickness of the gate blocking layer 320 at the sidewall of the gate conductive layer 310. A polysilicon layer 340 is arranged on the top of the gate conductive layer 310.
[0088] In some embodiments, as shown in Figure 4 The bottom of the gate conductive layer 310 is located in the second isolation layer 220. For example, along the thickness direction of the substrate 100, the bottom of the gate conductive layer 310 is higher than the bottom of the second isolation layer 220 and lower than the top of the second isolation layer 220, or is flush with the top of the second isolation layer 220; or the bottom of the gate conductive layer 310 is flush with the bottom of the second isolation layer 220.
[0089] In some embodiments, the bottom of the gate conductive layer 310 is located in the third isolation layer 230. For example, the bottom of the gate conductive layer 310 is flush with the top of the third isolation layer 230, or the bottom of the gate conductive layer 310 is lower than the top of the third isolation layer 230 and higher than the bottom of the third isolation layer 230.
[0090] In some embodiments, referring back to FIG. 1, Figures 7 to 10 In some embodiments, referring back to FIG. 1,
[0091] In some embodiments, referring back to FIG. 1, Figure 8 and Figure 9 In some embodiments, referring back to FIG. 1,
[0092] For example, in some embodiments, referring back to FIG. 1, Figure 8 and Figure 9 In some embodiments, referring back to FIG. 1, Figure 8 In some embodiments, referring back to FIG. 1, Figure 9 In some embodiments, referring back to FIG. 1,
[0093] In some embodiments, referring back to FIG. 1, Figures 5 to 10 In some embodiments, referring back to FIG. 1,
[0094] In some embodiments, referring back to FIG. 1, the bottom of the gate blocking layer 320 includes a first blocking layer 321. In the thickness direction of the substrate 100, the cross-sectional size of the first blocking layer 321 in the second horizontal direction D2 decreases successively from bottom to top, so that the profile of the first blocking layer 321 is in a reverse tapered structure.
[0095] In some embodiments, the bottom of the gate blocking layer 320 further comprises a second blocking layer 322, which is located below the first blocking layer 321 and directly contacts the first blocking layer 321; the profile of the second blocking layer 322 is one of a long strip structure and an inverted taper structure along the thickness direction D3 of the substrate 100.
[0096] In addition, the semiconductor device 10 provided by the embodiments of the present application further comprises a plurality of bit line structures 600, which extend along the second direction D2, and the plurality of bit line structures 600 are arranged at intervals along the first direction D1.
[0097] Please refer to Figure 2 and Figure 3 As shown, along the thickness direction D3 of the substrate 100 and from bottom to top, the bit line structure 600 comprises a bit line lower electrode 610, a bit line middle electrode 620 and a bit line upper electrode 630 stacked in sequence, the bit line lower electrode 610 comprises but is not limited to polycrystalline silicon doped with impurities. The bit line middle electrode comprises but is not limited to TiSiN. The bit line upper electrode 630 comprises but is not limited to a conductive material such as tungsten (W). In addition, the semiconductor device 10 further comprises a bit line covering layer 640 and a buffer layer 700. The bit line covering layer 640 can be arranged on the bit line structure 600, and the bit line covering layer 640 comprises but is not limited to silicon nitride. The buffer layer 700 is located below the bit line structure 600, and the bit line structure 600 is arranged on the buffer layer 700 to achieve electrical isolation between the bit line structure 600 and other structures through the buffer layer 700, and the sidewall of the bit line structure 600 is further covered with a bit line spacing layer 650 to achieve electrical isolation between the sidewall of the bit line structure 600 and other structures. The bit line spacing layer 650 can be a single-layer structure or a multi-layer structure, and the material of the bit line spacing layer 650 comprises but is not limited to one or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer (SiON), a silicon oxycarbonitride layer (SiOCN), air and a combination thereof. The semiconductor device further comprises a contact plug 660, which directly contacts the word line structure 300 located in the peripheral region.
[0098] Those skilled in the art of the present application should be able to easily understand that, under the premise of meeting the actual product requirements, the semiconductor device of the present application can also have other forms and is not limited to the foregoing. Further embodiments or variations of the semiconductor device of the present application will be described below. For simplicity of description, the following description mainly focuses on the differences between the embodiments, and the same parts are not repeated. In addition, the same components in the embodiments of the present application are marked with the same reference numerals for mutual reference between the embodiments.
[0099] The embodiment of the present application further provides a semiconductor device 10, comprising: a substrate 100 and a word line structure 300, the substrate 100 comprises an isolation structure 200 and an active structure 110 defined by the isolation structure 200, the isolation structure 200 comprises a first isolation layer 210, a second isolation layer 220 and a third isolation layer 230 stacked in sequence; the material of the second isolation layer 220 is different from the material of the first isolation layer 210 and the third isolation layer 230, the second isolation layer 220 comprises a first part 221 extending along a first direction and a second part 222 extending along the thickness direction of the substrate 100; the word line structure 300 crosses the isolation structure 200 and the active structure 110 along the first direction D1, and the bottom of the word line structure 300 in the peripheral region is lower than the top of the first part 221 along the thickness direction of the substrate 100. In this way, more word line structures 300 can be filled on the isolation structure 200 in the peripheral region, and since the word line structure 300 comprises a conductive material, the support of the conductive material is better than that of the insulating material, which can support the elements formed subsequently above the semiconductor peripheral region and reduce the probability of the elements above the peripheral region being tilted.
[0100] It should be noted that in the semiconductor device 10 provided by the embodiment of the present application, the isolation structure 200 in the substrate 100 can be arranged as the first isolation layer 210, the second isolation layer 220 and the third isolation layer 230 stacked in sequence, that is, the isolation structure 200 in the core region and the isolation structure 200 in the peripheral region can all be arranged as a stacked structure, so that the overall mechanical strength of the semiconductor device 10 can be improved, and the isolation materials of adjacent isolation layers are different, so that the electrical isolation performance between different regions is effectively improved and the overall performance of the semiconductor device 10 is improved. In addition, whether the word line structure 300 in the core region or the word line structure 300 in the peripheral region, the bottom of the word line structure 300 can be lower than the top of the first part 221 in the second isolation layer 220.
[0101] That is, the isolation structure 200 in the core region and the peripheral region can be set to have the first isolation layer 210, the second isolation layer 220 and the third isolation layer 230 stacked in the thickness direction of the substrate 100 from top to bottom according to specific requirements, wherein the second isolation layer 220 includes the first part 221 extending in the first direction D1 and the second part 222 extending in the thickness direction of the substrate 100, so that according to specific requirements, the bottom of the word line structure 300 in the core region and the peripheral region can be lower than the top of the first part 221 of the second isolation layer 220 in the corresponding region, therefore, it is not limited that the bottom of the word line structure 300 in the peripheral region is lower than the top of the first part 221 of the second isolation layer 220 in the peripheral region, in the whole semiconductor device 10, the bottom of the word line structure 300 in different regions is lower than the top of the first part 221 of the second isolation layer 220 in the corresponding isolation structure 200, or the bottom of part of the word line structure 300 in the same region is lower than the top of the first part 221 of the second isolation layer 220 in the corresponding isolation structure 200, etc., all of which are within the protection scope of the embodiments of the present application.
[0102] The embodiments of the present application also provide a semiconductor device 10, comprising a substrate 100 and a word line structure 300, the substrate 100 includes an isolation structure 200 and an active structure 110 defined by the isolation structure 200, the isolation structure 200 includes a first isolation layer 210, a second isolation layer 220 and a third isolation layer 230, the first isolation layer 210 is in direct contact with the active structure 110, the second isolation layer 220 is located on the first isolation layer 210, the second isolation layer 220 includes a first part 221 extending in the first direction and a second part 222 extending in the thickness direction of the substrate 100; the third isolation layer 230 is located on the second isolation layer 220; the material of the second isolation layer 220 is different from the material of the first isolation layer 210 and the third isolation layer 230; the word line structure 300 extends in the first direction and partially overlaps with the isolation structure 200, wherein in the first direction, the end surface of one end of the word line structure 300 is in direct contact with the end surface of the first part 221 of the second isolation layer 220.
[0103] In this embodiment, on the one hand, by designing the isolation structure 200 as a stacked structure, the overall mechanical strength of the semiconductor device 10 can be improved. Simultaneously, the different isolation materials of adjacent isolation layers effectively improve the electrical isolation performance between different regions, thereby enhancing the overall performance of the semiconductor device 10. Furthermore, during fabrication, the first or third isolation layer in the second isolation layer can be used as an etch stop layer. This allows control over the depth of the word line structure 300 within the isolation structure 200, ensuring that the word line structure 300 does not contact the active structure 110. Additionally, most of the word line structures 300 are located within the isolation structure 200 and do not occupy the area above the word line structure. This facilitates the integration of other components, further improving the integration level of the semiconductor device 10. On the other hand, the word line structure 300 extends along the first direction and partially overlaps with the isolation structure 200, and the end face of one end of the word line structure 300 in the first direction is in direct contact with the end face of the first part 221 of the second isolation structure. More word line structures 300 can be filled on the isolation structure 200. Since the word line structure 300 contains conductive material, the conductive material has better support than the insulating material, which can support the components subsequently formed above the semiconductor peripheral area, reduce the probability of tilting of the components located above the peripheral area, and improve the overall performance of the semiconductor device 10.
[0104] In some embodiments, please refer to Figure 2 As shown, the bottom of at least a portion of the word line structure 300 is lower than the top of the third isolation layer 230, but not lower than the bottom of the third isolation layer 230.
[0105] Please continue to refer to Figure 2 As shown, along the first direction, at least a portion of the bottom profile of the character line structure 300 is curved, exemplarily, as in... Figure 2 In the text, the bottom outline of part of the character line structure 300 is curved. This curve includes, but is not limited to, circular arcs, elliptical arcs, spline curves, or other arbitrary curved structures, without specific restrictions.
[0106] In this embodiment, by designing the bottom contour of at least a portion of the word line structure 300 as a curve, the electric field can be effectively dispersed, the electric field concentration reduced, the signal transmission rate of the word line structure 300 improved, and the overall performance of the device enhanced.
[0107] In general, terminology can be understood at least in part from usage in context. For example, and as used herein, the term "one or more" can describe any feature, structure, or characteristic in the singular or can describe combinations of features, structures, or characteristics, in the plural, depending on the context in which such terms are used. Similarly, terms, such as "a," "an," or "the," again, can be understood to convey a singular usage or to convey a plural usage, depending on the context in which such terms are used.
[0108] It will be readily understood that the terms "on," "above," and "on top of," as used herein, should be interpreted in the broadest context possible so that "on" means not only "directly on" but also includes the meaning of "on with intervening features or layers therebetween," and "above" or "on top of" includes not only the meaning of "above" or "on top of" but also can include the meaning of "above" or "on top of" with no intervening features or layers therebetween (i.e., directly on).
[0109] In addition, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90° or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
[0110] Finally, it should be noted that the above-described embodiments are merely intended to illustrate the technical solutions of the present application, but not to limit the same; even though the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions recorded in the above embodiments, or equivalent replacements can be made to some or all of the technical features thereof; and such modifications or replacements do not cause the essence of the corresponding technical solutions to depart from the scope of the technical solutions of the embodiments of the present application.
Claims
1. A semiconductor device, characterized in that, include: A substrate having a core region and a peripheral region adjacent to the core region, wherein the substrate includes an isolation structure and an active structure defined by the isolation structure, the isolation structure comprising: The first isolation structure is located in the core area; A second isolation structure is located in the peripheral region. The second isolation structure includes a first isolation layer, a second isolation layer, and a third isolation layer stacked sequentially. The material of the second isolation layer is different from the materials of the first isolation layer and the third isolation layer. The second isolation layer includes a first portion extending along a first direction and a second portion extending along the thickness direction of the substrate. A word line structure, which spans the isolation structure and the active structure along the first direction and is disposed in the core region and the peripheral region, wherein the bottom of the word line structure located in the peripheral region along the thickness direction of the substrate is lower than the top of the first part.
2. The semiconductor device according to claim 1, characterized in that, Along the thickness direction of the substrate, the word line structure located in the peripheral region penetrates the second isolation layer.
3. The semiconductor device according to claim 2, characterized in that, The bottom of the word line structure located in the peripheral area is lower than the top of the third isolation layer, but not lower than the bottom of the third isolation layer.
4. The semiconductor device according to any one of claims 1-3, characterized in that, The word line structure includes a gate conductive layer, a gate barrier layer covering the outer wall of the gate conductive layer, and a gate dielectric layer covering the outer wall of the gate barrier layer. The semiconductor device further includes a gate cover insulating layer, which is located on top of the word line structure and in direct contact with the word line structure. Along the thickness direction of the substrate, the projection of the gate cover insulating layer covers the projection of the word line structure.
5. The semiconductor device according to claim 4, characterized in that, The bottom outline of the character line structure located in the outer perimeter area is arc-shaped.
6. The semiconductor device according to claim 5, characterized in that, The bottom outline of the character line structure located in the outer perimeter area is an inverted cone shape.
7. The semiconductor device according to claim 4, characterized in that, At least the gate barrier layer has voids.
8. The semiconductor device according to claim 7, characterized in that, The bottom of the word line structure located in the peripheral region is located in the third isolation layer, and the gap is located in the gate barrier layer in the third isolation layer.
9. The semiconductor device according to claim 7, characterized in that, The gap is located between the gate barrier layer and the gate conductive layer.
10. The semiconductor device according to claim 4, characterized in that, The thickness of the gate barrier layer located at the bottom of the gate conductive layer is greater than the thickness of the gate barrier layer located on the sidewall of the gate conductive layer.
11. The semiconductor device according to claim 4, characterized in that, The bottom of the gate conductive layer is located within the second isolation layer; or... The bottom of the gate conductive layer is located in the third isolation layer.
12. The semiconductor device according to claim 11, characterized in that, The gate conductive layer includes a first portion located in the second isolation layer. Along the thickness direction of the substrate and from bottom to top, the cross-sectional size of the first portion gradually decreases so that the outline of the first portion has an inverted conical structure.
13. The semiconductor device according to claim 12, characterized in that, The gate conductive layer further includes a second portion, which is located below the first portion and in direct contact with the first portion; At least a portion of the second part is located in the second isolation layer along the second horizontal direction, and the cross-sectional dimension of the second part is smaller than the minimum cross-sectional dimension of the first part.
14. The semiconductor device according to claim 4, characterized in that, The bottom of the gate barrier layer is located in the third isolation layer, and the bottom contour of the gate barrier layer is either an arc shape or an inverted cone shape.
15. The semiconductor device according to claim 14, characterized in that, The bottom of the gate barrier layer includes a first barrier layer. Along the thickness direction of the substrate and from bottom to top, the cross-sectional dimensions of the first barrier layer decrease sequentially in the second horizontal direction, so that the outline of the first barrier layer has an inverted conical structure.
16. The semiconductor device according to claim 15, characterized in that, The bottom of the gate barrier layer also includes a second barrier layer, which is located below the first barrier layer and in direct contact with the first barrier layer. Along the thickness direction of the substrate, the outline of the second barrier layer is either an elongated strip structure or an inverted conical structure.
17. A semiconductor device, characterized in that, include: A substrate includes an isolation structure and an active structure defined by the isolation structure, the isolation structure including a first isolation layer, a second isolation layer and a third isolation layer stacked sequentially; the material of the second isolation layer is different from the materials of the first isolation layer and the third isolation layer; the second isolation layer includes a first portion extending along a first direction and a second portion extending along the thickness direction of the substrate. A word line structure, wherein the word line structure crosses the isolation structure and the active structure along a first direction, and along the thickness direction of the substrate, the bottom of the word line structure is lower than the top of the first part.
18. A semiconductor device, characterized in that, include: A substrate, including an isolation structure and an active structure defined by the isolation structure, the isolation structure comprising: The first isolation layer is in direct contact with the active structure; A second isolation layer is located on the first isolation layer, and the second isolation layer includes a first portion extending along a first direction and a second portion extending along the thickness direction of the substrate; A third isolation layer is located on top of the second isolation layer; the material of the second isolation layer is different from the materials of the first isolation layer and the third isolation layer. A character line structure, wherein the character line structure extends along a first direction and partially overlaps with the isolation structure, wherein, along the first direction, the end face of one end of the character line structure is in direct contact with the end face of the first part of the second isolation layer.
19. The semiconductor device according to claim 18, characterized in that, At least a portion of the word line structure has its bottom lower than the top of the third isolation layer, but not lower than the bottom of the third isolation layer.
20. The semiconductor device according to claim 18, characterized in that, Along the first direction, at least a portion of the bottom profile of the word line structure is curved.