Method for manufacturing deep groove in DRAM (Dynamic Random Access Memory)
By ion implantation to form a protective layer at the edge of the DRAM deep trench substrate, the problem of damage to the silicon substrate edge during etching and polishing is solved, simplifying the process flow, improving polishing efficiency, and reducing costs.
Patent Information
- Application Number
- CN202511041790.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-28
- Publication Date
- 2025-11-04
AI Technical Summary
During DRAM fabrication, the edges of the deep trench silicon substrate are susceptible to damage during chemical mechanical polishing (CMP), leading to breakage and polishing defects. Existing additional protective films affect polishing efficiency and increase costs.
An ion implantation layer is formed by implanting ions at a predetermined depth and concentration into the first silicon oxide layer at the substrate edge, thereby improving the edge's resistance to silicon etching, simplifying the process flow, and reducing the risk of grinding defects.
No additional protective film layer is required, simplifying the process, improving the stability and efficiency of chemical mechanical grinding, reducing grinding defects and fragmentation risks, and saving preparation costs.
Smart Images
Figure CN120897448A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor, and particularly relates to a manufacturing method of deep trench in DRAM. BACKGROUND
[0002] In the preparation of DRAM (Dynamic Random Access Memory), the deep trench is a process for preparing the DRAM. The manufacturing process of the deep trench is used for manufacturing the capacitor in the DRAM product. After the deep trench is formed, the conductive layer is filled in the deep trench, and then the chemical mechanical polishing process is used to polish and remove the excess silicon oxide and the conductive layer. When the deep trench etching is performed, if the protection of the edge of the substrate is not enough, the silicon substrate etching of the deep trench will cause the damage of the edge of the substrate. In the subsequent chemical mechanical polishing process, the damage and defects of the edge of the substrate are easy to cause the breakage in the process, thereby reducing the yield of the product. The common method for protecting the edge of the substrate is to use the additional oxide and / or nitride film to protect the edge of the substrate, so as to prevent the damage of the edge of the substrate. However, the additional nitride or oxide reduces the chemical mechanical efficiency, and the defects and damage of the edge are more likely to cause the breakage of the substrate or the polishing defects. SUMMARY
[0003] The present application aims to provide a manufacturing method of deep trench in DRAM, the ion implantation layer can protect the edge of the substrate, is easy to prepare, saves the preparation cost, and improves the stability of the chemical mechanical polishing.
[0004] In order to achieve the above-mentioned purpose, the present application provides a manufacturing method of deep trench in DRAM, comprising:
[0005] providing a substrate, at least a first silicon oxide layer is formed on the substrate;
[0006] applying a photoresist layer on the surface of the first silicon oxide layer, and removing the photoresist layer on the edge of the substrate by using the EBR process of photolithography;
[0007] forming an ion implantation layer by ion implantation of the first silicon oxide layer exposed on the edge of the substrate at a preset depth and a preset concentration, and removing the photoresist layer after the ion implantation;
[0008] forming a deep trench by photolithography and etching, the deep trench penetrates through the first silicon oxide layer and extends to part of the substrate;
[0009] filling a conductive layer in the deep trench, and the conductive layer covers the first silicon oxide layer;
[0010] polishing the conductive layer and the first silicon oxide layer by chemical mechanical polishing and stopping in the first silicon oxide layer, and removing the ion implantation layer in the first silicon oxide layer by polishing.
[0011] Optionally, the width of the ion implantation layer is the same as the width of the substrate edge.
[0012] Optionally, the width of the substrate edge is greater than 0mm and less than or equal to 3mm.
[0013] Optionally, the preset depth of the ion implantation layer is less than the thickness of the first silicon oxide layer.
[0014] Optionally, the preset depth of the ion implantation layer is 50nm-100nm.
[0015] Optionally, the doping ions of the ion implantation layer include nitrogen ions or carbon ions.
[0016] Optionally, the preset concentration of the ion implantation layer is 1×10 12 ions / cm 2 -1×10 16 ions / cm 2 .
[0017] Optionally, during the chemical mechanical polishing, the conductive layer on the first silicon oxide layer is polished and removed first, and then part of the first silicon oxide layer, the ion implantation layer and part of the conductive layer in the deep trench are polished and removed.
[0018] In the method for manufacturing a deep trench in a DRAM provided by the application, the method comprises the following steps: providing a substrate, wherein the substrate has at least a first silicon oxide layer; applying a photoresist layer on the surface of the first silicon oxide layer, and removing the photoresist layer on the edge of the substrate by using EBR process of photolithography; performing ion implantation on the first silicon oxide layer exposed on the edge of the substrate to form an ion implantation layer with a preset depth and a preset concentration, and removing the photoresist layer after the ion implantation; forming a deep trench by photolithography and etching, wherein the deep trench penetrates the first silicon oxide layer and extends to part of the substrate; filling a conductive layer in the deep trench, and covering the first silicon oxide layer with the conductive layer; polishing the conductive layer and the first silicon oxide layer by chemical mechanical polishing and stopping in the first silicon oxide layer, and polishing and removing the ion implantation layer in the first silicon oxide layer.
[0019] The application realizes modification of the first silicon oxide layer exposed at the edge of the substrate to form an ion implantation layer by ion implantation of the first silicon oxide layer exposed at the edge of the substrate at a preset depth and a preset concentration, so that the ion implantation layer can improve the ability of the edge of the substrate to resist silicon etching and plays a role in protecting the edge of the substrate during the deep trench etching process. The manufacturing method provided by the application forms a substrate edge protection structure by ion implantation of the first silicon oxide layer at the edge of the substrate. The manufacturing method provided by the application does not need to manufacture an additional substrate edge protection film layer when deep trench etching is performed, simplifying the process flow of deep trench capacitor manufacturing; at the same time, in this manufacturing method, the substrate edge and the middle film layer structure are consistent, reducing the risk of grinding defects and fragments during subsequent chemical mechanical grinding. According to the change of the aspect ratio value of the manufactured deep trench, the concentration and depth of ion implantation can be adaptively adjusted to form a corresponding substrate edge protection structure. BRIEF DESCRIPTION OF DRAWINGS
[0020] Figure 1 It is a cross-sectional view of the substrate provided in the manufacturing method of the deep trench in the DRAM.
[0021] Figure 2 It is a cross-sectional view of the photoresist layer formed in the manufacturing method of the deep trench in the DRAM.
[0022] Figure 3 It is a cross-sectional view of the substrate provided in the manufacturing method of the deep trench in the DRAM.
[0023] Figure 4 It is a cross-sectional view of the substrate provided in the manufacturing method of the deep trench in the DRAM.
[0024] Figure 5 It is a cross-sectional view of the substrate provided in the manufacturing method of the deep trench in the DRAM.
[0025] Figure 6 It is a cross-sectional view of the substrate provided in the manufacturing method of the deep trench in the DRAM.
[0026] Figure 7 It is a flowchart of the manufacturing method of the deep trench in the DRAM provided by an embodiment of the application.
[0027] Figure 8 It is a cross-sectional view of the substrate provided in the manufacturing method of the deep trench in the DRAM provided by an embodiment of the application.
[0028] Figure 9 It is a cross-sectional view of the photoresist layer formed in the manufacturing method of the deep trench in the DRAM provided by an embodiment of the application.
[0029] Figure 10 Figure 4 is a cross-sectional view of the DRAM after forming the ion implantation layer in the method for manufacturing a deep trench in a DRAM according to an embodiment of the present application.
[0030] Figure 11 Figure 5 is a cross-sectional view of the DRAM after forming the deep trench in the method for manufacturing a deep trench in a DRAM according to an embodiment of the present application.
[0031] Figure 12 Figure 6 is a cross-sectional view of the DRAM after forming the conductive layer in the method for manufacturing a deep trench in a DRAM according to an embodiment of the present application.
[0032] Figure 13 Figure 7 is a cross-sectional view of the DRAM after performing the chemical mechanical polishing in the method for manufacturing a deep trench in a DRAM according to an embodiment of the present application.
[0033] In the drawings, Figures 1-6 The reference signs in the drawings are as follows:
[0034] 10 - substrate; 10A - center region; 10B - edge region; 21 - first silicon oxide layer; 30 - nitride layer; 22 - second silicon oxide layer; 40 - photoresist layer; 50 - deep trench; 60 - conductive layer.
[0035] Figures 8-13 The reference signs in the drawings are as follows:
[0036] 100 - substrate; 100A - center region; 100B - edge region; 120 - doped substrate layer; 120a - doped region; 140 - buried insulating oxide layer; 160 - device layer; 200 - nitride layer; 310 - first silicon oxide layer; 320 - second silicon oxide layer; 400 - photoresist layer; 500 - ion implantation layer; 600 - deep trench; 700 - conductive layer. DETAILED DESCRIPTION
[0037] In order to resist the damage of silicon etching to the edge of the substrate when manufacturing the deep trench, a silicon nitride film with a thickness of about 80 nm and a silicon oxide film with a thickness of about 1000 nm are additionally grown at the edge of the substrate. When performing the chemical mechanical polishing process, the silicon nitride film additionally formed at the edge of the substrate affects the polishing efficiency of the center of the substrate, reduces the polishing rate, and thus affects the polishing effect of the chemical mechanical polishing process.
[0038] Figure 1 Figure 1 is a cross-sectional view of the substrate in the method for manufacturing a deep trench in a DRAM. Please refer to Figure 1, a substrate 10 is provided, the substrate 10 includes a center region 10A and an edge region 10B, the specific structure of the substrate 10 is not described here, the material of the substrate 10 includes silicon; the substrate 10 is sequentially formed with a first silicon oxide layer 21, a nitride layer 30 and a second silicon oxide layer 22 from bottom to top, the nitride layer 30 and the second silicon oxide layer 22 here are respectively the above-mentioned silicon nitride film with a thickness of about 80 nm and the silicon oxide film with a thickness of about 1000 nm, and other process layers on the substrate 10 are not described here.
[0039] Figure 2 It is a cross-sectional view of a photoresist layer after forming in a deep trench manufacturing method of a DRAM. Please refer to Figure 2 , the photoresist layer 40 is coated on the surface of the second silicon oxide layer 22, and the photoresist layer 40 on the center region 10A of the substrate 10 is removed.
[0040] Figure 3 It is a cross-sectional view of etching the second silicon oxide layer and the nitride layer after forming in a deep trench manufacturing method of a DRAM. Please refer to Figure 3 , the second silicon oxide layer 22 and the nitride layer 30 are etched to expose the first silicon oxide layer 21 on the center region 10A, the second silicon oxide layer 22 and the nitride layer 30 remaining after etching are used as edge protection layer, and the photoresist layer 40 is removed after etching.
[0041] Figure 4 It is a cross-sectional view of forming a deep trench after forming in a deep trench manufacturing method of a DRAM. Please refer to Figure 4 , at least the first silicon oxide layer 21 and part of the substrate 10 are etched to form a plurality of deep trenches 50, the deep trenches 50 are located in the center region 10A and the edge region 10B, and the edge protection layer can resist the damage of silicon etching to the edge region 10B of the substrate 10 when the deep trenches 50 are etched. Due to the existence of the additional edge protection layer, the depth of the deep trench 50 in the edge region 10B is slightly shallower than the depth of the deep trench 50 in the center region 10A.
[0042] Figure 5 It is a cross-sectional view of forming a conductive layer after forming in a deep trench manufacturing method of a DRAM. Please refer to Figure 5 , a conductive layer 60 is formed to fill the deep trench and cover the remaining second silicon oxide layer 22 and first silicon oxide layer 21.
[0043] Figure 6 It is a cross-sectional view of performing a chemical mechanical polishing process after forming in a deep trench manufacturing method of a DRAM. Please refer to Figure 5 and Figure 6, the chemical mechanical polishing of the conductive layer 60, the first silicon oxide layer 21, the remaining second silicon oxide layer 22 and the remaining nitride layer 30, however, the remaining nitride layer 30 will affect the polishing efficiency of the first silicon oxide layer 21 in the central region 10A of the substrate 10, so that the polishing rate is reduced, thereby affecting the polishing effect of the chemical mechanical polishing process.
[0044] Based on this, the present application provides a manufacturing method of a deep trench in a DRAM, comprising: providing a substrate, at least a first silicon oxide layer is formed on the substrate; coating a photoresist layer on the surface of the first silicon oxide layer, and removing the photoresist layer at the edge of the substrate by using the EBR process of photolithography; performing ion implantation on the first silicon oxide layer exposed at the edge of the substrate to form an ion implantation layer with a preset depth and a preset concentration, and removing the photoresist layer after ion implantation; forming a deep trench by photolithography and etching, the deep trench penetrates through the first silicon oxide layer and extends to part of the substrate; filling a conductive layer in the deep trench, and the conductive layer covers the first silicon oxide layer; and polishing the conductive layer and the first silicon oxide layer and stopping in the first silicon oxide layer, and the ion implantation layer in the first silicon oxide layer is removed by polishing. In the present application, the ion implantation layer can improve the ability of the edge of the substrate to resist silicon etching, and plays a role in protecting the edge of the substrate during the deep trench etching process. The manufacturing method provided by the present application forms a substrate edge protection structure by ion implantation on the first silicon oxide layer at the edge of the substrate. The manufacturing method provided by the present application does not need to manufacture an additional substrate edge protection film layer when performing deep trench etching, simplifying the process flow of deep trench capacitor manufacturing; at the same time, in this manufacturing method, the film layer structure at the edge of the substrate and in the middle is consistent, reducing the risk of polishing defects and fragments during subsequent chemical mechanical polishing. According to the change of the aspect ratio value of the manufactured deep trench, the concentration and depth of ion implantation can be adjusted to form a corresponding substrate edge protection structure.
[0045] To make the objectives, advantages and features of the present application clearer, the following will further describe the present application in detail with reference to the drawings and specific embodiments. It should be noted that the drawings are very simplified and not drawn to scale, and are only used to facilitate and clarify the purpose of assisting the description of the embodiments of the present application. In addition, the structures shown in the drawings are often part of the actual structures. In particular, different scales are sometimes used in different drawings to show different focuses.
[0046] Figure 7 The flow chart of the manufacturing method of a deep trench in a DRAM provided by the present embodiment. The present embodiment provides a manufacturing method of a deep trench in a DRAM, comprising:
[0047] Step S1: providing a substrate, at least a first silicon oxide layer is formed on the substrate;
[0048] Step S2: coating a photoresist layer on the surface of the first silicon oxide layer, and removing the photoresist layer at the edge of the substrate by using the EBR process of photolithography;
[0049] Step S3: ion implantation of the first silicon oxide layer exposed by the substrate edge to form an ion implantation layer, and the photoresist layer is removed after ion implantation;
[0050] Step S4: photoetching and etching to form a deep trench, the deep trench penetrates the first silicon oxide layer and extends to part of the substrate;
[0051] Step S5: filling the deep trench with a conductive layer, and the conductive layer covers the first silicon oxide layer;
[0052] Step S6: chemical mechanical polishing of the conductive layer and the first silicon oxide layer and stopping in the first silicon oxide layer, and the ion implantation layer in the first silicon oxide layer is removed by polishing.
[0053] Figure 8 The cross-sectional view of the substrate after the deep trench manufacturing method in the DRAM provided by the embodiment is provided. Figure 9 The cross-sectional view of the substrate after the deep trench manufacturing method in the DRAM provided by the embodiment is provided. Figure 10 The cross-sectional view of the substrate after the deep trench manufacturing method in the DRAM provided by the embodiment is provided. Figure 11 The cross-sectional view of the substrate after the deep trench manufacturing method in the DRAM provided by the embodiment is provided. Figure 12 The cross-sectional view of the substrate after the deep trench manufacturing method in the DRAM provided by the embodiment is provided. Figure 13 The cross-sectional view of the substrate after the deep trench manufacturing method in the DRAM provided by the embodiment is provided. The following will be described in detail Figures 8-13 The deep trench manufacturing method in the DRAM provided by the embodiment is described in detail.
[0054] Please refer to Figure 8 , execute step S1: provide a substrate 100, the substrate 100 is preferably an SOI substrate, the substrate 100 includes a doped substrate layer 120, an insulating buried oxygen layer 140 and a device layer 160 stacked from bottom to top, wherein the doped substrate layer 120 has a doped region 120a (deep well region) formed therein, the top surface of the doped region 120a is in contact with the bottom surface of the insulating buried oxygen layer 140, and the device layer 160 is doped to form an active region; the material of the doped substrate layer 120 and the device layer 160 is preferably silicon, and the material of the insulating buried oxygen layer 140 is preferably silicon oxide. The substrate 100 includes a central region 100A and an edge region 100B, wherein the edge region 100B surrounds the central region 100A, and in the embodiment, the width S of the substrate 100 edge (edge is the edge region 100B) can be greater than 0 mm and less than or equal to 3 mm, preferably 2 mm to 3 mm, and is not limited thereto.
[0055] The substrate 100 is formed with a second silicon oxide layer 320, a nitride layer 200 and a first silicon oxide layer 310 stacked in order from bottom to top; the material of the nitride layer 200 is preferably silicon nitride, the thickness of the first silicon oxide layer 310 is greater than the thickness of the second silicon oxide layer 320 and the nitride layer 200, and the second silicon oxide layer 320 serves as a pad oxide layer.
[0056] Please refer to Figure 9 , step S2 is performed: applying a photoresist layer 400 on the surface of the first silicon oxide layer 310, and removing the photoresist layer 400 on the edge of the substrate 100 by using an EBR (Edge Bead Removal) process of photolithography to expose the first silicon oxide layer 310 on the edge of the substrate 100, wherein the EBR process can be realized by wafer edge exposure and / or chemical edge removal.
[0057] Please refer to Figure 10 , step S3 is performed: taking the photoresist layer 400 as a mask, performing ion implantation of a preset depth and a preset concentration on the first silicon oxide layer 310 exposed on the edge of the substrate 100 to form an ion implantation layer 500 (the arrow direction in the figure is the ion implantation direction), so as to form the ion implantation layer 500 in the first silicon oxide layer 310 exposed on the edge of the substrate 100; and removing the photoresist layer 400 after ion implantation. In the embodiment, the preset depth of the ion implantation layer 500 is less than the thickness of the first silicon oxide layer 310, the width of the ion implantation layer 500 is the same as the width S of the edge of the substrate 100, and the preset depth of the ion implantation layer 500 is preferably 50-100 nm. In the embodiment, the ion implantation layer 500 is a substrate edge protection structure, the doping ions of the ion implantation layer 500 include nitrogen ions or carbon ions, and the preset concentration of the ion implantation layer 500 can be 1×1018 ions / cm3-1×1019 ions / cm3. 12 2 16 2 The material of the ion implantation layer 500 includes nitrogen-doped silicon oxide or carbon-doped silicon oxide, the depth of the ion implantation layer 500 is determined according to the doping energy of the ion implantation process, the depth of the ion implantation layer 500 is the thickness of the ion implantation layer 500, the concentration and depth of the ion implantation can be adjusted adaptively to form a corresponding substrate edge protection structure according to the change of the aspect ratio of the deep trench to be manufactured, and the adjustability of the process is enhanced. The first silicon oxide layer 310 exposed at the edge of the substrate 100 is modified to form the ion implantation layer 500 by ion implantation with a preset depth and a preset concentration, the modified ion implantation layer 500 is a nitrogen-rich or carbon-rich silicon oxide layer, the ion implantation layer 500 can improve the ability of the edge of the substrate 100 to resist silicon etching, and plays a role in protecting the edge of the substrate 100 in the subsequent process of manufacturing the deep trench; and there is no need to manufacture an additional substrate edge protection film layer (such as a silicon nitride film and a silicon oxide film), which simplifies the process flow of manufacturing the deep trench capacitor, is easier to manufacture, and saves manufacturing cost.
[0058] Please refer to Figure 11 , execute step S4: photoetching and etching to form a deep trench 600, specifically, a patterned photoresist (not shown in the figure) is formed on the first silicon oxide layer 310 by using a photoetching process, and then the first silicon oxide layer 310 on the substrate 100 and part of the substrate 100 are etched to form the deep trench 600, the deep trench 600 penetrates the first silicon oxide layer 310 and extends to part of the substrate 100, and the deep trench 600 is located in the center region 100A and the edge region 100B of the substrate 100; since the nitridation layer 200 and the second silicon oxide layer 320 are formed between the substrate 100 and the nitridation layer 200, the deep trench 600 also penetrates the nitridation layer 200 and the second silicon oxide layer 320, and the deep trench 600 penetrates part of the substrate 100, specifically, penetrates the device layer 160, the buried oxygen insulating layer 140 and part of the doped substrate layer 120 (part of the doped region 120a). The ion implantation layer 500 protects the edge of the substrate 100 when the deep trench 600 is formed, and the silicon material (the device layer 160 and the doped substrate layer 120) in the substrate 100 is etched when the deep trench 600 is manufactured, and the silicon etching is easy to cause etching damage to the edge of the substrate 100, and the ion implantation layer 500 is used to reduce the etching rate of the edge, so that the ion implantation layer 500 resists the damage to the edge of the substrate 100 caused by the etching process.
[0059] Please refer to Figure 12 , execute step S5: fill a conductive layer 700 in the deep trench 600, and the conductive layer 700 covers the first silicon oxide layer 310 and the ion implantation layer 500, and the material of the conductive layer 700 is preferably doped polysilicon; at least a dielectric layer (not shown in the figure) is formed between the conductive layer 700 and the inner wall (side wall and bottom wall) of the deep trench 600, and the material of the dielectric layer is preferably a high-K dielectric material.
[0060] Referring to Figure 12 and Figure 13 , step S6 is performed: chemical mechanical polishing the conductive layer 700 and the first silicon oxide layer 310, the polishing stops in the first silicon oxide layer 310, and the ion implantation layer 500 in the first silicon oxide layer 310 is removed; specifically, the conductive layer 700 on the first silicon oxide layer 310 is removed first, then part of the first silicon oxide layer 310, the ion implantation layer 500, and part of the conductive layer 700 in the deep trench 600 are removed, so as to remove the ion implantation layer 500, part of the thickness of the first silicon oxide layer 310, and part of the conductive layer 700 in the deep trench 600, and the polishing stops in the first silicon oxide layer 310. When the chemical mechanical polishing is performed, because the additional silicon nitride film and the silicon oxide film are not formed on the edge of the substrate 100, the film layer structure on the edge and the middle of the substrate 100 is consistent, the ion implantation layer 500 is obtained by modifying the first silicon oxide layer 310 exposed on the edge of the substrate 100, the surfaces of the first silicon oxide layer 310 and the ion implantation layer 500 are flush, after the conductive layer 700 on the first silicon oxide layer 310 is removed, the ion implantation layer 500, part of the thickness of the first silicon oxide layer 310, and part of the conductive layer 700 in the deep trench 600 are removed synchronously, the chemical mechanical polishing is more controllable, the uniformity of the chemical mechanical polishing is better, and the polishing rate is faster, the risk of polishing defects and debris during the chemical mechanical polishing is reduced, and thus the stability of the chemical mechanical polishing is improved.
[0061] In summary, in the method for manufacturing a deep trench in the DRAM provided by the application, the method comprises the following steps: providing a substrate, at least a first silicon oxide layer is formed on the substrate; applying a photoresist layer on the surface of the first silicon oxide layer, and removing the photoresist layer on the edge of the substrate by using the EBR process of photolithography; performing ion implantation on the first silicon oxide layer exposed on the edge of the substrate to form an ion implantation layer with a preset depth and a preset concentration, and removing the photoresist layer after the ion implantation; forming a deep trench by photolithography and etching, the deep trench penetrates through the first silicon oxide layer and extends to part of the substrate; filling a conductive layer in the deep trench, and the conductive layer covers the first silicon oxide layer; and chemically and mechanically polishing the conductive layer and the first silicon oxide layer and stopping in the first silicon oxide layer, and the ion implantation layer in the first silicon oxide layer is removed by polishing. In the application, the first silicon oxide layer exposed on the edge of the substrate is ion implanted with a preset depth and a preset concentration, so that the first silicon oxide layer exposed on the edge of the substrate is modified to form an ion implantation layer. The ion implantation layer can improve the ability of the edge of the substrate to resist silicon etching, and plays a role in protecting the edge of the substrate during the preparation of the deep trench etching process. The manufacturing method provided by the application forms a substrate edge protection structure by ion implantation on the first silicon oxide layer on the edge of the substrate. The manufacturing method provided by the application does not need to manufacture an additional substrate edge protection film layer when etching the deep trench, simplifying the process flow of the deep trench capacitor manufacturing process. At the same time, in this manufacturing method, the film layer structure of the edge of the substrate and the middle is consistent, reducing the risk of polishing defects and fragments during subsequent chemical mechanical polishing. According to the change of the aspect ratio value of the manufactured deep trench, the concentration and depth of ion implantation can be adjusted to form a corresponding substrate edge protection structure.
[0062] The above is only the preferred embodiment of the application, and does not limit the application in any way. Any person skilled in the art can make any form of equivalent replacement, modification or change to the technical solutions and technical content disclosed by the application without departing from the scope of the technical solutions of the application, and such changes still belong to the protection scope of the application.
Claims
1. A method for fabricating deep trenches in DRAM, characterized in that, include: A substrate is provided, on which at least a first silicon oxide layer is formed; A photoresist layer is coated on the surface of the first silicon oxide layer, and the photoresist layer at the edge of the substrate is removed using a photolithographic EBR process; An ion implantation layer is formed by ion implantation at a preset depth and concentration on the first silicon oxide layer exposed at the edge of the substrate, and the photoresist layer is removed after ion implantation. Photolithography and etching form deep trenches that penetrate the first silicon oxide layer and extend to a portion of the substrate; A conductive layer is filled in the deep trench, and the conductive layer covers the first silicon oxide layer; The conductive layer and the first silicon oxide layer are chemically and mechanically ground, stopping at the first silicon oxide layer, and the ion implantation layer in the first silicon oxide layer is removed during the grinding process.
2. The method for fabricating deep trenches in DRAM as described in claim 1, characterized in that, The width of the ion implantation layer is the same as the width of the edge of the substrate.
3. The method for fabricating deep trenches in DRAM as described in claim 2, characterized in that, The width of the substrate edge is greater than 0 mm and less than or equal to 3 mm.
4. The method for fabricating deep trenches in DRAM as described in claim 1, characterized in that, The preset depth of the ion implantation layer is less than the thickness of the first silicon oxide layer.
5. The method for fabricating a deep trench in DRAM as described in claim 4, characterized in that, The preset depth of the ion implantation layer is 50nm to 100nm.
6. The method for fabricating a deep trench in DRAM as described in claim 1, characterized in that, The doped ions in the ion implantation layer include nitrogen ions or carbon ions.
7. The method for fabricating a deep trench in DRAM as described in claim 6, characterized in that, The preset concentration of the ion implantation layer is 1×10⁻⁶. 12 ions / cm 2 ~1×10 16 ions / cm 2 .
8. The method for fabricating a deep trench in DRAM as described in claim 1, characterized in that, During chemical mechanical polishing, the conductive layer on the first silicon oxide layer is first removed by polishing, and then a portion of the first silicon oxide layer, the ion implantation layer, and a portion of the conductive layer in the deep trench are removed by polishing.