Flash memory and forming method thereof

Abstract

The invention provides a flash memory and a forming method thereof. A floating gate, a spacer layer and a control gate which are stacked are respectively formed above a substrate on two sides of a word line; the upper surface of the floating gate is arc-shaped on the cross section vertical to the substrate; no side wall is arranged right above the control gate, the control gate can be directly led out when contact holes are manufactured in the flash memory in a unified mode, the contact holes are formed in the one-time etching process through the same photomask, and the contact holes comprise the word line contact hole, the control gate contact hole and the source-drain contact hole. A conventional contact hole (such as a source drain contact hole and a word line contact hole) and a control gate contact hole can be completed only by one photomask and one photoetching process, the process is simple, and the cost is reduced. Meanwhile, the coupling area of the arc-shaped surface of the floating gate and the control gate is enlarged, so that the coupling rate from the control gate to the floating gate is improved, and the coupling efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of integrated circuit manufacturing, and particularly relates to a flash memory and a forming method thereof. BACKGROUND

[0002] Nord flash memory devices have occupied an increasingly important position in the field of non-volatile memories due to their low cost, low power consumption, and fast access speed. With the development of technology, data storage media applications have shifted from some traditional non-volatile memories to flash memory type memories. Large-capacity solid-state storage devices with flash memory as the main storage medium have become one of the mainstream solutions for data storage today.

[0003] As shown in Figure 1 The Nord flash memory device includes a floating gate 01 and a control gate 02 stacked together on both sides of a word line 04, and a composite dielectric layer is formed between the floating gate 01 and the control gate 02. By applying different operating voltages to the control gate 02 of the Nord flash memory device, the control of the read operation, the write operation, and the erase operation of the Nord flash memory device is realized. The side wall 03 is directly above the control gate 02, and the topography of the control gate 02 is defined by the side wall 03. Since the side wall 03 blocks the control gate 02, the control gate 02 cannot be directly led out when the contact hole of the Nord flash memory device is uniformly manufactured. A special photomask is needed to define the control gate contact hole, and the control gate 02 can be led out. In this way, the conventional contact hole (such as the source / drain contact hole and the word line contact hole) and the control gate contact hole need two photomasks and two photoetching processes to complete, which is complex and high in cost. SUMMARY

[0004] The purpose of the present application is to provide a flash memory and a forming method thereof, which can complete the conventional contact hole (such as the source / drain contact hole and the word line contact hole) and the control gate contact hole with only one photomask and one photoetching process, thus simplifying the process and reducing the cost. At the same time, the surface of the floating gate arc shape has a larger coupling area with the control gate, which improves the coupling rate of the control gate to the floating gate layer and enhances the coupling efficiency.

[0005] The present application provides a forming method of a flash memory, comprising:

[0006] Step S1, providing a substrate, a gate oxide layer, a floating gate layer, and a mask layer are sequentially formed on the substrate; an opening is formed in the mask layer, and the upper surface of the floating gate layer exposed by the opening is in an arc shape;

[0007] Step S2, a spacer layer, a control gate, and an offset layer are sequentially formed on the sidewalls on both sides of the mask layer opening;

[0008] Step S3, etching to remove the floating gate layer and the gate oxide layer between the offset layers on both sides to expose the substrate; etching the remaining floating gate layer as a floating gate transition layer;

[0009] Step S4, forming a tunneling oxide layer and a word line, the tunneling oxide layer covering at least the sidewall surfaces of the offset layer and the floating gate transition layer and the exposed substrate surface; the word line filling the cavity area in the tunneling oxide layer;

[0010] Step S5, removing the mask layer, etching to remove the part of the floating gate transition layer directly below the mask layer, and etching the remaining floating gate transition layer as a floating gate;

[0011] Step S6, forming an interlayer dielectric layer covering at least the substrate, the control gate and the word line; using the same mask in one etching process, a contact hole is formed by etching the interlayer dielectric layer, including a word line contact hole, a control gate contact hole and a source / drain contact hole.

[0012] Further, in step S1, the arc-shaped upper surface of the floating gate layer is formed by isotropic wet etching, and the etching solution includes a mixed solution of nitric acid and hydrofluoric acid.

[0013] Further, step S2 specifically includes:

[0014] Step S21, forming a spacer layer covering the surface of the mask layer and the arc-shaped surface of the floating gate layer;

[0015] Step S22, forming a control gate layer covering the spacer layer;

[0016] Step S23, using dry etching to remove the control gate layer and the spacer layer that are higher than the upper surface of the mask layer, and etching to remove the control gate layer and the spacer layer at the bottom of the groove to expose the floating gate layer, and retaining the spacer layer and the control gate layer on the sidewall of the mask layer opening, and the retained control gate layer serving as the control gate;

[0017] Step S24, forming the offset layer on the sidewall of the control gate on both sides.

[0018] Further, step S3 specifically includes forming an HTO layer on the sidewall of the offset layer on both sides;

[0019] Etching to remove the floating gate layer and the gate oxide layer between the HTO layers on both sides to expose the substrate; during this etching process, the HTO layers on both sides are also etched and consumed.

[0020] Further, the material of the offset layer comprises one or more than two combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbon nitride and silicon carbon oxynitride.

[0021] Further, after the floating gate is formed in step S5, the method further comprises:

[0022] forming an insulation layer on both sides of the word line, the insulation layer covering the sidewalls of the control gate, the spacer layer and the floating gate and part of the substrate; the insulation layer is in the shape of "L";

[0023] forming a side wall on both sides of the word line, the side wall being located at the L-shaped corner of the insulation layer.

[0024] The application further provides a flash memory comprising:

[0025] a substrate, the substrate being provided with a word line, the substrate on both sides of the word line being provided with a stacked floating gate, a spacer layer and a control gate respectively; in the cross section perpendicular to the substrate, the upper surface of the floating gate is in the shape of arc;

[0026] the control gate being provided with an offset layer on the side surface close to the word line;

[0027] a tunneling oxide layer, the tunneling oxide layer being located between the word line and the substrate, between the word line and the floating gate on both sides and between the word line and the offset layer on both sides;

[0028] an interlayer dielectric layer, the interlayer dielectric layer covering at least the substrate, the control gate and the word line;

[0029] a contact hole in the interlayer dielectric layer, the contact hole comprising a word line contact hole, a control gate contact hole, a source contact hole and a drain contact hole; the contact hole is formed in one etching process by using the same mask.

[0030] Further, the flash memory further comprises an insulation layer and a side wall on both sides of the word line, the insulation layer covering the sidewalls of the control gate, the spacer layer and the floating gate and part of the substrate; the insulation layer is in the shape of "L"; the side wall is located at the L-shaped corner of the insulation layer.

[0031] Further, the material of the floating gate, the control gate and the word line all comprises polycrystalline silicon.

[0032] Further, the upper surface height of the floating gate gradually increases from the side close to the word line to the side far away from the word line.

[0033] Compared with the prior art, the application has the following beneficial effects:

[0034] The application provides a flash memory and a forming method thereof, which comprises the following steps: S1, providing a substrate, a gate oxide layer, a floating gate layer and a mask layer are formed on the substrate, an opening is formed in the mask layer, and an upper surface of the floating gate layer exposed by the opening is in an arc shape; S2, a spacer layer, a control gate and an offset layer are sequentially formed on sidewalls of the mask layer on both sides of the opening; S3, the floating gate layer and the gate oxide layer between the offset layers on both sides are etched to expose the substrate; the remaining floating gate layer is etched as a floating gate transition layer; S4, a tunneling oxide layer and a word line are formed, the tunneling oxide layer covers at least the sidewall surfaces of the offset layer and the floating gate transition layer and the exposed substrate surface; the word line fills a cavity region in the tunneling oxide layer; S5, the mask layer is removed, and the floating gate transition layer located directly below the mask layer is etched to form a floating gate; S6, an interlayer dielectric layer is formed, the interlayer dielectric layer covers at least the substrate, the control gate and the word line; a contact hole is formed by etching the interlayer dielectric layer, and the contact hole comprises a word line contact hole, a control gate contact hole and a source / drain contact hole.

[0035] The application does not have a sidewall directly above the control gate, and the control gate can be directly led out when contact holes are formed in the flash memory, so that the contact holes are formed by using the same mask in one etching process, and the conventional contact holes (for example, the source / drain contact hole, the word line contact hole and the control gate contact hole) can be completed by using one mask and one photoetching process, so that the process is simple and the cost is reduced. Meanwhile, the coupling area of the floating gate with the arc-shaped surface and the control gate is increased, so that the coupling rate of the control gate to the floating gate layer is improved, and the coupling efficiency is improved. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1 It is a structural schematic diagram of a flash memory.

[0037] Figure 2 It is a flowchart of a forming method of a flash memory according to an embodiment of the application.

[0038] Figure 3 It is a schematic diagram of a flash memory after a mask layer is formed in the forming method of the flash memory according to the embodiment of the application.

[0039] Figure 4 It is a schematic diagram of a flash memory after the floating gate layer is isotropically etched in the forming method of the flash memory according to the embodiment of the application.

[0040] Figure 5 It is a schematic diagram of a flash memory after a control gate layer is formed in the forming method of the flash memory according to the embodiment of the application.

[0041] Figure 6 It is a schematic diagram of a flash memory after a control gate is formed in the forming method of the flash memory according to the embodiment of the application.

[0042] Figure 7 It is a schematic diagram of a flash memory after an offset layer is formed in the forming method of the flash memory according to the embodiment of the application.

[0043] Figure 8 A schematic view of the formation of an HTO layer in the formation method of the flash memory of the embodiment of the present application.

[0044] Figure 9 A schematic view of the formation of a floating gate transition layer in the formation method of the flash memory of the embodiment of the present application.

[0045] Figure 10 A schematic view of the formation of a word line in the formation method of the flash memory of the embodiment of the present application.

[0046] Figure 11 A schematic view of the formation of a contact hole in the formation method of the flash memory of the embodiment of the present application.

[0047] Figure 12 A top view of the flash memory in the formation method of the flash memory of the embodiment of the present application.

[0048] In the drawings, the reference signs are as follows:

[0049] 01-floating gate; 02-control gate; 03-side wall; 04-word line;

[0050] 10-substrate; 11-gate oxide layer; 12-floating gate layer; 120-floating gate transition layer; 121-floating gate; Y-mask layer; 13-separation layer; 14-control gate layer; 140-control gate; 15-offset layer; 16-HTO layer; 17-tunneling oxide layer; 18-word line; 19-insulating layer; 20-side wall; S-source region; D-drain region; 21-word line contact hole; 22-control gate contact hole; 23-source contact hole; 24-drain contact hole. DETAILED DESCRIPTION

[0051] The present application will be further described below in conjunction with the drawings and specific embodiments. The advantages and features of the present application will be more apparent according to the following description. It should be noted that the drawings are very simplified and use non-precise proportions, only to facilitate and clarify the purpose of assisting the description of the embodiments of the present application.

[0052] For ease of description, some embodiments of the present application can use spatial relative terms such as "above", "below", "top", "bottom", etc. to describe the relationship between one element or component and another (or other) element or component as shown in the drawings of the embodiments. It should be understood that, in addition to the orientation described in the drawings, the spatial relative terms are also intended to include different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the element or component described as "below" or "under" the other element or component will then be positioned "above" or "over" the other element or component. The terms "first", "second", etc. are used below to distinguish between similar elements, and are not necessarily used to describe a particular order or time sequence. It is understood that these terms as used can be replaced under appropriate circumstances.

[0053] The embodiment of the present application provides a flash memory forming method, as shown in the drawings, comprising: Figure 2

[0054] Step S1, providing a substrate, a gate oxide layer, a floating gate layer and a mask layer are sequentially formed on the substrate; an opening is formed in the mask layer, and an upper surface of the floating gate layer exposed by the opening is in an arc shape;

[0055] Step S2, a spacer layer, a control gate and an offset layer are sequentially formed on the sidewalls of the mask layer opening on both sides;

[0056] Step S3, the floating gate layer and the gate oxide layer between the offset layers on both sides are etched to expose the substrate; and the remaining floating gate layer is etched as a floating gate transition layer;

[0057] Step S4, a tunneling oxide layer and a word line are formed, the tunneling oxide layer covers at least the sidewall surfaces of the offset layer and the floating gate transition layer and the exposed substrate surface; and the word line fills a cavity region in the tunneling oxide layer;

[0058] Step S5, the mask layer is removed, and the part of the floating gate transition layer located directly below the mask layer is etched to remove, and the remaining floating gate transition layer is etched as a floating gate;

[0059] Step S6, an interlayer dielectric layer is formed, the interlayer dielectric layer covers at least the substrate, the control gate and the word line; a contact hole is formed by etching the interlayer dielectric layer by using the same mask in one etching process, and the contact hole comprises a word line contact hole, a control gate contact hole and a source / drain contact hole.

[0060] The steps of the flash memory forming method of the embodiment of the present application will be described in detail below with reference to the drawings.

[0061] As shown in the drawings, Figure 3 ​As shown, in step S1, a substrate 10 is provided, on which a gate oxide layer 11, a floating gate layer 12, and a mask layer Y are sequentially formed. An opening is formed in the mask layer Y, exposing a portion of the floating gate layer 12. In this embodiment, the substrate 10 may be made of silicon. In other embodiments, the substrate 10 may be made of silicon carbide, silicon-germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator, or germanium-on-insulator. The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP. The gate oxide layer 11 is made of silicon oxide; the floating gate layer 12 is made of polycrystalline silicon. The process for forming the floating gate layer 12 may be a deposition process, such as plasma chemical vapor deposition, low-pressure chemical vapor deposition, or sub-atmospheric pressure chemical vapor deposition. The mask layer material includes one or more combinations of silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride. In this embodiment, the mask layer material includes, for example, silicon nitride. The mask layer can be formed using chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD), etc.

[0062] like Figure 4 As shown, using mask layer Y as a mask, isotropic etching is performed on the floating gate layer 12, causing the exposed upper surface of the floating gate layer to have an arc shape. The material of the floating gate layer 12 is, for example, polycrystalline silicon. Specifically, isotropic wet etching is performed on the floating gate layer 12. The isotropic wet etching of the floating gate layer 12 can be based on a mixed solution of nitric acid (HNO3) and hydrofluoric acid (HF), and the etching rate and surface morphology can be controlled by adjusting the ratio and diluent (such as acetic acid or water). HNO3 oxidizes the polycrystalline silicon surface to generate silicon dioxide (SiO2). HF dissolves the generated SiO2, exposing a new silicon surface for further reaction. The diluent adjusts the reaction rate and etching uniformity.

[0063] like Figure 5 As shown, in step S21, a spacer layer 13 is formed, which covers the surface of the mask layer Y and the surface of the arc-shaped floating gate layer 12. The spacer layer 13 is, for example, a stacked first oxide layer, a silicon nitride layer, and a second oxide layer (abbreviated as ONO).

[0064] Step S22: Form a control gate layer 14, which covers spacer layers 13. Specifically, the control gate layer 14 covers spacer layers 13 located above and to the side of the mask layer Y. The control gate layer 14 also covers spacer layers 13 located on the surface of the arc-shaped floating gate layer 12. The control gate layer 14 within the opening region forms a hollow groove. The process for forming the control gate layer 14 can be a deposition process, such as plasma chemical vapor deposition, low-pressure chemical vapor deposition, or sub-atmospheric pressure chemical vapor deposition. The material of the control gate layer 14 includes polycrystalline silicon.

[0065] As shown in Figure 6 S23, the control gate layer 14 and the spacer layer 13 are etched, specifically, the control gate layer 14 and the spacer layer 13 above the upper surface of the mask layer are removed by dry etching, and the control gate layer 14 and the spacer layer 13 at the bottom of the groove are etched to expose the floating gate layer 12, and the spacer layer 13 and the control gate layer 14 on the sidewall of the opening of the mask layer are reserved, and the reserved control gate layer is the control gate 140. The spacer layer 13 is used to electrically isolate the floating gate layer 12 and the control gate 140.

[0066] As shown in Figure 7 and Figure 11 S24, the offset layer 15 is formed, which covers the sidewall of the control gate 140. The material of the offset layer 15 includes one or a combination of two or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbon nitride, and silicon carbon oxynitride. The offset layer 15 is used to make the subsequently formed floating gate 121 laterally exceed the control gate 140, that is, the floating gate 121 is closer to the word line 18 than the control gate 140.

[0067] As shown in Figure 8 The HTO (high temperature thermal oxidation) layer 16 is formed, which covers the sidewall of the offset layer 15. The HTO layer 16 can be prepared by low pressure chemical vapor deposition (LPCVD) or atmospheric pressure chemical vapor deposition (APCVD), and the reaction temperature is usually 700-900°C. The precursor gas is a silicon source and an oxygen source. The HTO layer 16 has high density and good dielectric properties. The SiO2 film formed at high temperature has high density. The HTO layer 16 is used to protect the offset layer 15 and the control gate 140 in the subsequent etching process of the floating gate layer 12 and the gate oxide layer 11.

[0068] As shown in Figure 8 and Figure 9 The floating gate layer 12 and the gate oxide layer 11 between the HTO layers 16 on both sides are etched to expose the substrate 10; the HTO layers 16 on both sides are also etched and consumed in this etching process; the remaining floating gate layer is the floating gate transition layer 120.

[0069] As shown in Figure 10 The tunneling oxide layer 17 is formed, which covers the upper surfaces of the mask layer Y, the spacer layer 13, the control gate 140, and the offset layer 15, and covers the sidewall surfaces of the offset layer 15 and the floating gate transition layer 120, and covers the surface of the exposed substrate 10.

[0070] The word line 18 is formed to cover the upper surface of the tunneling oxide layer 17 and fill the concave region in the tunneling oxide layer 17. The process of forming the word line 18 can be a deposition process, such as a plasma chemical vapor deposition process, a low pressure chemical vapor deposition process or a sub-atmospheric pressure chemical vapor deposition process. The material of the word line 18 includes polysilicon.

[0071] As shown in FIG. 6, the contact holes are formed in one etching process by using the same mask. The contact holes include the word line contact hole 21, the control gate contact hole 22, the source contact hole 23 and the drain contact hole 24. Figure 10 Figure 11 As shown in FIG. 6, the contact holes are formed in one etching process by using the same mask. The contact holes include the word line contact hole 21, the control gate contact hole 22, the source contact hole 23 and the drain contact hole 24.

[0072] Specifically, the portions of the word line 18 and the tunneling oxide layer 17 above the upper surface of the control gate 140 are removed. For example, the flash memory can be polished by using a chemical mechanical polishing process to remove the portions of the word line 18 and the tunneling oxide layer 17 above the upper surface of the control gate 140.

[0073] The mask layer Y is removed. The floating gate transition layer 120 located directly below the mask layer Y is etched to remove, and the remaining floating gate transition layer is left as the floating gate 121.

[0074] The insulating layer 19 located on both sides of the word line is formed to cover the sidewalls of the control gate 140, the spacer layer 13 and the floating gate 121 and part of the substrate 10. The insulating layer 19 is in the shape of "L".

[0075] The sidewall 20 located on both sides of the word line 18 is formed at the L-shaped corner of the insulating layer 19.

[0076] The interlayer dielectric layer (not shown) is formed to cover the substrate 10, the sidewall 20, the insulating layer 19, the control gate 140, the offset layer 15, the tunneling oxide layer 17 and the word line 18.

[0077] The contact holes are formed in one etching process by using the same mask. Specifically, the interlayer dielectric layer is etched to form the contact holes. The contact holes include the word line contact hole 21, the control gate contact hole 22, the source contact hole 23 and the drain contact hole 24. The source contact hole 23 is led out from the source region S in the substrate, and the drain contact hole 24 is led out from the drain region D in the substrate 10.

[0078] In the flash memory and the forming method thereof, there is no sidewall above the control gate 140, and the profile of the control gate 140 is no longer defined by the sidewall. The sidewall no longer shields the control gate 140, so that the control gate can be directly led out when the contact holes of the flash memory device are uniformly formed. The contact holes are formed in one etching process by using the same mask. In this way, the conventional contact holes (for example, the source contact hole, the word line contact hole) and the control gate contact hole 22 can be completed by using only one mask and one photolithography process, which is simple and reduces the cost.​

[0079] Meanwhile, the coupling between the floating gate 121 and the control gate 140 is a key mechanism in non-volatile memory such as NAND, NOR Flash, etc., and directly affects the programming, erasing and reading operations of the device. The coupling rate between the floating gate 121 and the control gate 140, which is related to the area overlap between the control gate 140 and the floating gate 121, affects the read / write speed of the flash memory. Moreover, the better (higher) the coupling rate is, the more the working voltage required by the storage unit can be reduced. The present application performs isotropic etching on the floating gate layer, so that the upper surface of the floating gate layer exposed by the opening is in an arc shape (for example, a circular arc shape). The coupling area between the arc-shaped surface of the floating gate layer and the control gate is larger, so that the coupling rate of the control gate to the floating gate layer is improved, and the coupling efficiency is improved.

[0080] Figure 11 A schematic view of the flash memory after forming the contact hole in the forming method of the flash memory of the embodiment of the present application. Figure 12 A top view of the flash memory in the forming method of the flash memory of the embodiment of the present application. Figure 11 A cross-sectional view at Aa in the forming method of the flash memory of the embodiment of the present application. Figure 12 A cross-sectional view at Aa in the forming method of the flash memory of the embodiment of the present application.

[0081] The present application also provides a flash memory, such as Figure 11 and Figure 12 The flash memory comprises:

[0082] a substrate 10, a word line 18 is formed on the substrate 10, a floating gate 121, a spacer layer 13 and a control gate 140 are formed on the substrate 10 on both sides of the word line 18; in a cross section perpendicular to the substrate 10, the upper surface of the floating gate 121 is in an arc shape;

[0083] an offset layer 15 is formed on the side surface of the control gate 140 close to the word line 18;

[0084] a tunneling oxide layer 17 is located between the word line 18 and the substrate 10, between the word line 18 and the floating gate 121 on both sides, and between the word line 18 and the offset layer 15 on both sides;

[0085] an interlayer dielectric layer (not shown) covers the substrate 10, the sidewall 20, the insulating layer 19, the control gate 140, the offset layer 15, the tunneling oxide layer 17 and the word line 18;

[0086] a contact hole in the interlayer dielectric layer, the contact hole comprises: a word line contact hole 21, a control gate contact hole 22, a source contact hole 23 and a drain contact hole 24; the contact hole is formed in one etching process by using the same mask.

[0087] The flash memory includes a plurality of parallel floating gate pattern areas F corresponding to the floating gate 121 and the control gate 140 formed on both sides of the word line 18 and in the middle of the word line 18.

[0088] In summary, the present application provides a flash memory and a forming method thereof, which comprises the following steps: S1, providing a substrate, forming a gate oxide layer, a floating gate layer and a mask layer on the substrate, and forming an opening in the mask layer, wherein the upper surface of the floating gate layer exposed by the opening is in an arc shape; S2, sequentially forming a spacer layer, a control gate and an offset layer on the sidewalls of the mask layer on both sides of the opening; S3, etching and removing the floating gate layer and the gate oxide layer between the offset layers on both sides to expose the substrate, etching the remaining floating gate layer as a floating gate transition layer; S4, forming a tunneling oxide layer and a word line, wherein the tunneling oxide layer covers at least the sidewall surfaces of the offset layer and the floating gate transition layer and the exposed substrate surface, and the word line fills the cavity area in the tunneling oxide layer; S5, removing the mask layer, etching and removing the part of the floating gate transition layer directly below the mask layer, and etching the remaining floating gate transition layer as a floating gate; S6, forming an interlayer dielectric layer, wherein the interlayer dielectric layer covers at least the substrate, the control gate and the word line, and forming a contact hole by etching the interlayer dielectric layer, wherein the contact hole comprises a word line contact hole, a control gate contact hole and a source / drain contact hole.

[0089] In the present application, there is no sidewall directly above the control gate, and the control gate can be directly led out when the contact hole is formed in the flash memory, and the contact hole is formed in one etching process by using the same mask, so that the conventional contact hole (for example, the source / drain contact hole, the word line contact hole and the control gate contact hole) can be completed by using only one mask and one photoetching process, thereby simplifying the process and reducing the cost. Meanwhile, the coupling area between the arc-shaped surface of the floating gate and the control gate is increased, so that the coupling rate of the control gate to the floating gate layer is improved, and the coupling efficiency is improved.

[0090] The embodiments in the present application are described in a progressive manner, and each embodiment focuses on the difference from other embodiments, and the same or similar parts between the embodiments can be referred to each other. For the method disclosed by the embodiments, the description is relatively simple because it corresponds to the device disclosed by the embodiments, and the relevant parts can be referred to the description of the method.

[0091] The above description is only a description of the preferred embodiments of the present application, and is not any limitation on the scope of the present application. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present application without departing from the spirit and scope of the present application by using the disclosed methods and technical contents. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, without departing from the technical solutions of the present application, shall fall within the protection scope of the technical solutions of the present application.

Claims

1. A method for forming flash memory, characterized in that, include: Step S1: Provide a substrate, on which a gate oxide layer, a floating gate layer and a mask layer are sequentially formed; an opening is formed in the mask layer, and the upper surface of the floating gate layer exposed by the opening is arc-shaped; Step S2: A spacer layer, a control grid, and an offset layer are sequentially formed on the sidewalls on both sides of the opening of the mask layer; Step S3: Etch away the floating gate layer and the gate oxide layer between the offset layers on both sides to expose the substrate; etch the remaining floating gate layer as a floating gate transition layer; Step S4: Form a tunneling oxide layer and word lines, wherein the tunneling oxide layer at least covers the sidewall surfaces of both the offset layer and the floating gate transition layer, as well as the exposed substrate surface; the word lines fill the cavity regions in the tunneling oxide layer; Step S5: Remove the mask layer, etch away the portion of the floating gate transition layer located directly below the mask layer, and etch the remaining floating gate transition layer as a floating gate; Step S6: Form an interlayer dielectric layer, wherein the interlayer dielectric layer at least covers the substrate, the control gate, and the word line; Using the same photomask in a single etching process, contact holes are formed by etching the interlayer dielectric layer. The contact holes include word line contact holes, control gate contact holes, and source / drain contact holes.

2. The method for forming flash memory as described in claim 1, characterized in that, In step S1, the arc-shaped upper surface of the floating gate layer is formed by isotropic wet etching, and the etching solution includes a mixed solution of nitric acid and hydrofluoric acid.

3. The method for forming flash memory as described in claim 1, characterized in that, Step S2 specifically includes: Step S21: Form a spacer layer that covers the surface of the mask layer and the surface of the arc-shaped floating gate layer; Step S22: Form a control gate layer, wherein the control gate layer covers the spacer layer; Step S23: Use dry etching to remove the control gate layer and the spacer layer that are above the upper surface of the mask layer, and etch away the control gate layer and the spacer layer at the bottom of the groove until the floating gate layer is exposed, while retaining the spacer layer and the control gate layer located on the sidewall of the opening of the mask layer, and the retained control gate layer serves as the control gate; Step S24: Form the offset layer on the sidewalls of the control gate on both sides.

4. The method for forming flash memory as described in claim 3, characterized in that, Step S3 specifically includes: forming an HTO layer on the sidewalls of the offset layer on both sides; The etching process removes the floating gate layer and the gate oxide layer between the HTO layers on both sides, exposing the substrate; the HTO layers on both sides are also etched away during this process.

5. The method for forming flash memory as described in claim 1, characterized in that, The offset layer is made of one or more of the following materials: silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide, and silicon carbide.

6. The method for forming flash memory as described in claim 1, characterized in that, In step S5, after forming the floating gate, the process further includes: An insulating layer is formed on both sides of the word line, the insulating layer covering the sidewalls of the control gate, the spacer layer and the floating gate, as well as part of the substrate; the insulating layer is "L" shaped; Side walls are formed on both sides of the letter line, and the side walls are located at the L-shaped corners of the insulating layer.

7. A flash memory, formed using the method of any one of claims 1 to 6, characterized in that, include: A substrate on which word lines are formed, and stacked floating gates, spacer layers and control gates are formed on the substrate on both sides of the word lines, respectively. In a cross-section perpendicular to the substrate, the upper surface of the floating gate is arc-shaped; An offset layer is formed on the surface of the control gate near the word line; A tunneling oxide layer is located between the word line and the substrate, between the word line and the floating gates on both sides, and between the word line and the offset layers on both sides. An interlayer dielectric layer, wherein the interlayer dielectric layer at least covers the substrate, the control gate, and the word line; The contact holes located in the interlayer dielectric layer include: word line contact holes, control gate contact holes, source contact holes, and drain contact holes; The contact holes are formed in a single etching process using the same photomask.

8. The flash memory as claimed in claim 7, characterized in that, The flash memory further includes: an insulating layer and sidewalls located on both sides of the word line, the insulating layer covering the sidewalls of the control gate, the spacer layer and the floating gate, as well as part of the substrate; the insulating layer is "L" shaped; the sidewalls are located at the L-shaped corners of the insulating layer.

9. The flash memory as claimed in claim 7, characterized in that, The floating gate, the control gate, and the word lines are all made of polycrystalline silicon.

10. The flash memory as claimed in claim 7, characterized in that, The height of the upper surface of the floating grid gradually increases from the side closer to the word line to the side farther away from the word line.

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