Semiconductor memory

Abstract

According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip includes a first conductor stacked via an insulator, and a first pillar passing through the first conductor. The circuit chip includes a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode includes a portion extending through the first memory chip from one side of the surface of the first memory chip and connected to the second conductor. A portion of the first conductor is located between the external connection electrode and the substrate.

Description

[0001] Related Application

[0002] This application is a divisional application. The parent application of this divisional application is the patent application for invention with application number 201811092138.3 and application date of September 19, 2018, and with the title of “Semiconductor Memory”.

[0003] Cross Reference to Related Applications

[0004] This application is based on and claims priority to Japanese Patent Application No. 2017-179348, filed September 19, 2017, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0005] Embodiments described herein relate generally to a semiconductor memory. BACKGROUND

[0006] NAND type flash memories having three-dimensionally stacked memory cells are known. SUMMARY

[0007] A semiconductor memory according to an embodiment includes a first memory chip, a circuit chip, and an external connection electrode. The first memory chip includes a plurality of first conductors stacked via insulators, and first pillars passing through the first conductors and forming cross points with the first conductors. Each of the cross points functions as a memory cell. The circuit chip includes a substrate, a control circuit formed on the substrate, and second conductors connected to the control circuit. The circuit chip is attached to the first memory chip. The external connection electrode is provided on a surface of the first memory chip and includes a portion extending through the first memory chip from one side of the surface of the first memory chip and connected to the second conductors. A portion of the first conductors is included between the external connection electrode and the substrate.

[0008] According to the embodiment, the semiconductor memory can reduce a chip area. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a block diagram showing a configuration example of a semiconductor memory according to a first embodiment.

[0010] Figure 2 shows one example of a circuit configuration of a memory cell array in a semiconductor memory according to the first embodiment.

[0011] Figure 3 shows one example of a planar layout of a semiconductor memory according to the first embodiment.

[0012] Figure 4 An example of a planar layout of a semiconductor memory according to the first embodiment is shown.

[0013] Figure 5 An example of a detailed planar layout of a memory cell array and a wiring area in a semiconductor memory according to the first embodiment is shown.

[0014] Figure 6 An example of a cross-sectional configuration of a memory cell array and a wiring area in a semiconductor memory according to the first embodiment is shown.

[0015] Figure 7 An example of a cross-sectional configuration of a memory cell array in a semiconductor memory according to the first embodiment is shown.

[0016] Figure 8 An example of a detailed planar layout of a memory cell array and a wiring area in a semiconductor memory according to the first embodiment is shown.

[0017] Figure 9 An example of a cross-sectional configuration of a memory cell array and a pad area in a semiconductor memory according to the first embodiment is shown.

[0018] Figure 10 An example of a design of a pad provided for a semiconductor memory according to the first embodiment is shown.

[0019] Figure 11 An example of a design of a pad provided for a semiconductor memory according to the first embodiment is shown.

[0020] Figure 12 An example of a production step of a semiconductor memory according to the first embodiment is shown.

[0021] Figure 13 An example of a production step of a semiconductor memory according to the first embodiment is shown.

[0022] Figure 14 An example of a production step of a semiconductor memory according to the first embodiment is shown.

[0023] Figure 15 An example of a production step of a semiconductor memory according to the first embodiment is shown.

[0024] Figure 16 An example of a planar layout of a semiconductor memory of a comparative example according to the first embodiment is shown.

[0025] Figure 17 An example of a cross-sectional configuration of a memory cell array and a pad area in a semiconductor memory of a comparative example according to the first embodiment is shown.

[0026] Figure 18 One example of a cross-sectional configuration of a memory cell array and a pad region in a semiconductor memory according to the second embodiment will be shown.

[0027] Figure 19 One example of a detailed planar layout of a memory cell array and a wiring region in a semiconductor memory according to the third embodiment will be shown.

[0028] Figure 20 One example of a detailed planar layout of a memory cell array in a semiconductor memory according to the third embodiment will be shown.

[0029] Figure 21 One example of a cross-sectional configuration of a memory cell array and a wiring region in a semiconductor memory according to the third embodiment will be shown.

[0030] Figure 22 One example of a cross-sectional configuration of a memory cell array and a pad region in a semiconductor memory according to the third embodiment will be shown.

[0031] Figure 23 One example of a planar layout of a semiconductor memory according to the fourth embodiment will be shown.

[0032] Figure 24 One example of a cross-sectional configuration of a memory cell array and a pad region in a semiconductor memory according to the fourth embodiment will be shown. DETAILED DESCRIPTION

[0033] Hereinafter, embodiments will be described with reference to the accompanying drawings. The drawings are schematic. Each of the embodiments will demonstrate devices and methods for embodying the technical idea of the present application. In the following description, like reference numerals can be used for components having substantially similar functions and configurations. A number can be added after the characters constituting a reference numeral so as to distinguish elements indicated by the reference numerals containing the same characters and having substantially similar configurations. If it is unnecessary to distinguish the elements indicated by the reference numerals containing the same characters, the elements will be indicated by the reference numerals containing only the same characters.

[0034] [1] First Embodiment

[0035] A semiconductor memory according to the first embodiment will be described.

[0036] [1-1] Configuration

[0037] [1-1-1] General Configuration of Semiconductor Memory 1

[0038] Figure 1A configuration example of a semiconductor memory 1 according to a first embodiment is shown. The semiconductor memory 1 is a NAND type flash memory capable of nonvolatile storage of data. For example, the semiconductor memory 1 includes a memory cell array 10, a row decoder 11, a sense amplifier 12, and a sequencer 13, as shown in Figure 1

[0039] The memory cell array 10 includes a plurality of blocks BLK0 to BLKn (n is an integer of 1 or more). A block BLK is a group of nonvolatile memory cells and is handled as a unit for data erasure, for example. The memory cell array 10 includes a plurality of bit lines and word lines, with each memory cell being associated with one bit line and one word line. A detailed configuration of the memory cell array 10 will be described later.

[0040] The row decoder 11 selects one block BLK based on address information ADD received from an external memory controller 2. The row decoder 11 then applies a given voltage to selected word lines and non-selected word lines, respectively, for example.

[0041] The sense amplifier 12 applies a given voltage to each bit line in accordance with write data DAT received from the memory controller 2. The sense amplifier 12 also evaluates data stored in the memory cells based on the voltages of the bit lines and sends the evaluated read data DAT to the memory controller 2.

[0042] The sequencer 13 controls the operation of the entire semiconductor memory 1 based on a command CMD received from the memory controller 2. Communication between the semiconductor memory 1 and the memory controller 2 supports a NAND interface standard, for example. The memory controller 2 sends a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, and a read enable signal REn, for example, and receives a ready / busy signal RBn. The memory controller 2 sends and receives an input / output signal I / O.

[0043] The signal CLE is a signal for notifying the semiconductor memory 1 that the received signal I / O is a command CMD. The signal ALE is a signal for notifying the semiconductor memory 1 that the received signal I / O is address information ADD. The signal WEn is a signal for instructing the semiconductor memory 1 to input the signal I / O. The signal REn is a signal for instructing the semiconductor memory 1 to output the signal I / O. The signal RBn is a signal for notifying the memory controller 2 that the semiconductor memory 1 is in a ready state of accepting an instruction from the memory controller 2 or in a busy state of not accepting an instruction. The signal I / O can be an 8-bit signal, for example, and includes a command CMD, address information ADD, data DAT, and the like.

[0044] ​The semiconductor memory 1 and the memory controller 2 described above can be combined into a single semiconductor device. This semiconductor device can be a memory card (e.g., an SD card), a solid state drive (SSD), or the like. TM

[0045] [1-1-2] Circuit configuration of memory cell array 10

[0046] Figure 2 One example of a circuit configuration of a memory cell array 10 according to a first embodiment is shown. A description of the circuit configuration of the memory cell array 10 according to the first embodiment will be given with a focus on one block BLK.

[0047] A block BLK includes four string units SU0 to SU3, as shown in Figure 2 Each string unit SU includes a plurality of NAND strings NS associated with bit lines BL0 to BLm (m is an integer of 1 or more), respectively. For example, a NAND string NS includes eight memory cell transistors MT0 to MT7 and selection transistors ST1 and ST2.

[0048] A memory cell transistor MT includes a control gate and a charge accumulation layer, and holds data in a nonvolatile manner. The memory cell transistors MT0 to MT7 included in each NAND string NS are connected in series between the source of the selection transistor ST1 and the drain of the selection transistor ST2. The control gates of the memory cell transistors MT0 to MT7 in one block BLK have a common connection with the respective word lines WL0 to WL7. A group of 1-bit data stored by the plurality of memory cell transistors MT (which are connected to the common word line WL) in each string unit SU is referred to as a "page".

[0049] The selection transistors ST1 and ST2 are used to select the string units SU in various operations. The gates of the selection transistors ST1 in each of the string units SU0 to SU3 in one block BLK have a common connection with the selection gate lines SGD0 to SGD3, respectively. The drains of the selection transistors ST1 corresponding to the same column in each block BLK have a common connection with the respective corresponding bit lines BL. The gates of the selection transistors ST2 in one block BLK have a common connection with the selection gate line SGS. The sources of the selection transistors ST2 in each block BLK have a common connection with the source line SL between the plurality of blocks BLK.

[0050] ​The circuit configuration of the memory cell array 10 is not limited to the aforementioned configuration. For example, the number of string units SU included in each block BL and the number of memory cell transistors MT and selection transistors ST1 and ST2 in each NAND string NS can be arbitrarily set. The number of word lines WL and selection gate lines SGD and SGS can be varied based on the number of memory cell transistors MT and selection transistors ST1 and ST2.

[0051] [1-1-3] Structure of semiconductor memory 1

[0052] Figure 3 One example of a planar layout of the semiconductor memory 1 according to the first embodiment is shown, in which the X axis corresponds to the extension direction of the word line WL, the Y axis corresponds to the extension direction of the bit line BL, and the Z axis corresponds to the direction perpendicular to the substrate surface of the semiconductor memory 1. The semiconductor memory 1 includes, for example, a memory chip 1-1 and a circuit chip 1-2, as shown in Figure 3

[0053] The memory chip 1-1 functions as a substantial storage area of the semiconductor memory 1. The circuit chip 1-2 controls communication with the memory controller 2 and functions as a control circuit of the memory chip 1-1. The memory chip 1-1 and the circuit chip 1-2 form circuits using different semiconductor substrates from each other. By arranging the memory chip 1-1 on the circuit chip 1-2 and bonding the memory chip 1-1 and the circuit chip 1-2 together, one semiconductor chip (semiconductor memory 1) is formed.

[0054] For example, the memory chip 1-1 includes memory cell arrays 10A and 10B, wiring areas 14A, 14B, and 14C, and a pad area 15A. For example, the circuit chip 1-2 includes row decoders 11A, 11B, and 11C, sense amplifiers 12A and 12B, peripheral circuits 16A and 16B, and a pad area 15B.

[0055] In the memory chip 1-1, the memory cell arrays 10A and 10B are formed to be capable of performing different operations in parallel. In the memory chip 1-1, the memory cell arrays 10A and 10B are disposed between the wiring areas 14 arranged in the X direction. More specifically, the memory cell array 10A is disposed between the wiring areas 14A and 14B, and the memory cell array 10B is disposed between the wiring areas 14B and 14C.

[0056] ​The wiring area 14 is an area for providing electrical connections between the memory cell array 10 provided in the memory chip 1-1 and the row decoders 11 provided in the circuit chip 1-2. When a configuration to drive the word lines WL from one side is employed, the wiring area 14 is disposed next to the memory cell array 10. When a configuration to drive the word lines WL from both sides is employed, the wiring area 14 is disposed to sandwich the memory cell array 10.

[0057] The pad area 15A is an area for disposing pads for connecting the circuit chip 1-2 and the memory controller 2. The pad area 15A is formed in the X direction adjacent to the memory cell arrays 10A and 10B.

[0058] In the circuit chip 1-2, the row decoders 11A, 11B, and 11C are provided to overlap the respective wiring areas 14A, 14B, and 14C of the memory chip 1-1. For example, the row decoders 11A and 11B are electrically connected to the word lines WL provided in the memory cell array 10A, and the row decoders 11B and 11C are electrically connected to the word lines WL provided in the memory cell array 10B.

[0059] The sense amplifiers 12A and 12B are provided to overlap the respective memory cell arrays 10A and 10B of the memory chip 1-1. For example, the sense amplifier 12A is electrically connected to the bit lines BL provided in the memory cell array 10A, and the sense amplifier 12B is electrically connected to the bit lines BL provided in the memory cell array 10B.

[0060] For example, the peripheral circuit 16 includes a sequencer 13, an input / output circuit that controls communication between the semiconductor memory 1 and the memory controller 2, and the like. For example, the peripheral circuit 16A is disposed between the row decoders 11A and 11B and adjacent to the sense amplifier 12A. The peripheral circuit 16B is disposed between the row decoders 11B and 11C and adjacent to the sense amplifier 12B.

[0061] The pad area 15B is formed adjacent to the peripheral circuits 16A and 16B and overlaps the pad area 15A of the memory chip 1-1. In the pad area 15B, for example, lines or the like drawn from the input / output circuits in the peripheral circuits 16A and 16B are provided. These lines and the like are drawn to the top face of the semiconductor memory 1 through the pads.

[0062] Figure 4 A planar layout of the semiconductor memory 1 is shown when the memory chip 1-1 and the circuit chip 1-2 have been joined to each other. As shown in Figure 4 The semiconductor memory 1 further includes a plurality of pads 17A and 17B arranged in the X direction.

[0063] The pads 17 are disposed on the surface of the memory chip 1-1 and serve as external connection electrodes of the semiconductor memory 1. The pad 17A is connected to the peripheral circuit 16A (not shown) via the pad region 15 of the memory chip 1-1 and the circuit chip 1-2. Similarly, the pad 17B is connected to the peripheral circuit 16B (not shown) via the pad region 15. The pad 17A is disposed to overlap the pad region 15 and the memory cell array 10A, and the pad 17B is disposed to overlap the pad region 15 and the memory cell array 10B. For example, aluminum can be employed as the pads 17.

[0064] The foregoing description has been assumed as an example in which two memory cell arrays 10 are provided. However, the number of memory cell arrays 10 included in the memory chip 1-1 can be arbitrarily set. In the semiconductor memory 1 according to the first embodiment, the layout of the row decoder 11, the sense amplifier 12, the wiring region 14, the pad region 15, and the peripheral circuit 16 can be arbitrarily changed based on the design of the memory cell array 10.

[0065] Figure 5 One example of a more detailed planar layout of the memory cell array 10 and the wiring region 14 in the semiconductor memory 1 according to the first embodiment is shown. A description of the structure of the memory cell array 10 and the wiring region 14 according to the first embodiment will be given with a focus on one string unit SU.

[0066] The semiconductor memory 1 is provided with a plurality of slits SLT extending in the X direction, as shown in Figure 5 The slits SLT are arranged in the Y direction, and one string unit SU is disposed between adjacent slits SLT. In other words, the slits SLT are formed between string units SU positioned next to each other, and provide insulation between adjacent string units SU.

[0067] The string unit SU includes a plurality of semiconductor pillars MH in the region of the memory cell array 10, and a plurality of contact plugs CC in the wiring region 14. One semiconductor pillar MH corresponds to, for example, one NAND string NS. The contact plugs CC are disposed to respectively correspond to, for example, the word lines WL0 to WL7 and the select gate lines SGD and SGS.

[0068] Figure 6 One example of an X-direction cross-sectional structure of the memory cell array 10 and the wiring region 14 in the semiconductor memory 1 according to the first embodiment is shown. Note that each cross-sectional view used in the following description can omit the interlayer insulating film as appropriate for descriptive purposes. In the semiconductor memory 1 according to the first embodiment, the memory chip 1-1 is disposed on top of the circuit chip 1-2, as shown in Figure 6

[0069] ​First, the detailed structure of the memory chip 1-1 will be described. In the memory chip 1-1, conductors 21 to 31 are sequentially disposed from the top, with insulators provided between the respective conductors. The conductors 21 to 31 are each formed in a plate shape extending in the X direction and the Y direction. For example, the conductors 21 to 31 each extend from a region of the memory cell array 10 to the wiring area 14, so that they are arranged in a stairway manner in the wiring area 14. The conductor 21 functions as a source line SL. The conductor 22 functions as a select gate line SGS. The conductors 23 to 30 function as respective word lines WL0 to WL7. The conductor 31 functions as a select gate line SGD.

[0070] A plurality of semiconductor pillars MH passes through the conductors 31 to 22 in a manner such that it extends from a bottom face of the conductor 31 to reach a bottom face of the conductor 21. A conductive contact plug BLC is provided at the bottom face of the respective semiconductor pillar MH. A conductor 32 is provided at the bottom face of the respective contact plug BLC. Each conductor 32 is linearly formed to extend in the Y direction, and functions as a bit line BL. One conductor 32 is electrically connected to one semiconductor pillar MH within each string cell SU.

[0071] Reference will be made to Figure 7 to illustrate one example of a more detailed cross-sectional structure of the memory cell array 10 in the semiconductor memory 1 according to the first embodiment. Figure 7 Corresponding to a cross-section along Figure 6 the Y direction, but from Figure 6 the Z direction in Figure 7 is reversed.

[0072] The structure corresponding to one string cell SU is disposed between adjacent slits SLT, as shown in Figure 7 . The slit SLT extends in the X direction and the Z direction, and provides insulation between the conductors 22 to 31 of one string cell SU and the conductors of an adjacent string cell SU.

[0073] For example, the semiconductor pillar MH includes a bulk insulating film 33, an insulating film 34, a tunnel oxide film 35, and a conductive semiconductor material 36. More specifically, the bulk insulating film 33 is formed on the inner wall of the storage hole forming the semiconductor pillar MH. The insulating film 34 is formed on the inner wall of the bulk insulating film 33. The tunnel oxide film 35 is formed on the inner wall of the insulating film 34. The conductive semiconductor material 36 is formed or (for example) buried inside the tunnel oxide film 35. The semiconductor material 36 can contain different materials.

[0074] In this structure of the semiconductor pillar MH, the insulating film 34 serves as a charge accumulation layer of the memory cell transistor MT, and a channel of the NAND string NS is formed in the semiconductor material 36. Next, the intersection between the semiconductor pillar MH and the conductor 22 serves as the select transistor ST2. The intersections between the semiconductor pillar MH and the conductors 23 to 30 serve as the memory cell transistors MT0 to MT7, respectively. The intersection between the semiconductor pillar MH and the conductor 31 serves as the select transistor ST1.

[0075] Referring back Figure 6 A description will be given of one example of a configuration for connecting the bit lines BL and the word lines WL of the memory chip 1-1 to the sense amplifiers 12 and the row decoders 11 of the circuit chip 1-2.

[0076] Focus will be on one bit line BL. A conductive contact plug 37 is provided at a bottom face of the conductor 32 serving as the bit line BL. A conductor 38 is provided at a bottom face of the contact plug 37. A jumper metal 39 is provided at a bottom face of the conductor 38. For example, copper can be employed as the jumper metal 39.

[0077] In this configuration, one jumper metal 39 is electrically connected to one bit line BL. The same configuration can be employed for the other bit lines BL, which are thus each connected to different groups of the contact plugs 37, the conductors 38, and the jumper metals 39 in regions not shown in the figure.

[0078] In the wiring area 14, a plurality of conductors 40 are provided under the conductor 21 in a number corresponding to the number of, for example, the contact plugs CC. For example, a contact plug CC is provided at a bottom face of the conductor 25 corresponding to the word line WL2, and a conductor 40 corresponding to the word line WL2 is provided at a bottom face of this contact plug CC. In a similar manner, the contact plugs CC corresponding to the respective lines are formed to be electrically connected to the corresponding ones of the stacked conductors 22 to 31, while being insulated from the other conductors.

[0079] Focusing on the conductor 40 corresponding to the word line WL2, a contact plug 41 is provided at a bottom face of the conductor 40. A conductor 42 is provided at a bottom face of the contact plug 41. A jumper metal 43 is provided at a bottom face of the conductor 42. For example, copper can be employed as the jumper metal 43.

[0080] In this configuration, one jumper metal 43 is electrically connected to one word line WL. The same configuration can be employed for the conductors 40 corresponding to the other word lines WL as well as the select gate lines SGS and SGD. They are thus each connected to different groups of the contact plugs 41, the conductors 42, and the jumper metals 43 in regions not shown in the figure.

[0081] Next, the detailed structure of the circuit chip 1-2 will be described. In the circuit chip 1-2, the sense amplifier 12 is disposed under the region of the memory cell array 10, and the row decoder 11 is disposed under the wiring area 14.

[0082] In the region of the sense amplifier 12, for example, a conductor 51 is disposed on the semiconductor substrate 50 via an insulating film. This conductor 51 serves as a gate electrode, and thus, a structure of a metal-oxide-semiconductor field effect transistor (MOSFET) including source / drain regions and the like is formed. The source and drain regions of this transistor are connected to respective conductors 53 via respective contact plugs 52. A tie metal 54 is disposed on one of the conductors 53. For example, copper can be employed as the tie metal 54.

[0083] One tie metal 39 is connected to the tie metal 54. That is, one bit line BL in the memory chip 1-1 is connected to a corresponding transistor in the sense amplifier 12 via the tie metals 39 and 54. The sense amplifier 12 includes a plurality of transistors in a region not shown in the figure, and these transistors are each electrically connected to a different bit line BL via different groups of the conductors 53 and the tie metal 54.

[0084] In the region of the row decoder 11, for example, a conductor 55 is disposed on the semiconductor substrate 50 via an insulating film. This conductor 55 serves as a gate electrode, and thus, a structure of a MOSFET including source / drain regions and the like is formed. The source and drain regions of this transistor are connected to respective conductors 57 via respective contact plugs 56. A tie metal 58 is disposed on one of the conductors 57. For example, copper can be employed as the tie metal 58.

[0085] One tie metal 43 is connected to the tie metal 58. That is, for example, one word line WL in the memory chip 1-1 is connected to a corresponding transistor in the row decoder 11 via the tie metals 43 and 58. The row decoder 11 includes a plurality of transistors in a region not shown in the figure, and these transistors are each electrically connected to a different word line WL or select gate line SGS or SGD via different groups of the conductors 57 and the tie metal 58.

[0086] Figure 8 One example of a more detailed planar layout of the tie metals 39 and 43 described above is shown. As shown in Figure 8 In the region of the memory cell array 10, different tie metals 39 are disposed on the arrayed bit lines BL, respectively, as shown in the figure. In the wiring area 14, the tie metals 43 are disposed with substantially equal spacing in the Y direction, and similarly disposed tie metals 43 are arrayed in the X direction with progressive displacement in the Y direction.

[0087] The junction metals 54 and 58 in the circuit chip 1-2 are similarly disposed so that, when the memory chip 1-1 and the circuit chip 1-2 are joined together, the corresponding junction metals come into contact with each other. Note that the layout of the junction metals 39 and 43 is not limited to this, and other layouts can also be applied.

[0088] Figure 9 One example of the Y-direction cross-sectional structure of the memory cell array 10 and the pad region 15 in the semiconductor memory 1 according to the first embodiment is shown. As shown in Figure 9 The peripheral circuit 16 is disposed near the pad region 15 and under the memory cell array 10.

[0089] In the region of the peripheral circuit 16, a conductor 59 is disposed on the semiconductor substrate 50 via an insulating film, for example. This conductor 59 functions as a gate electrode, and thus, an MOSFET structure including a source / drain region and the like is formed. The source and drain regions of this transistor are connected to respective conductors 61 via respective contact plugs 60.

[0090] In the pad region 15 of the circuit chip 1-2, a conductor 62 is disposed on the semiconductor substrate 50. The conductor 62 is electrically connected to the peripheral circuit 16. More specifically, the conductor 62 is included in an input / output circuit in the peripheral circuit 16. Copper, aluminum, or the like can be employed as the conductor 62, for example. A contact via TV leads from the top face of the conductor 62 to the insulating film INS at the topmost face of the memory chip 1-1. A conductor is formed or (for example) buried inside the contact via TV. To the extent that a conductor can be formed or buried in this way, the contact via TV is designed to be as small as possible. The conductor formed in the contact via TV is insulated from the conductors 21 to 31 in the memory chip 1-1.

[0091] The conductor formed in the contact via TV includes a portion exposed on the memory chip 1-1, and this portion functions as one pad 17. The pad 17 includes a portion overlapping the memory cell array 10 disposed in the memory chip 1-1, as shown in Figure 9 In other words, between the pad 17 and the semiconductor substrate 50, there is, for example, an end of a conductor functioning as a word line WL, and there is also a region of the semiconductor pillar MH. In the following description, the size of the pad 17 in the Y-direction will be referred to as the pad width WP.

[0092] Figure 10 and Figure 11 An example of the design of the pad 17 in the semiconductor memory 1 according to the first embodiment is shown. Specifically, the drawing illustrates an example of the shape of the contact via TV. The contact via TV can be provided linearly, as shown in Figure 10 or can be provided as a dot-like piece, as shown in Figure 11As shown in the diagram. Furthermore, multiple contact conductors TV can connect pad 17 to conductor 62, such as... Figure 11 As shown in the figure. The shape of the contact conductor TV corresponding to a pad 17 is not limited to these shapes, but can be a combination of linear and dot shapes, or other shapes.

[0093] Note that the structure of the semiconductor memory 1 according to the first embodiment is not limited to the structure described above. For example, in the context of the above description, the select gate lines SGS and SGD can each be formed from multiple conductor layers. The number of memory cell transistors MT contained in a NAND string NS can be varied by changing the number of conductors (corresponding to word lines WL) through which a semiconductor pillar MH passes.

[0094] For example, a NAND string NS may have a structure in which multiple semiconductor pillars MH are coupled in the Z direction. Connections between semiconductor pillars MH and conductor 32, and between contact plug CC and conductor 40, may be formed via other contact plugs or different conductors. Connections between connector metal 39 and conductor 32, connector metal 43 and conductor 40, connector metal 54 and conductor 53, and connector metal 58 and conductor 57 may be formed via other contact plugs or different conductors.

[0095] [1-2] Generation Method

[0096] In the following text, reference will be made to Figures 12 to 15 The steps described are as follows: forming each of the memory chip 1-1 and the circuit chip 1-2 up to forming the pad 17 in the semiconductor memory 1 according to the first embodiment.

[0097] Figure 12 The diagram shows the state in which memory chip 1-1 and circuit chip 1-2 are formed on different wafers before they are bonded together. Specifically, memory chip 1-1 is formed on semiconductor substrate 20, and circuit chip 1-2 is formed on semiconductor substrate 50. In the figure, memory chip 1-1 is rotated to face circuit chip 1-2, with memory cell array 10 positioned below semiconductor substrate 20.

[0098] Figure 12 The insulating film INS at the bottom layer and the insulating film INS at the top layer of the memory chip 1-1 formed on the semiconductor substrate 20 are also shown. The insulating film INS at the top layer of the circuit chip 1-2 formed on the semiconductor substrate 50 is also shown.

[0099] Memory chip 1-1 and circuit chip 1-2 are attached to each other, such as Figure 13As shown in the diagram. Specifically, semiconductor substrates 20 and 50 are arranged facing each other to clamp various circuits formed thereon, and mechanical pressure is applied to the circuits to achieve inter-wafer bonding. At this time, corresponding connector metals are bonded together in areas not shown.

[0100] More specifically, corresponding connector metals 39 and 54 are bonded together, and corresponding connector metals 43 and 58 are bonded together. After bonding the memory chip 1-1 and the circuit chip 1-2, the semiconductor substrate 20 of the memory chip 1-1 is removed. After removing the semiconductor substrate 20, the insulating film INS remains on the surface and acts as a passivation film to protect the surface of the memory chip 1-1.

[0101] Next, as Figure 14 As shown, a contact conductor TV is formed from one side of the memory chip 1-1 (from which the semiconductor substrate 20 has been removed) all the way to the conductor 62. Metal is formed or (for example) embedded in the formed contact conductor TV. The deposited metal on the memory chip 1-1 is processed to form the desired shape, such as... Figure 15 As shown in the image. In this way, a pad 17 with the desired shape is formed.

[0102] [1-3] Effects of the first embodiment

[0103] The semiconductor memory 1 according to the first embodiment described above can reduce the associated chip area. Specific effects of the semiconductor memory 1 according to the first embodiment will be described.

[0104] To reduce the bit cost of semiconductor memory, it is desirable to increase the area ratio (cell occupancy) of the memory cell array within the chip area of ​​the semiconductor memory. As a method for increasing the cell occupancy in semiconductor memory, it is known to form memory cell arrays and peripheral circuits on different wafers and to bond these wafers together into a single semiconductor chip.

[0105] In the case of a semiconductor memory structure in which a wafer having a memory cell array is bonded together with a wafer having peripheral circuitry, the memory cell array and the peripheral circuitry overlap on the semiconductor chip, thereby increasing the cell occupancy rate. Figure 16 and Figure 17 An example of a semiconductor memory with this structure is shown. Figure 16 and Figure 17 The planar layout and cross-sectional structure of the semiconductor memory 3 according to the comparative example of the first embodiment are shown respectively.

[0106] The semiconductor memory 3 according to the comparative example differs from the semiconductor memory 1 according to the first embodiment in the design of the pad 17. For example... Figure 16As shown in the comparative example, in the semiconductor memory 3 according to the comparative example, the size of the pad region 15 is designed based on the pad width WP of the pad 17 so that the pad 17 is completely disposed within the pad region 15.

[0107] Moreover, as Figure 17 As shown in the comparative example, the semiconductor memory 3 according to the comparative example has a structure in which the memory chip 3-1 and the circuit chip 3-2 are bonded together, and the semiconductor memory 3 is designed so that the stacked lines constituting the memory cell array 10 are not included under the pad 17. The area of the pad 17 is determined based on a bonding step in a later process for the semiconductor memory 3, and thus it is difficult to reduce. Furthermore, for the semiconductor memory 3 according to the comparative example, the pad region 15 is designed to be wide based on the area of the pad 17, which results in a decrease in the cell occupancy.

[0108] In contrast, the semiconductor memory 1 according to the first embodiment includes a region in which the pad 17 overlaps the memory cell array 10, as Figure 4 and 9 As shown in the comparative example. With this structure, the semiconductor memory 1 according to the first embodiment can reduce the size of the pad region 15 compared to the semiconductor memory 3 according to the comparative example. Therefore, the semiconductor memory 1 according to the first embodiment can increase the cell occupancy and suppress the bit cost associated therewith.

[0109] Moreover, for the semiconductor memory 1 according to the first embodiment, the memory chip 1-1 and the circuit chip 1-2 are formed using different wafers so that a thermal process to form the memory chip 1-1 and a thermal process to form the circuit chip 1-2 are controlled independently of each other. This can reduce a thermal load on the circuit chip 1-2 due to the thermal process for forming the memory chip 1-1, and thus can permit the adoption of low-resistance lines (e.g., copper lines) as the supply line and various lines in the circuit chip 1-2. Therefore, the semiconductor memory 1 according to the first embodiment can improve device performance.

[0110] Furthermore, for the semiconductor memory 1 according to the first embodiment, the memory chip 1-1 and the circuit chip 1-2 are bonded together to connect the memory cell array 10 and the peripheral circuit such as the sense amplifier 12. In other words, the semiconductor memory 1 according to the first embodiment allows the omission of a deep hole process for forming a connection from the memory cell array 10 to the circuit on the semiconductor substrate 50. Therefore, the semiconductor memory 1 according to the first embodiment can reduce production costs.

[0111] [2] Second Embodiment

[0112] The semiconductor memory 1 according to the second embodiment differs from the semiconductor memory 1 according to the first embodiment in the layout of the pad 17. For the semiconductor memory 1 according to the second embodiment, the differences from the semiconductor memory 1 according to the first embodiment will be described.

[0113] [2-1] Configuration

[0114] Figure 18 One example of the Y-direction cross-sectional structure of the memory cell array 10 and the pad region 15 in the semiconductor memory 1 according to the second embodiment is shown. As shown in Figure 18 In the structure of the memory cell array 10 in the region overlapping the pad 17, the cross-sectional structure of the semiconductor memory 1 according to the second embodiment differs from the reference Figure 9 The cross-sectional structure of the semiconductor memory 1 described for the first embodiment.

[0115] Specifically, in the semiconductor memory 1 according to the second embodiment, a stair portion similar to the structure of the wiring region 14 is formed in a region of the periphery of the memory cell array 10 where the wiring region 14 is not adjacent. In this region, more specifically, the ends of the conductors 23 to 30 each serving as, for example, a word line WL are arranged in a stepped manner. The width of this stair portion is formed to be smaller than, for example, the width in the wiring region 14. Also, the conductors to connect the memory chip 1-1 and the circuit chip 1-2 are not connected in this stair portion.

[0116] In the semiconductor memory 1 according to the second embodiment, the pad 17 is provided to overlap this stair portion of the memory cell array 10 but not to overlap the memory portion of the memory cell array 10 where the semiconductor pillars MH are disposed. The semiconductor memory 1 according to the second embodiment is the same as the semiconductor memory 1 according to the first embodiment in other configurations. Therefore, the description of these configurations will be omitted.

[0117] [2-2] Effects of the Second Embodiment

[0118] In the bonding step in the later process for the semiconductor memory 1, pressure is applied from the pad 17 toward the semiconductor substrate 50. In the semiconductor memory 1 according to the second embodiment, the stair portion involving no semiconductor pillars MH or the like is disposed between the semiconductor substrate 50 and the pad 17.

[0119] That is, for the semiconductor memory 1 according to the second embodiment, the pressure applied to the pad 17 at the bonding time in the later process is transmitted to the stair portion that contains no effective devices. In this way, the semiconductor memory 1 according to the second embodiment can avoid the pressure applied to the semiconductor pillars MH during the bonding in the later process.

[0120] The semiconductor memory 1 according to the second embodiment can thus suppress defects due to bonding in a later process. Accordingly, the semiconductor memory 1 according to the second embodiment can improve the yield associated therewith.

[0121] Further, the semiconductor memory 1 according to the second embodiment can reduce the size of the pad region 15 as much as it overlaps with the staircase portion. Accordingly, the semiconductor memory 1 according to the second embodiment can increase the cell occupancy and suppress the bit cost associated therewith.

[0122] [3] Third Embodiment

[0123] The semiconductor memory 1 according to the third embodiment further adds a structure having a plurality of coupled memory chips to the semiconductor memory 1 according to the first embodiment. For the semiconductor memory 1 according to the third embodiment, the differences from the semiconductor memory 1 according to the first and second embodiments will be described.

[0124] [3-1] Configuration

[0125] The semiconductor memory 1 according to the third embodiment includes the memory chip 1-1 and the circuit chip 1-2 as described for the first embodiment, and further includes a memory chip 1-3. The memory chip 1-3 has a configuration similar to that of the memory chip 1-1. The memory chip 1-1 and the memory chip 1-3 are formed using different wafers. The semiconductor memory 1 according to the third embodiment has a structure in which the memory chip 1-1 is attached to the circuit chip 1-2 and the memory chip 1-3 is attached to the memory chip 1-1.

[0126] Figure 19 One example of the detailed planar layout of the memory cell array 10 and the wiring region 14 in the semiconductor memory 1 according to the third embodiment is shown. Specifically, the drawing shows four string cells SU0 to SU3 arranged in the Y direction.

[0127] As shown in Figure 19 The planar layout of the semiconductor memory 1 according to the third embodiment differs from the planar layout of the semiconductor memory 1 according to the first embodiment described in Figure 5

[0128] Specifically, each string cell SU has a plurality of coupling regions CA in the area of the memory cell array 10. The coupling region CA is a region for forming a line to electrically connect the bit line BL of the memory chip 1-1 with the bit line BL of the memory chip 1-3. The coupling regions CA provided in each string cell SU are arranged in, for example, the Y direction. However, this is not a limitation. The coupling regions CA can be designed to cover any given range and position. ​

[0129] Figure 20 A more detailed planar layout of a region of the memory cell array 10 including the coupling region CA is shown. As Figure 20 The coupling region CA has a plurality of contact vias CV, as shown in An insulating film 44 is formed on the inner wall of the contact via CV. A conductor 45 is formed or, for example, buried in a portion of the contact via CV that is more inward than the insulating film 44. The conductor 45 is connected to a corresponding conductor 38 that is connected to a different bit line BL.

[0130] Figure 21 An example of an X-direction cross-sectional structure of the memory cell array 10 and the wiring region 14 in the semiconductor memory 1 according to the third embodiment is shown. Note that the figures used in the following description will, as appropriate, omit a portion of the conductors corresponding to the word lines WL for descriptive purposes. As Figure 21 In the semiconductor memory 1 according to the third embodiment, as shown in

[0131] In the memory chip 1-1, a contact via CV is provided on the top face of the conductor 38 connected between one bit line BL and the terminal metal 39. A conductor 45 in the contact via CV is insulated from the stacked line structure, such as the word line WL, by the insulating film 44. A conductor 46 is provided on the top face of the conductor 45. The conductor 46 is arranged to overlap the terminal metal 39 in the X-Y plane. The terminal metal 39 is electrically connected to this conductor 46.

[0132] In the case of this structure, the conductor 46 provided in the memory chip 1-1 contacts the terminal metal 39 provided in the memory chip 1-3, so that one bit line BL in the memory chip 1-1 and one bit line BL in the memory chip 1-3 are electrically connected to each other. In a similar manner, the other bit lines BL in the memory chip 1-1 are connected to the corresponding bit lines BL in the memory chip 1-3 via the conductors 45 in the corresponding pairs of contact vias CV.

[0133] Like the bit lines BL, the word lines WL in the memory chip 1-1 have a structure for electrically connecting lines corresponding to a common address between the memory chips 1-1 and 1-3. More specifically, an additional contact plug 47 is provided on the top face of the conductor 42 connected between one word line WL and the terminal metal 43. The contact plug 47 is connected to a conductor 48 provided in the same layer as the conductor 46. The conductor 48 is arranged to overlap the terminal metal 43 in the X-Y plane. The terminal metal 43 is electrically connected to this conductor 48.

[0134] In the case of this structure, the conductor 48 provided in the memory chip 1-1 contacts the tab metal 43 provided in the memory chip 1-3, so that one word line WL in the memory chip 1-1 and one word line WL in the memory chip 1-3 are electrically connected to each other. In a similar manner, the other word lines WL as well as the select gate lines SGS and SGD in the memory chip 1-1 are connected to the corresponding lines in the memory chip 1-3 via the corresponding contact plugs 47.

[0135] Figure 22 One example of a Y-direction cross-sectional structure of the memory cell array 10 and the pad region 15 in the semiconductor memory 1 according to the third embodiment is shown. As shown in Figure 22 In the semiconductor memory 1 according to the third embodiment, the contact via TV penetrates each of the memory chips 1-1 and 1-3, as shown in

[0136] More specifically, the contact via TV leads from the top face of the conductor 62 in the circuit chip 1-2 to the insulating film INS at the topmost face of the memory chip 1-3. A conductor is formed or, for example, buried in the contact via TV. To the extent that a conductor can be formed or buried in this way, the contact via TV is formed as small as possible. The conductor formed in the contact via TV is insulated from the word lines WL as well as the select gate lines SGS and SGD in each of the memory chips 1-1 and 1-3.

[0137] The conductor formed in the contact via TV includes a portion exposed on the memory chip 1-3, and this portion exposed on the memory chip 1-3 serves as one pad 17. As in the first embodiment, the pad 17 includes a portion overlapping the memory cell array 10 in the memory chips 1-1 and 1-3.

[0138] In the semiconductor memory 1 according to the third embodiment, the distance from the source line SL in the memory chip 1-3 to the top face of the memory chip 1-3 is greater than the distance from the source line SL in the memory chip 1-1 to the memory chip 1-3. This is because in the memory chip stacked as the uppermost layer, a thick insulating film INS is maintained so that the conductors 46 and 48 for connecting the stacked memory chips are not exposed.

[0139] In the semiconductor memory 1 according to the third embodiment described above, the addresses of the word lines WL having a common connection between the memory chips 1-1 and 1-3 are specified by the same address information ADD (e.g., page address), and the addresses of the bit lines BL having a common connection between the memory chips 1-1 and 1-3 are specified by the same address information ADD (e.g., column address).

[0140] In the semiconductor memory 1 according to the third embodiment, information for specifying a memory chip included in the address information ADD (for example) is mentioned to select one of memory chips 1-1 and 1-3. This enables the semiconductor memory 1 according to the third embodiment to select one of the word lines WL having the same address in memory chips 1-1 and 1-3, and to select one of the bit lines BL having the same address in memory chips 1-1 and 1-3. In other configurations, the semiconductor memory 1 according to the third embodiment is the same as the semiconductor memory 1 according to the first embodiment. Therefore, descriptions of these configurations will be omitted.

[0141] [3-2] Effects of the third embodiment

[0142] As described above, the semiconductor memory 1 according to the third embodiment has a structure in which memory chips 1-1 and 1-3 are stacked on circuit chip 1-2. Moreover, in the semiconductor memory 1 according to the third embodiment, pad 17 is provided to overlap above the memory cell array 10, as in the first embodiment.

[0143] This allows the semiconductor memory 1 according to the third embodiment to have a smaller area of ​​the mounting pad 17, as in the first embodiment. Therefore, the semiconductor memory 1 according to the third embodiment can increase cell occupancy and suppress the associated bit cost.

[0144] The preceding description assumes that two memory chips 1-1 and 1-3 are stacked on circuit chip 1-2 within semiconductor memory 1. However, this is not a limitation. For example, semiconductor memory 1 may contain three or more memory chips stacked on circuit chip 1-2. The number of stacked memory chips can be arbitrarily set. Even in such cases, the cell occupancy in semiconductor memory 1 may be increased by overlapping pad 17 above memory cell array 10.

[0145] [4] Fourth embodiment

[0146] The semiconductor memory 1 according to the fourth embodiment further includes wiring different from pad 17 added to the top surface of the semiconductor memory 1 according to the first embodiment. The differences between the semiconductor memory 1 according to the fourth embodiment and the semiconductor memory 1 according to the first to third embodiments will be described.

[0147] [4-1] Configuration

[0148] Figure 23 This illustrates the planar layout of the semiconductor memory 1 according to the fourth embodiment when the memory chip 1-1 and the circuit chip 1-2 are bonded to each other. Figure 23 The planar layout and reference of the semiconductor memory 1 according to the fourth embodiment are shown in the figure.Figure 4 The difference in the planar layout of the semiconductor memory 1 according to the first embodiment is that multiple metal wirings 70 are added.

[0149] Metal wiring 70 extends in the X direction (for example) and bridges from memory cell array 10A to memory cell array 10B. For example, aluminum may be used as the metal wiring 70. Metal wiring 70 serves as a supply line (for example) disposed between memory cell array 10A and memory cell array 10B. Metal wiring 70 is not used (for example) for external connections of the semiconductor memory 1.

[0150] The shape and number of the metal wiring 70 are not limited to Figure 23 The shape and number shown are not fixed, but can be arbitrarily set. Furthermore, the metal wiring 70 can be provided in a manner that allows it to be entirely disposed on a memory cell array 10. In addition, the metal wiring 70 is not limited to the uses mentioned above, but can be used as other types of wiring.

[0151] Figure 24 An example of a Y-direction cross-sectional structure of the memory cell array 10 and pad region 15 in the semiconductor memory 1 according to the fourth embodiment is shown. Figure 24 The cross-sectional structure of the semiconductor memory 1 according to the fourth embodiment, as shown in the figure, is compared with that of the reference. Figure 9 The difference in the cross-sectional structure of the semiconductor memory 1 according to the first embodiment is the addition of a configuration associated with the metal wiring 70. For this embodiment, the figures illustrate two metal wirings 70A and 70B.

[0152] Metal wiring 70A is connected to conductor 49 disposed within memory chip 1-1. For example, conductor 49 is a line disposed between the surface of memory chip 1-1 and source line SL and connected to circuitry within memory chip 1-1.

[0153] Metal wiring 70B connects to conductor 63 disposed within circuit chip 1-2. Conductor 63 connects to circuitry within circuit chip 1-2. More specifically, contact conductor TH extends from the top surface of conductor 63 to the surface of memory chip 1-1. This contact conductor TH traverses a region of memory cell array 10 in which no semiconductor pillar MH is provided.

[0154] An insulating film 64 is formed on the inner wall of the contact conductor TH and serves as a conductor for the metal wiring 70B or (for example) is embedded inside the insulating film 64. In this way, the metal wiring 70B extends inside the memory cell array 10 and is insulated from various lines, such as word lines WL and select gate lines SGS and SGD, by the insulating film 64.

[0155] The metal wiring 70 described above is formed at the same time as the pads 17, for example. First, holes (contact vias TV and contact vias TH) for connecting the pads 17 and the metal wiring 70 to respective circuits in the semiconductor memory 1 are formed, for example. Then, the conductors serving as the pads 17 and the metal wiring 70 are formed or embedded in the formed holes, for example. Thereafter, the pads 17 and the metal wiring 70 are processed into desired shapes.

[0156] [4-2] Effects of the Fourth Embodiment

[0157] As described above, in the semiconductor memory 1 according to the fourth embodiment, the metal wiring 70 is provided in the same layer as the pads 17. The metal wiring 70 serves as a low-resistance wire, for example, thereby achieving connection between different memory cell arrays 10.

[0158] That is, in the case of the semiconductor memory 1 according to the fourth embodiment, the resistance of the wire connecting the memory cell arrays 10 to each other can be reduced by employing the metal wiring 70. Therefore, the semiconductor memory 1 according to the fourth embodiment can improve device performance.

[0159] [5] Modification Examples, etc.

[0160] Semiconductor Memory According to Embodiments Figure 1 , 1> includes a first memory chip Figure 3 , 1-1>, a circuit chip Figure 3 , 1-2>, and an external connection electrode Figure 4 , 17>. The first memory chip includes a plurality of first conductors Figure 7 , 23 to 30> stacked via insulators, and first pillars Figure 7 , MH> passing through the first conductors and forming cross points with the first conductors. Each of the cross points serves as a memory cell. The circuit chip includes a substrate Figure 9 , 50>, a control circuit Figure 9 , 16> formed on the substrate, and second conductors Figure 9 , 62> connected to the control circuit. The circuit chip is attached to the first memory chip. The external connection electrode is provided on a surface of the first memory chip and includes a portion extending through the first memory chip from one side of the surface of the first memory chip and connected to the second conductors. A portion of the first conductors is included between the external connection electrode and the substrate. The semiconductor memory can thus reduce chip area.

[0161] In the above embodiments, one pad 17 has a larger area (size) than one of the terminal metals 39, 43, 54, or 58. In other words, for the semiconductor memory 1, the area of the pad 17 provided on the semiconductor memory 1 and used for connection with the external memory controller 2 is larger than the area of the pad used for connecting the memory chip 1-1 and the circuit chip 1-2.

[0162] In the above embodiments, one pad 17 has a larger area (size) than one of the terminal metals 39, 43, 54, or 58. In other words, for the semiconductor memory 1, the area of the pad 17 provided on the semiconductor memory 1 and used for connection with the external memory controller 2 is larger than the area of the pad used for connecting the memory chip 1-1 and the circuit chip 1-2.

[0163] The description of the above embodiments has assumed that the semiconductor memory 1 has a configuration in which memory cell transistors MT including a charge accumulation layer are arranged three-dimensionally. However, this is not a limitation. The structure and the production process for the pad region 15 described for the above embodiments can be applied to other semiconductor memories. For example, the structure described for the above embodiments can be applied to a semiconductor memory having a configuration in which phase change memory cells are arranged three-dimensionally, or to a semiconductor memory having a configuration in which memory cells using ferroelectric thin film materials are arranged three-dimensionally.

[0164] In the context of the present specification, the term "connected" means electrically connected, and does not exclude the presence of other elements interposed between the connected elements, for example.

[0165] While specific embodiments have been described in detail, such embodiments have been presented by way of example only, and not by way of limitation. Indeed, the novel embodiments described herein can be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein can be made without departing from the spirit of the disclosure. It is intended that the following claims be broad enough to encompass any and all such forms within the scope and spirit of the disclosure.

Claims

1. A semiconductor memory, comprising: a memory chip including: a first region and a second region, the first region including: an array of memory cells including memory cells, bit lines, and word lines, the second region adjacent to the first region in a first direction and including: contacts electrically connected to the word lines; and a circuit chip attached to the memory chip and including: a third region and a fourth region, the third region including: a sense amplifier electrically connected to the bit lines, the fourth region adjacent to the third region in the first direction and including: a row decoder electrically connected to the contacts; wherein the first region and the third region overlap in a second direction crossing the first direction, and the second region and the fourth region overlap in the second direction.

2. The semiconductor memory according to claim 1, wherein the word lines are one or more, The memory cell array further comprises: a stack of the one or more word lines and a pillar extending through the stack, each of intersections between the pillar and the one or more word lines constituting a memory cell, the circuit chip includes: a substrate on which the sense amplifier and the row decoder are located, and part of the bit lines are between the substrate and the one or more word lines.

3. The semiconductor memory according to claim 2, wherein The memory cell array further comprises: a source line above the stack, the pillar including: an upper portion contacting the source line.

4. The semiconductor memory according to claim 1, wherein The circuit chip further comprises: a fifth region adjacent to the third region in a third direction crossing the first and second directions, the fifth region including: control circuitry constituting to control the array of memory cells, and the first region and the fifth region overlap in the second direction.

5. The semiconductor memory according to claim 4, wherein the fifth region is adjacent to the fourth region in the first direction.

6. The semiconductor memory according to claim 1, wherein The memory chip further comprises: a sixth region adjacent to the first region and the second region in a third direction crossing the first and second directions, and the circuit chip further includes: a seventh region overlapping the sixth region in the second direction and including input / output circuitry.

7. The semiconductor memory according to claim 6, further comprising: a pad on the memory chip, the pad electrically connected to the input / output circuitry and overlapping the first region and the sixth region in the second direction.

8. A semiconductor memory, comprising: a memory chip including: first, second, third, fourth, and fifth regions configured in a first direction, the second region including: a first array of memory cells including memory cells, first bit lines, and first word lines, the fourth region including: a second array of memory cells including memory cells, second bit lines, and second word lines, the first region including: first contacts electrically connected to the first word lines, the fifth region including: second contacts electrically connected to the second word lines, the third region including: a sense amplifier electrically connected to the second bit lines, the fourth region including: a row decoder electrically connected to the second contacts, the first region and the third region overlap in a second direction crossing the first direction, and the second region and the fourth region overlap in the second direction. The third region includes: the first contact, the second contact, or both the first contact and the second contact; and a circuit chip attached to the memory chip and including: sixth, seventh, eighth, ninth, and tenth regions overlapping the first, second, third, fourth, and fifth regions, respectively, in a second direction crossing the first direction, The seventh region includes: a first sense amplifier electrically connected to the first bit line, The ninth region includes: a second sense amplifier electrically connected to the second bit line, The sixth region includes: a first row decoder electrically connected to the first contact, The tenth region includes: a second row decoder electrically connected to the second contact, The eighth region includes: the first row decoder, the second row decoder, or both the first row decoder and the second row decoder.

9. The semiconductor memory according to claim 8, wherein The first word line is one or more, The first memory cell array further comprises: The stack of the one or more first word lines and a first pillar extending through the stack of the one or more first word lines, each of intersections between the first pillar and the one or more first word lines constitutes a memory cell, The second word line is one or more, The second memory cell array further includes: a stack of the one or more second word lines and a second pillar extending through the stack of the one or more second word lines, each of intersections between the second pillar and the one or more second word lines constitutes a memory cell, The circuit chip includes: a substrate on which the first sense amplifier, the second sense amplifier, the first row decoder, and the second row decoder are located, Part of the first bit line is between the substrate and the one or more first word lines, and Part of the second bit line is between the substrate and the one or more second word lines.

10. The semiconductor memory according to claim 9, wherein The first memory cell array further comprises: A first source line above the stack of the one or more first word lines, the first pillar includes: an upper portion contacting the first source line, and The second memory cell array further includes: a second source line above the stack of the one or more second word lines, the second pillar includes: an upper portion contacting the second source line.

11. The semiconductor memory according to claim 8, wherein The circuit chip further comprises: eleventh and twelfth regions, The eleventh region is adjacent to the seventh region in a third direction crossing the first and second directions, the eleventh region includes: a first control circuit configured to control the first memory cell array, the second region overlaps the eleventh region in the second direction, The twelfth region is adjacent to the ninth region in the third direction and includes: a second control circuit configured to control the second memory cell array, the fourth region overlaps the twelfth region in the second direction.

12. The semiconductor memory according to claim 11, wherein The eleventh region is adjacent to the sixth region and the eighth region in the first direction, and The twelfth region is adjacent to the eighth region and the tenth region in the first direction.

13. The semiconductor memory according to claim 8, wherein The memory chip further comprises: a thirteenth region adjacent to the first to fifth regions in a third direction intersecting the first and second directions, and The circuit chip further includes a fourteenth region overlapping the thirteenth region in the second direction and including an input / output circuit.

14. The semiconductor memory according to claim 13, further comprising: a first pad and a second pad on the memory chip, the first pad and the second pad electrically connected to the input / output circuit, the first pad overlapping the second region and the thirteenth region in the second direction, the second pad overlapping the fourth region and the thirteenth region in the second direction.

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