Semiconductor device forming method
By covering the bottom and sidewalls of the trench with a compensation layer and adjusting the growth conditions, the distance between the trench edge and the semiconductor fin is increased, which solves the problem of low semiconductor device yield in existing processes and achieves higher manufacturing yield and process accuracy.
Patent Information
- Application Number
- CN202410482536.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-19
- Publication Date
- 2025-11-04
AI Technical Summary
In existing semiconductor device fabrication processes, the yield of semiconductor fin field-effect transistors is relatively low, mainly due to insufficient distance between the trench edge and the semiconductor fin caused by etching deviation and alignment deviation, resulting in damage to the gate layer structure.
A compensation layer is covered on the bottom and sidewalls of the trench. By real-time online detection and adjustment of growth conditions, a compensation layer of the target thickness is formed to increase the distance between the trench edge and the semiconductor fin. The compensation layer and the gate structure layer are removed at the bottom of the trench to form a through-hole isolation trench.
It improves the manufacturing yield of semiconductor devices, reduces the probability of damage to semiconductor fins and gate structure layers caused by the isolation trench process, and improves process accuracy and production efficiency.
Smart Images
Figure CN120897474A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of semiconductor manufacturing, and in particular, to a semiconductor device forming method. BACKGROUND
[0002] With the increasing demand of semiconductor technology for higher storage capacity, faster processing system, higher performance, the improvement of fin field effect transistor characteristics is more and more challenging. In the existing design, a logic chip is composed of standard cells, and the standard cell includes a plurality of groups of semiconductor fins, a plurality of groups of P-type transistors, a plurality of groups of N-type transistors, a plurality of groups of gate traces, and a plurality of gate metal cut spaces; in order to improve the performance of the semiconductor device (for example, to increase the saturation current), during the layout design, on the basis of keeping the area of the standard cell unchanged, the performance optimization is realized by increasing the number of semiconductor channels, that is, P-type semiconductor fins are added between P-type transistors, or N-type semiconductor fins are added between N-type transistors.
[0003] However, when the existing process is used to manufacture the fin field effect transistor with a large number of semiconductor channels, the yield of the semiconductor device is reduced. SUMMARY
[0004] The technical problem solved by the present application is to provide a semiconductor device forming method to improve the yield of the semiconductor device.
[0005] In order to solve the above problems, the embodiment of the present application provides a semiconductor device forming method, which comprises the following steps: providing a substrate; forming a semiconductor fin on the substrate; covering a gate structure layer on the surface of the semiconductor fin; forming a mask layer covering the gate structure layer; forming a trench in the mask layer; covering a compensation layer on the bottom and sidewall of the trench; removing the compensation layer and the gate structure layer at the bottom of the trench to form a partition trench penetrating through the gate structure layer; and filling a dielectric layer in the partition trench.
[0006] Optionally, the compensation layer is formed by using an advanced process control mode; the advanced process control mode comprises: detecting the relative position between the trench edge and the semiconductor fin in real time and online, and adjusting the growth conditions of the compensation layer in real time based on the detection result, and forming a compensation layer with a target thickness in the trench to compensate for the distance between the trench edge and the semiconductor fin.
[0007] Optionally, the material of the compensation layer comprises one or more of silicon nitride, silicon carbon nitride, and silicon oxynitride.
[0008] Optionally, the thickness of the compensation layer is in the range of 30 angstroms to 150 angstroms.
[0009] Optionally, the compensation layer is formed by using an atomic layer deposition technology.
[0010] Optionally, further comprising: forming an intermediate dielectric layer covering the gate structure layer before forming the mask layer; using the intermediate dielectric layer as a stop layer in the step of forming the trench in the mask layer; and removing the intermediate dielectric layer at the bottom of the trench in the step of forming the isolation trench.
[0011] Optionally, the intermediate dielectric layer has the same material as the compensation layer.
[0012] Optionally, the step of forming the trench in the mask layer comprises: forming the first trench and the second trench in sequence by two masks.
[0013] Optionally, the step of forming the compensation layer comprises: using an advanced process control mode to detect the relative position of the first trench edge and the semiconductor fin and the relative position of the second trench edge and the semiconductor fin in real time and on line, and adjusting the growth condition of the compensation layer in real time based on the detection result, and forming the compensation layer of the target thickness in the first trench and the second trench at the same time.
[0014] Optionally, the step of forming the compensation layer further comprises: using an advanced process control mode to detect the relative position of the first trench edge and the semiconductor fin in real time and on line, adjusting the growth condition of the compensation layer in real time based on the detection result, and forming the first compensation layer of the target thickness in the first trench; and using an advanced process control mode to detect the relative position of the second trench edge and the semiconductor fin in real time and on line, adjusting the growth condition of the compensation layer in real time based on the detection result, and forming the second compensation layer of the target thickness in the second trench.
[0015] Optionally, the step of forming the isolation trench further comprises: removing the compensation layer at the whole or partial thickness on the sidewall of the trench.
[0016] Optionally, the compensation layer is also located on the mask layer, and the step of forming the isolation trench further comprises: removing the compensation layer at the whole or partial thickness on the mask layer.
[0017] Optionally, the step of forming the mask layer comprises: forming the first mask layer, the second mask layer and the third mask layer in sequence from bottom to top on the surface of the gate structure layer; and the step of forming the isolation trench further comprises: removing the third mask layer and the second mask layer at the partial thickness.
[0018] Optionally, the material of the first mask layer comprises silicon oxide, the material of the second mask layer comprises silicon nitride, the material of the third mask layer comprises silicon oxide, the material of the compensation layer comprises silicon nitride, and the material of the dielectric layer comprises silicon nitride.
[0019] Optionally, the step of forming the isolation trench further comprises: removing the substrate at the partial thickness, so that the bottom of the isolation trench is located in the substrate.
[0020] Compared with the prior art, the technical scheme of the embodiment of the application has the following advantages:
[0021] In the semiconductor device forming method provided by the embodiment of the application, the compensation layer is covered on the bottom and sidewall of the trench; in the step of removing the compensation layer on the bottom of the trench and the gate structure layer to form the partition trench penetrating through the gate structure layer, the compensation layer is used to increase the distance between the trench edge and the semiconductor fin, so as to provide sufficient process space for the manufacturing of the partition trench, thus reducing the damage probability of the semiconductor fin and the gate structure layer on the semiconductor fin caused by the partition trench process, and improving the manufacturing yield of the semiconductor device.
[0022] In an optional solution, the compensation layer is formed by using an advanced process control mode; the advanced process control mode includes: detecting the relative position between the trench edge and the semiconductor fin in real time and on line, and adjusting the growth condition of the compensation layer in real time based on the detection result, and forming the compensation layer with a target thickness in the trench to compensate the distance between the trench edge and the semiconductor fin; by using the advanced process control mode, the process parameters can be adjusted in real time, and the compensation layer with the required target thickness can be automatically formed in the trench, which not only reduces the dependence on manual work, but also improves the production efficiency of forming the compensation layer, the accuracy of forming the target thickness of the compensation layer, and the manufacturing yield of the semiconductor device. BRIEF DESCRIPTION OF DRAWINGS
[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced as follows. Obviously, the drawings in the following description are only embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of the provided drawings.
[0024] Figures 1 to 5 is a structure diagram corresponding to each step in a semiconductor device forming method;
[0025] Figure 6 is Figures 1 to 5 is a diagram showing the relationship between the threshold voltage of the formed semiconductor device and the distance between the trench and the semiconductor fin;
[0026] Figures 7 to 15 is a structure diagram corresponding to each step in a semiconductor device forming method according to an embodiment of the present application;
[0027] Figure 16 is a structure diagram corresponding to each step in a semiconductor device forming method according to another embodiment of the present application. DETAILED DESCRIPTION
[0028] With reference to the drawings and the embodiments of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.
[0029] As described in the background, the prior art semiconductor fin field effect transistor manufacturing process has problems affecting the yield of semiconductor devices. The following will combine the Figures 1 to 5 semiconductor device forming method shown in the drawings to analyze the reasons why the manufacturing process affects the yield of semiconductor devices. The semiconductor device forming method mainly includes the following steps:
[0030] As shown in Figure 1 , a semiconductor fin 101 and a gate layer structure 102 covering the semiconductor fin 101 are formed on a substrate 100; the gate layer structure 102 includes a gate insulating layer (not shown).
[0031] As shown in Figure 2 , a mask layer A0 covering the gate layer structure 102 is formed; the mask layer A0 includes a bottom mask layer 103, an intermediate mask layer 104, and a top mask layer 105 from bottom to top.
[0032] As shown in Figure 3 , a mask trench 106 is formed by an exposure and development etching process; the mask trench 106 has a width w1; the mask trench 106 has the surface of the gate layer structure 102 as the bottom.
[0033] As shown in Figure 4 , the gate layer structure 102 and part of the substrate at the mask trench 106 are removed by an etching process to form an isolation trench 107, and the bottom of the isolation trench 107 is in the substrate 100.
[0034] As shown in Figure 5 , an isolation dielectric layer 108 is formed in the isolation trench 107 and on the remaining mask layer A0.
[0035] In the prior art semiconductor device manufacturing process of forming a mask trench 106, on the one hand, due to the existence of etching deviation, the width w1 of the formed mask trench 106 is larger than the design value, and the distances w2 and w3 between the edge of the mask trench 106 and the semiconductor fin 101 become smaller; on the other hand, due to the existence of alignment deviation, the distance w2 or w3 between the edge of the formed mask trench 106 and the semiconductor fin 101 is smaller than the design value; the above two factors cause the distance between the mask trench 106 and the semiconductor fin 101 to be unable to meet the process space required for forming an isolation trench 107, that is, in the process of etching to form the isolation trench 107, the gate structure 102 on the semiconductor fin 101a or the semiconductor fin 101b will be damaged, and as the spacing w0 between the semiconductor fins 101 gradually becomes smaller, the damage probability of the gate structure 102 increases, which affects the performance of the semiconductor device, thereby reducing the yield of the semiconductor device.
[0036] As Figure 6 shown in the threshold voltage and spacing (the spacing between the mask trench 106 and the semiconductor fin 101) relationship diagram; the horizontal coordinate is the spacing, and the vertical coordinate is the threshold voltage, wherein the mark A section of smaller spacing corresponds to the threshold voltage drift of the semiconductor fin 101a, and the mark B section of larger spacing corresponds to the stable threshold voltage of the semiconductor fin 101b, that is, the smaller the spacing (A section), the easier the threshold voltage of the semiconductor device to drift, and thus, the problem of low yield is caused.
[0037] To solve the technical problem, the embodiment of the present application provides a semiconductor device forming method, which comprises the following steps: providing a substrate; forming a semiconductor fin on the substrate; covering a gate structure layer on the surface of the semiconductor fin; forming a mask layer covering the gate structure layer; forming a trench in the mask layer; covering a compensation layer on the bottom and sidewall of the trench; removing the compensation layer and the gate structure layer at the bottom of the trench to form a partition trench penetrating through the gate structure layer; and filling a medium layer in the partition trench.
[0038] In the semiconductor device forming method provided by the embodiment of the present application, in the steps of covering a compensation layer on the bottom and sidewall of the trench and removing the compensation layer and the gate structure layer at the bottom of the trench to form a partition trench penetrating through the gate structure layer, the compensation layer is used to increase the distance between the edge of the trench and the semiconductor fin, so as to provide sufficient process space for the manufacturing of the partition trench, thereby reducing the damage probability of the semiconductor fin and the gate structure layer on the semiconductor fin in the partition trench process, and improving the yield of the semiconductor device.
[0039] In order to make the above-mentioned purposes, characteristics and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings.
[0040] ReferenceFigures 7 to 15 is a structural diagram corresponding to each step in a semiconductor device forming method according to an embodiment of the present application.
[0041] Referring to Figure 7 , a substrate 200 is provided, and a semiconductor fin 201 is formed on the substrate 200, which is used to form a semiconductor device channel. It should be noted that, for the sake of simplicity and clarity of the drawings, all embodiments of the present application are exemplified by taking four semiconductor fins 201 as an example, but this does not limit the present application.
[0042] In this embodiment, the substrate 200 is used to provide a process platform for the formation of a semiconductor device. The substrate 200 is a silicon substrate, and the material of the substrate 200 is single crystal silicon. In other embodiments, the material of the substrate 200 can also be one or more of germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium. The substrate 200 can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. In some other embodiments, an epitaxial layer (not shown) having the same crystal structure as the substrate 200 is formed on the surface of the substrate 200 to improve the quality of pattern transfer.
[0043] In this embodiment, the semiconductor fin 201 is formed by patterning the substrate 200, and the material of the semiconductor fin 201 is the same as that of the substrate 200, both of which are silicon. In some other embodiments, the material of the semiconductor fin 201 can be different from that of the substrate 200, for example, it can be one or more of germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium.
[0044] In this embodiment, a dry etching process is used to etch the substrate to form the semiconductor fin 201. The reaction gas used in the dry etching process includes one or more of fluorine gas, hydrogen fluoride, hydrogen trifluoride, fluorine radicals, and nitrogen trifluoride radicals. In other embodiments, a wet etching process can be used.
[0045] Continuing to refer to Figure 7 , a gate structure layer 202 is formed on the surface of the semiconductor fin 201; the gate structure layer 202 is used to control the opening and closing of the transistor of the semiconductor device.
[0046] Specifically, in a fin field-effect transistor (FinFET), the gate structure layer 202 spans multiple semiconductor fins 201, and when multiple FinFETs share a gate structure layer 202, a subsequent metal gate cut (MGC) process is needed to form a separation trench, so that the gate structure layer 202 between the FinFETs is disconnected.
[0047] In this embodiment, the step of forming the gate structure layer 202 includes forming a gate dielectric layer (not shown) covering the semiconductor fin 201 and a gate electrode layer (not shown) covering the gate dielectric layer; the gate dielectric layer is used to achieve electrical isolation between the gate electrode layer and the semiconductor fin 201, and the gate electrode layer is used for electrical connection between the gate structure layer 202 and an external circuit.
[0048] In this embodiment, the gate structure layer 202 is a metal gate structure layer, and the material of the gate electrode layer includes one or more of titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), titanium (Ti), titanium aluminum (TiAl), tungsten (W), aluminum (Al), titanium silicon nitride (TiSiN), and titanium aluminum carbide (TiAlC).
[0049] In this embodiment, the gate electrode layer is formed by a physical vapor deposition process; in other embodiments, a chemical vapor deposition process can be used.
[0050] In this embodiment, the formation of the gate structure layer 202 further includes forming a work function layer (not shown). The work function layer is used to adjust the threshold voltage of the semiconductor transistor. For example, when an NMOS transistor is formed, the work function layer is an N-type work function layer, and the material of the N-type work function layer includes one or more of titanium aluminum and titanium aluminum carbide; when a PMOS transistor is formed, the work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or more of titanium nitride, tantalum nitride, and titanium silicon nitride.
[0051] In this embodiment, the work function layer is formed by a physical vapor deposition, chemical vapor deposition, or atomic layer deposition process, and then the required impurity elements are introduced into the work function layer by an ion implantation, diffusion, or laser doping process to adjust the conductivity of the work function layer, thereby adjusting the threshold voltage of the semiconductor transistor.
[0052] In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer is a high-k dielectric material. The material of the high-k gate dielectric layer can be selected from zirconium oxide, silicon hafnium oxide, silicon hafnium oxynitride, tantalum hafnium oxide, titanium hafnium oxide, zirconium hafnium oxide, or aluminum oxide. In other embodiments, the gate dielectric layer can further include a gate oxide layer and a high-k gate dielectric layer on the gate oxide layer, or the gate dielectric layer can include a gate oxide layer.
[0053] In this embodiment, the gate dielectric layer is formed by a physical vapor deposition or atomic layer deposition process.
[0054] Referring to Figure 8 A mask layer Y0 covering the gate structure layer 202 is formed; the mask layer Y0 is used as a mask for forming an etching groove (or a partition groove).
[0055] It should be noted that in this embodiment, the mask layer Y0 is a hard mask, which is less affected by the semiconductor process and is more suitable for narrow trench process. For example, after high-temperature process, the hard mask pattern formed is not easy to deform and has high fine degree, so as to ensure the quality of pattern transfer. In other embodiments, the patterning method of hard mask can also not be used.
[0056] In this embodiment, the step of forming the mask layer Y0 includes sequentially forming a first mask layer 204, a second mask layer 205 and a third mask layer 206 on the surface of the gate structure layer 202 from bottom to top.
[0057] The material of the first mask layer 204 includes one or more of silicon oxide, silicon nitride and silicon carbide; the material of the second mask layer 205 includes one or more of silicon oxide, silicon nitride and silicon carbide; the material of the third mask layer 206 includes one or more of silicon oxide, silicon nitride and silicon carbide; in this embodiment, the material of the first mask layer 204 is silicon oxide, the material of the second mask layer 205 is silicon nitride, and the material of the third mask layer 206 is silicon oxide.
[0058] In this embodiment, the first mask layer 204, the second mask layer 205 and the third mask layer 206 can be sequentially formed on the surface of the gate structure layer 202 from bottom to top by using chemical vapor deposition or atomic layer deposition technology; the material of the first mask layer 204 is silicon oxide, which is dominant in compressive stress, and when it contacts with the substrate, it causes the substrate 200 to shrink; the material of the second mask layer 205 is silicon nitride, which is dominant in tensile stress, and can balance the substrate shrinkage caused by the compressive stress of the first mask layer 204; the material of the third mask layer 206 is silicon oxide, which is dominant in compressive stress, and when it contacts with the second mask layer 205, it can balance the substrate 200 expansion caused by the tensile stress of the second mask layer 205.
[0059] Continuing to refer to Figure 8 , the forming method further includes: after forming the gate structure layer 202 and before forming the mask layer Y0, forming an intermediate dielectric layer 203 covering the gate structure layer 202; the intermediate dielectric layer 203 is used as a stop layer when forming a trench in the mask layer subsequently.
[0060] The material of the intermediate dielectric layer 203 includes one or more of silicon oxide, silicon nitride, silicon carbon nitride and silicon carbon oxide; in this embodiment, the material of the intermediate dielectric layer 203 is silicon nitride.
[0061] It should be noted that in the embodiment, the intermediate medium layer material is the same as the subsequent compensation layer material, and the compensation layer and the intermediate medium layer at the bottom of the trench can be removed by one etching process when the isolation trench is formed, thereby saving the process procedure and improving the process efficiency; in other embodiments, the intermediate medium layer material can be different from the subsequent compensation layer material.
[0062] In the embodiment, the intermediate medium layer 203 is formed on the surface of the gate structure layer 202 by chemical vapor deposition or atomic layer deposition technology.
[0063] Reference Figures 9 to 12 A trench (not shown) is formed in the mask layer Y0, and the trench includes a first trench C1 and a second trench C2; the trench is used to provide a process window for subsequent formation of an isolation trench.
[0064] In the embodiment, the step of forming the trench in the mask layer Y0 includes: forming the first trench C1 and the second trench C2 arranged in a space by two masks in sequence; when the semiconductor fins 201 are in a narrow pitch, two masks can ensure the integrity of the first trench C1 and the second trench C2 to a greater extent relative to one mask, thereby improving the process reliability.
[0065] In the embodiment, the step of forming the trench includes: taking a photoresist pattern as a mask, and forming the trench by dry etching.
[0066] It should be noted that the trench is used to form an isolation trench for metal gate cut (MGC), and one or more semiconductor fins 201 are included between the formed trenches; for an embodiment in which multiple semiconductor fins 201 are included between the trenches, the pitch between the trench and the semiconductor fin 201 is small.
[0067] Specifically, continuing to refer to Figure 9 and Figure 10 , the specific process steps of forming the first trench C1 are as follows:
[0068] A photoresist G00 is formed on the surface of the mask layer Y0.
[0069] A first mask layer 204, a second mask layer 205, and a third mask layer 206 located below the first opening G1 are removed by a dry etching process by taking the intermediate medium layer 203 as a stop layer, to form the first trench C1 between the semiconductor fins 201; the photoresist G00 is removed by a photoresist stripping process.
[0070] A first mask layer 204, a second mask layer 205, and a third mask layer 206 located below the first opening G1 are removed by a dry etching process by taking the intermediate medium layer 203 as a stop layer, to form the first trench C1 between the semiconductor fins 201; the photoresist G00 is removed by a photoresist stripping process.
[0071] With reference to the foregoing Figure 11 and Figure 12 The specific process steps of forming the second trench C2 are as follows:
[0072] Forming photoresist G01 to fill the first trench C1 and cover the surface of the mask layer Y0.
[0073] Exposing and developing the photoresist G01 by using the second mask to form a second opening G2 at the corresponding position of the cut-off of the gate structure layer.
[0074] Taking the intermediate medium layer 203 as a stop layer, removing the first mask layer 204, the second mask layer 205 and the third mask layer 206 located below the second opening G2 by dry etching process to form the second trench C2 between the semiconductor fins 201; and removing the photoresist G01 by, for example, a photoresist stripping process.
[0075] With reference to the foregoing Figure 13 Covering the compensation layer on the bottom and sidewall of the trench to reduce the damage probability of the semiconductor fins 201 and the gate structure layer 202 located on the semiconductor fins 201 caused by the process of making the isolation trench.
[0076] In this embodiment, the compensation layer also covers the surface of the mask layer, that is, the compensation layer is located on the mask layer.
[0077] In this embodiment, the compensation layer 207 uses the same material as the intermediate medium layer 203, so that the same process as removing the intermediate medium layer 203 can be used when removing the intermediate medium layer 203 and the compensation layer 207 at the bottom of the trench, thereby improving the process compatibility.
[0078] The material of the compensation layer 207 includes one or more of silicon nitride, silicon carbon nitride and silicon oxynitride. In this embodiment, the material of the compensation layer 207 is silicon nitride.
[0079] The compensation layer is formed by using an advanced process control mode; the advanced process control mode includes real-time online detection of the relative position between the trench edge and the semiconductor fin, and real-time adjustment of the growth conditions of the compensation layer based on the detection results, and forming a compensation layer with a target thickness in the trench to compensate for the distance between the trench edge and the semiconductor fin.
[0080] It should be noted that by using the advanced process control mode, the compensation layer with the required target thickness is automatically formed in the trench by real-time detection and real-time adjustment of the process parameters, which not only reduces the dependence on manual operation and saves the process procedure, but also improves the production efficiency of forming the compensation layer, the accuracy of forming the target thickness of the compensation layer and the production yield of the semiconductor device.
[0081] For simplicity and clarity of the drawings, all embodiments of the present application are exemplified by two trenches, which do not limit the present application.
[0082] With reference to Figure 13 , the step of forming the compensation layer comprises: using an advanced process control mode to detect the relative positions of the edges of the first trench C1 and the second trench C2 to the semiconductor fin 201 in real time and online, and adjusting the growth conditions of the compensation layer in real time based on the detection results, and simultaneously forming the compensation layer 207 of a target thickness in the first trench C1 and the second trench C2.
[0083] Specifically, after the second trench C2 is formed, before the partition trench is formed, the relative positions of the edges of the first trench C1 and the second trench C2 to the semiconductor fin 201 are detected in real time and online, that is, the distances a1 and a2 of the edge of the first trench C1 to the semiconductor fin 201, and the distances b1 and b2 of the edge of the second trench C2 to the semiconductor fin 201 are detected in real time, and the detected distances a1, a2, b1 and b2 are compared with the limit distance c0 (the limit distance c0: the minimum distance required for not damaging the semiconductor fin and the gate structure layer when the partition trench is formed; the limit distance c0 is not shown) by the advanced process control mode, if the distances a1, a2, b1 and b2 are greater than or equal to the limit distance c0, the compensation layer does not need to be compensated on the bottom and sidewall of the first trench C1 and the second trench C2; if one or more of the distances a1, a2, b1 and b2 are less than the limit distance c0, the advanced process control mode automatically compensates the compensation layer 207 of a target thickness in the first trench C1 and the second trench C2 on the bottom and sidewall at the same time according to the smallest distance among the distances a1, a2, b1 and b2, for example, if the smallest distance is a1, the target thickness of the compensation layer 207 is greater than or equal to c0 minus a1.
[0084] The film layer formed by atomic layer deposition has the advantages of thinness and uniformity, dense structure, and good adhesion to the trench; in this embodiment, the atomic layer deposition technology is used to form the compensation layer 207.
[0085] It should be noted that if the thickness of the compensation layer 207 is too large, the process production cycle is increased; if the thickness of the compensation layer 207 is too small, the compensation requirement cannot be met when compensating the distance between the trench edge and the semiconductor; in this embodiment, the thickness of the compensation layer 207 is in the range of 30 angstroms to 150 angstroms.
[0086] With reference to Figure 14, removing the compensation layer 207 and the gate structure layer 202 at the bottom of the trench to form a partition trench penetrating through the gate structure layer 202; the partition trench is used to disconnect the gate structure layer 202 and provide space for subsequent filling of the dielectric layer.
[0087] In the embodiment, the step of forming the partition trench includes: taking the mask layer Y0 as a mask, removing the compensation layer 207, the intermediate dielectric layer 203 and the gate structure layer 202 at the bottom of the trench by a dry etching process to form the partition trench; the partition trench includes a partition trench D1 and a partition trench D2; the partition trench D1 corresponds to the first trench C1, and the partition trench D2 corresponds to the second trench C2.
[0088] With reference to Figure 14 In the embodiment, in the step of forming the partition trench, the compensation layer 207 at the entire or partial thickness of the sidewall of the trench is also removed by the dry etching process; the compensation layer 207 at the sidewall of the trench increases the spacing between the partition trench and the semiconductor fin by its own thickness, and also protects the sidewall of the trench during the formation of the partition trench.
[0089] With reference to Figure 14 In the step of forming the partition trench, the compensation layer 207 at the entire or partial thickness of the mask layer Y0 is also removed by the dry etching process. In the embodiment, the compensation layer 207 on the mask layer Y0 is removed when the partition trench is formed, so that a separate step of removing the compensation layer 207 is not needed, thereby improving the process efficiency.
[0090] With reference to Figure 14 It should be noted that in the step of forming the partition trench, the third mask layer 206 and the second mask layer 205 at a partial thickness are also removed by the dry etching process, thereby reducing the difficulty of subsequent removal of the mask layer.
[0091] With reference to Figure 14 In the embodiment, in the step of forming the partition trench, the substrate at a partial thickness is also removed by the dry etching process, so that the bottom of the partition trench is located in the substrate 200, thereby facilitating effective isolation between FinFETs.
[0092] With reference to Figure 15 A dielectric layer 208 is filled in the partition trench; the dielectric layer 208 is used to realize physical isolation or electrical isolation between the gate structure layers of the FinFETs.
[0093] The material of the dielectric layer 208 includes one or more of silicon nitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, silicon carbonitride and silicon boronitride. In the embodiment, the material of the dielectric layer 208 is silicon nitride.
[0094] In this embodiment, a dielectric layer 208 is formed in the partition trench by chemical vapor deposition. The dielectric layer 208 also covers the surface of the mask layer Y0. The excess film layer, such as the dielectric layer 208, can be removed by chemical mechanical polishing (CMP).
[0095] refer to Figure 16 This is another optional embodiment of the present invention; in comparison Figure 16 and Figure 13 As can be seen, the difference between the embodiments of the present invention and the aforementioned embodiments is that: an advanced process control mode is adopted to form a compensation layer of target thickness in the first trench V1 and the second trench V2 respectively, that is: the relative position between the edge of the first trench V1 and the semiconductor fin 300 is detected online in real time, the growth conditions of the compensation layer are adjusted in real time based on the detection results, and a first compensation layer 301 of target thickness is formed in the first trench V1; and the relative position between the edge of the second trench V2 and the semiconductor fin 300 is detected online in real time, the growth conditions of the compensation layer are adjusted in real time based on the detection results, and a second compensation layer 302 of target thickness is formed in the second trench V2.
[0096] It should be noted that by adopting an advanced process control mode, the required target thickness compensation layer is automatically formed in the trench through real-time detection and adjustment of process parameters. Specifically, a first compensation layer 301 is formed at the bottom and sidewall of the first trench V1 to compensate for the target thickness, and a second compensation layer 302 is formed at the bottom and sidewall of the second trench V2 to compensate for the target thickness. This not only reduces the reliance on manual labor, but also improves the accuracy of forming the target thickness of the compensation layer and the yield of semiconductor device manufacturing.
[0097] Continue to refer to Figure 16 Specifically, after the second trench V2 is formed but before the isolation trench is formed, the relative positions of the edges of the first trench V1 and the second trench V2 with the semiconductor fin 300 are detected in real time online. That is, the distances e1 and e2 between the edges of the first trench V1 and the semiconductor fin 300, and the distances f1 and f2 between the edges of the second trench V2 and the semiconductor fin 300 are detected in real time. The advanced process control mode automatically compares the detected distances e1, e2, f1, and f2 with the limit distance c0 (limit distance c0: the minimum distance required to form the isolation trench without damaging the semiconductor fin and gate structure layer; limit distance c0 is not shown).
[0098] If the distance e1 and the distance e2 are greater than or equal to the limit distance c0, no compensation layer is needed to compensate the bottom and sidewall of the first trench V1; if one or both of the distance e1 and the distance e2 are less than the limit distance c0, the advanced process control mode automatically compensates the first compensation layer 301 of the target thickness on the bottom and sidewall of the first trench V1 according to the minimum distance of the distance e1 and the distance e2, for example, the minimum distance is e1, and the target thickness of the first compensation layer 301 is greater than or equal to c0 minus e1.
[0099] If the distance f1 and the distance f2 are greater than or equal to the limit distance c0, no compensation layer is needed to compensate the bottom and sidewall of the second trench V2; if one or both of the distance f1 and the distance f2 are less than the limit distance c0, the advanced process control mode automatically compensates the second compensation layer 302 of the target thickness on the bottom and sidewall of the second trench V2 according to the minimum distance of the distance f1 and the distance f2, for example, the minimum distance is f1, and the target thickness of the second compensation layer 302 is greater than or equal to c0 minus f1.
[0100] The film layer formed by the atomic layer deposition method has the advantages of thinness and uniformity, dense structure, and good adhesion to the trench; in the embodiment, the atomic layer deposition technology is used to form the first compensation layer 301 and the second compensation layer 302.
[0101] It should be noted that if the thickness of the first compensation layer 301 and the second compensation layer 302 is too large, the process production cycle is increased; if the thickness of the first compensation layer 301 and the second compensation layer 302 is too small, the compensation requirement cannot be met when compensating the distance between the trench edge and the semiconductor; in the embodiment, the thickness of the first compensation layer 301 and the second compensation layer 302 is in the range of 30 angstroms to 150 angstroms.
[0102] In summary, in the semiconductor device forming method provided by the embodiment of the present application, the compensation layer is covered on the bottom and sidewall of the trench, the compensation layer and the gate structure layer on the bottom of the trench are removed, and the step of forming the partition trench penetrating through the gate structure layer, the compensation layer is used to increase the distance between the trench edge and the semiconductor fin, and sufficient process space is provided for the production of the partition trench, so as to reduce the damage probability of the semiconductor fin and the gate structure layer on the semiconductor fin caused by the partition trench process, thereby improving the production yield of the semiconductor device.
[0103] Although the present application has been disclosed with reference to the preferred embodiments, it is not intended to limit the present application, and any person skilled in the art can make possible changes and modifications to the technical solutions of the present application using the disclosed methods and technical contents without departing from the spirit and scope of the present application. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application without departing from the technical solutions of the present application shall fall within the protection scope of the technical solutions of the present application.
Claims
1. A method for forming a semiconductor device, characterized in that, include: Provide a base; Semiconductor fins are formed on the substrate; A gate structure layer is covered on the surface of the semiconductor fin; Form a mask layer covering the gate structure layer; Trenches are formed in the mask layer; A compensation layer is applied to the bottom and sidewalls of the trench; Remove the compensation layer and gate structure layer at the bottom of the trench to form a barrier trench that penetrates the gate structure layer; A medium layer is filled into the partition trench.
2. The forming method as described in claim 1, characterized in that, The compensation layer is formed using an advanced process control model. The advanced process control mode includes: real-time online detection of the relative position between the trench edge and the semiconductor fin, and real-time adjustment of the growth conditions of the compensation layer based on the detection results, and formation of a compensation layer of target thickness in the trench to compensate for the distance between the trench edge and the semiconductor fin.
3. The forming method as described in claim 1, characterized in that, The material of the compensation layer includes one or more of silicon nitride, silicon carbonitride, and silicon oxynitride.
4. The forming method as described in claim 1, characterized in that, The thickness of the compensation layer is in the range of 30 angstroms to 150 angstroms.
5. The forming method as described in claim 1, characterized in that, The compensation layer is formed using atomic layer deposition (ALD) technology.
6. The forming method as described in claim 1, characterized in that, Also includes: After forming the gate structure layer and before forming the mask layer, an intermediate dielectric layer is formed to cover the gate structure layer; In the step of forming trenches in the mask layer, the intermediate dielectric layer is used as a stop layer; In the process of forming the partition trench, the intermediate medium layer located at the bottom of the trench is also removed.
7. The forming method as described in claim 6, characterized in that, The intermediate medium layer is made of the same material as the compensation layer.
8. The forming method as described in claim 1, characterized in that, The step of forming trenches in the mask layer is as follows: First trenches and second trenches are formed sequentially by two photomasks.
9. The forming method as described in claim 8, characterized in that, The steps for forming the compensation layer include: using an advanced process control mode to detect the relative positions of the edge of the first trench and the semiconductor fin and the edge of the second trench and the semiconductor fin in real time, adjusting the growth conditions of the compensation layer in real time based on the detection results, and simultaneously forming a compensation layer of the target thickness in the first trench and the second trench.
10. The forming method as described in claim 8, characterized in that, The steps for forming the compensation layer also include: An advanced process control mode is adopted to detect the relative position of the first trench edge and the semiconductor fin in real time online. Based on the detection results, the growth conditions of the compensation layer are adjusted in real time, and a first compensation layer of the target thickness is formed in the first trench; and An advanced process control mode is adopted to detect the relative position of the edge of the second trench and the semiconductor fin in real time. Based on the detection results, the growth conditions of the compensation layer are adjusted in real time, and a second compensation layer of the target thickness is formed in the second trench.
11. The forming method as described in claim 1, characterized in that, In the step of forming the partition trench, a compensation layer of all or part of its thickness located on the sidewall of the trench is also removed.
12. The forming method as described in claim 1, characterized in that, The compensation layer is also located on the mask layer, and in the step of forming the isolation trench, the compensation layer, of all or part of its thickness, located on the mask layer is also removed.
13. The forming method as described in claim 12, characterized in that, The steps for forming the mask layer include: A first mask layer, a second mask layer, and a third mask layer are formed sequentially from bottom to top on the surface of the gate structure layer; In the step of forming the partition trench, the third mask layer and a portion of the thickness of the second mask layer are also removed.
14. The forming method as described in claim 13, characterized in that, The first mask layer material includes silicon oxide, the second mask layer material includes silicon nitride, the third mask layer material includes silicon oxide, the compensation layer material includes silicon nitride, and the dielectric layer material includes silicon nitride.
15. The forming method as described in claim 1, characterized in that, In the step of forming the partition trench, a portion of the base thickness is removed so that the bottom of the partition trench is located within the base.