Semiconductor device and preparation method thereof
By avoiding ion doping of the second polysilicon layer during the fabrication process of semiconductor devices, a superimposed polysilicon gate structure is formed, which solves the problem of easy breakdown of the gate oxide layer and improves the reliability and insulation quality of the device.
Patent Information
- Application Number
- CN202511047279.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-28
- Publication Date
- 2025-11-04
AI Technical Summary
In the prior art, the gate oxide layer of vertical double-diffused metal oxide semiconductor devices is prone to breakdown under high-intensity electric fields, leading to device failure. This is mainly due to the impurity segregation phenomenon at the gate-insulating medium interface affecting the insulation quality.
During the fabrication process, a second polysilicon dielectric layer is deposited on the original first polysilicon dielectric layer, and ion doping of the second polysilicon layer is avoided during the etching process, forming a gate structure composed of the first polysilicon layer and the second polysilicon layer, reducing the impurity segregation effect at the heterogeneous interface and improving the interface quality of the insulating layer.
This effectively reduces the probability of semiconductor devices breaking down at the insulating layer, thus improving the reliability and stability of the devices.
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Figure CN120897478A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application belongs to the technical field of semiconductor, and particularly relates to a semiconductor device and a preparation method thereof. BACKGROUND
[0002] A semiconductor device represented by a vertical double-diffused metal oxide semiconductor (VDMOS) controls the opening or closing of a conductive channel inside the device by changing a gate voltage. The gate and the conductive channel are insulated by a gate oxide layer, and the gate and the source are also insulated by the gate oxide layer. The gate oxide layer is usually an insulating layer structure with a thickness of ten nanometers, which is directly exposed to a high-intensity gate-drain electric field.
[0003] Therefore, it is necessary to improve the quality of the gate oxide layer to avoid the permanent failure of the semiconductor device caused by the breakdown of the gate oxide layer. SUMMARY
[0004] The embodiments of the present application provide a semiconductor device and a preparation method thereof, which can alleviate the segregation phenomenon of the doping elements of the semiconductor device at the gate interface to improve the gate insulation quality and improve the reliability of the semiconductor device.
[0005] In a first aspect, the embodiments of the present application provide a preparation method of a semiconductor device, and the preparation method comprises the following steps.
[0006] forming an epitaxial layer on a substrate, and forming a well region of a second conductivity type and a source region of a first conductivity type on a side of the epitaxial layer away from the substrate by ion implantation, the well region comprising a channel region sandwiched between the source region and the epitaxial layer along a first direction;
[0007] forming a first insulating medium layer on the side of the epitaxial layer away from the substrate;
[0008] performing a patterning process on the first insulating medium layer to obtain a first insulating layer;
[0009] forming a first polysilicon medium layer on a side of the first insulating layer away from the substrate, and performing a first conductivity type doping on the first polysilicon medium layer;
[0010] forming a second polysilicon medium layer on a side of the first polysilicon medium layer away from the substrate;
[0011] performing a patterning process on the first polysilicon medium layer and the second polysilicon medium layer to obtain a first polysilicon layer and a second polysilicon layer, and a normal projection of the first polysilicon layer on the substrate covers at least a normal projection of the channel region on the substrate;
[0012] forming a second insulating layer on a side of the second polysilicon layer away from the substrate.
[0013] In some optional embodiments, the preparation method further comprises:
[0014] The second insulating layer and the second polysilicon layer are patterned to obtain a first via penetrating through the second insulating layer and the second polysilicon layer;
[0015] The gate bus is formed at least in the first via, and the gate bus forms an ohmic contact with the first polysilicon layer.
[0016] In some optional embodiments, the preparation method further comprises:
[0017] The second insulating layer is patterned to obtain a second via penetrating through the second insulating layer and the first insulating layer;
[0018] The source is formed at least in the second via, and a projection of the source on the substrate partially overlaps a projection of the source region on the substrate.
[0019] In some optional embodiments, the doping ions of the first polysilicon layer include boron ions.
[0020] In some optional embodiments, the patterning of the first insulating layer includes:
[0021] The first mask plate is provided, and an etching process is performed on the hollowed-out region of the first mask plate to obtain a second sub-part not subjected to etching and a first sub-part formed by etching;
[0022] A growth process is performed on the first insulating layer.
[0023] In a second aspect, the embodiments of the present application provide a semiconductor device, which is prepared by using the preparation method of the semiconductor device provided in any of the embodiments of the first aspect.
[0024] In a third aspect, the embodiments of the present application provide a semiconductor device, which includes a substrate, an epitaxial layer, a gate, a first insulating layer, a source, and a second insulating layer. The epitaxial layer is arranged on one side of the substrate along a thickness direction. The epitaxial layer has a well region and a source region on a side opposite to the substrate. The well region has a conductive type opposite to that of the epitaxial layer, and the source region has a conductive type same as that of the epitaxial layer. The gate includes a first polysilicon layer and a second polysilicon layer arranged in a stacking manner away from the substrate. The first polysilicon layer has a conductive type same as that of the well region. The first insulating layer is arranged between the first polysilicon layer and the epitaxial layer. The source is arranged on the side of the epitaxial layer opposite to the substrate and forms an ohmic contact with the source region. The second insulating layer is arranged between the gate and the source and covers at least a side of the second polysilicon layer opposite to the substrate.
[0025] In some optional embodiments, the semiconductor device further comprises a gate bus, which is disposed on the side of the first polysilicon layer away from the substrate and is in conductive connection with the first polysilicon layer.
[0026] In some optional embodiments, the first insulating layer comprises a first sub-portion and a second sub-portion, the second sub-portion is disposed between the first sub-portion and the gate bus along the first direction, and the dimension of the second sub-portion in the thickness direction is greater than the dimension of the first sub-portion in the thickness direction.
[0027] In some optional embodiments, the semiconductor device further comprises a regulating portion, which is disposed on the side of the second sub-portion away from the substrate, and the orthographic projection of the regulating portion on the substrate partially overlaps the orthographic projection of the well region on the substrate.
[0028] The preparation method of the semiconductor device of the embodiments of the present application deposits a second polysilicon dielectric layer on the original first polysilicon dielectric layer, and etches the first polysilicon dielectric layer and the second polysilicon dielectric layer together by means of the original mask to obtain a gate electrode formed by the superposition of the first polysilicon layer and the second polysilicon layer. The second polysilicon layer away from the substrate is not subjected to ion doping treatment, so as to avoid the impurity segregation effect at the heterojunction interface between the second polysilicon layer and the second insulating layer due to ion doping, improve the interface quality of the second insulating layer, reduce the probability of breakdown of the semiconductor device at the second insulating layer, and improve the reliability of the semiconductor device. BRIEF DESCRIPTION OF DRAWINGS
[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required to be used in the embodiments of the present application will be briefly introduced. Those skilled in the art can also obtain other drawings according to these drawings without creative labor.
[0030] Figure 1 It is a structural schematic diagram of a semiconductor device in the prior art;
[0031] Figures 2a to 2i It is a process schematic diagram of a preparation method of a semiconductor device of an embodiment of the present application;
[0032] Figure 3 It is a structural schematic diagram of a semiconductor device of an embodiment of the present application;
[0033] Figure 4 It is a sectional view schematic diagram of a gate bus of a semiconductor device of an embodiment of the present application.
[0034] The drawings are not necessarily drawn according to the actual scale.
[0035] Specific marker information in the drawings is as follows:
[0036] 100, drain;
[0037] 210, substrate; 220, epitaxial layer; 230, well region; 240, source region;
[0038] 300, first insulating medium layer; 310, first sub-part; 320, second sub-part;
[0039] 410, first polysilicon layer; 411, first polysilicon medium layer; 420, second polysilicon layer; 421, second polysilicon medium layer; 430, gate bus; 440, regulating part;
[0040] 500, second insulating layer; 501, first via; 502, second via;
[0041] 600, source electrode; 610, passivation layer;
[0042] First direction X; second direction Y; thickness direction Z. DETAILED DESCRIPTION
[0043] The embodiments of the technical scheme of the present application will be described in detail below with reference to the drawings. The following embodiments are only used to more clearly illustrate the technical scheme of the present application, and therefore only serve as examples, and cannot limit the protection scope of the present application.
[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present application; the terms "include" and "have" and any variations thereof in the specification and claims of the present application and the above description of drawings are intended to cover non-exclusive inclusion.
[0045] In the description of the embodiments of the present application, the technical terms "first", "second", etc. are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features. In the description of the embodiments of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly and specifically limited.
[0046] Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The appearance of the phrase in various places in the specification does not necessarily all refer to the same embodiment, nor is it necessarily independent or alternative to other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.
[0047] In the description of the embodiments of the present application, the term "and / or" is merely an association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the three cases of A alone, A and B together, and B alone. In addition, the character " / " in this paper generally represents that the front and rear associated objects are in an "or" relationship.
[0048] In the description of the embodiments of the present application, the term "a plurality of" means two or more (including two), and similarly, "a plurality of groups" means two or more groups (including two groups), and "a plurality of pieces" means two or more pieces (including two pieces).
[0049] In the description of the embodiments of the present application, the technical terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, which is only for the convenience of describing the embodiments of the present application and simplifying the description, and does not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the embodiments of the present application.
[0050] In the description of the embodiments of the present application, unless otherwise explicitly specified and limited, the technical terms "mounting", "connection", "connection", "fixing" and the like should be understood in a broad sense, for example, it can be fixedly connected, or it can be detachably connected, or it can be integrated; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the embodiments of the present application can be understood according to the specific circumstances.
[0051] With the continuous development of power electronic systems towards high frequency and high voltage, semiconductor devices are more and more widely used as switching control devices, becoming the key execution unit of power electronic systems.
[0052] Please refer to Figure 1 Taking a vertical double-diffused metal oxide semiconductor (VDMOS) as an example, the VDMOS adopts a vertical conduction structure, and the switching of the channel is controlled by the gate electrode below the source metal to realize the switching control function of the device. Among them, an insulating medium is provided between the gate and the source metal to prevent short circuit between the gate and the source, which can cause the device to fail.
[0053] In the related art, the partial gate uses the same doping polycrystalline silicon as the conductivity type of the well region to realize the modulation of the threshold voltage and the improvement of the stability of the gate. However, the concentration of impurities in the materials on both sides of the interface is different, and there is a segregation phenomenon of impurities at the interface between the gate polycrystalline silicon and the insulating medium, which negatively affects the quality of the insulating medium, thereby reducing the reliability of the VDMOS device.
[0054] To solve the problems in the prior art, the embodiments of the present application provide a semiconductor device and a preparation method thereof, which can improve the segregation effect at the interface between the gate and the insulating medium to improve the quality of the insulating medium, and further improve the reliability of the semiconductor device. First, the semiconductor device provided by the embodiments of the present application will be introduced.
[0055] In a first aspect, referring to Figures 2a to 2i The embodiments of the present application provide a preparation method of a semiconductor device, the preparation method comprising:
[0056] S100, forming an epitaxial layer 220 on a substrate 210, and forming a well region 230 of a second conductivity type and a source region 240 of a first conductivity type on a side of the epitaxial layer 220 away from the substrate 210 by ion implantation, the well region 230 comprising a channel region sandwiched between the source region 240 and the epitaxial layer 220 along a first direction;
[0057] S210, forming a first insulating medium layer 300 on a side of the epitaxial layer 220 away from the substrate 210;
[0058] S220, patterning the first insulating medium layer 300 to obtain a first insulating layer;
[0059] S310, forming a first polycrystalline silicon medium layer 411 on a side of the first insulating layer away from the substrate 210, and doping the first polycrystalline silicon medium layer 411 with the first conductivity type;
[0060] S320, forming a second polycrystalline silicon medium layer 421 on a side of the first polycrystalline silicon medium layer 411 away from the substrate 210;
[0061] S330, patterning the first polycrystalline silicon medium layer 411 and the second polycrystalline silicon medium layer 421 to obtain a first polycrystalline silicon layer 410 and a second polycrystalline silicon layer 420, and the orthographic projection of the first polycrystalline silicon layer 410 on the substrate 210 at least covers the orthographic projection of the channel region on the substrate 210;
[0062] S400, forming a second insulating layer 500 on a side of the second polycrystalline silicon layer 420 away from the substrate 210.
[0063] Optionally, in step S310, the first polycrystalline silicon medium layer 411 is doped with the first conductivity type by ion implantation or diffusion process.
[0064] Optionally, in step S310, the polycrystalline silicon is prepared after pre-doping to directly form the first polycrystalline silicon dielectric layer 411 of the first conductivity type.
[0065] Optionally, in step S310, the first polycrystalline silicon dielectric layer 411 is prepared by a chemical vapor deposition process.
[0066] Optionally, in step S310, the first polycrystalline silicon dielectric layer 411 is prepared by a crystallization process.
[0067] Optionally, in step S320, the second polycrystalline silicon dielectric layer 421 is prepared by a chemical vapor deposition process.
[0068] Optionally, in step S320, the second polycrystalline silicon dielectric layer 421 is prepared by a crystallization process.
[0069] Optionally, in step S330, the first polycrystalline silicon dielectric layer 411 and the second polycrystalline silicon dielectric layer 421 are patterned by an etching process. Illustratively, the etching process includes at least one of dry etching, wet etching, electrochemical etching, and laser etching.
[0070] According to the preparation method of the semiconductor device provided by the first aspect of the present application, a second polycrystalline silicon dielectric layer 421 is deposited on the original first polycrystalline silicon dielectric layer 411, and the first polycrystalline silicon dielectric layer 411 and the second polycrystalline silicon dielectric layer 421 are etched together by means of the original mask to obtain a gate formed by the superposition of the first polycrystalline silicon layer 410 and the second polycrystalline silicon layer 420. The second polycrystalline silicon layer 420 facing the substrate 210 is not subjected to ion doping treatment, so as to avoid the occurrence of impurity segregation effect at the heterojunction interface between the second polycrystalline silicon layer 420 and the second insulating layer 500 due to ion doping, improve the interface quality of the second insulating layer 500, reduce the probability of breakdown of the semiconductor device at the second insulating layer 500, and improve the reliability of the semiconductor device.
[0071] It can be understood that the formation of the second polycrystalline silicon dielectric layer 421 does not need to rely on the mask, and the formation of the second polycrystalline silicon layer can rely on the mask of the first polycrystalline silicon layer and be prepared synchronously in the same etching process. Therefore, the addition of the second polycrystalline silicon layer does not need to change the pattern of the mask or increase the number of photolithography, which facilitates the process improvement of the existing production line, and realizes the improvement of the reliability of the semiconductor device at a lower cost.
[0072] According to some embodiments of the first aspect of the present application, step S310 includes:
[0073] S311, forming a first sub-layer on the side of the first insulating layer facing away from the substrate 210, and doping the first sub-layer with the first conductivity type. S312, forming a second sub-layer on the first sub-layer, and doping the second sub-layer with the second conductivity type.
[0074] S312, forming a second sub-layer on the side of the first sub-layer away from the substrate 210, and doping the second sub-layer with the first conductive type.
[0075] Optionally, the ion doping concentration of the second sub-layer is less than or equal to the ion doping concentration of the first sub-layer.
[0076] According to some embodiments of the first aspect of the present application, the preparation method further comprises:
[0077] S511, performing a patterning process on the second insulating layer 500 and the second polysilicon layer 420 to obtain a first via hole 501 penetrating through the second insulating layer 500 and the second polysilicon layer 420;
[0078] S512, forming a gate bus 430 in at least the first via hole 501, the gate bus 430 forming an ohmic contact with the first polysilicon layer 410.
[0079] Optionally, in step S512, the gate bus 430 is made of a metal material capable of forming an ohmic contact with the first polysilicon layer 410.
[0080] Thus, the gate bus 430 can form a better conductive connection with the first polysilicon layer 410 to control the gate potential of the semiconductor device.
[0081] According to some embodiments of the first aspect of the present application, the preparation method further comprises:
[0082] S521, performing a patterning process on the second insulating layer 500 to obtain a second via hole 502 penetrating through the second insulating layer 500 and the first insulating layer;
[0083] S522, forming a source electrode 600 in at least the second via hole 502, the orthographic projection of the source electrode 600 on the substrate 210 partially overlapping the orthographic projection of the source region 240 on the substrate 210.
[0084] Thus, the conductive connection between the source electrode 600 and the source region 240 is realized.
[0085] Optionally, the preparation method further comprises:
[0086] S523, forming a passivation layer 610 on the side of the source electrode 600 away from the substrate.
[0087] Optionally, the passivation layer 610 comprises silicon dioxide.
[0088] According to some embodiments of the first aspect of the present application, the first conductive type is P-type.
[0089] Optionally, the doping ions of the first polysilicon dielectric layer 411 comprise boron ions.
[0090] Therefore, the segregation effect of the hole type doping impurities forms a better alleviation effect, and the quality of the second insulating layer 500 is further improved.
[0091] According to some embodiments of the first aspect of the application, step S220 comprises:
[0092] S221A, a first mask is set, and an etching process is performed on the hollow area of the first mask to obtain the second sub-part 320 without etching and the first sub-part 310 formed by etching;
[0093] S222A, a growth process is performed on the first insulating medium layer 300.
[0094] It can be understood that in step S222A, the growth process is performed on the first sub-part 310 and the second sub-part 320 obtained after etching.
[0095] Optionally, in step S222A, the growth process is thermal oxidation growth.
[0096] According to some embodiments of the first aspect of the application, step S220 comprises:
[0097] S221B, a growth process is performed on the first insulating medium layer 300;
[0098] S222B, a first mask is set, and an etching process is performed on the hollow area of the first mask to obtain the second sub-part 320 without etching and the first sub-part 310 formed by etching.
[0099] It can be understood that in step S221B, the growth process is performed on the entire first insulating medium layer 300.
[0100] Optionally, in step S221B, the growth process is thermal oxidation growth or low-temperature oxidation growth.
[0101] In a second aspect, the embodiments of the application provide a semiconductor device, which is prepared by the preparation method of the semiconductor device provided in any one of the embodiments of the first aspect.
[0102] It can be understood that the semiconductor device has all the beneficial effects of the preparation method provided in any one of the embodiments of the first aspect.
[0103] In a third aspect, please refer to Figure 3The embodiment of the present application provides a semiconductor device, which comprises a substrate 210, an epitaxial layer 220, a gate, a first insulating layer, a source 600 and a second insulating layer 500, the epitaxial layer 220 is arranged on one side of the substrate 210 along a thickness direction, one side of the epitaxial layer 220 away from the substrate 210 is provided with a well region 230 and a source region 240, the well region 230 is opposite to the conductive type of the epitaxial layer 220, and the source region 240 is the same as the conductive type of the epitaxial layer 220; the gate comprises a first polysilicon layer 410 and a second polysilicon layer 420 which are arranged in a stacking manner away from the substrate 210, the first polysilicon layer 410 is the same as the conductive type of the well region 230; the first insulating layer is arranged between the first polysilicon layer 410 and the epitaxial layer 220; the source 600 is arranged on one side of the epitaxial layer 220 away from the substrate 210 and forms an ohmic contact with the source region 240; the second insulating layer 500 is arranged between the gate and the source 600, and the second insulating layer 500 covers at least one side of the second polysilicon layer 420 away from the substrate 210.
[0104] Optionally, the first insulating layer comprises silicon dioxide.
[0105] Optionally, the second insulating layer 500 comprises silicon dioxide.
[0106] It can be understood that the semiconductor device further comprises a passivation layer 610 arranged on one side of the source 600 away from the substrate 210, and the passivation layer 610 is used for protecting the source 600.
[0107] Therefore, the semiconductor device realizes the switching control of the channel in the well region 230 through the first polysilicon layer 410 which is the same as the conductive type of the well region 230, and prevents the impurities in the first polysilicon layer 410 from diffusing to the second insulating layer 500 through the second polysilicon layer 420 arranged between the first polysilicon layer 410 and the second insulating layer 500, thereby alleviating the segregation effect to improve the quality of the second insulating layer 500, and further improving the reliability of the semiconductor device.
[0108] According to some embodiments of the third aspect of the present application, the orthographic projection of the first polysilicon layer 410 on the substrate 210 falls within the orthographic projection range of the second polysilicon layer 420 on the substrate 210.
[0109] Optionally, the orthographic projection of the second polysilicon layer 420 on the substrate 210 is consistent with the orthographic projection range of the first polysilicon layer 410 on the substrate 210.
[0110] Optionally, the orthographic projection of the second polysilicon layer 420 on the substrate 210 covers the orthographic projection of the first polysilicon layer 410 on the substrate 210. Specifically, any edge line of the orthographic projection of the first polysilicon layer 410 on the substrate 210 falls within the orthographic projection range of the second polysilicon layer 420 on the substrate 210.
[0111] Optionally, the first polysilicon layer 410 and the second polysilicon layer 420 are prepared synchronously by an etching process.
[0112] Optionally, the second polysilicon layer 420 is prepared after the first polysilicon layer 410. Illustratively, the second polysilicon layer 420 is deposited into the epitaxial layer 220 where the first polysilicon layer 410 is formed, and the second polysilicon layer 420 covers the top wall and at least part of the sidewall of the first polysilicon layer 410.
[0113] Thus, the second polysilicon layer 420 can further suppress the possible segregation effect at the interface between the first polysilicon layer 410 and the second insulating layer 500, and reduce the probability of breakdown caused by defects of the semiconductor device at the second insulating layer 500.
[0114] According to some embodiments of the third aspect of the present application, the first polysilicon layer 410 includes a first sub-layer and a second sub-layer stacked in a direction away from the substrate 210, and the second polysilicon layer 420 is disposed on a side of the second sub-layer away from the substrate 210.
[0115] In other words, no matter whether the first polysilicon layer 410 is a single-layer structure or a multi-layer structure, the first polysilicon layer 410 is at least separated from the second insulating layer 500 in the thickness direction by the second polysilicon layer 420 to suppress the possible segregation effect at the hetero-interface.
[0116] According to some embodiments of the third aspect of the present application, referring to Figure 4 , the semiconductor device further includes a gate bus line 430 disposed on a side of the first polysilicon layer 410 away from the substrate 210 and conductively connected with the first polysilicon layer 410.
[0117] Specifically, the semiconductor device has a cell region, a terminal region, and a gate bus line region, and the terminal region is located between the cell region and the gate bus line region. It can be understood that the gate bus line 430 is located in the gate bus line region. The gate bus line 430 is conductively connected with a plurality of gate electrodes in the cell region to keep the synchronization of opening or closing of each cell in the semiconductor device.
[0118] According to some embodiments of the third aspect of the present application, the first insulating layer includes a first sub-portion 310 and a second sub-portion 320, and the second sub-portion 320 is disposed between the first sub-portion 310 and the gate bus line 430 in the first direction, and the size of the second sub-portion 320 in the thickness direction is greater than the size of the first sub-portion 310 in the thickness direction.
[0119] Optionally, at least part of the first sub-portion 310 is located in the cell region.
[0120] Optionally, at least part of the second sub-portion 320 is located in the gate bus line region.
[0121] Optionally, the terminal region includes the partial first sub-region 310 and the partial second sub-region 320.
[0122] According to some embodiments of the third aspect of the present application, the semiconductor further includes a regulation portion 440, which is disposed on a side of the second sub-region 320 away from the substrate 210, and a projection of the regulation portion 440 on the substrate 210 partially overlaps with a projection of the well region 230 on the substrate 210.
[0123] Optionally, the regulation portion 440 is made of the same material as the second polysilicon layer 420.
[0124] Further optionally, the regulation portion 440 is prepared synchronously with the second polysilicon layer 420 through a patterning process.
[0125] Optionally, the regulation portion 440 is located in the terminal region.
[0126] It can be understood that a side of the regulation portion 440 away from the substrate 210 is covered with the passivation layer 610.
[0127] Optionally, the regulation portion 440 and the passivation layer 610 further form the first polysilicon layer 410 therebetween.
[0128] In the fourth aspect, the embodiments of the present application further provide an electronic device, which includes the semiconductor device prepared by the preparation method of the semiconductor device provided in any one of the embodiments of the first aspect, or the electronic device includes the semiconductor device provided in any one of the embodiments of the third aspect.
[0129] It can be understood that the electronic device has all the beneficial effects of the preparation method provided in any one of the embodiments of the first aspect, or the electronic device has all the beneficial effects of the semiconductor device provided in any one of the embodiments of the third aspect.
[0130] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, but not limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application, and they should be covered in the scope of the claims and the specification of the present application. Especially, as long as there is no structural conflict, each technical feature mentioned in the embodiments can be combined in any way. The present application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.
Claims
1. A method for fabricating a semiconductor device, characterized in that, include: An epitaxial layer is formed on a substrate, and a well region of a second conductivity type and a source region of a first conductivity type are formed on the side of the epitaxial layer facing away from the substrate by ion implantation. The well region includes a channel region sandwiched between the source region and the epitaxial layer along a first direction. A first insulating dielectric layer is formed on the side of the epitaxial layer facing away from the substrate; The first insulating layer is obtained by patterning the first insulating dielectric layer; A first polysilicon dielectric layer is formed on the side of the first insulating layer facing away from the substrate, and the first polysilicon dielectric layer is doped with a first conductivity type. A second polysilicon dielectric layer is formed on the side of the first polysilicon dielectric layer facing away from the substrate; The first polysilicon dielectric layer and the second polysilicon dielectric layer are patterned to obtain the first polysilicon layer and the second polysilicon layer, wherein the orthogonal projection of the first polysilicon layer on the substrate at least covers the orthogonal projection of the channel region on the substrate. A second insulating layer is formed on the side of the second polysilicon layer facing away from the substrate.
2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The preparation method further includes: A first via is obtained by patterning the second insulating layer and the second polysilicon layer; A gate bus is formed at least within the first via, and the gate bus forms an ohmic contact with the first polysilicon layer.
3. The method for fabricating a semiconductor device according to claim 2, characterized in that, The preparation method further includes: Patterning the second insulating layer yields a second via that connects the second insulating layer and the first insulating layer; A source electrode is formed at least within the second via, and the orthogonal projection of the source electrode onto the substrate partially overlaps with the orthogonal projection of the source region onto the substrate.
4. The method for fabricating a semiconductor device according to claim 1, characterized in that, The doping ions in the first polycrystalline silicon dielectric layer include boron ions.
5. The method for fabricating a semiconductor device according to claim 1, characterized in that, The process of patterning the first insulating dielectric layer to obtain the first insulating layer includes: Set up a first mask, and perform an etching process on the hollow area of the first mask to obtain an unetched second sub-part and an etched first sub-part; A growth process is performed on the first insulating dielectric layer.
6. A semiconductor device, characterized in that, It is prepared by the method of preparing a semiconductor device as described in any one of claims 1 to 5.
7. A semiconductor device, characterized in that, include: Substrate; An epitaxial layer is disposed on one side of the substrate along the thickness direction. A well region and a source region are provided on the side of the epitaxial layer facing away from the substrate. The conductivity type of the well region is opposite to that of the epitaxial layer, and the conductivity type of the source region is the same as that of the epitaxial layer. The gate includes a first polysilicon layer and a second polysilicon layer stacked along a direction away from the substrate, wherein the first polysilicon layer has the same conductivity type as the well region; A first insulating layer is sandwiched between the first polysilicon layer and the epitaxial layer; The source electrode is disposed on the side of the epitaxial layer facing away from the substrate and forms an ohmic contact with the source region; A second insulating layer is sandwiched between the gate and the source, and the second insulating layer at least covers the side of the second polysilicon layer facing away from the substrate.
8. The semiconductor device according to claim 7, characterized in that, The semiconductor device further includes a gate bus, which is disposed on the side of the first polysilicon layer away from the substrate and is electrically connected to the first polysilicon layer.
9. The semiconductor device according to claim 8, characterized in that, The first insulating layer includes a first sub-part and a second sub-part, the second sub-part being disposed between the first sub-part and the gate bus along a first direction, and the second sub-part having a larger dimension in the thickness direction than the first sub-part having a larger dimension in the thickness direction.
10. The semiconductor device according to claim 9, characterized in that, The semiconductor further includes a control section disposed on the side of the second sub-section facing away from the substrate, wherein the orthogonal projection of the control section on the substrate partially overlaps with the orthogonal projection of the well region on the substrate.