Semiconductor device and method of manufacturing the same

Abstract

The embodiment of the invention relates to a semiconductor device and a manufacturing method thereof. According to one embodiment, a semiconductor device includes: a semiconductor portion including a first semiconductor layer, a second semiconductor layer provided on the first semiconductor layer, and a third semiconductor layer provided in a first trench of the second semiconductor layer; the first electrode is arranged on the back surface of the first semiconductor layer; a first metal film in contact with the second semiconductor layer in the first trench; a second metal film in contact with the third semiconductor layer and the first metal film in the first trench; and a second electrode in contact with the second metal film in the first trench. The first metal film includes a high work function metal, and the second metal film includes a low work function metal having a lower work function than the first metal film.

Description

[0001] Related applications

[0002] This application enjoys priority based on Japanese Patent Application No. 2024-065551 (filed on April 15, 2024). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to semiconductor devices and methods for manufacturing the same. Background Technology

[0004] In semiconductor devices such as MOSFETs with trench gates, there is a known structure that uses trench contacts to electrically connect the source electrode to the semiconductor layer.

[0005] In semiconductor devices with trench contact structures as described above, it is necessary to reduce contact resistance in order to reduce on-resistance. Summary of the Invention

[0006] One embodiment of a semiconductor device includes: a semiconductor section having a first semiconductor layer, a second semiconductor layer disposed on the first semiconductor layer, and a third semiconductor layer disposed in a first trench of the second semiconductor layer; a first electrode disposed on the back side of the first semiconductor layer; a first metal film in contact with the second semiconductor layer in the first trench; a second metal film in contact with the third semiconductor layer and the first metal film in the first trench; and a second electrode in contact with the second metal film in the first trench. The first metal film comprises a high work function metal, and the second metal film comprises a low work function metal with a lower work function than the first metal film.

[0007] According to one embodiment of the present invention, a semiconductor device and a method thereof capable of reducing contact resistance can be provided. Attached Figure Description

[0008] Figure 1 This is a cross-sectional view of the semiconductor device according to the first embodiment.

[0009] Figure 2 It is a cross-sectional view used to illustrate the process of forming the gate electrode, the third electrode, and the insulating film in the second trench.

[0010] Figure 3 This is a cross-sectional view used to illustrate the process of forming a first trench in the second semiconductor layer.

[0011] Figure 4 This is a cross-sectional view used to illustrate the process of forming a PSG film on the inner surface of the first trench.

[0012] Figure 5 This is a cross-sectional view used to illustrate the process of forming the third semiconductor layer.

[0013] Figure 6 This is a cross-sectional view used to illustrate the process of removing the PSG membrane.

[0014] Figure 7 This is a cross-sectional view used to illustrate the process of etching the first trench to a deeper location.

[0015] Figure 8 This is a cross-sectional view used to illustrate the process of forming a first metal film on the inner surface of the first trench.

[0016] Figure 9 This is a cross-sectional view used to illustrate the process of embedding an insulating film in the first trench.

[0017] Figure 10 This is a cross-sectional view used to illustrate the process of etching back the insulating film.

[0018] Figure 11 This is a cross-sectional view used to illustrate the process of removing a portion of the first metal film.

[0019] Figure 12 This is a cross-sectional view used to illustrate the process of removing the insulating film.

[0020] Figure 13 This is a cross-sectional view used to illustrate the process of forming the second metal film 60 and the third semiconductor layer containing silicide.

[0021] Figure 14 This is a cross-sectional view used to illustrate the process of embedding the third electrode into the first trench.

[0022] Figure 15 This is a cross-sectional view of a comparative example semiconductor device.

[0023] Figure 16 This is a cross-sectional view of the semiconductor device according to the second embodiment.

[0024] Figure 17 This is a cross-sectional view used to illustrate the process of forming a first metal film in a first trench.

[0025] Figure 18 This is a cross-sectional view used to illustrate the process of etching back the first metal film.

[0026] Figure 19 This is a cross-sectional view used to illustrate the process of forming the second metal film.

[0027] Figure 20 This is a cross-sectional view used to illustrate the process of forming a third semiconductor layer containing silicide.

[0028] Figure 21 This is a cross-sectional view used to illustrate the process of embedding the third electrode into the first trench. Detailed Implementation

[0029] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. These embodiments are not intended to limit the present invention.

[0030] (First Implementation)

[0031] Figure 1 This is a cross-sectional view of the semiconductor device according to the first embodiment. In the following description, the X-axis, Y-axis, and Z-axis shown in each figure are sometimes used to describe the arrangement and structure of the various parts of the semiconductor device. The X-axis, Y-axis, and Z-axis are orthogonal to each other and represent the X direction, Y direction, and Z direction, respectively. In addition, sometimes the Z direction is described as the top and its opposite direction as the bottom. In this embodiment, the X direction and Y direction correspond to the first direction and the third direction, respectively, representing in-plane directions parallel to the surface (or back surface) of the semiconductor device 1. The Z direction corresponds to the second direction, representing an out-of-plane direction orthogonal to the surface (or back surface) of the semiconductor device 1.

[0032] In addition, p, p + The statement indicates that the concentration of p-type impurities increases in this order. Furthermore, n... - n, n + The statement refers to the fact that the concentration of n-type impurities increases in this order.

[0033] Impurity concentration can be determined, for example, by SIMS (Secondary Ion Mass Spectrometry). Furthermore, the relative level of impurity concentration can be determined, for example, by the level of carrier concentration obtained through SCM (Scanning Capacitance Microscopy). Additionally, distances such as the depth of the semiconductor region can be determined, for example, by SIMS.

[0034] Figure 1 The semiconductor device 1 shown is a Schottky-type low-voltage MOSFET. The semiconductor device 1 includes a semiconductor section 10, a first electrode 20, a second electrode 30, a gate electrode 40, a third electrode 41, a first metal film 50, and a second metal film 60.

[0035] The semiconductor section 10 is made of, for example, silicon. A first electrode 20 is provided on the back side of the semiconductor section 10, and a second electrode 30 is provided on the surface of the semiconductor section 10. The first electrode 20 is the drain electrode. The second electrode 30 is the source electrode. The first electrode 20 is formed, for example, of a metallic material including nickel (Ni) and aluminum (Al). On the other hand, the second electrode 30 is formed, for example, of a metallic material including tungsten (W) and aluminum (Al).

[0036] The semiconductor section 10 includes a first semiconductor layer 11, a second semiconductor layer 12, and a third semiconductor layer 13. Each semiconductor layer has an n-type conductivity. The following describes each semiconductor layer.

[0037] The first semiconductor layer 11 is n + The first semiconductor layer 11 has a back surface that contacts the first electrode 20. The second semiconductor layer 12 has a surface that contacts the first semiconductor layer 11.

[0038] The second semiconductor layer 12 is n - The second semiconductor layer 12 contains a lower concentration of n-type impurities than the first semiconductor layer 11. A third semiconductor layer 13, a first trench TR1, a second trench TR2, a first metal film 50, and a second metal film 60 are disposed within the second semiconductor layer 12.

[0039] The third semiconductor layer 13 is n + The third semiconductor layer 13 contains a higher concentration of n-type impurities than the second semiconductor layer 12. Furthermore, the third semiconductor layer 13 contains silicide. In this embodiment, titanium silicide (TiSi) is contained in the third semiconductor layer 13. However, the silicide contained in the third semiconductor layer 13 is not limited to titanium silicide. The third semiconductor layer 13 is in contact with the second metal film 60.

[0040] The first trench TR1 is a so-called contact trench. In this embodiment, the first trench TR1 is disposed between two second trenches TR2 arranged along the X direction. The depth of the first trench TR1 from the surface of the semiconductor portion 10 is less than the depth of the second trenches TR2 from the surface of the semiconductor portion 10. A third semiconductor layer 13, a first metal film 50, a second metal film 60, and a second electrode 30 are disposed in the first trench TR1.

[0041] The first metal film 50 is in contact with the second semiconductor layer 12 at the lower part of the first trench TR1. The material of the first metal film 50 is a high work function metal. In this embodiment, the first metal film 50 is formed of platinum (Pt). However, the material of the first metal film 50 is not limited to platinum, and can also be other high work function metals such as Ni and Co.

[0042] The second metal film 60 extends from the upper part to the lower part of the first trench TR1. Similarly, the second electrode 30 also extends from the upper part to the lower part of the first trench TR1. Therefore, at the lower part of the first trench TR1, the second metal film 60 is located between the first metal film 50 and the second electrode 30. Furthermore, the second metal film 60 is located on the side of the first trench TR1 between the third semiconductor layer 13 and the second electrode 30.

[0043] The second metal film 60 has, for example, a two-layer structure, comprising a metal layer and a barrier metal layer. The metal layer is in contact with the first metal film 50 and the third semiconductor layer 13. The barrier metal layer is stacked on top of the metal layer. The material of the metal layer is, for example, titanium (Ti). On the other hand, the material of the barrier metal layer is titanium nitride (TiN). However, the materials of the metal layer and the barrier metal layer are not limited to titanium and titanium nitride; any metal with a low work function lower than that of the first metal film 50 is acceptable.

[0044] A gate electrode 40, a third electrode 41, and an insulating film 42 are disposed in the second trench TR2. The internal structure of the second trench TR2 will be described below.

[0045] The gate electrode 40 and the third electrode 41 are separately configured in the Z direction. Specifically, the gate electrode 40 is disposed on the upper part of the second trench TR2, and the third electrode 41 is disposed on the lower part of the second trench TR2.

[0046] The third electrode 41 is the so-called field plate. The third electrode 41 is electrically connected to the second electrode 30. The third electrode 41 is electrically insulated from the gate electrode 40 by an insulating film 42. The insulating film 42 is, for example, a silicon oxide film (SiO2).

[0047] In addition, the insulating film 42 also functions as a gate insulating film to electrically insulate the gate electrode 40 from the semiconductor section 10. The second semiconductor layer 12 is positioned opposite the gate electrode 40 across the gate insulating film. The third semiconductor layer 13 is in contact with the gate insulating film.

[0048] Here, refer to Figures 2 to 14 The manufacturing method of the semiconductor device 1 according to this embodiment will be described. Here, the main manufacturing steps will be described.

[0049] First, such as Figure 2 As shown, a second trench TR2 is formed in a second semiconductor layer 12 stacked on the first semiconductor layer 11, and a gate electrode 40, a third electrode 41, and an insulating film 42 are formed in the second trench TR2. The gate electrode 40 and the third electrode 41 are formed, for example, using polysilicon.

[0050] Next, as Figure 3 As shown, a first trench TR1 is formed in the second semiconductor layer 12. The first trench TR1 is formed, for example, by RIE (Reactive Ion Etching). However, in this process, the formation of the first trench TR1 is interrupted at the moment when the depth for forming the third semiconductor layer 13 is reached, in other words, at the same height level as the upper surface of the gate electrode 40.

[0051] Next, as Figure 4As shown, a PSG (Phosphorous Silicate Glass) film 70 is formed on the inner surface of the first trench TR1. The PSG film 70 can be formed, for example, by CVD (Chemical Vapor Deposition).

[0052] Next, the PSG film 70 is subjected to heat treatment. Through this heat treatment, the n-type impurities contained in the PSG film 70 thermally diffuse into the second semiconductor layer 12. The result is as follows: Figure 5 As shown, the third semiconductor layer 131 is formed on the inner surface of the first trench TR1, which is in contact with the PSG film 70.

[0053] Next, as Figure 6 As shown, the PSG film 70 is removed. As a result, the third semiconductor layer 131 is exposed. Furthermore, the method for forming the third semiconductor layer 131 is not limited to thermal diffusion from the PSG film 70 described above. The third semiconductor layer 131 can also be formed, for example, by ion implantation of n-type impurities into the second semiconductor layer 12.

[0054] Next, as Figure 7 As shown, for example, the first trench TR1 is etched to a deeper location via RIE. In this process, the depth of the first trench TR1 reaches the depth to which the first metal film 50 is formed, in other words, it reaches the same height level as the bottom surface of the gate electrode 40.

[0055] Next, as Figure 8 As shown, a first metal film 50 is formed on the inner surface of the first trench TR1. At this time, the third semiconductor layer 131 is covered by the first metal film 50.

[0056] Next, as Figure 9 As shown, an insulating film 80 is embedded within the first trench TR1. The insulating film 80 is formed, for example, using silicon nitride or TEOS (Tetra Ethoxy Silane). The insulating film 80 is preferably formed by a low-temperature film formation method, such as plasma CVD, plasma ALD (Atomic Layer Deposition), or SOG (Spin On Glass). By using these film formation methods, the formation of platinum silicide (PtSi) into the third semiconductor layer 131 can be avoided.

[0057] Next, as Figure 10 As shown, the insulating film 80 is etched back. In this process, the insulating film 80 is etched back in such a way that the upper surface of the insulating film 80 in the first trench TR1 is at the same height as the bottom surface of the third semiconductor layer 131.

[0058] Next, as Figure 11 As shown, the portion of the first metal film 50 formed on the side of the first trench TR1 is removed; in other words, the portion that is not in contact with the insulating film 80 is removed. The first metal film 50 is etched, for example, using a solution such as aqua regia.

[0059] Next, as Figure 12 As shown, the insulating film 80 is removed. This exposes the first metal film 50.

[0060] Next, as Figure 13 As shown, a second metal film 60 is formed such that a third semiconductor layer 131 and a first metal film 50 are covered within a first trench TR1. Next, a third semiconductor layer 13 containing silicide is formed by heat-treating the second metal film 60.

[0061] Finally, as Figure 14 As shown, the second electrode 30 is embedded in the first trench TR1. In addition, outside of this process, the first electrode 20 is formed on the back side of the first semiconductor layer 11.

[0062] Here, a comparative example that is compared with this embodiment will be described.

[0063] Figure 15 This is a cross-sectional view of a comparative example semiconductor device. Figure 15 In this drawing, the same reference numerals are used to mark the same components as those in the semiconductor device 1 described above, and repeated descriptions are omitted.

[0064] In the semiconductor device 100 of this comparative example, a first metal film 50 containing a high work function metal is sandwiched between the third semiconductor layer 131 and the second metal film 60. That is, a Schottky bond is formed between the upper mesa region, which is the contact area between the third semiconductor layer 131 and the first metal film 50, and the lower mesa region, which is the contact area between the first metal film 50 and the second semiconductor layer 12.

[0065] In the semiconductor device 100 having the structure described above, as the n-type impurity concentration of the third semiconductor layer 131 increases, the contact resistance decreases. However, as... Figure 15 As shown, the third semiconductor layer 131 is formed to be thinner than the sidewalls of the first trench TR1. Therefore, the process of locally implanting a high concentration of n-type impurities into the third semiconductor layer 131 is difficult.

[0066] Therefore, in this embodiment, the third semiconductor layer 13 is in contact with the second metal film 60, which contains a metal with a low work function. As a result, an ohmic bond is formed between the third semiconductor layer 13 and the second metal film 60 in the upper mesa region, and a Schottky bond is formed between the first metal film 50, which contains a metal with a high work function, and the second semiconductor layer 12 in the lower mesa region.

[0067] Therefore, according to this embodiment, the contact resistance can be reduced by a method other than increasing the n-type impurity concentration of the third semiconductor layer 131.

[0068] Furthermore, if a third semiconductor layer 131 containing a high concentration of n-type impurities is formed by thermal diffusion of the PSG film 70 as in this embodiment, then a local ion implantation process is not required.

[0069] (Second Implementation)

[0070] Figure 16 This is a cross-sectional view of the semiconductor device according to the second embodiment. Figure 16 In this drawing, the same reference numerals are used to denote the same components as those in the semiconductor device 1 of the first embodiment described above, and repeated descriptions are omitted. In the semiconductor device 1 of the first embodiment described above, the second metal film 60 and the second electrode 30 extend from the upper part to the lower part of the first trench TR1.

[0071] In contrast, in the semiconductor device 2 of the second embodiment, such as Figure 16 As shown, a first metal film 50 is embedded in the lower part of the first trench TR1. Therefore, the second metal film 60 and the second electrode 30 terminate in the upper part of the first trench TR1.

[0072] The following is for reference Figures 17-21 The manufacturing method of the semiconductor device 2 according to this embodiment will be described. Furthermore, the process up to the formation of the third semiconductor layer 131 by thermal diffusion through the PSG film 70 (see [reference]). Figures 2-7 The same as the first embodiment, therefore the description is omitted.

[0073] In this embodiment, after forming the third semiconductor layer 131 and etching the first trench TR1 to a deeper location, as... Figure 17 As shown, a first metal film 50 is formed in the first trench TR1. At this time, the first trench TR1 is filled with the first metal film 50.

[0074] Next, as Figure 18 As shown, the first metal film 50 is etched back. In this embodiment, the first metal film 50 is etched back in such a way that the upper surface of the first metal film 50 in the first trench TR1 is at the same height as the upper surface of the gate electrode 40.

[0075] Next, as Figure 19 As shown, the second metal film 60 is formed in such a way that the third semiconductor layer 131 and the first metal film 50 are covered in the first trench TR1.

[0076] Next, the second metal film 60 is heat-treated. Thus, as... Figure 20 As shown, a third semiconductor layer 13 containing silicide is formed.

[0077] Finally, as Figure 21 As shown, the second electrode 30 is embedded in the first trench TR1. In addition, outside of this process, the first electrode 20 is formed on the back side of the first semiconductor layer 11.

[0078] In this embodiment described above, similarly to the first embodiment, an ohmic bond is formed between the third semiconductor layer 13 and the second metal film 60 in the upper mesa region, and a Schottky bond is formed between the first metal film 50 and the second semiconductor layer 12 in the lower mesa region.

[0079] Therefore, according to this embodiment, similar to the first embodiment, the contact resistance can be reduced by a method other than increasing the n-type impurity concentration of the third semiconductor layer 131. Furthermore, in this embodiment, when the third semiconductor layer 131 containing a high concentration of n-type impurities is formed by thermal diffusion through the PSG film 70, a localized ion implantation process is not required.

[0080] Several embodiments of the present invention have been described, but these embodiments are given as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

[0081] [Explanation of Labels in the Attached Image]

[0082] 1, 2: Semiconductor devices

[0083] 10: Semiconductor Division

[0084] 11: First semiconductor layer

[0085] 12: Second semiconductor layer

[0086] 13: Third semiconductor layer

[0087] 20: First electrode

[0088] 30: Second electrode

[0089] 40: Gate electrode

[0090] 41: Third electrode

[0091] 42: Insulating film

[0092] 50: First metal film

[0093] 60: Second metal film

[0094] 70: PSG film

[0095] 131: Third semiconductor layer

[0096] TR1: First trench

[0097] TR2: Second trench

Claims

1. A semiconductor device comprising: The semiconductor section includes a first semiconductor layer, a second semiconductor layer disposed on the first semiconductor layer, and a third semiconductor layer disposed in a first trench of the second semiconductor layer; The first electrode is disposed on the back side of the first semiconductor layer; A first metal film is in contact with the second semiconductor layer in the first trench; The second metal film is in contact with the third semiconductor layer and the first metal film in the first trench; as well as The second electrode is in contact with the second metal film in the first trench. The first metal film contains a metal with a high work function. The second metal film contains a low work function metal that is lower than the work function of the first metal film.

2. The semiconductor device according to claim 1, wherein, The third semiconductor layer contains silicide.

3. The semiconductor device according to claim 1 or 2, wherein, The third semiconductor layer is disposed on the upper part of the first trench. The first metal film is disposed at the lower part of the first trench.

4. The semiconductor device according to claim 3, wherein, The first metal film and the second electrode extend from the upper part to the lower part of the first trench.

5. The semiconductor device according to claim 3, wherein, The first metal film and the second electrode terminate at the upper part of the first trench. The first metal film is embedded in the lower part of the first trench.

6. The semiconductor device according to claim 1 or 2, wherein, The first trench is disposed between two second trenches arranged in the second semiconductor layer. The second trench contains: a gate electrode, a third electrode electrically connected to the second electrode, and an insulating film electrically insulating the gate electrode from the second electrode.

7. The semiconductor device according to claim 2, wherein, The silicide is titanium silicide, the high work function metal is platinum, and the low work function metal is titanium.

8. The semiconductor device according to claim 1 or 2, wherein, The second semiconductor layer and the third semiconductor layer each contain n-type impurities, and the concentration of n-type impurities contained in the third semiconductor layer is higher than the concentration of n-type impurities contained in the second semiconductor layer.

9. A method for manufacturing a semiconductor device, A first trench is formed in a second semiconductor layer formed on top of the first semiconductor layer. A third semiconductor layer, a first metal film containing a high work function metal and in contact with the second semiconductor layer, and a second metal film containing a low work function metal that is in contact with the third semiconductor layer and the first metal film are sequentially formed in the first trench. A first electrode is formed on the back side of the first semiconductor layer, and a second electrode is formed in the first trench to contact the second metal film.

10. The method of manufacturing a semiconductor device according to claim 9, wherein, A phosphosilicate glass film, i.e., a PSG film, is formed on the inner surface of the first trench. The third semiconductor layer is formed by heat treatment of the PSG film.

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