Semiconductor device including oxide semiconductor and method of manufacturing same

Abstract

The invention relates to a semiconductor device including an oxide semiconductor and a method of manufacturing the same. The semiconductor device includes: a crystalline first oxide semiconductor pattern having at least one etched surface; and a crystallized second oxide semiconductor layer disposed on the etched surface of the first oxide semiconductor pattern. The method for manufacturing a semiconductor device includes: forming a crystalline first oxide semiconductor layer over a substrate; forming a first oxide semiconductor pattern having an etched side surface by selectively etching the first oxide semiconductor layer; and forming a crystallized second oxide semiconductor layer on a side surface of the first oxide semiconductor pattern.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0058432, filed on May 2, 2024, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present invention relate generally to semiconductor technology, and more specifically to semiconductor devices including oxide semiconductors and methods of manufacturing the same. Background Technology

[0004] Typically, amorphous silicon, or polycrystalline silicon, is primarily used as a semiconductor layer in semiconductor devices such as transistors. Amorphous silicon has the advantages of being relatively inexpensive and capable of ensuring uniform device characteristics through simple processes, but it has the disadvantage of low carrier mobility. Polycrystalline silicon can be obtained by crystallizing amorphous silicon and can have relatively high carrier mobility. However, a recrystallization process is required to form polycrystalline silicon, and it is difficult to ensure uniform device characteristics.

[0005] Recently, oxide semiconductors have been proposed as semiconductor materials that combine the advantages of polycrystalline silicon and amorphous silicon, namely high carrier mobility (an advantage of polycrystalline silicon) and uniform device characteristics (an advantage of amorphous silicon). Summary of the Invention

[0006] Embodiments of the present invention relate to a semiconductor device capable of compensating for etching damage in oxide semiconductors and a method for manufacturing the semiconductor device.

[0007] According to one embodiment of the present invention, a semiconductor device is provided, comprising: a first crystalline oxide semiconductor pattern having at least one etched surface; and a second crystalline oxide semiconductor layer disposed on the etched surface of the first oxide semiconductor pattern.

[0008] According to another embodiment of the present invention, a method for manufacturing a semiconductor device is provided, comprising: forming a crystalline first oxide semiconductor layer on a substrate; forming a first oxide semiconductor pattern having etched side surfaces by selectively etching the first oxide semiconductor layer; and forming a crystalline second oxide semiconductor layer on the side surfaces of the first oxide semiconductor pattern.

[0009] According to one embodiment of the present invention, a method for manufacturing a semiconductor device includes: providing a first oxide semiconductor pattern crystalline on a substrate; forming an etched surface by exposing at least a portion of the top surface of the first oxide semiconductor pattern to an etching process; and forming a second oxide semiconductor layer on the etched surface. Attached Figure Description

[0010] Figures 1A to 1C This is a cross-sectional view illustrating a semiconductor device and a method for manufacturing the same according to an embodiment of the present invention.

[0011] Figures 2A to 2F This is a cross-sectional view illustrating a semiconductor device and a method for manufacturing the same according to another embodiment of the present invention.

[0012] Figures 3A to 3C This is a cross-sectional view illustrating a semiconductor device and a method for manufacturing the same according to another embodiment of the present invention.

[0013] Figure 4 This is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.

[0014] Figure 5A and Figure 5B This is a cross-sectional view illustrating a semiconductor device and a method for manufacturing the same according to another embodiment of the present invention.

[0015] Figures 6A to 6C This is a cross-sectional view illustrating a semiconductor device and a method for manufacturing the same according to another embodiment of the present invention. Detailed Implementation

[0016] In the following, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0017] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Throughout this disclosure, the same reference numerals refer to the same portions in various figures and embodiments of the invention. The drawings are not necessarily drawn to scale, and in some cases, the scale may be enlarged to clearly illustrate the features of the embodiments. When a first layer is referred to as being “on” a second layer or “on” a substrate, it refers not only to the case where the first layer is formed directly on the second layer or substrate, but also to the case where a third layer exists between the first layer and the second layer or substrate.

[0018] Oxide semiconductors can be used as semiconductor elements (e.g., channels for transistors) in semiconductor devices. Oxide semiconductors can be exposed to etching processes used to pattern themselves or other constituent elements; therefore, at least a portion of the oxide semiconductor can have a surface exposed to the etching process (hereinafter referred to as the etched surface). Etching damage can occur on the etched surface of the oxide semiconductor. The term "etching damage" refers to a reduction in the thickness / width / volume of the oxide semiconductor caused by over-etching, etc., and / or surface irregularities formed on the etched surface. As the integration density of semiconductor devices increases, and therefore the size of the patterned oxide semiconductor decreases, etching damage can have various adverse effects on the characteristics of the semiconductor device. Furthermore, complex situations such as unexpected changes in the physical properties of the oxide semiconductor may occur. For example, impurities such as hydrogen ions can penetrate into the oxide semiconductor through the etched surface, thereby increasing oxygen vacancies in the oxide semiconductor. Methods for compensating for etching damage in oxide semiconductors and preventing / reducing hydrogen ion penetration into the oxide semiconductor will be described below.

[0019] Figures 1A to 1C This is a cross-sectional view illustrating a semiconductor device and a method for manufacturing the same according to an embodiment of the present invention. Figure 1C A semiconductor device according to an embodiment of the present invention is shown. Figure 1A and Figure 1B Manufacturing process is shown Figure 1C Intermediate processes for semiconductor devices.

[0020] First, a method for manufacturing semiconductor devices will be described.

[0021] See Figure 1A A first oxide semiconductor layer 10 can be provided. The first oxide semiconductor layer 10 may include an oxide of at least one metal. The at least one metal may be selected from group 12, 13, or 14 metals. Examples of these metals include zinc (Zn), indium (In), gallium (Ga), tin (Sn), cadmium (Cd), germanium (Ge), hafnium (Hf), etc. For example, the first oxide semiconductor layer 10 may include a variety of oxide semiconductors, such as indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), zinc tin oxide (ZTO), gallium indium oxide (IGO), etc. The first oxide semiconductor layer 10 may be formed by a variety of deposition methods. The first oxide semiconductor layer 10 may be in a crystalline state.

[0022] Exposed to subsequent etching processes and Figure 1B The surface of the first oxide semiconductor layer 10 described herein may be simply referred to as the first surface 10S.

[0023] See Figure 1BThe first surface 10S of the first oxide semiconductor layer 10 can be exposed to an etching process to form a first oxide semiconductor pattern 10A having an etched surface ES. The first oxide semiconductor pattern 10A can refer to the first oxide semiconductor layer 10 exposed to the etching process, and the etched surface ES can refer to the first surface 10S exposed to the etching process. The etching process can include dry etching, wet etching, or a combination thereof. Various etching damages may occur on the etched surface ES of the first oxide semiconductor pattern 10A.

[0024] For example, due to over-etching of the first oxide semiconductor layer 10, the etched surface ES of the oxide semiconductor pattern 10A may be more recessed than the first surface 10S of the first oxide semiconductor layer 10. Therefore, the thickness T2 of the first oxide semiconductor pattern 10A can be reduced compared to the thickness T1 of the first oxide semiconductor layer 10. In some cases, the first oxide semiconductor layer 10 may have little or no over-etching, in which case the thickness T1 of the first oxide semiconductor layer 10 and the thickness T2 of the first oxide semiconductor pattern 10A can be substantially the same. In short, the thickness T2 of the first oxide semiconductor pattern 10A can be equal to or less than the thickness T1 of the first oxide semiconductor layer 10. According to this embodiment of the invention, the first surface 10S can be shown in the horizontal direction, thus describing the reduction of the thickness T1 of the first oxide semiconductor layer 10 during the etching process, but the concept of the invention is not limited thereto. According to another embodiment of the invention, the first surface 10S can correspond to the vertical direction, in which case the width of the first oxide semiconductor layer 10 in the horizontal direction can be reduced during the etching process.

[0025] Furthermore, as another example, unevenness can be formed on the etched surface ES of the first oxide semiconductor pattern 10A. Therefore, the flatness of the etched surface ES of the first oxide semiconductor pattern 10A can be lower than the flatness of the first surface 10S of the first oxide semiconductor layer 10. Moreover, the roughness of the etched surface ES of the first oxide semiconductor pattern 10A can be greater than the roughness of the first surface 10S of the first oxide semiconductor layer 10.

[0026] See Figure 1CA second oxide semiconductor layer 20 can be formed on the etched surface ES of the first oxide semiconductor pattern 10A. The second oxide semiconductor layer 20 can be formed on the etched surface ES of the first oxide semiconductor pattern 10A by vapor deposition. The second oxide semiconductor layer 20 can also be formed on the etched surface ES of the first oxide semiconductor pattern 10A by liquid phase deposition. Other suitable methods can also be used. For example, the second oxide semiconductor layer 20 can be formed by using the first oxide semiconductor pattern 10A as a seed crystal, similar to epitaxial growth. The second oxide semiconductor layer 20 formed in this way can, together with the first oxide semiconductor pattern 10A, compensate for various etching damages that occur in the first oxide semiconductor pattern 10A during the formation of a predetermined semiconductor element. For example, the predetermined semiconductor element can be a transistor channel.

[0027] The second oxide semiconductor layer 20 can compensate for the reduction in the thickness T1 of the first oxide semiconductor layer 10. Therefore, the sum of the thickness T3 of the second oxide semiconductor layer 20 and the thickness T2 of the first oxide semiconductor pattern 10A can be equal to or greater than the thickness T1 of the first oxide semiconductor layer 10. When the second oxide semiconductor layer 20 and the first oxide semiconductor pattern 10A are used to form a semiconductor element, the first oxide semiconductor pattern 10A can be the main element, and the second oxide semiconductor layer 20 can be an auxiliary element. Therefore, the thickness T3 of the second oxide semiconductor layer 20 can be less than the thickness T2 of the first oxide semiconductor pattern 10A.

[0028] The second oxide semiconductor layer 20 can prevent various defects caused by unevenness by covering the unevenness of the etched surface ES of the first oxide semiconductor pattern 10A. The second oxide semiconductor layer 20 may have a surface contacting the etched surface ES and a surface opposite to the first surface (i.e., the surface opposite to the etched surface ES). Hereinafter, the surface of the second oxide semiconductor layer 20 opposite to the etched surface ES may be referred to as the first surface 20S of the second oxide semiconductor layer 20. The flatness of the first surface 20S of the second oxide semiconductor layer 20 may be greater than the flatness of the etched surface ES of the first oxide semiconductor pattern 10A. Furthermore, the roughness of the first surface 20S of the second oxide semiconductor layer 20 may be less than the roughness of the etched surface ES of the first oxide semiconductor pattern 10A.

[0029] Figure 1C The semiconductor device shown can be manufactured using the methods described above.

[0030] See back Figure 1CThe semiconductor device may include a crystallized first oxide semiconductor pattern 10A and a crystallized second oxide semiconductor layer 20 disposed on the etched surface ES of the first oxide semiconductor pattern 10A.

[0031] The etched surface ES of the first oxide semiconductor pattern 10A may include unevenness. Therefore, the roughness of the etched surface ES of the first oxide semiconductor pattern 10A can be greater than the roughness of the first surface 20S of the second oxide semiconductor layer 20. Furthermore, the flatness of the etched surface ES of the first oxide semiconductor pattern 10A can be less than the flatness of the first surface 20S of the second oxide semiconductor layer 20. The thickness T3 or width of the second oxide semiconductor layer 20 can be less than the thickness T2 or width of the first oxide semiconductor pattern 10A.

[0032] The first oxide semiconductor pattern 10A and the second oxide semiconductor layer 20 can be formed from the same material. For example, the constituent elements and their concentrations of the first oxide semiconductor pattern 10A and the second oxide semiconductor layer 20 can be substantially the same. For example, the first oxide semiconductor pattern 10A and the second oxide semiconductor layer 20 can include IGZO, and the concentrations of indium, gallium, zinc, and oxygen in the first oxide semiconductor pattern 10A can be substantially the same as the concentrations of indium, gallium, zinc, and oxygen in the second oxide semiconductor layer 20. However, the concept of the invention is not limited thereto. For example, in one embodiment, by forming the second oxide semiconductor layer 20 from a material different from the material of the first oxide semiconductor pattern 10A, the characteristics of the semiconductor device formed from the first oxide semiconductor pattern 10A and the second oxide semiconductor layer 20 can be improved. For example, in one embodiment, the constituent elements of the second oxide semiconductor layer 20 and the first oxide semiconductor pattern 10A can be the same, but the concentrations of the constituent elements can be different. In another embodiment, at least one constituent element of the second oxide semiconductor layer 20 can be different from the constituent elements of the first oxide semiconductor pattern 10A. The following may be referenced. Figures 2A to 6C To describe various examples of the constituent elements.

[0033] The method of the present invention for compensating for etching damage in oxide semiconductors can be applied to a variety of semiconductor devices, particularly semiconductor devices including transistors and methods for manufacturing the same. In the following, reference is made to… Figures 2A to 6C Several other embodiments are described. These embodiments are described by focusing on any differences from the embodiments described above of the present invention.

[0034] Figures 2A to 2F This is a cross-sectional view illustrating a semiconductor device and a method for manufacturing the same according to another embodiment of the present invention.

[0035] First, a method for manufacturing semiconductor devices can be described.

[0036] See Figure 2A A first oxide semiconductor layer 110 can be formed on the substrate 100. The first oxide semiconductor layer 110 can be formed directly on the top surface of the substrate 100. The first oxide semiconductor layer 110 can be in direct contact with the top surface of the substrate 100.

[0037] Substrate 100 may include one or more layers. The one or more layers of the substrate may be made of one or more materials. Substrate 100 may include various materials, such as semiconductor materials and dielectric materials. Although not shown, the uppermost part of substrate 100 may include a dielectric material.

[0038] The first oxide semiconductor layer 110 may cover the top surface of the substrate 100. The first oxide semiconductor layer 110 may be formed by any suitable deposition method. The first oxide semiconductor layer 110 may be in a crystalline state.

[0039] See Figure 2B The first oxide semiconductor pattern 110A can be formed by forming a mask pattern M1 on the first oxide semiconductor layer 110 and using the mask pattern M1 as an etching barrier to etch the first oxide semiconductor layer 110.

[0040] The first oxide semiconductor pattern 110A may have an island shape, the width of which in the horizontal direction is greater than its thickness in the vertical direction. The horizontal direction refers to a direction substantially parallel to the top surface of the substrate 100. The vertical direction refers to a direction substantially perpendicular to the top surface of the substrate 100.

[0041] The side surface of the first oxide semiconductor pattern 110A may correspond to the surface exposed to the etching process (i.e., the etched surface). The side surface of the first oxide semiconductor pattern 110A may be referred to as the first etched surface ES1. Due to etching damage, the first etched surface ES1 may have a shape that is recessed inward compared to the side surface of the mask pattern M1. However, the concept of the invention is not limited thereto; the first etched surface ES1 may be substantially aligned with the side surface of the mask pattern M1 (see dashed line). Furthermore, as shown below... Figure 2C As mentioned above, due to etching damage, unevenness can be formed on the first etched surface ES1.

[0042] See now Figure 2CA second oxide semiconductor layer 120 can be formed on the first etched surface ES1. The second oxide semiconductor layer 120 can be formed by a suitable deposition method, including, for example, vapor deposition or liquid phase deposition. In one embodiment, the second oxide semiconductor layer 120 can be formed by using the first oxide semiconductor pattern 110A as a seed crystal, similar to an epitaxial growth method. The second oxide semiconductor layer 120 can be formed while a mask pattern M1 has already been formed. After the second oxide semiconductor layer 120 is formed, the mask pattern M1 can be removed.

[0043] The second oxide semiconductor layer 120 may have a shape surrounding the first etched surface ES1 on the side surface (i.e., the first etched surface ESL) of the island-shaped first oxide semiconductor pattern 110A. Therefore, the second oxide semiconductor layer 120 can compensate for etching damage occurring on the side surface of the first oxide semiconductor pattern 110A. The second oxide semiconductor layer 120 may have a contact surface that contacts the first etched surface ES1 of the first oxide semiconductor pattern 110A and a first surface 120S opposite to the contact surface. The flatness of the first surface 120S of the second oxide semiconductor layer 120 may be greater than the flatness of the first etched surface ES1 of the first oxide semiconductor pattern 110A. Furthermore, the roughness of the first surface 120S of the second oxide semiconductor layer 120 may be less than the roughness of the first etched surface ES1 of the first oxide semiconductor pattern 110A. The horizontal width W20 of the second oxide semiconductor layer 120 may be less than the horizontal width W10 of the first oxide semiconductor pattern 110A.

[0044] The second oxide semiconductor layer 120 can reduce and / or prevent any impurities (such as hydrogen) from penetrating into the first etched surface ES1 of the first oxide semiconductor pattern 110A. Because some constituent elements of the first oxide semiconductor pattern 110A are partially lost, defects are formed on the first etched surface ES1 of the first oxide semiconductor pattern 110A. Therefore, various impurities (such as hydrogen) used in subsequent processes may easily penetrate into the first oxide semiconductor pattern 110A. The second oxide semiconductor layer 120 can act as a barrier to impurity penetration. Furthermore, when the second oxide semiconductor layer 120 is used as an impurity storage layer and contains specific elements, the effect of blocking impurity penetration can be further improved. For example, as the gallium concentration of the second oxide semiconductor layer 120 increases, the hydrogen storage capacity of the second oxide semiconductor layer 120 can increase. Therefore, hydrogen penetration into the first etched surface ES1 of the first oxide semiconductor pattern 110A can be reduced. In one embodiment, the first oxide semiconductor pattern 110A does not contain gallium, while the second oxide semiconductor layer 120 contains gallium. In another embodiment, the first oxide semiconductor pattern 110A contains gallium, while the second oxide semiconductor layer 120 contains a gallium concentration greater than that of the first oxide semiconductor pattern 110A.

[0045] The first oxide semiconductor pattern 110A and the second oxide semiconductor layer 120 can respectively provide the channel region and source / drain region of the transistor. Although not shown, multiple structures can be arranged to be spaced apart from each other in the horizontal direction, each structure including the first oxide semiconductor pattern 110A and the second oxide semiconductor layer 120. Multiple structures can be formed simultaneously.

[0046] See Figure 2D An isolation layer 130 can be formed on the substrate 100 to fill the space other than the first oxide semiconductor pattern 110A and the second oxide semiconductor layer 120. The isolation layer 130 can fill the space between the spaced-apart structures of the first oxide semiconductor pattern 110A and the second oxide semiconductor layer 120. The isolation layer 130 can include any suitable dielectric material. The isolation layer 130 can include various dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. It can be deposited to cover... Figure 2C The dielectric material resulting from the process is then subjected to a planarization process until the top surfaces of the first oxide semiconductor pattern 110A and the second oxide semiconductor layer 120 are exposed, thereby forming an isolation layer 130. Any suitable deposition method can be used.

[0047] Subsequently, a gate dielectric layer 140 can be formed over the first oxide semiconductor pattern 110A, the second oxide semiconductor layer 120, and the isolation layer 130. The gate dielectric layer 140 can be formed by various deposition methods. The gate dielectric layer 140 can include various dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, or high-k materials with a dielectric constant higher than that of silicon oxide.

[0048] Subsequently, a gate structure 150 can be formed on the gate dielectric layer 140. The gate structure 150 may include a gate electrode layer 152 formed on the gate dielectric layer 140 and a gate passivation layer 154 formed on the gate electrode layer 152. The gate passivation layer 154 may be formed on the gate electrode layer 152. The gate structure 150 can be formed by depositing a conductive material for forming the gate electrode layer 152 and a dielectric material for forming the gate passivation layer 154 on the gate dielectric layer 140, and then selectively etching them. When the conductive material for forming the gate electrode layer 152 is etched, the gate passivation layer 154 can be used as a hard mask. The gate electrode layer 152 may include a variety of conductive materials, such as metals, metal compounds, or metal alloys thereof, such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), titanium (Ti), ruthenium (Ru), molybdenum (Mo), etc., and the gate electrode layer 152 may have a single-layer structure or a multi-layer structure. The gate passivation layer 154 may include a variety of dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, etc., and the gate passivation layer 154 may have a single-layer structure or a multi-layer structure.

[0049] The portion of the first oxide semiconductor pattern 110A that overlaps with the gate structure 150 can form the channel region of the transistor. The portions of the first oxide semiconductor pattern 110A disposed on both sides of the gate structure 150 can form the source / drain regions of the transistor. For example, the portion of the first oxide semiconductor pattern 110A disposed on one side of the gate structure 150 can form the source region of the transistor, while the portion of the first oxide semiconductor pattern 110A disposed on the other side of the gate structure 150 can form the drain region of the transistor.

[0050] See Figure 2E It can form a coverage Figure 2D The interlayer dielectric layer 160 is formed by a deposition process. The interlayer dielectric layer 160 may include various dielectric materials, such as silicon oxide, silicon nitride, and silicon oxynitride. The top surface of the interlayer dielectric layer 160 may be formed at a height equal to or higher than the top surface of the gate structure 150.

[0051] Subsequently, contact holes 165 exposing a portion of the first oxide semiconductor pattern 110A can be formed by selectively etching the interlayer dielectric layer 160 and the gate dielectric layer 140. Here, contact holes 165 can be formed to expose the source and drain regions of the transistor in the first oxide semiconductor pattern 110A, respectively. Contact holes 165 can have a tapered shape, with their width decreasing in the direction approaching the first oxide semiconductor pattern 110A.

[0052] Here, the portion of the top surface of the first oxide semiconductor pattern 110A corresponding to the bottom surface of the contact hole 165 is the surface exposed to the etching process, hereinafter referred to as the second etched surface ES2. Furthermore, hereinafter, the remaining portion of the top surface of the first oxide semiconductor pattern 110A, excluding the second etched surface ES2, can be referred to as the remaining top surface portion. Due to etching damage, the second etched surface ES2 may have a shape with a lower depression than the remaining top surface portion of the first oxide semiconductor pattern 110A. The height from the top surface of the substrate 100 to the second etched surface ES2 (i.e., the thickness T20 of the portion of the first oxide semiconductor pattern 110A corresponding to the second etched surface ES2) may be less than the height from the top surface of the substrate 100 to the remaining top surface portion of the first oxide semiconductor pattern 110A (i.e., the thickness T10 of the remaining portion of the first oxide semiconductor pattern 110A not corresponding to the second etched surface ES2). However, the concept of the present invention is not limited thereto; the second etched surface ES2 may be disposed at substantially the same height as the remaining top surface portion of the first oxide semiconductor pattern 110A (see dashed line). In addition, unevenness may form on the second etched surface ES2 due to etching damage.

[0053] See Figure 2F A third oxide semiconductor layer 170 can be formed on the second etched surface ES2. The third oxide semiconductor layer 170 can be formed by a suitable deposition method. For example, in one embodiment, the third oxide semiconductor layer 170 can be formed by vapor deposition. In another embodiment, the third oxide semiconductor layer 170 can be formed by liquid phase deposition. The third oxide semiconductor layer 170 can be formed by using the first oxide semiconductor pattern 110A as a seed crystal, i.e., similar to an epitaxial growth method.

[0054] A third oxide semiconductor layer 170 can be formed by filling the lower portion of the contact hole 165 to cover the second etched surface ES2. Therefore, the third oxide semiconductor layer 170 can compensate for etching damage occurring on the second etched surface ES2 of the first oxide semiconductor pattern 110A. The third oxide semiconductor layer 170 may have a bottom surface contacting the second etched surface ES2 of the first oxide semiconductor pattern 110A, and a top surface (i.e., a first surface 170S) opposite to the bottom surface. The flatness of the first surface 170S of the third oxide semiconductor layer 170 can be greater than the flatness of the second etched surface ES2 of the first oxide semiconductor pattern 110A. Furthermore, the roughness of the first surface 170S of the third oxide semiconductor layer 170 can be less than the roughness of the second etched surface ES2 of the first oxide semiconductor pattern 110A. The thickness T30 of the third oxide semiconductor layer 170 can be less than the thickness T20 of the portion of the first oxide semiconductor pattern 110A corresponding to the second etched surface ES2.

[0055] The third oxide semiconductor layer 170 can reduce and / or prevent any impurities (such as hydrogen) from penetrating into the second etched surface ES2 of the first oxide semiconductor pattern 110A. Furthermore, when the third oxide semiconductor layer 170 is used as an impurity storage layer and contains specific elements, the effect of blocking impurity penetration can be further enhanced. For example, as the gallium concentration of the third oxide semiconductor layer 170 increases, the hydrogen storage capacity of the third oxide semiconductor layer 170 can increase, thereby reducing hydrogen penetration through the second etched surface ES2 of the first oxide semiconductor pattern 110A. Even if the first oxide semiconductor pattern 110A does not contain gallium, the third oxide semiconductor layer 170 can contain gallium. Furthermore, when the first oxide semiconductor pattern 110A contains gallium, the third oxide semiconductor layer 170 can contain gallium at a concentration greater than that of the first oxide semiconductor pattern 110A.

[0056] Furthermore, the third oxide semiconductor layer 170 may also include elements that can reduce the resistance of the third oxide semiconductor layer 170 to reduce the contact plug 180 (see...). Figure 2FThe contact resistance between the third oxide semiconductor layer 170 and the first oxide semiconductor pattern 110A. An example of such an element is indium. It has been found that the resistance of the third oxide semiconductor layer 170 decreases as the indium concentration of the third oxide semiconductor layer 170 increases. The third oxide semiconductor layer 170 may contain indium even if the first oxide semiconductor pattern 110A does not contain indium. Furthermore, when the first oxide semiconductor pattern 110A contains indium, the third oxide semiconductor layer 170 may contain indium at a concentration greater than that of the first oxide semiconductor pattern 110A. For example, when the first oxide semiconductor pattern 110A includes typical IGZO (i.e., IGZO that meets stoichiometric ratios), the third oxide semiconductor layer 170 may include indium-rich IGZO. Indium-rich IGZO can refer to a material with an indium content higher than that of gallium and zinc, for example, a material with an indium content of about 40% or higher. Since the resistance of indium-rich IGZO is lower than that of typical IGZO, it can have metallic properties. As a result, the resistance of the third oxide semiconductor layer 170 can be less than the resistance of the first oxide semiconductor pattern 110A.

[0057] See now Figure 2F Contact plugs 180 can be formed to fill the remaining space of contact holes 165 forming the third oxide semiconductor layer 170. Contact plugs 180 can be formed after the third oxide semiconductor layer 170 is formed. Contact plugs 180 can be formed by depositing a conductive material with a thickness sufficient to fill the contact holes 165, followed by a planarization process to expose the top surface of the interlayer dielectric layer 160. Contact plugs 180 can include various conductive materials, such as metals, metal compounds, or metal alloys thereof, such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), titanium (Ti), ruthenium (Ru), molybdenum (Mo), etc. To ensure smooth current flow from the first oxide semiconductor pattern 110A through the third oxide semiconductor layer 170 and contact plugs 180, the resistance of contact plugs 180 can be less than the resistance of the third oxide semiconductor layer 170, and the thickness T40 of contact plugs 180 can be greater than the thickness T30 of the third oxide semiconductor layer 170. Since the contact plug 180 is disposed on the third oxide semiconductor layer 170 and fills the contact hole 165 together with the third oxide semiconductor layer 170, the side surface of the contact plug 180 and the side surface of the third oxide semiconductor layer 170 can be aligned with each other. The contact plug 180 can correspond to the source / drain electrodes electrically connected to the source / drain regions of the transistor.

[0058] Figure 2F The semiconductor device shown can be manufactured using the methods described above for manufacturing semiconductor devices.

[0059] See back Figure 2FAccording to this embodiment of the present invention, the semiconductor device may include: a first oxide semiconductor pattern 110A, a gate structure 150, and a contact plug 180, wherein the gate structure 150 is formed on the first oxide semiconductor pattern 110A, a gate dielectric layer 140 is disposed between the gate structure 150 and the first oxide semiconductor pattern 110A, and the contact plug 180 is disposed on at least one side of the gate structure 150 and electrically connected to the first oxide semiconductor pattern 110A.

[0060] Here, the first oxide semiconductor pattern 110A may include a first etched surface ES1 formed on the side surface of the first oxide semiconductor pattern 110A and a second etched surface ES2 formed on at least a portion of the top surface of the first oxide semiconductor pattern 110A. A second oxide semiconductor layer 120 may be formed on the first etched surface ES1 of the first oxide semiconductor pattern 110A, and a third oxide semiconductor layer 170 may be formed on the second etched surface ES2 of the second oxide semiconductor pattern 110A. The third oxide semiconductor layer 170 may be located between the contact plug 180 and the second etched surface ES2 of the first oxide semiconductor pattern 110A.

[0061] Since the constituent elements of the semiconductor device according to this embodiment of the invention have been described in detail in the description of the manufacturing process of the semiconductor device, further detailed description of the constituent elements may be omitted herein.

[0062] Figures 3A to 3C This is a cross-sectional view illustrating a semiconductor device and a method for manufacturing the same according to another embodiment of the present invention.

[0063] See Figure 3A A structure is provided, comprising: a substrate 200; a first oxide semiconductor pattern 210A formed on the substrate 200; a second oxide semiconductor layer 220 formed on a first etched surface ES1 of the first oxide semiconductor pattern 210A; and an isolation layer 230 filling the space on the substrate 200 excluding the first oxide semiconductor pattern 210A and the second oxide semiconductor layer 220. This structure can be configured to perform the above-described... Figures 2A to 2C The process and Figure 2D It is formed using a process that is essentially the same as some of the processes.

[0064] See Figure 3B An interlayer dielectric layer 260 can be formed to cover Figure 3A The results of the process.

[0065] Subsequently, the interlayer dielectric layer 260 can be selectively etched to form an opening 265 that exposes a portion of the first oxide semiconductor pattern 210A. Here, the opening 265 can provide space in which the gate dielectric layer and gate structure (which can be described later) will be formed. Although not shown, from a plan view perspective, the opening 265 can have a line shape extending in a direction through the cross section.

[0066] For example, the portion of the top surface of the first oxide semiconductor pattern 210A corresponding to the bottom surface of the opening 265 can be a surface exposed to the etching process, hereinafter referred to as the third etched surface ES3. Furthermore, hereinafter, the remaining portion of the top surface of the first oxide semiconductor pattern 210A, excluding the third etched surface ES3, can be referred to as the remaining top surface portion of the first oxide semiconductor pattern 210A. Due to etching damage, the third etched surface ES3 can have a shape that is lower than the remaining top surface portion of the first oxide semiconductor pattern 210A. However, the concept of the invention is not limited thereto; the third etched surface ES3 can be disposed at substantially the same height as the remaining top surface portion of the first oxide semiconductor pattern 210A (see dashed line). Furthermore, due to etching damage, unevenness may form on the third etched surface ES3.

[0067] See Figure 3C A fourth oxide semiconductor layer 270 can be formed on the third etched surface ES3. For example, the fourth oxide semiconductor layer 270 can be formed by vapor deposition or liquid phase deposition. The fourth oxide semiconductor layer 270 can be formed by using the first oxide semiconductor pattern 210A as a seed crystal, i.e., similar to an epitaxial growth method.

[0068] A fourth oxide semiconductor layer 270 can be formed by filling the lower portion of opening 265 to cover the third etched surface ES3. Therefore, the fourth oxide semiconductor layer 270 can compensate for etching damage occurring on the third etched surface ES3 of the first oxide semiconductor pattern 210A. The fourth oxide semiconductor layer 270 may have a top surface (i.e., a first surface 270S) opposite to the third etched surface ES3 of the first oxide semiconductor pattern 210A. The flatness of the first surface 270S of the fourth oxide semiconductor layer 270 may be greater than the flatness of the third etched surface ES3 of the first oxide semiconductor pattern 210A. Furthermore, the roughness of the first surface 270S of the fourth oxide semiconductor layer 270 may be less than the roughness of the third etched surface ES3 of the first oxide semiconductor pattern 210A. The thickness of the fourth oxide semiconductor layer 270 may be less than the thickness of the portion of the first oxide semiconductor pattern 210A corresponding to the third etched surface ES3.

[0069] The fourth oxide semiconductor layer 270 can reduce and / or prevent any impurities (such as hydrogen) from penetrating into the third etched surface ES3 of the first oxide semiconductor pattern 210A. Furthermore, when the fourth oxide semiconductor layer 270 is used as an impurity storage layer and contains specific elements, the effect of blocking impurity penetration can be further enhanced. For example, as the gallium concentration of the fourth oxide semiconductor layer 270 increases, the hydrogen storage capacity of the fourth oxide semiconductor layer 270 can increase, thereby reducing hydrogen penetration through the third etched surface ES3 of the first oxide semiconductor pattern 210A. Even if the first oxide semiconductor pattern 210A does not contain gallium, the fourth oxide semiconductor layer 270 can contain gallium. Furthermore, when the first oxide semiconductor pattern 210A contains gallium, the fourth oxide semiconductor layer 270 can contain gallium at a concentration greater than that of the first oxide semiconductor pattern 210A.

[0070] Subsequently, a gate dielectric layer 240 can be conformally formed along the sidewalls and bottom surface of the opening 265 in the remaining space of the opening 265 forming the fourth oxide semiconductor layer 270. The gate dielectric layer 240 can be formed with a thickness that does not completely fill the opening 265.

[0071] Subsequently, a gate structure 250 can be formed to fill the remaining space of the opening 265 forming the gate dielectric layer 240. The gate structure 250 may include a gate electrode layer 252 and a gate passivation layer 254. The gate electrode layer 252 fills the lower portion of the remaining space of the opening 265 forming the gate dielectric layer 240, while the gate passivation layer 254 fills the upper portion of the remaining space of the opening 265 forming the gate dielectric layer 240. The gate electrode layer 252 can be formed by depositing a conductive material of sufficient thickness to fill the remaining space of the opening 265 forming the gate dielectric layer 240, and then recessing the conductive material until it reaches the desired height. The gate passivation layer 254 can be formed by depositing a dielectric material of sufficient thickness to fill the remaining space of the opening 265 forming the gate electrode layer 252, and then performing a planarization process to expose the top surface of the interlayer dielectric layer 260.

[0072] Figure 3C The semiconductor device shown can be manufactured using the methods described above for manufacturing semiconductor devices.

[0073] exist Figures 2A to 3C The above embodiments of the present invention have described a planar transistor in which the channel is formed in a direction substantially parallel to the surface of the substrate, but the concept of the invention is not limited thereto. The present invention can be applied to vertical transistors in which the channel is formed in a direction substantially perpendicular to the surface of the substrate. Reference is made below. Figures 4 to 6C This embodiment is described.

[0074] Figure 4This is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.

[0075] See Figure 4 The semiconductor device may include a substrate 300, a first conductive line 310 disposed on the substrate 300 and extending in a horizontal direction, an oxide semiconductor pattern 320 disposed on the first conductive line 310 and having a columnar shape, and a gate electrode layer 340 disposed on a side surface of the oxide semiconductor pattern 320, and a gate dielectric layer 330 disposed between the gate electrode layer 340 and the oxide semiconductor pattern 320.

[0076] According to this embodiment of the invention, the oxide semiconductor pattern 320 may have a cylindrical shape, such that the channel region of the transistor can be formed in a direction perpendicular to the top surface of the substrate 300. Here, the cylindrical shape may refer to a shape in which the width in the horizontal direction is smaller than the width (i.e., the thickness) in the vertical direction.

[0077] The portion of the oxide semiconductor pattern 320 facing the gate electrode layer 340 can correspond to the channel region of the transistor, while the portions of the oxide semiconductor pattern 320 disposed above and below the channel region can correspond to the source / drain regions of the transistor.

[0078] The first conductor 310 can be coupled to the bottom surface of the oxide semiconductor pattern 320 to electrically connect to the oxide semiconductor pattern 320, thereby providing the required voltage or current to the oxide semiconductor pattern 320. The first conductor 310 can correspond to a bit line.

[0079] The gate electrode layer 340 may face a portion of the side surface of the oxide semiconductor pattern 320, and the current flow in the channel region can be controlled according to the voltage or current supplied to the gate electrode layer 340. According to this embodiment of the invention, the gate electrode layer 340 is shown disposed on both sides of the oxide semiconductor pattern 320, but the concept of the invention is not limited thereto. The gate electrode layer 340 may have a shape surrounding the side surface of the oxide semiconductor pattern 320, or it may face a portion of the side surface. Although not shown, the gate electrode layer 340 may have a line shape extending in the direction of the penetration section, and the gate electrode layer 340 may correspond to a word line.

[0080] The top surface of the oxide semiconductor pattern 320 can be electrically connected to another constituent element, such as a memory element.

[0081] Even when vertical transistors are formed as described above, the oxide semiconductor pattern 320 can still be exposed to the etching process, resulting in etching damage. Methods for compensating for this etching damage will be described below.

[0082] Figure 5A and Figure 5BThese are cross-sectional views illustrating a semiconductor device and a method for manufacturing the same according to another embodiment of the present invention. Specifically, these views depict the formation of... Figure 4 The process of the oxide semiconductor pattern 320 shown.

[0083] See Figure 5A The first oxide semiconductor pattern 410A can be formed by forming an oxide semiconductor layer on the substrate 400 and etching the oxide semiconductor layer using a mask pattern M2.

[0084] The first oxide semiconductor pattern 410A may have a cylindrical shape, with its width (i.e., thickness) in the vertical direction being greater than its width in the horizontal direction. The side surface of the first oxide semiconductor pattern 410A may be referred to as the etched surface ES4. Due to etching damage, the etched surface ES4 may have a shape that is concave inward compared to the side surface of the mask pattern M2. However, embodiments of the invention are not limited to this; the etched surface ES4 may be substantially aligned with the side surface of the mask pattern M2 (see dashed line). Furthermore, due to etching damage, unevenness may form on the etched surface ES4.

[0085] See Figure 5B A second oxide semiconductor layer 420 can be formed on the etched surface ES4. For example, the second oxide semiconductor layer 420 can be formed by vapor deposition or liquid phase deposition. The second oxide semiconductor layer 420 can be formed using a first oxide semiconductor pattern 410A as a seed crystal, similar to epitaxial growth. The second oxide semiconductor layer 420 can be formed while a mask pattern M2 has already been formed. After forming the second oxide semiconductor layer 420, the mask pattern M2 can be removed.

[0086] The second oxide semiconductor layer 420 may have a shape surrounding the side surface (i.e., etched surface ES4) of the first oxide semiconductor pattern 410A, which is in the shape of a pillar. Therefore, the second oxide semiconductor layer 420 can compensate for etching damage that occurs on the side surface of the first oxide semiconductor pattern 410A.

[0087] The second oxide semiconductor layer 420 can reduce and / or prevent any impurities (such as hydrogen) from penetrating into the etched surface ES4 of the first oxide semiconductor pattern 410A. Furthermore, when the second oxide semiconductor layer 420 is used as an impurity storage layer and contains specific elements, the effect of blocking impurity penetration can be further enhanced. For example, the second oxide semiconductor layer 420 may include a gallium-rich oxide semiconductor with excellent hydrogen storage capabilities.

[0088] The first oxide semiconductor pattern 410A and the second oxide semiconductor layer 420 can correspond to the above. Figure 4 The oxide semiconductor pattern 320.

[0089] Figures 6A to 6C These are cross-sectional views illustrating a semiconductor device and a method for manufacturing the same according to another embodiment of the present invention. Specifically, these views depict the process for forming... Figure 4 The process of the oxide semiconductor pattern 320 shown.

[0090] See Figure 6A Holes 525 that provide space for the columnar oxide semiconductor pattern to be formed can be formed by forming an interlayer dielectric layer 520 on the substrate 500 and selectively etching the interlayer dielectric layer 520.

[0091] Subsequently, the gate dielectric layer 530 may be conformally formed on the interlayer dielectric layer 520 including the via 525 to have a thickness that does not completely fill the via 525. Then, a first oxide semiconductor layer 540 may be formed on the gate dielectric layer 530 to have a thickness sufficient to fill the via 525.

[0092] See Figure 6B The first oxide semiconductor pattern 540A for filling the via 525 can be formed by performing an etching process (e.g., an etch-back process) on the first oxide semiconductor layer 540. During this process, a portion of the gate dielectric layer 530 disposed on the top surface of the interlayer dielectric layer 520 can be removed to form the gate dielectric pattern 530A for filling the via 525. The first oxide semiconductor pattern 540A may have a pillar shape, and the gate dielectric pattern 530A may have a shape surrounding the side surfaces of the first oxide semiconductor pattern 540A.

[0093] Here, the top surface of the first oxide semiconductor pattern 540A may correspond to the etched surface ES5. Due to etching damage, the etched surface ES5 may have a shape that is lower than the top surface depression of the interlayer dielectric layer 520. However, embodiments of the present invention are not limited to this, and the etched surface ES5 may be disposed at substantially the same height as the top surface of the interlayer dielectric layer 520 (see dashed line). Furthermore, due to etching damage, unevenness may form on the etched surface ES5.

[0094] See Figure 6C A second oxide semiconductor layer 550 can be formed on the etched surface ES5. The second oxide semiconductor layer 550 can be formed by any suitable deposition method, including, for example, vapor deposition or liquid phase deposition. The second oxide semiconductor layer 550 can be formed by using the first oxide semiconductor pattern 540A as a seed crystal, similar to epitaxial growth.

[0095] The second oxide semiconductor layer 550 can reduce and / or prevent any impurities (such as hydrogen) from penetrating into the etched surface ES5 of the first oxide semiconductor pattern 540A. Furthermore, when the second oxide semiconductor layer 550 serves as an impurity storage layer and contains specific elements, the effect of blocking impurity penetration can be further enhanced. For example, the second oxide semiconductor layer 550 may include a gallium-rich oxide semiconductor with excellent hydrogen storage capabilities. Additionally, when another conductor (such as a contact plug) electrically connected to the second oxide semiconductor layer 550 is disposed on the second oxide semiconductor layer 550, elements that reduce resistance during the formation of the second oxide semiconductor layer 550, such as indium, may also be included in the second oxide semiconductor layer 550. A process similar to that used for forming the third oxide semiconductor layer 170 according to the above embodiments of the present invention can be performed. In this case, the contact resistance between the first oxide semiconductor pattern 540A and the other conductor can be reduced.

[0096] The first oxide semiconductor pattern 540A and the second oxide semiconductor layer 550 can correspond to the above. Figure 4 The oxide semiconductor pattern 320.

[0097] The embodiments of the present invention described above can be applied to all semiconductor devices, including NMOS transistors, PMOS transistors, or CMOS transistors, and their manufacturing methods. For example, they can be applied to non-volatile memories, volatile memories, non-memory devices, and many other semiconductor devices. Non-volatile memories include flash memory, resistive random access memory (RRAM), phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), etc.; volatile memories include dynamic random access memory (DRAM), static random access memory (SRAM), etc.; non-memory devices include logic circuits, etc.; and many other semiconductor devices include CMOS image sensors (CIS), etc.

[0098] According to embodiments of the present invention, the semiconductor device and the method of manufacturing the semiconductor device are capable of compensating for etching damage to oxide semiconductors.

[0099] Although the invention has been described with reference to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the concept and scope of the invention as defined in the appended claims. Furthermore, these embodiments can be combined to form additional embodiments.

Claims

1. A semiconductor device, comprising: A crystalline first oxide semiconductor pattern having at least one etched surface; as well as A crystalline second oxide semiconductor layer is disposed on the etched surface of the first oxide semiconductor pattern.

2. The semiconductor device according to claim 1, wherein, The roughness of the etched surface of the first oxide semiconductor pattern is greater than the roughness of the first surface of the second oxide semiconductor layer opposite to the etched surface.

3. The semiconductor device according to claim 1, wherein, The thickness or width of the second oxide semiconductor layer is less than the thickness or width of the portion of the first oxide semiconductor pattern corresponding to the etched surface.

4. The semiconductor device according to claim 1, wherein, The second oxide semiconductor layer includes a first element, and The first oxide semiconductor pattern does not contain the first element, or the concentration of the first element contained therein is lower than the concentration of the first element in the second oxide semiconductor layer.

5. The semiconductor device according to claim 4, wherein, The first element contains gallium.

6. The semiconductor device according to claim 1, wherein, The resistance of the second oxide semiconductor layer is lower than that of the first oxide semiconductor pattern.

7. The semiconductor device according to claim 6, wherein, The second oxide semiconductor layer includes indium, and The first oxide semiconductor pattern does not contain indium, or the concentration of indium contained therein is lower than the concentration of indium in the second oxide semiconductor layer.

8. The semiconductor device according to claim 6, further comprising: conductor, The second oxide semiconductor layer is located between the first oxide semiconductor pattern and the conductor.

9. The semiconductor device according to claim 1, further comprising: A gate structure is disposed on the first oxide semiconductor pattern, and a gate dielectric layer is disposed between the gate structure and the first oxide semiconductor pattern. as well as A contact plug is disposed on at least one side surface of the gate structure above the first oxide semiconductor pattern. The second oxide semiconductor layer is located between the contact plug and the first oxide semiconductor pattern.

10. The semiconductor device according to claim 9, wherein, The side surface of the contact plug and the side surface of the second oxide semiconductor layer are aligned with each other.

11. The semiconductor device according to claim 1, further comprising: A gate structure is disposed on the first oxide semiconductor pattern, and a gate dielectric layer is disposed between the gate structure and the first oxide semiconductor pattern. The second oxide semiconductor layer is located between the gate structure and the first oxide semiconductor pattern.

12. The semiconductor device according to claim 1, wherein, The etched surface corresponds to the side surface of the first oxide semiconductor pattern.

13. The semiconductor device according to claim 12, wherein, The first oxide semiconductor pattern has a columnar shape, and The second oxide semiconductor layer is formed as a side surface surrounding the first oxide semiconductor pattern.

14. The semiconductor device according to claim 1, wherein, The etched surface corresponds to at least a portion of the top surface of the first oxide semiconductor pattern.

15. The semiconductor device according to claim 14, wherein, The first oxide semiconductor pattern has a columnar shape, and The second oxide semiconductor layer is formed to cover the top surface of the first oxide semiconductor pattern.

16. A method for manufacturing a semiconductor device, the method comprising: A crystalline first oxide semiconductor layer is formed on the substrate; A first oxide semiconductor pattern having etched side surfaces is formed by selectively etching the first oxide semiconductor layer; as well as A crystalline second oxide semiconductor layer is formed on the side surface of the first oxide semiconductor pattern.

17. The method according to claim 16, wherein, In forming the second oxide semiconductor layer Use vapor phase deposition or liquid phase deposition.

18. The method of claim 16, further comprising: After forming the first oxide semiconductor pattern An etched surface is formed by exposing at least a portion of the top surface of the first oxide semiconductor pattern to an etching process; as well as A third oxide semiconductor layer is formed on the etched surface.

19. A method for manufacturing a semiconductor device, the method comprising: A first oxide semiconductor pattern is provided on a substrate; An etched surface is formed by exposing at least a portion of the top surface of the first oxide semiconductor pattern to an etching process; as well as A second oxide semiconductor layer is formed on the etched surface.

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