Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, relates to the technical field of semiconductors, and aims to reduce the distance between a first transistor and a second transistor along the thickness direction of a substrate, reduce the parasitic resistance and parasitic capacitance of the semiconductor device and improve the working performance of the semiconductor device. The semiconductor device includes a substrate, a first transistor, and a second transistor. Wherein the first transistor and the second transistor are arranged on the substrate at intervals in the thickness direction of the substrate, and the second transistor is located above the first transistor. A first active structure included in the first transistor and a second active structure included in the second transistor are arranged in a staggered mode in the direction parallel to the surface of the substrate. Each of the first active structure and the second active structure comprises a channel region and source and drain regions located on the two sides of the channel region in the length direction. The manufacturing method of the semiconductor device is used for manufacturing the semiconductor device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and particularly relates to a semiconductor device and a manufacturing method thereof. BACKGROUND

[0002] The three-dimensional stacked transistor includes two transistors vertically stacked along the thickness direction of the substrate, and the lateral spacing of the two transistors is eliminated, which allows the effective channel width to be further increased, thereby improving the working performance and integration of the semiconductor device.

[0003] However, in the existing three-dimensional stacked transistor, the spacing of the upper and lower two transistors along the thickness direction of the substrate is large, which increases the parasitic resistance and parasitic capacitance of the semiconductor device, and is not conducive to improving the working performance of the semiconductor device. SUMMARY

[0004] The present application relates to the technical field of semiconductor, and particularly relates to a semiconductor device and a manufacturing method thereof.

[0005] In order to achieve the above-mentioned purpose, in a first aspect, the present application provides a semiconductor device, which comprises a substrate, a first transistor and a second transistor. The first transistor and the second transistor are arranged on the substrate along the thickness direction of the substrate, and the second transistor is located above the first transistor. The first active structure included in the first transistor and the second active structure included in the second transistor are arranged staggered along the direction parallel to the surface of the substrate. The first active structure and the second active structure each include a channel region and source-drain regions located on both sides of the channel region along the length direction.

[0006] In the case of adopting the above technical solution, the semiconductor device includes the first transistor and the second transistor arranged spaced apart along the thickness direction of the substrate. Obviously, the first transistor and the second transistor can constitute a three-dimensional stacked transistor (CFET device) to improve the integration of the semiconductor device.

[0007] In addition, the first active structure included in the first transistor and the second active structure included in the second transistor are staggered along a direction parallel to the surface of the substrate. In the first transistor and the second transistor, two source / drain regions located on the same side along the length direction of the gate stack structure can be staggered along the direction parallel to the surface of the substrate, in other words, along the thickness direction of the substrate, the source / drain region located below can be exposed outside the source / drain region located above, which is conducive to making the source / drain contact structures formed subsequently electrically connected to the corresponding source / drain regions through the staggered spacing therebetween. This not only prevents device failure caused by the overlap of different source / drain contact structures, but also eliminates the need to set a conductive structure for leading out between the two, which is conducive to reducing the thickness of the isolation material (which can be the first isolation structure below) for electrically insulating the source / drain regions included in the first transistor and the second transistor, thereby reducing the parasitic capacitance of the semiconductor device. At the same time, due to the small thickness of the isolation material, the length of the source / drain contact structure for leading out the source / drain region below (or the length of the source / drain contact structure for leading out the source / drain region above) is also small, which reduces the parasitic resistance of the semiconductor device and is conducive to improving the working performance of the semiconductor device.

[0008] In an example, the semiconductor device further includes a first isolation structure. Along the thickness direction of the substrate, the first isolation structure is arranged between the source / drain region included in the first active structure and the source / drain region included in the second active structure.

[0009] In an example, along the thickness direction of the substrate, the thickness of the first isolation structure is greater than or equal to 5 nm and less than or equal to 30 nm.

[0010] In an example, the first isolation structure is integrally formed.

[0011] In an example, the semiconductor device further includes a first semiconductor part arranged on the substrate, and the first semiconductor part and the first active structure are distributed laterally along the surface of the substrate. The second active structure is arranged above the first semiconductor part. The first isolation structure directly covers both sides of the first semiconductor part along the length direction and covers the source / drain region included in the first active structure, and the first isolation structure is located below the source / drain region included in the second active structure.

[0012] In an example, the channel region included in the first active structure is parallelly distributed with the first semiconductor part.

[0013] In an example, the channel region included in the first active structure is of the same shape and / or material as the first semiconductor part.

[0014] In an example, the semiconductor device further includes a second semiconductor part arranged above the first active structure, and the second semiconductor part and the second active structure are distributed laterally along a direction parallel to the surface of the substrate.

[0015] In an example, the second active structure includes a channel region parallel to the second semiconductor portion.

[0016] In an example, the second active structure includes a channel region of the same shape and / or material as the second semiconductor portion.

[0017] In an example, in a case where the semiconductor device further includes a first semiconductor portion, the second active structure includes a channel region aligned with the first semiconductor portion.

[0018] In an example, the first active structure includes a channel region aligned with the second semiconductor portion.

[0019] In an example, the first transistor and the second transistor further include a first source-drain contact structure and a second source-drain contact structure. The first source-drain contact structure is in electrical contact with one of the source-drain regions included in the first active structure, and the second source-drain contact structure is in electrical contact with one of the source-drain regions included in the second active structure. The first source-drain contact structure and the second source-drain contact structure are located on the same side of the gate stack structure included in the first transistor and / or the second transistor along a length direction, and are spaced apart along a surface direction of the substrate. The first source-drain contact structure and the second source-drain contact structure extend along a direction perpendicular to the surface direction of the substrate.

[0020] In an example, the first source-drain contact structure and the second source-drain contact structure respectively extend to an upper surface of the source-drain regions included in the first active structure and the second active structure from the same side of the substrate along a thickness direction. Or, the first source-drain contact structure and the second source-drain contact structure respectively extend to a lower surface of the source-drain regions included in the first active structure and the second active structure from the same side of the substrate along the thickness direction.

[0021] In an example, the first transistor and the second transistor further include a third source-drain contact structure. The third source-drain contact structure includes a vertical extension, and a lateral extension in electrical contact with the vertical extension. The vertical extension is located above and in electrical contact with another one of the source-drain regions included in the first active structure. The lateral extension is located above or below another one of the source-drain regions included in the second active structure, and is used to electrically connect the vertical extension with another one of the source-drain regions included in the second active structure.

[0022] In an example, the vertical extension extends along a direction perpendicular to the surface direction of the substrate.

[0023] In an example, the first transistor and the second transistor are of opposite conductivity types.

[0024] In an example, along a width direction of the channel region, a distance between the channel region included in the first active structure and the channel region included in the second active structure is greater than or equal to 10 nm and less than or equal to 40 nm.

[0025] In a second aspect, the present application provides a method for manufacturing a semiconductor device, comprising: first, forming a first fin structure and a second fin structure on a substrate. The first fin structure and the second fin structure are spaced apart along a direction parallel to a surface of the substrate. The first fin structure and the second fin structure each comprise, along a thickness direction of the substrate, a lower fin portion, a semiconductor isolation portion, and an upper fin portion arranged in sequence. Next, the upper fin portions included in the first fin structure and the second fin structure are protected, and source-drain regions are epitaxially formed on both sides of the lower fin portions included in the first fin structure and the second fin structure. Next, the source-drain regions on both sides of the lower fin portions included in the second fin structure are etched and removed. Next, the lower fin portions included in the first fin structure and the second fin structure are protected, and source-drain regions are epitaxially formed on both sides of the upper fin portions included in the first fin structure and the second fin structure. Next, the source-drain regions on both sides of the upper fin portions included in the first fin structure are etched and removed.

[0026] In an example, the protecting the upper fin portions included in the first fin structure and the second fin structure comprises: forming a first mask structure spanning over the first fin structure and the second fin structure. Next, portions of the first fin structure and the second fin structure exposed outside the first mask structure are etched and removed. Next, a second mask structure is formed on the substrate, covering both sides of the lower fin portions included in the first fin structure and the second fin structure along a length direction. Next, a third mask structure is formed, covering both sides of the upper fin portions included in the first fin structure and the second fin structure along a length direction; the material of the third mask structure is different from that of the second mask structure. Next, the second mask structure is selectively removed.

[0027] In an example, the protecting the lower fin portions included in the first fin structure and the second fin structure comprises: forming a first isolation structure covering both sides of the lower fin portions included in the second fin structure along a length direction, and covering the source-drain regions that have been formed.

[0028] In an example, after the source-drain regions on both sides of the upper fin portions included in the first fin structure are etched and removed, the method for manufacturing a semiconductor device further comprises: using a semiconductor process, forming a first transistor based on the lower fin portion remaining in the first fin structure and the source-drain regions adjacent thereto, and forming a second transistor based on the upper fin portion remaining in the second fin structure and the source-drain regions adjacent thereto.

[0029] In an example, after forming the first transistor and the second transistor, the method further includes: forming a first source-drain contact structure electrically connected to one of the source-drain regions included in the first transistor; forming a second source-drain contact structure electrically connected to one of the source-drain regions included in the second transistor; the first source-drain contact structure and the second source-drain contact structure are located on the same side of the gate stack structure included in the first transistor and / or the second transistor along a length direction, and are spaced apart; the first source-drain contact structure extends along a direction perpendicular to a surface of the substrate.

[0030] In an example, after forming the first transistor and the second transistor, the method further includes: forming a third source-drain contact structure electrically connected to another one of the source-drain regions included in the first transistor and another one of the source-drain regions included in the second transistor; the third source-drain contact structure includes a vertical extension and a lateral extension electrically connected to the vertical extension; the vertical extension is located above the another one of the source-drain regions included in the first transistor and is electrically connected to the another one of the source-drain regions included in the first transistor; the lateral extension is located above or below the another one of the source-drain regions included in the second transistor and is used to electrically connect the vertical extension and the another one of the source-drain regions included in the second transistor.

[0031] The beneficial effects of the second aspect of the present application and its various implementations can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0032] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings:

[0033] Figure 1 Structure of a semiconductor device provided by an embodiment of the present application during manufacturing Figure 1 ;

[0034] Figure 2 Structure of a semiconductor device provided by an embodiment of the present application during manufacturing Figure 2 ;

[0035] Figure 3 Structure of a semiconductor device provided by an embodiment of the present application during manufacturing Figure 3 ;

[0036] Figure 4 Structure of a semiconductor device provided by an embodiment of the present application during manufacturing Figure 4 ;

[0037] Figure 5Structure of semiconductor device in manufacturing process provided for the embodiment of the present application Figure 5 ;

[0038] Figure 6 Structure of semiconductor device in manufacturing process provided for the embodiment of the present application Figure 6 ;

[0039] Figure 7 Structure of semiconductor device in manufacturing process provided for the embodiment of the present application Figure 7 ;

[0040] Figure 8 Structure of semiconductor device in manufacturing process provided for the embodiment of the present application Figure 8 ;

[0041] Figure 9 Structure of semiconductor device in manufacturing process provided for the embodiment of the present application Figure 9 ;

[0042] Figure 10 Structure of semiconductor device in manufacturing process provided for the embodiment of the present application Figure 10 ;

[0043] Figure 11 Structure of semiconductor device in manufacturing process provided for the embodiment of the present application Figure 10 ;

[0044] Figure 12 Structure of semiconductor device in manufacturing process provided for the embodiment of the present application Figure 10 ;

[0045] Figure 13 Structure of semiconductor device in manufacturing process provided for the embodiment of the present application Figure 10 ;

[0046] Figure 14 Structure of semiconductor device in manufacturing process provided for the embodiment of the present application Figure 10 ;

[0047] Figure 15 Structure of semiconductor device in manufacturing process provided for the embodiment of the present application Figure 10 ;

[0048] Figure 16 Structure of semiconductor device in manufacturing process provided for the embodiment of the present application Figure 10 ;

[0049] Figure 17 Structure of semiconductor device in manufacturing process provided for the embodiment of the present application Figure 10 ;

[0050] Figure 18 Structure of semiconductor device in manufacturing process Figure 10 Eight.

[0051] The reference signs: 11 is a substrate, 12 is a first transistor, 13 is a second transistor, 14 is a first isolation structure, 15 is a channel region, 16 is a source / drain region, 17 is a gate stack structure, 18 is a gate side wall, 19 is a first well region, 20 is a second well region, 21 is an isolation region, 22 is a source / drain contact structure, 23 is an insulating dielectric layer, 24 is a third source / drain contact structure, 25 is a first source / drain contact structure, 26 is a second source / drain contact structure, 27 is a first fin structure, 28 is a second fin structure, 29 is a sacrificial layer, 30 is a channel layer, 31 is a lower fin portion, 32 is an upper fin portion, 33 is a semiconductor isolation portion, 34 is a first mask structure, 35 is a sacrificial gate, 36 is a second isolation structure, 37 is a shallow trench isolation structure. DETAILED DESCRIPTION

[0052] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. It is to be understood, however, the description herein is merely exemplary of the application and is not intended to limit the present application. Further, in the following description, the description of well-known structures and techniques is omitted to avoid obscuring the concept of the present application.

[0053] In the drawings, various structural diagrams according to embodiments of the present application are shown. These diagrams are not drawn to scale, in which certain details are exaggerated for the purpose of clarity, and certain details can be omitted. The shapes of various regions, layers, and the relative sizes and positional relationships among them shown in the drawings are merely exemplary, and in actuality, they can be deviated due to manufacturing tolerances or technical limitations, and regions / layers having different shapes, sizes, and relative positions can be additionally designed by those skilled in the art as needed.

[0054] In the context of the present application, when a layer / element is said to be located "on" another layer / element, the layer / element can be directly located on the other layer / element, or an intervening layer / element can be present therebetween. In addition, if a layer / element is located "on" another layer / element in one orientation, it can be located "under" the other layer / element when the orientation is reversed. In order to make the technical problems to be solved by the present application, technical solutions and beneficial effects thereof more clear, the present application will be further described in detail below in conjunction with the drawings and embodiments. It should be understood that the specific embodiments described herein are merely intended to explain the present application, and are not intended to limit the present application.

[0055] In addition, the terms "first", "second", etc. are used only for descriptive purposes and are not to be construed as indicating or implying relative importance or an indicated number of technical features. Therefore, the features defined as "first", "second", etc. can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly and specifically limited.

[0056] In the description of the present application, it should be noted that, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connecting" should be understood broadly, for example, it can be fixed connection, or detachable connection, or integrally connected; it can be mechanical connection, or electrical connection; it can be directly connected, or indirectly connected through intermediate medium, or it can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0057] The three-dimensional stacked transistor includes two transistors vertically stacked along the thickness direction of the substrate, eliminates the lateral spacing of the two transistors, allows the effective channel width to be further increased, and thus helps to improve the working performance and integration of the semiconductor device.

[0058] However, in the existing three-dimensional stacked transistor, the source-drain regions included in the upper and lower transistors are substantially aligned in the direction parallel to the substrate surface. At this time, if the upward leading-out mode is adopted, the source-drain regions included in the lower transistor cannot be exposed outside the source-drain regions included in the upper transistor; if the downward leading-out mode is adopted, the source-drain regions included in the upper transistor cannot be exposed outside the source-drain regions included in the lower transistor. In the above case, it is necessary to provide a conductive structure for leading-out between the source-drain regions included in the upper and lower transistors, so as to electrically connect the blocked source-drain regions with the source-drain contact structure, thereby ensuring that the source-drain contact structures respectively electrically connected with the source-drain regions on the same side of the gate stack structure in the upper and lower transistors are isolated, preventing device failure. However, the provision of the conductive structure for leading-out between the source-drain regions included in the upper and lower transistors will result in a larger thickness of the isolation structure for isolating the source-drain regions included in the upper and lower transistors, thereby resulting in an increase in the parasitic capacitance of the semiconductor device, and the increase in the thickness of the isolation structure will also result in an increase in the leading-out length of the source-drain contact structure, resulting in an increase in the parasitic resistance of the semiconductor device, which is not conducive to improving the working performance of the semiconductor device.

[0059] To solve the above technical problems, the embodiment of the present application provides a semiconductor device and a manufacturing method thereof. In the semiconductor device provided by the embodiment of the present application, the active structure of the first transistor and the active structure of the second transistor are staggered in the direction parallel to the surface of the substrate, so as to reduce the thickness of the first isolation structure, thereby reducing the parasitic resistance and parasitic capacitance of the semiconductor device, and improving the working performance of the semiconductor device.

[0060] In the first aspect, the embodiment of the present application provides a semiconductor device. As shown in Figure 14 and Figure 15 , the semiconductor device comprises a substrate 11, a first transistor 12 and a second transistor 13. The first transistor 12 and the second transistor 13 are arranged on the substrate 11 in the thickness direction of the substrate 11, and the second transistor 13 is located above the first transistor 12. The first transistor 12 comprises a first active structure, and the second transistor 13 comprises a second active structure. The first active structure and the second active structure are staggered in the direction parallel to the surface of the substrate 11. The first active structure and the second active structure each comprise a channel region 15 and a source / drain region 16 located on both sides of the channel region 15 in the length direction.

[0061] In the above technical solution, as shown in Figures 15 to 18 , the first transistor 12 and the second transistor 13 of the semiconductor device are arranged in the thickness direction of the substrate 11. Obviously, the first transistor 12 and the second transistor 13 can constitute a three-dimensional stacked transistor (CFET device) to improve the integration of the semiconductor device. In addition, the first active structure of the first transistor 12 and the first active structure of the second transistor 13 are staggered in the direction parallel to the surface of the substrate 11. At this time, among the first transistor 12 and the second transistor 13, the two source / drain regions 16 located on the same side in the length direction of the gate stack structure 17 can be staggered in the direction parallel to the surface of the substrate 11. In other words, in the thickness direction of the substrate 11, the source / drain region 16 located below can be exposed outside the source / drain region 16 located above, so as to make the source / drain contact structure 22 formed subsequently electrically connected with the corresponding source / drain region 16 through the staggered interval therebetween, which not only prevents the device from failing due to the overlap of different source / drain contact structures 22, but also eliminates the need to set a conductive structure for leading out between them, thereby reducing the thickness of the isolation material (which can be the first isolation structure 14 in the following) for electrically insulating the source / drain regions 16 of the first transistor 12 and the second transistor 13, thereby reducing the parasitic capacitance of the semiconductor device. At the same time, due to the small thickness of the isolation material, the length of the source / drain contact structure 22 for leading out the source / drain region 16 below (or the length of the source / drain contact structure 22 for leading out the source / drain region 16 above) is also small, which reduces the parasitic resistance of the semiconductor device, and improves the working performance of the semiconductor device.

[0062] In actual application, the structure and material of the substrate are not limited in the embodiments of the present application, as long as they can be applied to the semiconductor device provided by the embodiments of the present application.

[0063] For example, the substrate can be a substrate made of any one of semiconductor materials such as silicon, silicon germanium, germanium, etc.

[0064] For example, the substrate can be a substrate made of any one of semiconductor materials such as silicon, silicon germanium, germanium, etc.

[0065] The material of the substrate can be determined according to the manufacturing process of the first transistor and the second transistor, and the lead-out direction of the source-drain contact structure included in the first transistor and the second transistor. For example, when the source-drain contact structure included in the first transistor and the second transistor is led out in the upward direction (i.e., in the manner from the first transistor to the second transistor), the substrate can be a substrate made of a semiconductor material. When the source-drain contact structure included in the first transistor and the second transistor is led out in the downward direction (i.e., in the manner from the second transistor to the first transistor), the substrate can be a substrate made of an insulating material.

[0066] In some cases, as shown in FIG. 1, the semiconductor device can further include a first isolation structure 14. Along the thickness direction of the substrate 11, the first isolation structure 14 is arranged between the source-drain region 16 included in the first transistor 12 and the source-drain region 16 included in the second transistor 13, so as to prevent electric leakage and device failure. Figures 15 to 18 In some cases, as shown in FIG. 2, the surface of the substrate 11 can include a first well region 19 and a second well region 20 arranged at intervals, and an isolation region 21 located at least between the first well region 19 and the second well region 20. Moreover, the first transistor 12 is arranged directly on the first well region 19, and the second transistor 13 is arranged above the second well region 20. In the above case, the first isolation structure 14 can be directly covered on the second well region 20 and the source-drain region 16 included in the first transistor 12, and located below the source-drain region 16 included in the second transistor 13. Alternatively, the semiconductor device can further include an insulating material directly covered on the second well region 20; and the first isolation structure 14 is covered on the insulating material and the source-drain region 16 included in the first transistor 12.

[0067] Figures 15 to 18 In some cases, as shown in FIG. 3, the surface of the substrate 11 can include a first well region 19 and a second well region 20 arranged at intervals, and an isolation region 21 located at least between the first well region 19 and the second well region 20. Moreover, the first transistor 12 is arranged directly on the first well region 19, and the second transistor 13 is arranged above the second well region 20. In the above case, the first isolation structure 14 can be directly covered on the second well region 20 and the source-drain region 16 included in the first transistor 12, and located below the source-drain region 16 included in the second transistor 13. Alternatively, the semiconductor device can further include an insulating material directly covered on the second well region 20; and the first isolation structure 14 is covered on the insulating material and the source-drain region 16 included in the first transistor 12.

[0068] In some cases, as shown in FIG. 4, the semiconductor device can further include an insulating medium layer 23, so as to reduce the risk of electric leakage of the semiconductor device, and improve the yield of the source-drain region 16 included in the second transistor 13, and improve the working performance of the semiconductor device. The insulating medium layer 23 is covered on the second transistor 13, and covered on the part of the first isolation structure 14 corresponding to the first transistor 12. Figure 15 In some cases, as shown in FIG. 4, the semiconductor device can further include an insulating medium layer 23, so as to reduce the risk of electric leakage of the semiconductor device, and improve the yield of the source-drain region 16 included in the second transistor 13, and improve the working performance of the semiconductor device. The insulating medium layer 23 is covered on the second transistor 13, and covered on the part of the first isolation structure 14 corresponding to the first transistor 12.​

[0069] The material of the insulating medium layer can include any one of silicon oxide, silicon nitride, or silicon oxynitride, etc., as long as it can be applied to the semiconductor device provided by the embodiments of the present application.

[0070] From the aspect of the conductive type, the conductive types of the first transistor and the second transistor can be the same or opposite. The specific conductive types of the first transistor and the second transistor can be set according to actual requirements.

[0071] From the aspect of the device type, the device types of the first transistor and the second transistor are not specifically limited in the embodiments of the present application, as long as they can be applied to the semiconductor device provided by the embodiments of the present application. The device types of the first transistor and the second transistor can be the same or different.

[0072] For example, the first transistor and / or the second transistor can be a fin field effect transistor or a gate-all-around transistor.

[0073] For example, in the case where the first transistor and / or the second transistor is a fin field effect transistor, the first transistor and / or the second transistor includes a source / drain region, a channel region, and a gate stack structure. The source / drain region is arranged on both sides of the channel region along the length direction, and the gate stack structure covers the top and both sides of the channel region.

[0074] For example, in the case where the first transistor and / or the second transistor is a gate-all-around transistor, the first transistor and / or the second transistor includes a source / drain region, a channel region, and a gate stack structure. The source / drain region is arranged on both sides of the channel region along the length direction. The channel region includes at least one layer of nanostructure suspended between the source / drain regions. The gate stack structure surrounds the outer periphery of each layer of nanostructure. The number of layers of nanostructure included in the channel region is not specifically limited in the embodiments of the present application.

[0075] It should be noted that the source region included in the second transistor can be located on the same side of the gate stack structure as the source region included in the first transistor along the length direction, or the drain region included in the second transistor can be located on the same side of the gate stack structure as the source region included in the first transistor along the length direction.

[0076] Secondly, because the active structures included in the first transistor and the second transistor are arranged in a staggered manner along the surface direction parallel to the substrate, when the first mask structure is selectively removed, the channel regions included in the first transistor and the second transistor can be released respectively, and the gate stack structures included in the first transistor and the second transistor can be formed respectively, so as to facilitate obtaining the first transistor and the second transistor with different gate stack structures in material and / or thickness, and realizing the regulation of the driving voltage of the first transistor and the second transistor.

[0077] In addition, as Figures 15 to 18As shown, the first active structure included by the first transistor 12 and the second active structure included by the second transistor 13 are arranged in a staggered manner along a direction parallel to the surface of the substrate 11, and the staggered interval of the two can be set according to actual requirements.

[0078] For example, along the width direction of the channel region, the interval of the channel region included by the first transistor and the channel region included by the second transistor can be greater than or equal to 10 nm and less than or equal to 40 nm. For example, the interval of the channel region included by the first transistor and the channel region included by the second transistor can be 10 nm, 12 nm, 15 nm, 18 nm, 20 nm, 22 nm, 25 nm, 28 nm, 30 nm, 32 nm, 35 nm, 38 nm, or 40 nm, etc. The interval of the channel region included by the first transistor and the channel region included by the second transistor is within the above range, which is beneficial to prevent the formation range of the source-drain region from being too small due to the small interval, and is beneficial to improve the driving performance of the semiconductor device. It can also prevent the semiconductor device from having a low lateral integration degree due to the large interval, and is beneficial to realize the miniaturization of the semiconductor device.

[0079] It should be noted that, as shown in Figure 13 and Figure 14 , the semiconductor device can further include a first semiconductor part arranged on the substrate 11, and the first semiconductor part and the first active structure are distributed laterally along the surface of the substrate 11. The second active structure is arranged above the first semiconductor part. The first isolation structure 14 directly covers both sides of the first semiconductor part along the length direction, and covers the source-drain region 16 included by the first active structure, and the first isolation structure 14 is located below the source-drain region 16 included by the second active structure.

[0080] In the actual manufacturing process, as shown in Figure 13 and Figure 14 , the first semiconductor part can be at least part of the upper fin part 32 included by the first fin structure 27 remaining after forming the channel region 15 included by the first transistor 12 and the second transistor 13. The first semiconductor part is arranged above the first well region 19.

[0081] Specifically, as shown in Figure 13 and Figure 14 , the channel region 15 included by the first active structure can be distributed in parallel with the first semiconductor part. Alternatively, the extension direction of the channel region 15 included by the first active structure can also intersect with the extension direction of the first semiconductor part, but the channel region 15 included by the first active structure is distributed in a spaced manner with the first semiconductor part.

[0082] In addition, as shown in Figure 13 and Figure 14As shown, the semiconductor device can further include a second semiconductor portion disposed above the first active structure, the second semiconductor portion and the second active structure being laterally distributed along a direction parallel to the surface of the substrate.

[0083] In actual manufacturing processes, as shown in Figure 13 and Figure 14 , the second semiconductor portion can be at least part of the lower fin portion 31 included in the second fin structure 28 remaining after forming the channel region 15 included in the first transistor 12 and the second transistor 13. The second semiconductor portion is disposed on the second well region 20. Further, the channel region 15 included in the second active structure can be distributed in parallel to the second semiconductor portion. Alternatively, the extension direction of the channel region 15 included in the second active structure can also intersect with the extension direction of the second semiconductor portion, but the channel region 15 included in the second active structure is distributed apart from the second semiconductor portion.

[0084] The structure and material of the above-mentioned first semiconductor portion and the second semiconductor portion can be set according to actual needs.

[0085] For example, as shown in Figure 13 and Figure 14 , the channel region 15 included in the first active structure can be the same in shape and / or material as the first semiconductor portion. In this case, the first semiconductor portion can be formed at the same time as the channel region 15 included in the first active structure is manufactured, which can improve the manufacturing efficiency of the semiconductor device. Further, the channel region 15 included in the first active structure in the first transistor can be self-aligned with the first semiconductor portion (at this time, the sidewall of the channel region 15 included in the first active structure is substantially aligned with the sidewall of the first semiconductor portion).

[0086] For example, as shown in Figure 13 and Figure 14 , the channel region 15 included in the second active structure can be the same in shape and / or material as the second semiconductor portion. In this case, the second semiconductor portion can be formed at the same time as the channel region 15 included in the second active structure is manufactured, which can improve the manufacturing efficiency of the semiconductor device. Further, the channel region 15 included in the second active structure can be self-aligned with the second semiconductor portion (at this time, the sidewall of the channel region 15 included in the second active structure is substantially aligned with the sidewall of the second semiconductor portion).

[0087] It is worth noting that, as shown in Figures 6 to 18As shown, in the case that the first active structure includes the channel region 15 self-aligned with the first semiconductor part, and the second active structure includes the channel region 15 self-aligned with the second semiconductor part, in the actual manufacturing process, the first fin structure 27 and the second fin structure 28 can be formed on the substrate 11 in a spaced distribution, and the source-drain region 16 on both sides of the lower fin part 31 included in the second fin structure 28 is removed by selective etching, and the source-drain region 16 on both sides of the upper fin part 32 included in the first fin structure 27 is selectively removed, so as to realize the staggered arrangement of the source-drain region 16 included in the first transistor 12 and the second transistor 13. By controlling the staggered interval of the first fin structure 27 and the second fin structure 28, the staggered arrangement interval of the active structure included in the first transistor 12 and the second transistor 13 can be accurately controlled, so as to improve the yield of the semiconductor device, and also reduce the manufacturing difficulty of the semiconductor device.

[0088] The specific structure of the first semiconductor part can be determined according to the device type of the first transistor. For example, when the first transistor is a fin field effect transistor, the first semiconductor part has the same structure and material as the channel region included in the first transistor. When the first transistor is a gate-all-around transistor, the first semiconductor part can have the same structure and material as the channel region included in the first transistor; or the first semiconductor part not only includes a nanostructure of the same material as the channel region included in the first transistor, but also includes a sacrificial layer located between the nanostructures (which is not removed in the process of forming the channel region included in the second transistor).

[0089] As for the second semiconductor part, the specific structure of the second semiconductor part can be determined according to the device type of the second transistor. For example, when the second transistor is a fin field effect transistor, the second semiconductor part has the same structure and material as the channel region included in the second transistor. When the second transistor is a gate-all-around transistor, the second semiconductor part can have the same structure and material as the channel region included in the second transistor; or the second semiconductor part not only includes a nanostructure of the same material as the channel region included in the second transistor, but also includes a sacrificial layer located between the nanostructures (which is not removed in the process of forming the channel region included in the first transistor).

[0090] In actual application, for example, Figures 16 to 18As shown, the first transistor 12 and the second transistor 13 further include a first source-drain contact structure 25 and a second source-drain contact structure 26. The first source-drain contact structure 25 is in electrical contact with one of the source-drain regions 16 included in the first active structure, and the second source-drain contact structure 26 is in electrical contact with one of the source-drain regions 16 included in the second active structure. The first source-drain contact structure 25 and the second source-drain contact structure 26 are located on the same side of the gate stack structure 17 along the length direction, and are spaced apart along the surface direction of the substrate 11. The first source-drain contact structure 25 and the second source-drain contact structure 26 extend along the surface direction perpendicular to the substrate 11. In this case, since the first active structure and the second active structure are staggered along the surface direction parallel to the substrate 11, it is not necessary to provide a lead structure between the two, which facilitates reducing the thickness of the first isolation structure 14, and reducing the parasitic capacitance and parasitic resistance of the semiconductor device. At the same time, it also facilitates reducing the space occupied by the first source-drain contact structure 25 and the second source-drain contact structure 26, and facilitating the miniaturization of the semiconductor device.

[0091] Specifically, as shown in FIG. 1, the first source-drain contact structure 25 and the second source-drain contact structure 26 can extend to the upper surfaces of the source-drain regions 16 included in the first active structure and the second active structure, respectively, from the same side of the substrate 11 along the thickness direction. Alternatively, as shown in FIG. 2, the first source-drain contact structure 25 and the second source-drain contact structure 26 can also extend to the lower surfaces of the source-drain regions 16 included in the first active structure and the second active structure, respectively, from the same side of the substrate 11 along the thickness direction. In this case, the wiring difficulty on the front surface of the semiconductor device can be reduced, and electrical interference can be avoided, which facilitates improving the electrical performance of the device. Figure 16 Figure 17 Specifically, as shown in FIG. 1, the first source-drain contact structure 25 and the second source-drain contact structure 26 can extend to the upper surfaces of the source-drain regions 16 included in the first active structure and the second active structure, respectively, from the same side of the substrate 11 along the thickness direction. Alternatively, as shown in FIG. 2, the first source-drain contact structure 25 and the second source-drain contact structure 26 can also extend to the lower surfaces of the source-drain regions 16 included in the first active structure and the second active structure, respectively, from the same side of the substrate 11 along the thickness direction. In this case, the wiring difficulty on the front surface of the semiconductor device can be reduced, and electrical interference can be avoided, which facilitates improving the electrical performance of the device.

[0092] Specifically, as shown in FIG. 1, the first source-drain contact structure 25 and the second source-drain contact structure 26 can extend to the upper surfaces of the source-drain regions 16 included in the first active structure and the second active structure, respectively, from the same side of the substrate 11 along the thickness direction. Alternatively, as shown in FIG. 2, the first source-drain contact structure 25 and the second source-drain contact structure 26 can also extend to the lower surfaces of the source-drain regions 16 included in the first active structure and the second active structure, respectively, from the same side of the substrate 11 along the thickness direction. In this case, the wiring difficulty on the front surface of the semiconductor device can be reduced, and electrical interference can be avoided, which facilitates improving the electrical performance of the device. Figure 18

[0093] In this case, the vertical extension part can extend along the surface direction perpendicular to the substrate, so as to reduce the space occupied by the third source-drain contact structure, and facilitate the miniaturization of the semiconductor device. The extension direction of the lateral extension part can be parallel to the surface direction of the substrate.

[0094] ​​In addition, if the interval between the other source-drain regions included in the first transistor and the second transistor along the direction of the surface of the substrate is small, the electrical connection between the two can be achieved by only one vertically extending portion, which can simplify the structure of the semiconductor device and reduce the manufacturing difficulty of the semiconductor device.

[0095] For the first isolation structure, along the thickness direction of the substrate, the first isolation structure is arranged between the source-drain region included in the first transistor and the source-drain region included in the second transistor. The material of the first isolation structure can include any one of silicon oxide, silicon nitride, silicon oxynitride, and the like. The first isolation structure can be a single-layer structure in which each part is made of the same material, or a laminated structure including multiple materials (the distribution of different materials can be set according to actual needs, which is not specifically limited here).

[0096] As for the thickness of the first isolation structure, it can be determined according to the requirements for the electrical insulation of the first isolation structure in the actual application scenario, and the requirements for the parasitic capacitance and parasitic resistance of the semiconductor device, which is not specifically limited here.

[0097] For example, along the thickness direction of the substrate, the thickness of the first isolation structure can be greater than or equal to 5 nm and less than or equal to 30 nm. For example, the thickness of the first isolation structure can be 5 nm, 8 nm, 10 nm, 12 nm, 15 nm, 18 nm, 20 nm, 22 nm, 25 nm, 28 nm, or 30 nm, and the like.

[0098] In some cases, as shown in Figure 15 Each part of the first isolation structure 14 can be integrally formed (i.e., formed at the same time) to simplify the manufacturing process of the semiconductor device and improve the manufacturing efficiency of the semiconductor device.

[0099] In an example, as shown in Figure 13 and Figure 14 The semiconductor device can further include a second isolation structure 36. The second isolation structure 36 is arranged between the gate stack structure 17 included in the first transistor 12 and the gate stack structure 17 included in the second transistor 13 to reduce the electrical interference between the first transistor 12 and the second transistor 13 and improve the electrical performance of the semiconductor device. The material of the second isolation structure 36 can include any one of silicon oxide or silicon nitride.

[0100] In some cases, as shown in Figure 15As shown, the semiconductor device provided by the embodiment of the present application can further include a gate side wall 18. The gate side wall 18 is arranged on both sides of the gate stack structure 17 included in the first transistor 12 and the second transistor 13 along the length direction, for spacing the gate stack structure 17 from the adjacent other conductive structures, reducing the risk of leakage. The material of the gate side wall 18 can include any one of silicon oxide, silicon nitride or silicon oxynitride, etc.

[0101] In some cases, as Figure 15 As shown, the semiconductor device provided by the embodiment of the present application can further include a shallow trench isolation structure 37. The shallow trench isolation structure 37 is formed on the substrate 11, for defining the active area of the substrate 11, reducing the risk of leakage, and further improving the yield and working performance of the semiconductor device.

[0102] As for the material of the shallow trench isolation structure, it can include any one of silicon oxide, silicon nitride or silicon oxynitride, etc., which is not specifically limited here.

[0103] In the second aspect, the embodiment of the present application provides a manufacturing method of a semiconductor device. The semiconductor device formed by the manufacturing method provided by the second aspect of the embodiment of the present application has the same structure as the semiconductor device provided by the first aspect, and therefore the beneficial effects of the second aspect and various implementation manners thereof in the embodiment of the present application can be analyzed with reference to the beneficial effects in the first aspect and various implementation manners thereof, which will not be repeated here.

[0104] The manufacturing process will be described below according to the perspective view or sectional view of Figures 1 to 18 the operation shown. Specifically, the manufacturing method of the semiconductor device includes the following steps:

[0105] First, as Figures 1 to 3 shown, the first fin structure 27 and the second fin structure 28 are formed on the substrate 11. The first fin structure 27 and the second fin structure 28 are spaced apart along the direction parallel to the surface of the substrate 11. Along the thickness direction of the substrate 11, the first fin structure 27 and the second fin structure 28 each include a lower fin portion 31, a semiconductor isolation portion 33 and an upper fin portion 32 arranged in sequence.

[0106] In the actual manufacturing process, the lower fin portion included in the first fin structure is used to manufacture the first transistor, and therefore the specific structure of the lower fin portion included in the first fin structure and the second fin structure can be determined according to the device type and structure of the first transistor.

[0107] Exemplarily, in the case that the first transistor is a fin field effect transistor, the lower fin portions of the first fin structure and the second fin structure can be single-layered strip-shaped semiconductor structures; or can also be strip-shaped semiconductor structures including multiple semiconductor layers. And the materials and widths of the lower fin portions of the first fin structure and the second fin structure are respectively the same as the material and width of the channel region of the first transistor.

[0108] Exemplarily, in the case that the first transistor is a ring gate transistor, the lower fin portions of the first fin structure and the second fin structure can include alternately stacked sacrificial layers and channel layers. In the alternately stacked sacrificial layers and channel layers, the film layer at the bottom layer and the film layer at the top layer are both sacrificial layers. Among them, the channel layers included in the lower fin portions of the first fin structure and the second fin structure are used to manufacture the nanostructure in the channel region of the first transistor, so the width of the lower fin portion and the material of the channel layer included in the lower fin portion can be determined according to the material and width of the channel region of the first transistor. As for the sacrificial layers included in the lower fin portion, the channel region of the first transistor needs to be released by removing the sacrificial layers of the lower fin portion covered by the first mask structure. And when the sacrificial layers included in the lower fin portion are selectively removed, the upper fin portion (or the channel layer included in the upper fin portion) remains, so the material of the sacrificial layers included in the lower fin portion can be any semiconductor material different from the channel layer included in the lower fin portion and the upper fin portion (or the channel layer included in the upper fin portion). For example: in the case that the materials of the channel layers included in the lower fin portion and the upper fin portion are silicon, the material of the sacrificial layers included in the lower fin portion can be germanium silicon or germanium.

[0109] Similarly, the upper fin portions included in the second fin structure are used to manufacture the second transistor, so the specific structure of the upper fin portions included in the first fin structure and the second fin structure can be determined according to the device type and structure of the second transistor.

[0110] Exemplarily, in the case that the second transistor is a fin field effect transistor, the upper fin portions of the first fin structure and the second fin structure can be single-layered strip-shaped semiconductor structures; or can also be strip-shaped semiconductor structures including multiple semiconductor layers. And the materials and widths of the upper fin portions are respectively the same as the material and width of the channel region of the second transistor.

[0111] Exemplarily, in the case that the second transistor is a ring-gate transistor, the upper fin part in the first fin structure and the second fin structure can include at least one semiconductor layer. Each semiconductor layer includes a sacrificial layer and a channel layer on the sacrificial layer. The channel layer included in the upper fin part is used to manufacture a nanostructure in the channel region included in the second transistor, and thus the material of the channel layer included in the upper fin part in the first fin structure and the second fin structure can be determined according to the material of the channel region included in the second transistor. As for the sacrificial layer included in the upper fin part, the channel region included in the second transistor needs to be released by removing the sacrificial layer of the upper fin part covered by the first mask structure. In addition, when the sacrificial layer included in the upper fin part is selectively removed, the lower fin part (or the channel layer included in the lower fin part) remains, and thus the material of the sacrificial layer included in the upper fin part can be any semiconductor material different from the channel layer included in the upper fin part and the lower fin part (or the channel layer included in the lower fin part). In addition, in the case that the first transistor and the second transistor are both ring-gate transistors, the material of the sacrificial layer included in the lower fin part and the upper fin part can be the same, so as to reduce the limitation of the epitaxial critical thickness and improve the formation quality of the semiconductor device. Of course, the materials of the lower fin part and the upper fin part can also be different.

[0112] As for the semiconductor isolation part included in the first fin structure and the second fin structure, the semiconductor isolation part plays a pre-occupying role, and the semiconductor isolation part not covered by the first mask structure will be removed later, and a first isolation structure will be formed on the source-drain region included in the first transistor and the substrate after the source-drain region included in the first transistor is formed. Thus the thickness of the semiconductor isolation part can be determined according to the thickness requirement of the first isolation structure. As for the material of the semiconductor isolation part, it can be any semiconductor material different from the lower fin part and the upper fin part, which is not limited here.

[0113] Exemplarily, as shown in FIG. 1, an epitaxial process or the like can be used to form the sacrificial layer 29 and the channel layer 30 for manufacturing the lower fin part 31 and the upper fin part 32 along the thickness direction of the substrate 11, and form the semiconductor isolation layer for manufacturing the semiconductor isolation part 33. Figure 1 Then, as shown in FIG. 2, a photolithography and etching process or the like is used to perform a patterning process on the above-mentioned sacrificial layer 29, channel layer 30, semiconductor isolation layer, and part of the substrate 11, so as to form at least two Fin structures distributed in a spaced manner. Figure 2 Next, as shown in FIG. 3, a deposition and etching process or the like can be used to form a shallow trench isolation structure 37 for defining an active region between adjacent Fin structures. The top height of the shallow trench isolation structure 37 is less than or equal to the bottom height of the sacrificial layer 29 located at the bottom layer. The part of the at least two Fin structures exposed outside the shallow trench isolation structure 37 includes the first fin structure 27 and the second fin structure 28. Figure 3

[0114] ​It should be noted that when the manufactured semiconductor device does not include the shallow trench isolation structure mentioned above, only the sacrificial layer, the channel layer and the semiconductor isolation layer can be patterned; and after the patterning process, the first fin structure and the second fin structure can be directly obtained.

[0115] Next, the upper fin portion included in the first and second fin structures is protected.

[0116] For example, such as Figure 4 As shown, a first mask structure 34 can be formed across the first fin structure 27 and the second fin structure 28 using processes such as deposition and etching. The specific structure and material of the first mask structure 34 can be set according to actual needs, as long as it can provide mask protection in the future.

[0117] For example, such as Figure 4 As shown, the first mask structure 34 may include a sacrificial gate 35. The material of the sacrificial gate 35 may include an easily removable material such as polysilicon.

[0118] For example, such as Figure 4 As shown, the first mask structure 34 may include a sacrificial gate 35 and gate sidewalls 18 located at least on both sides of the sacrificial gate 35 along its length. The material of the sacrificial gate 35 may include an easily removable material such as polysilicon. The material of the gate sidewalls 18 can be referred to above.

[0119] For example, the first mask structure described above may also include a gate oxide layer and a sacrificial gate located on the gate oxide layer. The material of the gate oxide layer may include silicon oxide or the like.

[0120] In one example, after forming the first mask structure, the semiconductor device manufacturing method further includes: removing the remaining semiconductor isolation portion using processes such as dry etching or wet etching. Next, as... Figure 4 As shown, a second isolation structure 36 is formed between the remaining lower fin 31 and the remaining upper fin 32 using processes such as deposition and etching.

[0121] It should be noted that the gate sidewalls on both sides of the first mask structure along its length can be formed simultaneously with the fabrication of the second isolation structure to improve the manufacturing efficiency of the semiconductor device. Alternatively, the second isolation structure can be fabricated using processes such as deposition and etching after the gate sidewalls have been formed.

[0122] Next, as Figure 5 As shown, dry etching or wet etching processes can be used to remove the portions of the first fin structure 27 and the second fin structure 28 exposed outside the first mask structure 34 (if the second isolation structure 36 is formed at this time, selective etching of the second isolation structure 36 is also required).

[0123] Next, a second mask structure can be formed on the substrate by deposition and etching processes, covering both sides of the lower fins included in the first fin structure and the second fin structure along the length direction. The material of the second mask structure is not limited in the embodiments of the present application. The top of the second mask structure needs to be higher than the top of the lower fin and lower than the bottom of the upper fin.

[0124] Next, a third mask structure can be formed on the substrate by deposition and etching processes, covering both sides of the upper fins included in the first fin and the second fin along the length direction; the material of the third mask structure is different from that of the second mask structure. The material of the third mask structure is not limited in the embodiments of the present application, as long as it is different from that of the second mask structure and is easy to remove.

[0125] For example, the material of the second mask structure can include silicon oxide, and the material of the third mask structure can include silicon nitride.

[0126] Next, the second mask structure can be selectively removed by wet etching or dry etching processes, so as to expose the lower fins.

[0127] Next, as shown in FIG. 3, the source / drain regions 16 can be formed on both sides of the remaining lower fins 31 in the first fin structure 27 and the second fin structure 28 under the protection of the third mask structure. Figure 6 Alternatively, in actual application, the source / drain regions can be directly formed on both sides of the remaining lower fins in the first fin structure and the second fin structure by epitaxy processes. Then, the source / drain regions located at the outer periphery of the remaining upper fins are removed by etching processes (when the semiconductor isolation portions are formed, the source / drain regions on both sides of the semiconductor isolation portions also need to be removed).

[0128] Next, as shown in FIG. 4, the source / drain regions 16 on both sides of the lower fins 31 included in the second fin structure 28 are etched and removed.

[0129] Figure 7 In actual manufacturing, a mask material can be formed on the source / drain regions on both sides of the lower fins of the first fin structure by deposition and etching processes. The source / drain regions on both sides of the lower fins of the second fin structure are exposed. Then, the source / drain regions on both sides of the lower fins of the second fin structure are selectively removed by dry etching or wet etching processes. Subsequently, the mask material on the source / drain regions on both sides of the lower fins of the first fin structure is removed.

[0130] Next, as shown in FIG. 5, the lower fins included in the first fin structure and the second fin structure are protected.

[0131] Next, as shown in FIG. 6, the lower fins included in the first fin structure and the second fin structure are protected. Figure 8 ​​

[0132] For example, such as Figure 8 As shown, a first isolation structure 14 can be formed by using processes such as deposition and etching, covering the substrate 11 and the source / drain regions 16 located on both sides of the lower fin portion 31 of the first fin structure.

[0133] Next, as Figure 9 As shown, source / drain regions 16 are formed on both sides of the remaining upper fin portion 32 in the first and second fin structures. It should be noted that... Figure 9 This is just an illustration. In the actual manufacturing process, the source and drain regions 16 located on both sides of the two upper fins 32 can be distributed at intervals along the surface direction parallel to the substrate 11. With this arrangement, when one set of source and drain regions 16 is etched, the other set of source and drain regions 16 will not be affected.

[0134] Next, as Figure 10 As shown, the source / drain regions 16 on both sides of the upper fin portion of the first fin structure are etched away. The operation process for this step can refer to the operation process for etching away the source / drain regions 16 on both sides of the lower fin portion 31 of the second fin structure described above, and will not be repeated here.

[0135] Next, as Figure 11 As shown, an insulating dielectric layer 23 covering the substrate 11 can be formed using processes such as deposition and planarization. The top of this insulating dielectric layer 23 is flush with the top of the first mask structure 34. The material of the insulating dielectric layer 23 can be referred to the previous text and will not be repeated here.

[0136] Next, as Figure 12 As shown, dry etching or wet etching processes can be used to remove at least part of the first mask structure.

[0137] It should be noted that the decision to remove the entire first mask structure or only a portion thereof can be determined based on the specific structure of the first mask structure. For example, if the first mask structure includes only a sacrificial gate or only a sacrificial gate and a gate oxide layer, the entire first mask structure needs to be removed. If the first mask structure includes both a sacrificial gate and a gate sidewall, the gate sidewall needs to be retained, meaning only a portion of the first mask structure needs to be removed.

[0138] Next, as Figures 13 to 15 As shown, a first transistor 12 is formed based on the remaining lower fin portion in the first fin structure and the source / drain region 16 adjacent to itself, and a second transistor 13 is formed based on the remaining upper fin portion in the second fin structure and the source / drain region 16 adjacent to itself.

[0139] The specific execution method of this operation can be set according to the device types of the first and second transistors and actual needs. For example, when the first and second transistors are finned field-effect transistors, after removing the first mask structure, the remaining lower fin portion in the first fin structure forms the channel region included in the first transistor. The remaining upper fin portion in the second fin structure forms the channel region included in the second transistor.

[0140] For example, in the case where the first transistor and / or the second transistor is a gate-around transistor, after removing the first mask structure, it is also necessary to remove the remaining sacrificial layer to release the channel region.

[0141] Next, as Figure 15 As shown, a gate stack structure 17 can be formed on the outer periphery of the channel region 15 using processes such as atomic layer deposition.

[0142] Next, as Figures 16 to 18 As shown, a source-drain contact structure is formed that makes electrical contact with the source-drain regions 16 included in the first transistor 12 and the second transistor 13. The specific formation process of the source-drain contact structure can be determined according to its specific structure and lead-out direction, and is not specifically limited here.

[0143] For example, such as Figure 16 As shown, etching and deposition processes can be used to form a first source-drain contact structure 25 that penetrates the first isolation structure 14 along a direction perpendicular to the surface of the substrate 11, covering one of the source-drain regions 16 included in the first transistor 12, and penetrating the portion of the insulating dielectric layer 23 at the same height as the second transistor 13. The first source-drain contact structure 25 is electrically connected to one of the source-drain regions 16 included in the first transistor 12. Next, as... Figure 16 As shown, a second source-drain contact structure 26 can be formed by etching and deposition processes, penetrating the insulating dielectric layer 23 and covering the portion above one of the source-drain regions 16 included in the second transistor 13, along a direction perpendicular to the surface of the substrate 11. The second source-drain contact structure 26 is electrically connected to the other of the source-drain regions 16 included in the second transistor 13. The first source-drain contact structure 25 and the second source-drain contact structure 26 are disposed on the same side of the first transistor 12 and the second transistor 13 along the length direction of the gate stack structure 17, and the first source-drain contact structure 25 and the second source-drain contact structure 26 are spaced apart.

[0144] In this case, the embodiments of the present invention do not specifically limit the formation order of the first source-drain contact structure and the second source-drain contact structure. The first source-drain contact structure can be formed first, followed by the second source-drain contact structure. Alternatively, the second source-drain contact structure can be formed first, followed by the first source-drain contact structure.

[0145] For example, when the source-drain contact structure includes a first source-drain contact structure and a second source-drain contact structure, and the first source-drain contact structure and the second source-drain contact structure extend downwards, such as... Figure 17 As shown, a first source-drain contact structure 25 can be formed penetrating the substrate 11 along a direction perpendicular to the surface of the substrate 11. The first source-drain contact structure 25 is electrically connected to one of the source-drain regions 16 included in the first transistor 12. Next, as... Figure 17 As shown, a second source-drain contact structure 26 is formed that penetrates the substrate 11 along a direction perpendicular to the surface of the substrate 11 and penetrates the portion of the first isolation structure 14 and the first transistor 12 at the same height. The second source-drain contact structure 26 is electrically connected to one of the source-drain regions 16 included in the second transistor 13.

[0146] In actual manufacturing, when the first and second source / drain contact structures extend downwards, processes such as chemical mechanical polishing, dry etching, and wet etching can be used to thin the substrate. Etching processes are then used to selectively etch the substrate to form contact holes, and physical vapor deposition processes are employed to form the first and second source / drain contact structures filling the contact holes. In other embodiments of the invention, during the etching of the actual contact holes, the top or bottom of the source / drain region 16 may also be etched into a plane, so that the contact surfaces of the first and second source / drain contact structures 25 and 26 with the top or bottom of the source / drain region 16 become planar. In other embodiments, the cross-section of the contact hole may also be larger than the surface area of ​​the source / drain region.

[0147] For example, such as Figure 18 As shown, a third source-drain contact structure 24 is formed that is electrically connected to both the other source-drain region 16 included in the first transistor 12 and the other source-drain region 16 included in the second transistor 13. The third source-drain contact structure 24 includes a vertical extension and a lateral extension electrically connected to the vertical extension. The vertical extension is located above and electrically connected to the other source-drain region 16 included in the first transistor 12. The lateral extension is located above or below the other source-drain region 16 included in the second transistor 13 and is used to electrically connect the vertical extension to the other source-drain region 16 included in the second transistor 13. In this way, a common-drain connection can be achieved in the SRAM cell and the inverter without wasting the overall transistor area, while also reducing the capacitance caused by device contacts.

[0148] Specifically, a mask material can be first formed on a portion of the insulating dielectric layer 23 using processes such as photolithography and etching. Then, under the protection of the mask material, contact holes are formed. Next, a third source-drain contact structure filling the contact holes is formed using processes such as physical vapor deposition.

[0149] It should be noted that the above is only a brief introduction to the manufacturing process of the source-drain contact structure, so that the person skilled in the art can easily implement the embodiments provided by the present application. The person skilled in the art can fully conceive other ways to manufacture the source-drain contact structure.

[0150] In the above description, the technical details of patterning, etching, etc. of each layer are not described in detail. However, those skilled in the art should understand that the layers, regions, etc. of the required shape can be formed by various technical means. In addition, those skilled in the art can also design methods that are not exactly the same as the methods described above in order to form the same structure. In addition, although each embodiment is described above, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0151] The embodiments of the present application are described above. However, these embodiments are only for a clearer illustration and not for limiting the scope of the present application. The scope of the present application is defined by the appended claims and their equivalents. Without departing from the scope of the present application, those skilled in the art can make various substitutions and modifications, which should fall within the scope of the present application.

Claims

1. A semiconductor device, characterized in that, include: A substrate, a first transistor, and a second transistor; the first transistor and the second transistor are disposed on the substrate at a distance along the thickness direction of the substrate, and the second transistor is located above the first transistor; The first active structure of the first transistor and the second active structure of the second transistor are offset from each other along a direction parallel to the surface of the substrate; both the first active structure and the second active structure include a channel region and source / drain regions located on both sides of the channel region along its length.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a first isolation structure; along the thickness direction of the substrate, the first isolation structure is disposed between the source / drain regions included in the first active structure and the source / drain regions included in the second active structure.

3. The semiconductor device according to claim 2, characterized in that, Along the thickness direction of the substrate, the thickness of the first isolation structure is greater than or equal to 5 nm and less than or equal to 30 nm; And / or, the various parts of the first isolation structure are integrally formed.

4. The semiconductor device according to claim 2, characterized in that, The semiconductor device further includes a first semiconductor portion disposed on the substrate, and the first semiconductor portion and the first active structure are laterally distributed along the surface of the substrate; The second active structure is disposed above the first semiconductor portion; the first isolation structure directly covers both sides of the first semiconductor portion along its length and covers the source and drain regions included in the first transistor, and the first isolation structure is located below the source and drain regions included in the second transistor.

5. The semiconductor device according to claim 4, characterized in that, The channel region included in the first active structure is distributed parallel to the first semiconductor portion; And / or, the channel region included in the first active structure has the same shape and / or material as the first semiconductor portion.

6. The semiconductor device according to any one of claims 2 to 5, characterized in that, The semiconductor device further includes a second semiconductor portion disposed above the first active structure, the second semiconductor portion and the second active structure being laterally distributed along a surface direction parallel to the substrate.

7. The semiconductor device according to claim 6, characterized in that, The channel region included in the second active structure is distributed in parallel with the second semiconductor portion; And / or, the channel region included in the second active structure has the same shape and / or material as the second semiconductor portion.

8. The semiconductor device according to claim 6, characterized in that, When the semiconductor device further includes a first semiconductor portion, the channel region included in the second active structure is aligned with the first semiconductor portion; And / or, the channel region included in the first active structure is aligned with the second semiconductor portion.

9. The semiconductor device according to claim 1, characterized in that, The first transistor and the second transistor further include a first source-drain contact structure and a second source-drain contact structure; the first source-drain contact structure is electrically contacted with one of the source-drain regions included in the first active structure, and the second source-drain contact structure is electrically contacted with one of the source-drain regions included in the second active structure. The first source-drain contact structure and the second source-drain contact structure are located on the same side along the length direction of the gate stack structure included in the first transistor and / or the second transistor, and are spaced apart along the surface direction of the substrate; the first source-drain contact structure and the second source-drain contact structure extend along the surface direction perpendicular to the substrate.

10. The semiconductor device according to claim 9, characterized in that, The first source-drain contact structure and the second source-drain contact structure extend from the same side of the substrate along the thickness direction to the upper surface of the source-drain region included in the first active structure and the second active structure, respectively; Alternatively, the first source-drain contact structure and the second source-drain contact structure extend from the same side of the substrate along the thickness direction to the lower surface of the source-drain region included in the first active structure and the second active structure, respectively.

11. The semiconductor device according to claim 9, characterized in that, The first transistor and the second transistor further include a third source-drain contact structure; the third source-drain contact structure includes a vertical extension and a lateral extension electrically in contact with the vertical extension; the vertical extension is located above the other of the source-drain regions included in the first active structure and is electrically in contact with the other of the source-drain regions included in the first active structure. The lateral extension is located above or below the other of the source / drain regions included in the second active structure, and is used to electrically connect the vertical extension to the other of the source / drain regions included in the second active structure.

12. The semiconductor device according to claim 11, characterized in that, The vertical extension extends along a surface direction perpendicular to the substrate.

13. The semiconductor device according to claim 1, characterized in that, The first transistor and the second transistor have opposite conduction types; And / or, along the width direction of the channel region, the distance between the channel region included in the first active structure and the channel region included in the second active structure is greater than or equal to 10 nm and less than or equal to 40 nm.

14. A method for manufacturing a semiconductor device, characterized in that, include: A first fin-like structure and a second fin-like structure are formed on the substrate; The first fin structure and the second fin structure are distributed at intervals along a direction parallel to the surface of the substrate; along the thickness direction of the substrate, both the first fin structure and the second fin structure include a lower fin, a semiconductor isolation portion and an upper fin, which are arranged sequentially. The upper fin portion included in the first fin structure and the second fin structure is protected, and source / drain regions are formed on both sides of the lower fin portion included in the first fin structure and the second fin structure. The source and drain regions on both sides of the lower fin portion included in the second fin structure are etched away; The lower fin portion included in the first fin structure and the second fin structure is protected, and source / drain regions are formed on both sides of the upper fin portion included in the first fin structure and the second fin structure. The source and drain regions on both sides of the upper fin portion of the first fin structure are etched away.

15. The method for manufacturing a semiconductor device according to claim 14, characterized in that, The protection of the upper fin portion included in the first fin structure and the second fin structure includes: A first mask structure is formed that spans the first fin structure and the second fin structure; Etching removes the portions of the first fin structure and the second fin structure that are exposed outside the first mask structure; A second mask structure is formed on the substrate, covering both sides of the lower fin along the length direction, including the lower fin and the upper fin. A third mask structure is formed covering both sides of the upper fin along the length direction, including the lower fin and the upper fin; the material of the third mask structure is different from the material of the second mask structure; The second mask structure is selectively removed.

16. The method for manufacturing a semiconductor device according to claim 14, characterized in that, The protection of the lower fin portion included in the first fin structure and the second fin structure includes: A first isolation structure is formed covering both sides of the lower fin portion of the second fin structure along its length and covering the already formed source / drain region.

17. The method for manufacturing a semiconductor device according to claim 14, characterized in that, The method for manufacturing the semiconductor device after etching away the source / drain regions on both sides of the upper fin portion of the first fin structure further includes: Using semiconductor technology, a first transistor is formed based on the remaining lower fin portion of the first fin structure and the source / drain region adjacent to it, and a second transistor is formed based on the remaining upper fin portion of the second fin structure and the source / drain region adjacent to it.

18. The method for manufacturing a semiconductor device according to claim 17, characterized in that, After forming the first transistor and the second transistor, the method for manufacturing the semiconductor device further includes: A first source-drain contact structure is formed that is electrically connected to one of the source-drain regions included in the first transistor; A second source-drain contact structure is formed to electrically contact one of the source-drain regions included in the second transistor; the first source-drain contact structure and the second source-drain contact structure are located on the same side along the length direction of the first transistor and / or the gate stack structure included in the second transistor, and are spaced apart; the first source-drain contact structure extends along a surface direction perpendicular to the substrate.

19. The method for manufacturing a semiconductor device according to claim 17, characterized in that, After forming the first transistor and the second transistor, the method for manufacturing the semiconductor device further includes: A third source-drain contact structure is formed that is electrically connected to both the other source-drain region included in the first transistor and the other source-drain region included in the second transistor. The third source-drain contact structure includes a vertical extension and a lateral extension electrically contacting the vertical extension. The vertical extension is located above and electrically contacting the other source-drain region included in the first transistor. The lateral extension is located above or below the other source-drain region included in the second transistor and is used to electrically connect the vertical extension to the other source-drain region included in the second transistor.

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