Single photon avalanche diode device and manufacturing method thereof
By forming a single-photon avalanche diode unit in bulk silicon and monolithically integrating it with a thin-film fully depleted silicon-on-insulator transistor, the high power consumption problem of single-photon avalanche diode devices is solved, achieving a combination of high detection performance and ultra-low power consumption, and expanding the application scenarios for battery-free operation.
Patent Information
- Application Number
- CN202511002246.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-18
- Publication Date
- 2025-11-04
AI Technical Summary
In the existing technology, single-photon avalanche diode devices have high power consumption after integration with standard CMOS processes, which makes it difficult to meet the requirements for low power consumption, and they fail to effectively combine the high detection sensitivity with the ultra-low power consumption characteristics of thin-film fully depleted silicon-on-insulator transistors.
By forming a single-photon avalanche diode unit in bulk silicon and monolithically integrating it with a thin-film fully depleted silicon-on-insulator transistor, and using the thin-film fully depleted silicon-on-insulator transistor as a passive quenching circuit element, a series connection is formed to achieve a combination of high detection performance and ultra-low power consumption.
It significantly reduces the static and dynamic power consumption of the device system, simplifies the circuit structure, saves chip area, and expands the application scenarios for battery-free operation, making it particularly suitable for IoT devices and long-term autonomous space probes in orbit.
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Figure CN120897537A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor technology, and in particular to a single photon avalanche diode device and a manufacturing method thereof. BACKGROUND
[0002] A single photon avalanche diode (SPAD) is a kind of photoelectric detector with extremely high internal gain, and its sensitivity can reach the level of a single photon. At present, in order to facilitate system integration and reduce manufacturing cost, SPAD devices are mostly integrated with standard complementary metal oxide semiconductor (CMOS) process. However, the traditional CMOS process has limitations in power consumption control, especially in application scenarios with strict requirements on power consumption, it is difficult for SPAD systems based on standard CMOS process to meet the requirements of low power consumption or even passive operation.
[0003] On the other hand, thin film fully depleted silicon-on-thin-BOX (SOTB) is an advanced low-power semiconductor process technology. SOTB technology effectively suppresses the leakage current by introducing a thin buried oxide (BOX) layer between the substrate and the top layer of silicon. Its outstanding advantage is that it simultaneously realizes extremely low operating current and extremely low standby current, breaking the limitation that the two cannot be achieved in traditional processes. This makes SOTB technology very suitable for extremely low-power applications that are driven by harvesting environmental energy (i.e. energy harvesting), such as Internet of Things (IoT) devices, wearable medical devices, and sensor nodes deployed in remote or special environments (such as space).
[0004] The inventors have found in their research that the prior art lacks a technical solution that combines the high detection sensitivity of SPAD with the ultra-low power consumption characteristics of SOTB process. Specifically, how to monolithically integrate a SPAD formed in bulk silicon with a SOTB transistor formed on a local insulating layer, and use the SOTB transistor as a SPAD ultra-low power quenching circuit element, is a technical problem that needs to be solved in the field. SUMMARY
[0005] The present application aims to solve at least part of the problems existing in the prior art. Specifically, the single photon avalanche diode (SPAD) device in the prior art is usually integrated with a standard complementary metal oxide semiconductor (CMOS) process in order to achieve high integration, but this often comes with higher power consumption, especially in the quenching circuit part. On the other hand, although there are ultra-low power consumption processes such as thin film fully depleted silicon-on-thin-BOX (SOTB), the prior art fails to provide a technical solution that effectively monolithically integrates the high detection performance of bulk silicon SPAD with the ultra-low power consumption characteristics of SOTB transistor, in order to simultaneously realize high sensitivity photon detection and extremely low system power consumption.
[0006] To achieve the above object and other related objects, the present application provides a single photon avalanche diode device, comprising:
[0007] a substrate of a first conductive type;
[0008] a single photon avalanche diode unit formed in the substrate of the first conductive type;
[0009] a buried oxide layer arranged on a local region on a surface of the substrate of the first conductive type; and
[0010] a thin-film fully-depleted silicon-on-insulator transistor formed on the buried oxide layer;
[0011] wherein the single photon avalanche diode unit and the thin-film fully-depleted silicon-on-insulator transistor are connected in series to constitute a quenching circuit for the single photon avalanche diode unit.
[0012] Preferably, the single photon avalanche diode unit comprises:
[0013] a deep well of a second conductive type formed in the substrate and serving as a cathode region of the unit;
[0014] a well of the first conductive type formed in the deep well of the second conductive type and serving as an anode region of the unit, wherein an interface region between the anode region and the cathode region forms an avalanche region;
[0015] a high-doped first-conductive-type implant region arranged in the anode region and serving as an anode of the unit; and
[0016] a well of the second conductive type in which a high-doped second-conductive-type implant region is arranged and serves as a cathode of the unit.
[0017] Preferably, the thin-film fully-depleted silicon-on-insulator transistor comprises a semiconductor layer arranged on the buried oxide layer and in which a source of the second conductive type and a drain of the second conductive type are formed.
[0018] Preferably, the anode of the single photon avalanche diode unit is electrically connected to the source of the thin-film fully-depleted silicon-on-insulator transistor.
[0019] Preferably, the first conductive type is P type and the second conductive type is N type.
[0020] Preferably, a core working voltage of the thin-film fully-depleted silicon-on-insulator transistor is 0.75 volts.
[0021] Correspondingly, the present application provides a manufacturing method of a single photon avalanche diode device, comprising:
[0022] Step one, providing a substrate of first conductive type;
[0023] Step two, forming a deep well of second conductive type in the substrate to serve as a cathode region, forming a well of first conductive type in the deep well of second conductive type to serve as an anode region, and forming a well of second conductive type;
[0024] Step three, forming a high-doped injection region of first conductive type in the anode region to constitute an anode and a high-doped injection region of second conductive type in the well of second conductive type to constitute a cathode by ion implantation process; meanwhile, forming a thin film fully-depleted silicon-on-insulator transistor and its source and drain on a partial region of the substrate surface; and
[0025] Step four, performing metal interconnection on the anode, cathode and the thin film fully-depleted silicon-on-insulator transistor to form a series connection between the single photon avalanche diode unit and the thin film fully-depleted silicon-on-insulator transistor.
[0026] Preferably, in step four, the anode is electrically connected with the source of the thin film fully-depleted silicon-on-insulator transistor.
[0027] Preferably, the first conductive type is P type and the second conductive type is N type.
[0028] As described above, the single photon avalanche diode device and its manufacturing method have the following beneficial effects:
[0029] The present application uses a thin film fully-depleted silicon-on-insulator transistor as a series quenching element of a single photon avalanche diode unit, which takes advantage of the extremely low leakage current and operating voltage characteristics of the transistor, significantly reducing the static and dynamic power consumption of the quenching circuit and even the entire device system. This makes the device have the potential to work without a battery relying on energy harvesting technology, greatly expanding its application scenarios.
[0030] The series structure of the present application is essentially a passive quenching circuit, which is simpler in structure than complex active quenching and reset circuits, does not require additional control logic, thereby saving valuable chip area and improving the integration density of the device. BRIEF DESCRIPTION OF DRAWINGS
[0031] Figure 1 A single photon avalanche diode device provided by an embodiment of the present application is shown in the schematic diagram;
[0032] Figure 2 A process flow diagram of the present application is shown. DETAILED DESCRIPTION
[0033] Following, the advantages and effects of the present application will be described in detail by specific examples. Other advantages and effects of the present application can be easily understood by those skilled in the art from the description. The present application can also be implemented or applied by other different specific embodiments, and the details in the description can be modified or changed based on different views and applications without departing from the spirit of the present application.
[0034] Please refer to Figure 1 The embodiment of the present application provides a single photon avalanche diode device, comprising:
[0035] a substrate 101 of a first conductive type;
[0036] a single photon avalanche diode unit formed in the substrate 101 of the first conductive type;
[0037] a buried oxide layer 105 arranged on a local region on the surface of the substrate 101 of the first conductive type; and
[0038] a thin film fully-depleted silicon-on-insulator transistor 106 formed on the buried oxide layer 105; wherein the single photon avalanche diode unit and the thin film fully-depleted silicon-on-insulator transistor 106 are connected in series.
[0039] The present application realizes the combination of high detection performance and ultra-low power quenching circuit by monolithic integration of the single photon avalanche diode unit in the bulk silicon and the thin film fully-depleted silicon-on-insulator transistor 106 formed on the local insulating layer, and provides a new technical solution for developing high-energy efficiency and high-integration optical detection system.
[0040] In some embodiments, the first conductive type is P type and the second conductive type is N type. This configuration of conductive type is compatible with the current mainstream complementary metal oxide semiconductor process, which is convenient for manufacturing by using the existing process platform, thereby significantly reducing the development and production cost. It should be understood that those skilled in the art can replace all the first conductive type with N type and all the second conductive type with P type according to the design needs, and the technical effects of the present application can also be achieved, and this exchange scheme also falls within the protection scope of the present application.
[0041] In some embodiments, the single photon avalanche diode unit includes: a deep second-conductivity-type well 102 formed in the substrate 101 and serving as a cathode region of the unit; a first-conductivity-type well 103 formed in the deep second-conductivity-type well 102 and serving as an anode region of the unit, wherein an interface region between the anode region and the cathode region forms an avalanche region 104; a high-doped first-conductivity-type implant region 109 disposed in the anode region and serving as an anode of the unit; and a second-conductivity-type well 107 in which a high-doped second-conductivity-type implant region 108 is disposed and serving as a cathode of the unit. The structure effectively electrically isolates the light-sensitive core region from the substrate 101 through the deep second-conductivity-type well 102, preventing crosstalk of substrate 101 noise. At the same time, by disposing the avalanche region 104 at the interface between the deep second-conductivity-type well 102 and the first-conductivity-type well 103, the junction depth and electric field distribution can be precisely controlled, and the uniformity of photon detection efficiency and breakdown voltage can be optimized. The high-doped implant regions on the surface of the deep buried cathode region (deep second-conductivity-type well 102) and anode region (first-conductivity-type well 103) are respectively set as electrode lead-out ends, which is a reliable way to achieve low-impedance ohmic contact and ensure stable operation of the device.
[0042] In some embodiments, the thin-film fully-depleted silicon-on-insulator transistor 106 includes a semiconductor layer disposed on the buried oxide layer 105 and has a second-conductivity-type source and a second-conductivity-type drain formed in the semiconductor layer. Due to its fully-depleted channel and underlying insulating layer, the transistor has extremely low leakage current, thereby achieving ultra-low operating power consumption and standby power consumption.
[0043] In some embodiments, the core operating voltage of the thin-film fully-depleted silicon-on-insulator transistor 106 is 0.75 volts. This extremely low operating voltage significantly reduces the total power consumption of the entire device system, enabling it to operate by harvesting weak environmental energy (such as light energy, thermal energy, etc.), thus realizing the possibility of battery-free operation, and is therefore particularly suitable for application scenarios with extreme requirements for power consumption and endurance, such as long-standby Internet of Things nodes, implantable medical devices, and even space probes that need to operate autonomously in orbit for a long time.
[0044] The series connection of the single photon avalanche diode unit and the thin film fully-depleted SOI transistor 106 forms a novel quenching circuit. When the single photon avalanche diode unit occurs avalanche due to the detection of photons, the large current flowing through the thin film fully-depleted SOI transistor 106 as a load generates a voltage drop, which rapidly reduces the bias voltage between the single photon avalanche diode unit to below the avalanche voltage, thereby achieving rapid "quenching" of the avalanche. Compared with the traditional active quenching circuit, the scheme of using the thin film fully-depleted SOI transistor 106 as a passive quenching element not only greatly simplifies the circuit structure and saves the chip area, but more importantly, it itself does not consume static power and only consumes energy when the avalanche occurs, perfectly matching the design goal of ultra-low power consumption.
[0045] In some embodiments, the anode of the single photon avalanche diode unit is electrically connected to the source of the thin film fully-depleted SOI transistor 106. This specific connection structure is simple and easy to implement, and can efficiently use the on-state resistance of the transistor to complete the voltage clamping of the diode and achieve reliable quenching function.
[0046] The embodiment of the present application also provides a preparation method of a single photon avalanche diode device, comprising the following steps:
[0047] Step one, providing a substrate 101 of a first conductivity type. For example, a single crystal silicon wafer doped with P type can be provided.
[0048] Step two, forming a deep well 102 of a second conductivity type in the substrate 101 to serve as a cathode region, forming a well 103 of the first conductivity type in the deep well 102 of the second conductivity type to serve as an anode region, and forming a well 107 of the second conductivity type. Specifically, this step can be achieved by multiple high-energy ion implantation and subsequent thermal annealing process. For example, first, the area of the deep well 102 of the second conductivity type is defined by a first photolithography mask, and ion implantation of the second conductivity type impurities (such as phosphorus or arsenic) with high energy and accurate dose is performed to form the deep well 102 of the second conductivity type. Then, the area of the well 103 of the first conductivity type is defined in the deep well 102 of the second conductivity type by using a second photolithography mask, and ion implantation of the first conductivity type impurities (such as boron) with low energy is performed. At the same time, the area of the well 107 of the second conductivity type for cathode contact is defined by using a third photolithography mask, and corresponding ion implantation is performed. After the implantation, a high-temperature rapid thermal annealing (RTA) process is usually needed to activate the implanted impurities and repair the lattice damage.
[0049] Step three, form a high concentration of the first conductivity type implant 109 in the anode region to constitute the anode, and form a high concentration of the second conductivity type implant 108 in the well 107 of the second conductivity type to constitute the cathode by ion implantation process. Meanwhile, form a thin film fully depleted SOI transistor 106 and its source and drain on the surface of the substrate 101 in a local region.
[0050] The process of forming the thin film fully depleted SOI transistor 106 on the surface of the substrate 101 in a local region can be performed simultaneously with the ion implantation described above, or in separate steps. The process can include forming a trench in a specific region of the surface of the substrate 101 using a shallow trench isolation (STI) process, then filling the trench with oxide and performing chemical mechanical planarization (CMP), and then forming a high quality semiconductor layer (typically single crystal silicon) on the oxide by epitaxial growth or amorphous silicon deposition and recrystallization. Subsequently, for the thin film fully depleted SOI transistor 106, the step typically includes gate formation (including gate oxide layer and polysilicon gate electrode deposition and etching), ion implantation of the source and drain using the gate as a self-aligned mask, spacer formation and subsequent activation annealing, and other standard CMOS processes. At the same time, the region of the anode can be defined using a fourth photolithographic mask, and a high concentration of the first conductivity type implant 109 can be formed in the surface layer of the first conductivity type well 103 by low energy, high dose ion implantation of the first conductivity type impurity. Similarly, the region of the cathode can be defined using a fifth photolithographic mask, and a high concentration of the second conductivity type implant 108 can be formed in the surface layer of the second conductivity type well 107.
[0051] Step four, perform metal interconnection on the anode, cathode and thin film fully depleted SOI transistor 106 to form a series connection between the single photon avalanche diode unit and the thin film fully depleted SOI transistor 106. This step is part of the back end of line (BEOL) metal interconnection process. Specifically, first deposit an interlayer dielectric layer (such as silicon dioxide or low-k material) on the entire wafer surface, then open contact holes at the locations where electrical connections are needed (such as the anode, cathode and source, drain and gate electrodes of the transistor) by photolithography and etching processes to expose the underlying semiconductor or polysilicon. Then, fill the metal (such as tungsten) to form a plug by physical vapor deposition (PVD) or chemical vapor deposition (CVD) and perform planarization. Finally, deposit and etch a first layer of metal (such as aluminum or copper) to form a wire to complete the electrical connection between the specified nodes.
[0052] In some embodiments, in step four, the anode is electrically connected to the source of the thin film fully depleted SOI transistor 106.
[0053] In some embodiments, the first conductivity type is P-type and the second conductivity type is N-type. With this configuration of conductivity types, the fabrication process can make the most of a standard P-type substrate 101 CMOS process line without the need for substantial modification of key process equipment and flow, thus having good process inheritance and economy.
[0054] It is to be noted that the drawings provided in the embodiments merely schematically illustrate the basic concept of the present application, and only the components related to the present application are shown in the drawings, not the number, shape and size of the components when actually implemented. The shape, number and ratio of the components when actually implemented can be arbitrarily changed, and the layout of the components can be more complicated.
[0055] The above embodiments only illustratively explain the principles and effects of the present application, and are not intended to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical thought disclosed by the present application should be covered by the claims of the present application.
Claims
1. A single photon avalanche diode device, characterized by, The application comprises: a substrate of a first conductivity type; a single photon avalanche diode unit formed in the substrate of the first conductivity type; a buried oxide layer disposed on a local region of a surface of the substrate of the first conductivity type; and a thin-film fully-depleted silicon-on-insulator transistor formed on the buried oxide layer; wherein the single photon avalanche diode unit and the thin-film fully-depleted silicon-on-insulator transistor are connected in series to form a quenching circuit for the single photon avalanche diode unit. The single photon avalanche diode unit comprises:
2. The single photon avalanche diode device of claim 1, wherein, a deep well of a second conductivity type formed in the substrate and serving as a cathode region of the unit; a well of the first conductivity type formed in the deep well of the second conductivity type and serving as an anode region of the unit, wherein an interface region of the anode region and the cathode region forms an avalanche region; a high-doped first-conductivity-type implant region disposed in the anode region and serving as an anode of the unit; and a well of the second conductivity type in which a high-doped second-conductivity-type implant region is disposed and serving as a cathode of the unit. The thin-film fully-depleted silicon-on-insulator transistor comprises a semiconductor layer disposed on the buried oxide layer and in which a source of the second conductivity type and a drain of the second conductivity type are formed.
3. The single photon avalanche diode device of claim 1, wherein: The anode of the single photon avalanche diode unit is electrically connected to the source of the thin-film fully-depleted silicon-on-insulator transistor.
4. The single photon avalanche diode device according to claim 1 or 2, characterized in that: The first conductivity type is P-type and the second conductivity type is N-type.
5. The single photon avalanche diode device according to any one of claims 1 to 3, characterized in that: The core working voltage of the thin-film fully-depleted silicon-on-insulator transistor is 0.75 volts.
6. The single photon avalanche diode device of claim 1, wherein: The application comprises:
7. A method of manufacturing a single photon avalanche diode device, characterized by, Step 1, providing a substrate of a first conductivity type; Step 2, forming a deep well of a second conductivity type in the substrate to serve as a cathode region, forming a well of the first conductivity type in the deep well of the second conductivity type to serve as an anode region, and forming a well of the second conductivity type; Step 3, forming a high-doped first-conductivity-type implant region in the anode region by an ion implantation process to form an anode, forming a high-doped second-conductivity-type implant region in the well of the second conductivity type to form a cathode, and forming a thin-film fully-depleted silicon-on-insulator transistor and its source and drain on a local region of a surface of the substrate; Step 4, performing metal interconnection on the anode, the cathode, and the thin-film fully-depleted silicon-on-insulator transistor to form a series connection of the single photon avalanche diode unit and the thin-film fully-depleted silicon-on-insulator transistor. In Step 4, the anode is electrically connected to the source of the thin-film fully-depleted silicon-on-insulator transistor. The first conductivity type is P-type and the second conductivity type is N-type.
8. The method of manufacturing a single photon avalanche diode device according to claim 7, wherein: 9. The method of manufacturing a single photon avalanche diode device according to claim 7, wherein: