Solar cell and photovoltaic module

Abstract

The invention provides a solar cell and a photovoltaic module, and the solar cell comprises a semiconductor substrate which is provided with a first surface and a second surface which are opposite to each other; the doped semiconductor layer is arranged on the first surface of the semiconductor substrate; the dielectric layer is arranged on one side, deviating from the semiconductor substrate, of the doped semiconductor layer; the dielectric layer comprises a plurality of openings, and the openings expose a partial region of the doped semiconductor layer; a plurality of holes are formed in the side, away from the semiconductor substrate, of the part, exposed out of the opening, of the doped semiconductor layer, and a circle of annular protruding part is formed on the edge of each hole; the electrode is arranged on the side, away from the semiconductor substrate, of the dielectric layer, and the electrode penetrates through the opening in the dielectric layer to be electrically connected with the doped semiconductor layer. As the electrode is formed on the doped semiconductor layer with the uneven surface, the risk that the electrode is separated from the doped semiconductor layer is reduced, and the structural reliability of the solar cell is improved.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to Chinese application No. 2025100825962, filed on January 17, 2025, entitled A Solar Cell and a Photovoltaic Module, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] The present application relates to the field of photovoltaic technology, in particular to a solar cell and a photovoltaic module. BACKGROUND

[0004] At present, solar cells are used more and more widely as a new energy alternative. Among them, photovoltaic solar cells are devices that convert the light energy of the sun into electrical energy. Specifically, solar cells use the photovoltaic principle to generate carriers, and then use electrodes to lead out the carriers, thereby facilitating the effective use of electrical energy.

[0005] The traditional high-temperature metallization process uses high-temperature silver paste to sinter on the dielectric layer such as silicon nitride, and the paste can penetrate the silicon nitride interface and form a good metal contact with the lower doped semiconductor layer. However, due to the high cost of high-temperature silver paste, the industry has been actively researching other metallization processes in recent years. SUMMARY

[0006] The present application aims to provide a solar cell and a photovoltaic module for reducing the cost of metallization process, and increasing the bonding force between the electrode and the doped semiconductor layer on the semiconductor substrate, reducing the risk of electrode separation from the doped semiconductor layer, and improving the structural stability of the solar cell.

[0007] According to a first aspect of the present application, a solar cell is provided, comprising:

[0008] a semiconductor substrate having opposite first and second faces;

[0009] a doped semiconductor layer disposed on the first face of the semiconductor substrate;

[0010] a dielectric layer disposed on the side of the doped semiconductor layer away from the semiconductor substrate; the dielectric layer comprises a plurality of openings exposing part of the doped semiconductor layer; the part of the doped semiconductor layer exposed in the openings away from the semiconductor substrate is formed with a plurality of holes, and the edges of the holes are formed with a ring-shaped protrusion;

[0011] an electrode disposed on the side of the dielectric layer away from the semiconductor substrate, the electrode being electrically connected to the doped semiconductor layer through the openings on the dielectric layer.

[0012] According to the technical scheme, compared with directly forming the electrode by using a high-temperature sintering process, the electrode can be formed by using a low-temperature metallization process at the opening, and the cost of the metallization process can be reduced. In addition, the plurality of holes are formed on the side of the exposed portion of the doped semiconductor layer in the opening away from the semiconductor substrate, the edges of the holes are formed with a ring-shaped protruding part, and the side of the exposed portion of the doped semiconductor layer in the opening away from the semiconductor substrate is formed with uneven surface features, so that the surface roughness and the specific surface area of the doped semiconductor layer at the opening are increased. Based on this, since the electrode of the solar cell is formed on the doped semiconductor layer with uneven surface, the contact area between the exposed portion of the doped semiconductor layer in the opening and the electrode is increased, which is conducive to increasing the bonding force between the electrode and the doped semiconductor layer, enhancing the connection strength between the electrode and the doped semiconductor layer, reducing the risk of the electrode being separated from the doped semiconductor layer, and improving the structural reliability of the solar cell. In addition, since the contact area between the exposed portion of the doped semiconductor layer in the opening and the electrode is increased, the contact resistance between the doped semiconductor layer and the electrode can be reduced, the contact performance can be improved, and the photoelectric conversion efficiency of the solar cell can be further improved.

[0013] In some embodiments, the width of the ring-shaped protruding part is greater than 0 μm and less than or equal to 0.3 μm. In some embodiments, the width of the ring-shaped protruding part is greater than 0 μm and less than or equal to 0.3 μm.

[0014] It is considered that if the width of the ring-shaped protruding part is too large, for example, 0.4 μm, 0.7 μm or 1 μm or more, the specific surface area of the doped semiconductor layer will be reduced, thereby reducing the surface roughness of the doped semiconductor layer and being not conducive to increasing the contact area between the electrode and the doped semiconductor layer. Therefore, the width of the ring-shaped protruding part is less than or equal to 0.3 μm.

[0015] Further, it is considered that if the width of the ring-shaped protruding part is too small, the ring-shaped protruding part is easy to break, which does not contribute to increasing the contact area between the electrode and the doped semiconductor layer, and the silicon in the ring-shaped protruding part (i.e., the silicon in the doped semiconductor layer) is easy to be pulled off by the electrode, which is not conducive to increasing the adhesion between the electrode and the doped semiconductor layer. Therefore, in some examples, the width of the ring-shaped protruding part is greater than or equal to 0.05 μm.

[0016] The width range of the ring-shaped protruding part is conducive to increasing the surface roughness of the doped semiconductor layer, thereby being conducive to increasing the contact area between the electrode and the doped semiconductor layer, increasing the bonding force between the electrode and the doped semiconductor layer, enhancing the connection strength between the electrode and the doped semiconductor layer, reducing the risk of the electrode being separated from the doped semiconductor layer, and improving the structural reliability of the solar cell.

[0017] In some embodiments, the height of the annular protrusion is greater than 0 μm and less than or equal to 0.5 μm.

[0018] If the height of the annular protrusion is too high, for example, 0.6 μm, 0.8 μm or 1 μm or more, the annular protrusion is easy to break, which does not contribute to increasing the contact area between the electrode and the doped semiconductor layer, and the annular protrusion is easy to be pulled apart by the electrode, which reduces the pulling force between the electrode and the doped semiconductor layer, and is not conducive to increasing the adhesion between the electrode and the doped semiconductor layer. Therefore, the height of the annular protrusion is less than or equal to 0.5 μm.

[0019] Further, if the height of the annular protrusion is too low, it is not conducive to increasing the surface roughness of the doped semiconductor layer. Therefore, in some examples, the height of the annular protrusion is greater than or equal to 0.001 μm.

[0020] The height range of the annular protrusion described above is conducive to increasing the surface roughness of the doped semiconductor layer, thereby increasing the contact area between the electrode and the doped semiconductor layer, increasing the adhesion between the electrode and the doped semiconductor layer, enhancing the connection strength between the two, reducing the risk of the electrode being separated from the doped semiconductor layer, and improving the structural reliability of the solar cell.

[0021] In some embodiments, the maximum radial dimension of the hole is greater than 0 μm and less than or equal to 3 μm.

[0022] If the maximum radial dimension of the hole is too large, for example, 4 μm, 5 μm or 10 μm or more, the number of holes will decrease, which will reduce the specific surface area of the doped semiconductor layer exposed in the opening part, thereby reducing the contact area between the doped semiconductor layer and the electrode, and reducing the adhesion between the electrode and the doped semiconductor layer. Therefore, the maximum radial dimension of the hole is less than or equal to 3 μm.

[0023] Further, if the maximum radial dimension of the hole is too small, it will result in a small surface roughness of the doped semiconductor layer, and it is difficult to fill the conductive material used to manufacture the electrode into the small-sized hole when forming the electrode on the doped semiconductor layer, which cannot ensure the connection strength and contact performance between the electrode and the doped semiconductor layer. Therefore, in some examples, the maximum radial dimension of the hole is greater than or equal to 0.02 μm.

[0024] The maximum radial dimension range of the hole used in the present application is conducive to increasing the surface roughness of the doped semiconductor layer, increasing the contact area between the electrode and the doped semiconductor layer, increasing the adhesion between the electrode and the doped semiconductor layer, enhancing the connection strength between the two, reducing the risk of the electrode being separated from the doped semiconductor layer, and thereby improving the structural reliability of the solar cell.

[0025] In some embodiments, the ratio of the maximum radial dimension of the hole to the width of the annular protrusion is less than or equal to 60.

[0026] If the ratio is too large, for example, 80, 90, or 100 or more, that is, the maximum radial dimension of the hole is large and the width of the annular protrusion is small, the number of holes will decrease, and the width of the annular protrusion is small, which will reduce the specific surface area of the doped semiconductor layer at the opening, thereby reducing the surface roughness of the doped semiconductor layer at the opening, and is not conducive to increasing the contact area between the electrode and the doped semiconductor layer. Therefore, the ratio of the maximum radial dimension of the hole to the width of the annular protrusion in the present application is less than or equal to 60.

[0027] Further, if the ratio is too small, that is, the width of the annular protrusion is large and the maximum radial dimension of the hole is small, which will reduce the specific surface area of the doped semiconductor layer, thereby reducing the surface roughness of the doped semiconductor layer, and is not conducive to increasing the contact area between the electrode and the doped semiconductor layer. In addition, the small maximum radial dimension of the hole will result in a small surface roughness of the doped semiconductor layer, and it is difficult to fill the conductive material used to manufacture the electrode into the small hole when forming the electrode on the doped semiconductor layer, which cannot ensure the connection strength and contact performance between the electrode and the doped semiconductor layer. Therefore, in some examples, the ratio of the maximum radial dimension of the hole to the width of the annular protrusion is greater than or equal to 0.06.

[0028] The ratio of the maximum radial dimension of the hole to the width of the annular protrusion used in the present application can be beneficial to increase the surface roughness of the doped semiconductor layer, increase the contact area between the electrode and the doped semiconductor layer, increase the bonding force between the electrode and the doped semiconductor layer, enhance the connection strength between the two, reduce the risk of the electrode separating from the doped semiconductor layer, and thus improve the structural reliability of the solar cell.

[0029] In some embodiments, the portion of the doped semiconductor layer exposed at the opening away from the side of the semiconductor substrate is further formed with a plurality of discontinuous protrusions.

[0030] The discontinuous protrusions described in the present application are beneficial to increase the surface roughness of the doped semiconductor layer at the opening, thereby further increasing the contact area between the electrode and the doped semiconductor layer, increasing the bonding force between the electrode and the doped semiconductor layer, enhancing the connection strength between the two, reducing the risk of the electrode separating from the doped semiconductor layer, and improving the structural reliability of the solar cell.

[0031] In some embodiments, at least two of the holes are in contact with each other.

[0032] The two holes of the application contact each other, so that when the electrode is formed on the doped semiconductor layer, the conductive material for manufacturing the electrode formed in the two or more holes in contact with each other is electrically connected together, so that the bonding force between the electrode and the doped semiconductor layer can be increased, the connection strength between the two can be enhanced, the risk of the electrode being separated from the doped semiconductor layer can be reduced, and the structural reliability of the solar cell can be improved.

[0033] In some embodiments, the doped semiconductor layer includes a doped polysilicon layer, and the doped semiconductor layer further includes: amorphous silicon disposed on a side of the doped polysilicon layer away from the semiconductor substrate at a portion of the doped semiconductor layer exposed to the opening.

[0034] With the above technical solution, after the opening of the dielectric layer, it is necessary to use etching liquid to etch and remove the residue. Since the amorphous silicon has good corrosion resistance, the amorphous silicon is distributed on the side of the doped polysilicon layer away from the semiconductor substrate at a portion of the doped semiconductor layer exposed to the opening. In this way, the amorphous silicon can protect the underlying doped polysilicon layer, prevent the underlying doped polysilicon layer from being severely corroded by the etching liquid, and thus cause severe recombination. Moreover, the amorphous silicon has good passivation effect, which is conducive to reducing the recombination caused by the direct contact between the doped polysilicon layer and the electrode.

[0035] In some embodiments, the doped semiconductor layer includes a doped polysilicon layer, and the doped semiconductor layer further includes: amorphous silicon located at an edge of the opening of the dielectric layer and below the dielectric layer and disposed on a side of the doped polysilicon layer away from the semiconductor substrate.

[0036] With the above technical solution, after the opening of the dielectric layer, it is necessary to use etching liquid to etch and remove the residue. When the etching liquid is used to etch and remove the residue, the edge of the opening of the dielectric layer and the portion below the dielectric layer will also be side-etched. In this case, since the amorphous silicon has good corrosion resistance, the amorphous silicon is distributed on the side of the doped polysilicon layer away from the semiconductor substrate at the edge of the opening of the dielectric layer and below the dielectric layer. In this way, the amorphous silicon can protect the underlying doped polysilicon layer, prevent the underlying doped polysilicon layer from being severely corroded by the etching liquid, and thus cause severe recombination. Moreover, the amorphous silicon has good passivation effect, which is conducive to reducing the recombination caused by the direct contact between the doped polysilicon layer and the electrode.

[0037] In some embodiments, the length of the amorphous silicon distributed in the direction parallel to the semiconductor substrate from the edge of the opening of the dielectric layer is greater than 0 μm and less than or equal to 6 μm.

[0038] With the above technical solution, if the length range of the amorphous silicon is too large, the lateral transmission resistance of the amorphous silicon is larger than that of the polycrystalline silicon, which is not conducive to the lateral transmission of the carriers and reduces the photoelectric conversion efficiency of the solar cell. In addition, if the length range of the amorphous silicon is large, a large amount of heat is required when forming the opening in the dielectric layer, and a large amount of heat can cause excessive damage to the doped semiconductor layer when forming the opening in the dielectric layer, thereby causing poor passivation effect of the doped semiconductor layer. Therefore, the length of the amorphous silicon from the edge of the opening of the dielectric layer along the direction parallel to the semiconductor substrate is less than or equal to 6 μm.

[0039] Further, considering that if the length range of the amorphous silicon is too small, in the case of serious side etching, the effect of preventing corrosion cannot be effectively achieved, therefore in some examples, the length of the amorphous silicon from the edge of the opening of the dielectric layer along the direction parallel to the semiconductor substrate is greater than or equal to 0.001 μm.

[0040] In some embodiments, the depth of the amorphous silicon along the thickness direction of the semiconductor substrate is greater than 0 nm and less than or equal to 350 nm.

[0041] With the above technical solution, considering that if the depth of the amorphous silicon is too large, the transmission resistance of the carriers will be large, which will affect the electrical performance of the solar cell, therefore the depth of the amorphous silicon is less than or equal to 350 nm.

[0042] Further, considering that if the depth of the amorphous silicon is too small, it cannot protect the lower doped semiconductor layer and prevent the lower doped semiconductor layer from being damaged by the corrosion liquid, and cannot effectively passivate the surface of the doped polycrystalline silicon, therefore in some examples, the depth of the amorphous silicon is greater than or equal to 0.001 nm.

[0043] In some embodiments, a gap is formed between the edge of the opening of the dielectric layer and the doped semiconductor layer below.

[0044] With the above technical solution, since hydrogen will escape from the dielectric layer under the action of laser during laser opening, the gap can provide space for hydrogen escape during laser opening, thereby facilitating the relief or avoidance of dielectric layer film explosion in the non-opening area caused by laser opening, facilitating the accurate control of the size of the opening area, and reducing the damage to the doped semiconductor layer in the non-opening area caused by laser opening, and effectively ensuring the passivation effect of the solar cell.

[0045] In some embodiments, the doped semiconductor layer includes a doped polysilicon layer, and the doped semiconductor layer further includes: amorphous silicon located at edges of the opening of the dielectric layer and below the dielectric layer, and disposed on a side of the doped polysilicon layer away from the semiconductor substrate; and a length of the amorphous silicon distributed along a direction parallel to the semiconductor substrate layer from the edges of the opening of the dielectric layer is greater than a length of the aperture.

[0046] According to the above technical solution, after the dielectric layer is opened, the residual needs to be removed by using an etching liquid. In the process of removing the residual by using the etching liquid, the etching liquid is more likely to remain in the aperture and is not easy to flow out. In order to prevent the etching liquid from corroding the doped polysilicon in the aperture and causing damage to the doped polysilicon, in some embodiments of the present application, amorphous silicon is formed on a side of the doped polysilicon layer away from the semiconductor substrate at edges of the opening of the dielectric layer and below the dielectric layer, and a length of the amorphous silicon distributed is greater than a length of the aperture.

[0047] In some embodiments, the aperture includes at least one metal material in the electrode.

[0048] According to the above technical solution, the aperture includes at least one metal material in the electrode, which can increase the contact area between the electrode and the doped semiconductor layer, thereby reducing the contact resistance between the electrode and the doped semiconductor layer, increasing the bonding force between the electrode and the doped semiconductor layer, reducing the risk of the electrode being separated from the doped semiconductor layer, and improving the structural reliability of the solar cell.

[0049] In some embodiments, the metal material includes one or more of nickel, copper, silver, or tin.

[0050] According to the above technical solution, the metal material is filled into the aperture, thereby increasing the contact area between the electrode and the doped semiconductor layer, reducing the contact resistance between the electrode and the doped semiconductor layer, increasing the bonding force between the electrode and the doped semiconductor layer, enhancing the connection strength between the electrode and the doped semiconductor layer, reducing the risk of the electrode being separated from the doped semiconductor layer, improving the structural reliability of the solar cell, and the metal can also block the diffusion of deep-level impurities or other metals into the doped semiconductor layer and the semiconductor substrate, thereby reducing the recombination of the doped semiconductor layer and the semiconductor substrate and reducing the loss of recombination.

[0051] In some embodiments, a portion of the doped semiconductor layer exposed to the opening has a first surface roughness on a side away from the semiconductor substrate, and a portion of the doped semiconductor layer not exposed to the opening has a second surface roughness on a side away from the semiconductor substrate, and the first surface roughness is greater than the second surface roughness.

[0052] In some embodiments, the portion of the doped semiconductor layer exposed in the opening away from the side of the semiconductor substrate has silicon oxide formed thereon.

[0053] With the above technical solution, after the medium layer is opened, the residual needs to be removed by using an etching liquid. When the residual is removed by using the etching liquid, since the silicon oxide is located above the doped semiconductor layer, the etching liquid reacts with the silicon oxide preferentially, which can reduce the etching of the next layer, i.e., the doped semiconductor layer, by the etching liquid, thereby reducing the damage caused by opening. In addition, the silicon oxide has good passivation effect, and the silicon oxide can passivate the surface of the doped semiconductor layer, which is conducive to reducing the recombination loss caused by the direct contact between the doped semiconductor layer and the electrode.

[0054] In some embodiments, the medium layer includes aluminum oxide, and the portion of the doped semiconductor layer exposed in the opening away from the side of the semiconductor substrate includes aluminum.

[0055] With the above technical solution, since aluminum is a metal element, in the case that there is residual aluminum element on the portion of the doped semiconductor layer exposed in the opening away from the side of the semiconductor substrate, the contact resistance between the electrode and the doped semiconductor layer can be reduced, which is more conducive to the shunting of the carriers, reduces the recombination rate of the carriers, and further improves the photoelectric conversion efficiency of the solar cell.

[0056] In some embodiments, the portion of the doped semiconductor layer exposed in the opening has a first thickness, and the portion of the doped semiconductor layer not exposed in the opening has a second thickness, wherein the first thickness is less than the second thickness.

[0057] With the above technical solution, the thickness of the doped semiconductor layer at the opening is less than the thickness of the doped semiconductor layer at the non-opening, which reduces the transmission distance of the carriers from the semiconductor substrate to the electrode and reduces the longitudinal transmission resistance. In particular, for a non-sintered electrode, the thickness of the doped semiconductor layer can be made smaller, thereby reducing the longitudinal transmission resistance, ensuring that the doped semiconductor layer has a higher carrier shunting capacity, reducing the recombination rate of the carriers, and further improving the photoelectric conversion efficiency of the solar cell.

[0058] In some embodiments, the portion of the doped semiconductor layer exposed in the opening has a through hole penetrating through the doped semiconductor layer.

[0059] With the above technical solution, in the case that the portion of the doped semiconductor layer exposed in the opening includes a through hole penetrating through the doped semiconductor layer, in some examples, when the electrode is formed, the material forming the electrode can directly contact the semiconductor substrate through the through hole, so that a small amount of carriers generated by the semiconductor substrate can be directly transmitted to the electrode, thereby reducing the resistance and being conducive to improving the shunting capacity of the carriers and further improving the photoelectric conversion rate of the solar cell.

[0060] In some embodiments, the edge region of the opening includes residual material of the dielectric layer. Since the edge region of the opening has more defects, the recombination of carriers is more serious, thus part of the material of the dielectric layer is reserved at the edge of the opening, so as to passivate the edge of the opening, reduce the recombination, and improve the photoelectric conversion rate of the solar cell.

[0061] In some embodiments, the middle region of the opening includes residual material of the dielectric layer. Considering that the middle region of the opening is subjected to laser or wet method for a longer time when the opening on the dielectric layer is formed, the damage to the doped semiconductor layer in the middle region is more serious, thus part of the material of the dielectric layer is reserved in the middle region of the opening, so that the material of the dielectric layer reserved in the middle region of the opening can protect the doped semiconductor layer in the middle region from being damaged seriously, and also passivate the middle region of the opening to reduce the recombination of carriers in the middle region. According to the second aspect of the present application, a photovoltaic module is provided, which includes a plurality of cell strings, each of the cell strings including a plurality of solar cells and a plurality of interconnects for connecting the plurality of solar cells in series; and each of the solar cells includes any one of the solar cells according to the first aspect of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0062] The accompanying drawings, which are included to provide a further understanding of the present application, form a part of the present application and illustrate the illustrative embodiments of the present application and together with the description serve to explain the present application. In the drawings:

[0063] Figure 1 A first structure cross-sectional view of a solar cell according to an embodiment of the present application;

[0064] Figure 2 A second structure cross-sectional view of a solar cell according to an embodiment of the present application;

[0065] Figure 3 An opening diagram of a solar cell after laser opening according to an embodiment of the present application;

[0066] Figure 4 A topography diagram of a doped semiconductor layer of a solar cell at an opening according to an embodiment of the present application;

[0067] Figure 5 A cross-sectional structure diagram of a solar cell according to an embodiment of the present application;

[0068] Figure 6 A surface oxygen element scanning diagram of a solar cell after laser opening according to an embodiment of the present application;

[0069] Figure 7A third structure cross-sectional view of a solar cell according to an embodiment of the present application is provided.

[0070] In the drawing: 11 is a semiconductor substrate, 12 is a doped semiconductor layer, 13 is a dielectric layer, 14 is an opening, 15 is a hole, 16 is a ring-shaped protrusion, 17 is an electrode, 17-1 is a connecting electrode, 17-2 is a conductive contact layer, 19 is a second passivation layer, 20 is a first passivation layer, 21 is a discontinuous protrusion, and 22 is a pore. DETAILED DESCRIPTION

[0071] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. It is to be understood, however, that the description is merely exemplary of the present application, and is not intended to limit the present application. Further, in the following description, the description of well-known structures and techniques is omitted to avoid obscuring the concept of the present application.

[0072] Various structure diagrams according to embodiments of the present application are shown in the drawings. These diagrams are not drawn to scale, in which some details are exaggerated and some are omitted in the interest of clarity. The shapes of various regions, layers, and the relative sizes and positions of them shown in the drawings are merely exemplary, and in actuality, they can be deviated due to manufacturing tolerances or technical limitations, and regions / layers having different shapes, sizes, and relative positions can be additionally designed by those skilled in the art according to actual needs.

[0073] In the context of the present application, when a layer / element is said to be located "on" another layer / element, the layer / element can be directly located on the other layer / element, or an intervening layer / element can be present therebetween. In addition, if a layer / element is located "on" another layer / element in one orientation, it can be located "under" the other layer / element when the orientation is reversed. In order to make the technical problems to be solved, technical solutions and beneficial effects of the present application more clear, the present application will be further described in detail below in conjunction with the drawings and embodiments. It should be understood that the specific embodiments described herein are merely intended to explain the present application, and not to limit the present application.

[0074] Further, the terms "first", "second", etc. are used only for descriptive purposes and should not be construed as indicating or implying relative importance or a specific number of the technical features indicated. Thus, the features defined with "first", "second", etc. can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly and specifically limited. The meaning of "several" is one or more, unless otherwise explicitly and specifically limited.

[0075] In the description of the present application, it should be noted that unless specifically defined and limited otherwise, the terms "mounting", "connecting", "connection" should be understood broadly, for example, it can be fixed connection, or detachable connection, or integrally connected; it can be mechanical connection, or electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, or it can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0076] The existing solar cell generally includes a semiconductor substrate, a doped semiconductor layer, a dielectric layer and an electrode. The light-facing surface and / or the back surface of the semiconductor substrate is formed with the doped semiconductor layer. The dielectric layer is formed on the side of the doped semiconductor layer away from the semiconductor substrate as a surface passivation layer and / or an anti-reflection layer, wherein the surface passivation layer is used to passivate the surface defects on the side of the doped semiconductor layer away from the semiconductor substrate, and reduce the carrier recombination efficiency of the doped semiconductor layer; the anti-reflection layer is used to reduce the reflection of incident light and improve the light absorption rate of the semiconductor substrate. The electrode at least partially penetrates the dielectric layer and is in electrical contact with the doped semiconductor layer to lead out the carriers collected by the doped semiconductor layer and form a photoelectric current.

[0077] In actual application process, screen printing, electroplating or physical vapor deposition process can be used to form the above electrode. At present, screen printing process is generally used to form the electrode, and high-temperature silver paste is used as the material for manufacturing the electrode. The cost of the high-temperature silver paste is very high, so in the whole manufacturing cost of the solar cell, in addition to the cost of the semiconductor substrate itself, the manufacturing cost of the electrode is also very high, and therefore reducing the manufacturing cost of the electrode has become an urgent problem to be solved in the industry.

[0078] In view of this problem, the industry removes part of the dielectric layer at the interface of the dielectric layer such as silicon nitride to form a bare doped semiconductor layer contact window, and uses a low-temperature metallization process to manufacture the electrode, for example, using a low-temperature paste instead of a high-temperature silver paste, or using an electroplating process to form the electrode. However, the bonding force between the electrode formed by the low-temperature metallization process and the doped semiconductor layer is lower than the bonding force provided by the intermetallic compound formed by the internal glass body of the silver paste and the silicon interface in the electrode manufactured by the high-temperature silver paste, so that the electrode is at a higher risk of being separated from the doped semiconductor layer, and the structural reliability of the solar cell is reduced.

[0079] To solve the above technical problems, the present application provides a solar cell. In terms of the type of the cell, the solar cell provided by the present application includes but is not limited to any of the following photovoltaic cells capable of converting light energy into electrical energy. For example, the solar cell provided by the present application can be any of the following solar cells: a tunnel oxide passivated contact (Topcon) cell, a doped poly-Si full back contact (TBC) cell, a hybrid passivated back contact (HPBC) cell, a bifacial hybrid cell, etc.

[0080] In terms of the position of the electrode, the solar cell provided by the present application can be a back contact cell, as shown in FIG. 1, in which the positive electrode and the negative electrode of the solar cell are both formed on the back side of the semiconductor substrate. Figure 1 Alternatively, the solar cell provided by the present application can be a double-sided contact cell, as shown in FIG. 2, in which the positive electrode and the negative electrode of the solar cell are formed on the light-receiving side and the back side of the semiconductor substrate, respectively. Figure 2 Alternatively, the solar cell provided by the present application can be a double-sided contact cell, as shown in FIG. 2, in which the positive electrode and the negative electrode of the solar cell are formed on the light-receiving side and the back side of the semiconductor substrate, respectively.

[0081] Referring to FIG. 1 and FIG. 2, Figures 1-3 the solar cell provided by the present application includes a semiconductor substrate 11, a doped semiconductor layer 12, a dielectric layer 13, and an electrode 17.

[0082] Here, the semiconductor substrate 11 has a first side and a second side. The first side of the semiconductor substrate 11 can correspond to the back side of the solar cell, and the second side of the semiconductor substrate 11 can correspond to the light-receiving side of the solar cell. The present application does not make specific limitations on the surface topography of the first side and the second side of the semiconductor substrate 11. For example, Figure 2 as shown in FIG. 1, both the first side and the second side of the semiconductor substrate 11 are flat surfaces. For another example, Figure 1 as shown in FIG. 2, the second side of the semiconductor substrate 11 can be a textured surface, and the first side of the semiconductor substrate 11 is at least partially flat. For another example, both the first side and the second side of the semiconductor substrate 11 are textured surfaces.

[0083] In one embodiment, the semiconductor substrate 11 can be a silicon substrate. The semiconductor substrate 11 can be of N-type or P-type, or the semiconductor substrate 11 can be of near-intrinsic conductivity type, and the crystal type of the semiconductor substrate 11 can be single crystal or polycrystal, etc.

[0084] The doped semiconductor layer 12 can be disposed on the first side of the semiconductor substrate 11. It can be understood that the doped semiconductor layer 12 can also be disposed on the second side of the semiconductor substrate 11, or the doped semiconductor layer 12 can be disposed on both the first side and the second side of the semiconductor substrate 11, as shown in FIG. 3. Figure 2

[0085] ​The forming position of the doped semiconductor layer 12 on the semiconductor substrate 11 can be determined according to the type of the solar cell. It should be noted that the doped semiconductor layer 12 in the embodiments of the present application refers to a doped semiconductor layer with a hole formed on the side away from the semiconductor substrate at the opening of the dielectric layer, which can also be referred to as a first doped semiconductor layer; in some examples, the doped semiconductor layer 12 in the embodiments of the present application refers to a semiconductor layer with a hole formed on the side away from the semiconductor substrate at the opening of the dielectric layer, and the hole edge is formed with a ring-shaped protruding part. The third doped semiconductor layer described below is different from the doped semiconductor layer (i.e. the first doped semiconductor layer), which refers to a semiconductor layer without a hole.

[0086] For example, when the solar cell provided by the embodiments of the present application is a double-sided contact cell, the doped semiconductor layer 12 can be formed only on the first side or the second side of the semiconductor substrate 11. In this case, the conductivity type of the doped semiconductor layer 12 can be opposite to that of the semiconductor substrate 11, and at this time the solar cell further comprises a third doped semiconductor layer formed on the side of the semiconductor substrate 11 away from the doped semiconductor layer 12 and having the same conductivity type as the semiconductor substrate; or when the doped semiconductor layer is formed only on the first side or the second side of the semiconductor substrate 11, the conductivity type of the doped semiconductor layer can also be the same as that of the semiconductor substrate 11, and the solar cell further comprises a third doped semiconductor layer formed on the side of the semiconductor substrate away from the doped semiconductor layer, and the conductivity type of the third doped semiconductor layer is opposite to that of the semiconductor substrate. Of course, when the solar cell provided by the embodiments of the present application is a double-sided contact cell, the solar cell can also not include the above-mentioned third doped semiconductor layer.

[0087] Alternatively, the doped semiconductor layer 12 can also be formed on both the first side and the second side of the semiconductor substrate 11, and at this time the conductivity types of the two doped semiconductor layers 12 respectively located on the first side and the second side of the semiconductor substrate 11 are opposite.

[0088] When the solar cell provided by the embodiments of the present application is a double-sided contact cell, the doped semiconductor layer 12 can be provided on the entire first side and / or second side of the semiconductor substrate 11, or can be provided on a local area of the first side and / or second side of the semiconductor substrate 11.

[0089] Specifically, the conductivity type of the doped semiconductor layer 12 can be determined according to the actual application scenario, which is not limited here.

[0090] For example, when the solar cell provided by the embodiment of the present application is a back contact cell, the doped semiconductor layer 12 is formed on the first side of the semiconductor substrate 11. The conductive type of the doped semiconductor layer 12 can be the same as that of the semiconductor substrate 11, in which case the solar cell further comprises a third doped semiconductor layer formed on the first side of the semiconductor substrate 11 and alternating with the doped semiconductor layer 12, the conductive type of the third doped semiconductor layer being opposite to that of the semiconductor substrate 11; or the conductive type of the doped semiconductor layer 12 can be opposite to that of the semiconductor substrate 11, in which case the solar cell can comprise a third doped semiconductor layer formed on the first side of the semiconductor substrate 11 and alternating with the doped semiconductor layer 12, the conductive type of the third doped semiconductor layer being the same as that of the semiconductor substrate 11. Of course, when the solar cell provided by the embodiment of the present application is a back contact cell, the solar cell can not comprise the third doped semiconductor layer; or the conductive types of the doped semiconductor layers 12 on different regions of the first side of the semiconductor substrate 11 are opposite, and the doped semiconductor layers 12 with opposite conductive types are alternating.

[0091] When the solar cell further comprises a third doped semiconductor layer, the conductive type of the third doped semiconductor layer can be determined according to actual needs, as long as the conductive types of the doped semiconductor layer 12 and the third doped semiconductor layer are opposite. For example, the materials of the doped semiconductor layer 12 and the third doped semiconductor layer can be semiconductor materials such as silicon, germanium, silicon carbide or gallium arsenide, which can be amorphous, microcrystalline, single crystal, nanocrystalline or polycrystalline in terms of internal arrangement of the substances. The materials of the doped semiconductor layer 12 and the third doped semiconductor layer can be the same or different.

[0092] The dielectric layer 13 is arranged on the side of the doped semiconductor layer 12 away from the semiconductor substrate 11. The dielectric layer 13 is provided with a plurality of openings 14 penetrating therethrough, and the openings 14 expose at least part of the doped semiconductor layer 12. The part of the doped semiconductor layer 12 exposed in the openings 14 is formed with a plurality of holes 15 on the side away from the semiconductor substrate 11. The edges of the holes are formed with a ring-shaped protruding portion 16.

[0093] It should be noted that in the embodiment of the present application, the holes do not penetrate the doped semiconductor layer and are blind holes.

[0094] The medium layer 13 can passivate the surface of the doped semiconductor layer 12 and reduce the carrier recombination rate. Since the medium layer 13 is an insulating layer that is not conductive, the medium layer 13 is provided with a through opening 14. The opening 14 in the present application can be circular, square, or oval or other shapes. The opening 14 exposes at least part of the doped semiconductor layer 12. Moreover, the side of the part of the doped semiconductor layer 12 exposed in the opening 14 away from the semiconductor substrate 11 is provided with a plurality of holes 15. In this way, the electrode can be formed by a low-temperature metallization process at the opening 14, which can reduce the cost of the metallization process. Moreover, since the side of the part of the doped semiconductor layer 12 exposed in the opening 14 away from the semiconductor substrate 11 is provided with a plurality of holes 15, the side of the part of the doped semiconductor layer 12 exposed in the opening 14 away from the semiconductor substrate 11 has a rough surface feature, which is beneficial to increase the roughness and specific surface area of the surface of the doped semiconductor layer 12 at the opening. Based on this, compared with the prior art in which the electrode 17 is formed on the doped semiconductor layer with a relatively flat surface, when the electrode 17 in the solar cell provided by the embodiment of the present application is formed on the doped semiconductor layer 12 with a rough surface, the contact area between the part of the doped semiconductor layer 12 exposed in the opening 14 and the electrode 17 is large, which is beneficial to increase the bonding force between the electrode 17 and the doped semiconductor layer 12, enhance the connection strength between the two, reduce the risk of the electrode 17 being separated from the doped semiconductor layer 12, and improve the structural reliability of the solar cell. At the same time, since the contact area is large, the contact resistance between the electrode 17 and the doped semiconductor layer 12 can be reduced, the contact performance can be improved, and the photoelectric conversion efficiency of the solar cell can be further improved.

[0095] The material of the medium layer 13 is an insulating material. For example, the material of the medium layer 13 can include at least one of silicon nitride, silicon oxynitride, silicon carbide, and aluminum oxide. In some examples, the material of the medium layer 13 includes silicon nitride. In this case, since silicon nitride has a high resistivity, when the material of the medium layer 13 includes silicon nitride, the insulating performance of the medium layer 13 can be improved, and the passivation effect is good. Therefore, the medium layer 13 including silicon nitride passivates the surface of the doped semiconductor layer 12, which is beneficial to reduce the carrier recombination rate. In addition, since silicon nitride also has a good antireflection effect, the photoelectric conversion efficiency of the solar cell can be improved.

[0096] The medium layer 13 can be a single-layer structure or a multi-layer structure. In some examples, the medium layer 13 can include a passivation layer, and can further include other possible layers such as an anti-reflection layer, etc., or include a passivation layer and an anti-reflection layer arranged in a stack. The structure of the medium layer 13 is not specifically limited in the embodiments of the present application, and can be arranged as needed for the solar cell. For example, for a TBC cell, the medium layer 13 on the back light side can include a passivation layer and an anti-reflection layer arranged in a stack; for a Topcon cell, the medium layer 13 on the back light side can include an anti-reflection layer, or a passivation layer and an anti-reflection layer arranged in a stack; and the medium layer on the light side of the TBC cell and the Topcon cell can include a passivation layer and an anti-reflection layer arranged in a stack.

[0097] The thickness of the medium layer 13 can be determined according to the actual application scenario, and is not specifically limited here. Secondly, for the openings arranged in the medium layer 13, since the electrodes need to pass through the openings and penetrate the medium layer 13 to be electrically connected with the doped semiconductor layer 12, the distribution and size of the openings in the medium layer 13 can be determined according to the contact range of the electrodes 17 with the doped semiconductor layer 12 in the actual application scenario.

[0098] In some embodiments, the solar cell can further include a first passivation layer 20 between the semiconductor substrate 11 and the doped semiconductor layer 12. The first passivation layer 20 can at least passivate the surface of the semiconductor substrate 11 corresponding to the doped semiconductor layer 12, to reduce the recombination rate of the carriers on the surface of the semiconductor substrate 11. Moreover, the doped semiconductor layer 12 formed on the first passivation layer 20 can selectively collect the carriers of the corresponding conductivity type in the semiconductor substrate 11, to further improve the photoelectric conversion efficiency of the solar cell provided by the embodiments of the present application.

[0099] The first passivation layer 20 can be a single layer, or a multi-layer, or can be composed of different materials in different regions. The material of the first passivation layer 20 can be determined according to the material of the doped semiconductor layer 12. For example, when the material of the doped semiconductor layer 12 includes one or more of doped amorphous silicon, doped microcrystalline silicon, or doped nanocrystalline silicon, the first passivation layer 20 can be an intrinsic amorphous silicon layer, an intrinsic microcrystalline silicon layer, an intrinsic nanocrystalline silicon layer, or a mixed layer of at least two of the three. At this time, the doped semiconductor layer 12 and the first passivation layer 20 can form a heterojunction structure.

[0100] For example, when the doped semiconductor layer 12 is a doped polysilicon layer, the first passivation layer 20 can be a tunneling passivation layer. In this case, the doped semiconductor layer 12 and the first passivation layer 20 can form a tunneling passivation contact structure. In addition, the material of the tunneling passivation layer can include any dielectric material having a tunneling passivation effect. For example, the material of the tunneling passivation layer can include one or more of silicon oxide, aluminum oxide, titanium oxide, hafnium dioxide, gallium oxide, tantalum pentoxide, niobium pentoxide, silicon nitride, silicon carbon nitride, aluminum nitride, titanium nitride, titanium carbon nitride.

[0101] In some embodiments, the doped semiconductor layer 12 is formed only on one side of the first surface or the second surface of the semiconductor substrate 11, and the solar cell can further include a second passivation layer 19 formed on the side of the semiconductor substrate 11 away from the doped semiconductor layer 12, which can passivate the side of the semiconductor substrate 11 away from the doped semiconductor layer 12, reduce the rate of recombination of carriers on the surface of the semiconductor substrate 11, and further improve the photoelectric conversion efficiency of the solar cell. Specifically, the material and thickness of the second passivation layer 19 are not limited in the embodiments of the present application, and can refer to the material of the dielectric layer described above. For example, the material of the second passivation layer 19 can include one or more of silicon oxide, aluminum oxide, silicon nitride, etc.

[0102] The surface topography (e.g., roughness, contact area of the electrode and the doped semiconductor layer, etc.) of the part of the doped semiconductor layer 12 exposed on the side of the semiconductor substrate 11 away from the opening 14 directly affects the stability of the electrode structure, and therefore reasonable topography characteristics can solve or at least alleviate the problem of easy detachment of the electrode from the doped semiconductor layer, ensuring the structural reliability of the solar cell. For example, for the solar cell provided by the embodiments of the present application, the part of the doped semiconductor layer exposed on the side of the semiconductor substrate 11 away from the opening can have one or more of the following topography characteristics.

[0103] Referring to Figure 4 Referring to the topography of the doped semiconductor layer at the opening, it can be seen that the part of the doped semiconductor layer 12 exposed on the side of the semiconductor substrate 11 away from the opening 14 forms a plurality of holes 15. In some examples, the edge of the hole 15 forms a ring-shaped protruding portion 16. The circular (or circular-like) area surrounded by the bright circle in the figure is the hole 15, and the bright circle is a ring-shaped protruding portion 16 formed at the edge of the hole 15. In some examples, the ring-shaped protruding portion 16 can be formed by melting and re-solidifying the material of the doped semiconductor layer, similar to the form of a circular crater, which is protruding relative to the hole-in area and / or the hole-out area of the hole 15.

[0104] It should be noted that when the medium layer 13 is perforated by the laser, the morphology of the doped semiconductor layer exposed at the opening and the morphology of the doped semiconductor layer at different positions exposed at the opening can be controlled by controlling the laser parameters, such as the spot size of the laser, the laser irradiation area, the energy of the laser at different positions, etc.

[0105] It can be understood that since the annular protruding portion 16 is formed by melting and then solidifying the doped semiconductor layer, the material of the annular protruding portion 16 includes silicon when the doped semiconductor layer is a doped polysilicon layer. Compared with directly forming the electrode by using a high-temperature sintering process, the electrode can be formed by a low-temperature metallization process at the opening in the present application, which can reduce the cost of the metallization process. Moreover, by forming a plurality of holes on the side of the portion of the doped semiconductor layer exposed at the opening away from the semiconductor substrate, a ring of annular protruding portions is formed at the edges of the holes, thereby forming uneven surface features on the side of the portion of the doped semiconductor layer exposed at the opening away from the semiconductor substrate, which is beneficial to increasing the surface roughness and the specific surface area. Based on this, since the electrode of the solar cell provided by the present application is formed on the doped semiconductor layer with uneven surface, the contact area between the portion of the doped semiconductor layer exposed at the opening and the electrode is increased, which is beneficial to increasing the bonding force between the electrode and the doped semiconductor layer, enhancing the connection strength between the two, reducing the risk of the electrode being separated from the doped semiconductor layer, and improving the structural reliability of the solar cell. In addition, since the contact area between the portion of the doped semiconductor layer exposed at the opening and the electrode is increased, the contact resistance between the doped semiconductor layer and the electrode can be reduced, the contact performance can be improved, and the photoelectric conversion efficiency of the solar cell can be further improved.

[0106] When the opening is formed on the medium layer, in some examples, the medium layer in the middle region of the opening is completely removed, i.e., the middle region of the opening does not include residual material of the medium layer. This is beneficial to increasing the contact area between the electrode and the doped semiconductor layer, reducing the contact resistance, and improving the bonding force between the electrode and the doped semiconductor layer.

[0107] In other examples, the middle region of the opening includes residual material of the medium layer. In this case, part of the material of the medium layer in the middle region of the opening is removed, and part of the material of the medium layer remains. Considering that when the opening on the medium layer is formed, the middle region of the opening is subjected to the laser or the wet method for a relatively long time, the damage to the doped semiconductor layer in the middle region can be more serious. Based on this, part of the material of the medium layer remains in the middle region of the opening, which can protect the doped semiconductor layer in the middle region from being damaged seriously and can also passivate the middle region of the opening to reduce the recombination of carriers in the middle region.

[0108] In some examples, the edge region of the opening includes residual material of the dielectric layer. Since the edge region of the opening has more defects and more serious recombination of carriers, the edge region of the opening retains part of the material of the dielectric layer, which can passivate the edge region of the opening, reduce recombination, and improve the photoelectric conversion rate of the solar cell.

[0109] In other examples, the dielectric layer of the edge region of the opening is completely removed, i.e., the edge region of the opening does not include residual material of the dielectric layer. This is beneficial to increase the area of the exposed doped conductive layer, thereby increasing the contact area between the electrode and the doped semiconductor layer, reducing the contact resistance, and improving the bonding force between the electrode and the doped semiconductor layer.

[0110] It should be noted that when the dielectric layer in the middle region of the opening is completely removed, the dielectric layer in the edge region of the opening can include residual material of the dielectric layer, or the dielectric layer in the edge region of the opening can be completely removed. When the middle region of the opening includes residual material of the dielectric layer, the edge region of the opening can include residual material of the dielectric layer, or the dielectric layer in the edge region of the opening can be completely removed. When the middle region of the opening includes residual material of the dielectric layer and the edge region of the opening includes residual material of the dielectric layer, since the dielectric layer in the edge region of the opening is affected by the laser and the dielectric layer in the middle region of the opening is affected by the laser differently, the dielectric layer in the edge region of the opening, the dielectric layer in the middle region of the opening, and the dielectric layer in the non-opening region will differ, for example, in thickness, density, etc.

[0111] In some examples, the doped semiconductor layer is exposed in the opening, and the doped semiconductor layer in the edge region of the opening is formed with a ring-shaped protrusion and / or a discontinuous protrusion. In this case, the doped semiconductor layer in the middle region of the opening can be formed with a ring-shaped protrusion and / or a discontinuous protrusion, or can not be formed with a ring-shaped protrusion and / or a discontinuous protrusion.

[0112] For example, the width of the ring-shaped protrusion 16 is greater than 0 μm and less than or equal to 0.3 μm. If the width of the ring-shaped protrusion 16 is too large, for example, 0.4 μm, 0.7 μm, or 1 μm or more, the specific surface area of the doped semiconductor layer will not increase significantly, thereby reducing the surface roughness of the doped semiconductor layer and not conducive to increasing the contact area between the electrode and the doped semiconductor layer. Therefore, the width of the ring-shaped protrusion 16 is less than or equal to 0.3 μm.

[0113] Further, if the width of the annular protrusion 16 is too small, the annular protrusion 16 is easily broken, which does not contribute to increasing the contact area between the electrode and the doped semiconductor layer, and the silicon in the annular protrusion 16 (i.e. the silicon in the doped semiconductor layer) is easily pulled out by the electrode, which is not conducive to increasing the adhesion between the electrode and the doped semiconductor layer. Therefore, in some examples, the width of the annular protrusion 16 is greater than or equal to 0.05 μm.

[0114] The width of the annular protrusion 16 can be, for example, 0.05 μm, 0.07 μm, 0.09 μm, 0.1 μm, 0.15 μm, 0.2 μm or 0.3 μm.

[0115] The width range of the annular protrusion 16 is conducive to increasing the surface roughness of the doped semiconductor layer, thereby increasing the contact area between the electrode and the doped semiconductor layer, increasing the adhesion between the electrode and the doped semiconductor layer, enhancing the connection strength between the electrode and the doped semiconductor layer, reducing the risk of the electrode being separated from the doped semiconductor layer, and improving the structural reliability of the solar cell.

[0116] For example, the height of the annular protrusion 16 is greater than 0 μm and less than or equal to 0.5 μm. If the height of the annular protrusion 16 is too high, for example, 0.6 μm, 0.8 μm, 1 μm or more, the annular protrusion 16 is easily broken, which does not contribute to increasing the contact area between the electrode and the doped semiconductor layer, and the annular protrusion 16 is easily pulled out by the electrode, which reduces the pulling force between the electrode and the doped semiconductor layer, and is not conducive to increasing the adhesion between the electrode and the doped semiconductor layer. Therefore, the height of the annular protrusion 16 is less than or equal to 0.5 μm.

[0117] Further, if the height of the annular protrusion 16 is too low, it is not conducive to increasing the surface roughness of the doped semiconductor layer. Therefore, in some examples, the height of the annular protrusion 16 is greater than or equal to 0.001 μm.

[0118] The height of the annular protrusion 16 can be, for example, 0.001 μm, 0.005 μm, 0.008 μm, 0.01 μm, 0.05 μm, 0.06 μm, 0.07 μm, 0.08 μm, 0.09 μm, 0.1 μm, 0.2 μm, 0.3 μm or 0.5 μm.

[0119] The height range of the annular protrusion 16 is conducive to increasing the surface roughness of the doped semiconductor layer, thereby increasing the contact area between the electrode and the doped semiconductor layer, increasing the adhesion between the electrode and the doped semiconductor layer, enhancing the connection strength between the electrode and the doped semiconductor layer, reducing the risk of the electrode being separated from the doped semiconductor layer, and improving the structural reliability of the solar cell.

[0120] For example, the hole 15 can be a semi-spherical hole. The semi-spherical hole can be a strict semi-spherical hole, or can be an approximate semi-spherical hole, i.e., can have some small deformation relative to the semi-spherical hole, such as a deformation within an allowable tolerance range (e.g., within 5% or 10%) relative to the semi-spherical hole.

[0121] For example, the hole 15 has a maximum radial dimension greater than 0 μm and less than or equal to 3 μm. If the maximum radial dimension of the hole 15 is too large, such as 4 μm, 5 μm, or 10 μm or more, the number of holes 15 will decrease, which will reduce the specific surface area of the doped semiconductor layer exposed in the opening portion, thereby reducing the contact area between the electrode and the doped semiconductor layer and reducing the bonding force between the electrode and the doped semiconductor layer. Therefore, the maximum radial dimension of the hole 15 is less than or equal to 3 μm.

[0122] Further, if the maximum radial dimension of the hole 15 is too small, the surface roughness of the doped semiconductor layer will be small, and when forming the electrode on the doped semiconductor layer, it will be difficult to fill the conductive material used to manufacture the electrode into the small hole 15, and it will not be possible to ensure the connection strength and contact performance between the electrode and the doped semiconductor layer. Therefore, in some examples, the maximum radial dimension of the hole is greater than or equal to 0.02 μm. Optionally, the maximum radial dimension of the hole is greater than or equal to 0.02 μm and less than or equal to 0.1 μm.

[0123] For example, the maximum radial dimension of the hole 15 described above can be 0.02 μm, 0.03 μm, 0.04 μm, 0.05 μm, 0.06 μm, 0.07 μm, 0.08 μm, 0.09 μm, 0.1 μm, 0.4 μm, 0.5 μm, 0.7 μm, 0.9 μm, 1 μm, 1.5 μm, 2 μm, or 3 μm.

[0124] The use of the above-described range of maximum radial dimensions of the hole 15 is advantageous for increasing the surface roughness of the doped semiconductor layer, increasing the contact area between the electrode and the doped semiconductor layer, increasing the bonding force between the electrode and the doped semiconductor layer, enhancing the connection strength between the two, reducing the risk of the electrode detaching from the doped semiconductor layer, and thereby improving the structural reliability of the solar cell.

[0125] For example, the ratio of the maximum radial dimension of the hole 15 to the width of the annular protrusion is less than or equal to 60. If the ratio is too large, for example, 80, 90, or 100 or more, that is, the maximum radial dimension of the hole 15 is large and the width of the annular protrusion 16 is small, the number of holes 15 will be reduced, and the width of the annular protrusion 16 is small, which will reduce the specific surface area of the doped semiconductor layer at the opening, thereby reducing the surface roughness of the doped semiconductor layer at the opening, and is not conducive to increasing the contact area between the electrode and the doped semiconductor layer. Therefore, the ratio of the maximum radial dimension of the hole 15 to the width of the annular protrusion 16 is less than or equal to 60.

[0126] Further, if the ratio is too small, that is, the width of the annular protrusion 16 is large and the maximum radial dimension of the hole 15 is small, which will also reduce the specific surface area of the doped semiconductor layer, thereby reducing the surface roughness of the doped semiconductor layer, and is not conducive to increasing the contact area between the electrode and the doped semiconductor layer. And the maximum radial dimension of the hole 15 is small, which will result in a small surface roughness of the doped semiconductor layer, and when forming an electrode on the doped semiconductor layer, it is difficult to fill the conductive material used to manufacture the electrode into the small-sized hole 15, and it is difficult to ensure the connection strength and contact performance between the electrode and the doped semiconductor layer. Therefore, in some examples, the ratio of the maximum radial dimension of the hole to the width of the annular protrusion is greater than or equal to 0.06.

[0127] The ratio of the maximum radial dimension of the hole 15 to the width of the annular protrusion 16 described above can be, for example, 0.06, 0.08, 0.1, 0.2, 0.3, 1, 10, 15, 18, 20, 30, 35, 40, or 60.

[0128] The ratio of the maximum radial dimension of the hole 15 to the width of the annular protrusion 16 described above is conducive to increasing the surface roughness of the doped semiconductor layer, increasing the contact area between the electrode and the doped semiconductor layer, increasing the bonding force between the electrode and the doped semiconductor layer, enhancing the connection strength between the two, reducing the risk of the electrode separating from the doped semiconductor layer, and thereby improving the structural reliability of the solar cell.

[0129] For example, at least two holes 15 are in contact with each other, so that when forming an electrode on the doped semiconductor layer, the conductive material used to manufacture the electrode formed in the two or more holes in contact with each other is electrically connected together, which can increase the bonding force between the electrode and the doped semiconductor layer, enhance the connection strength between the two, reduce the risk of the electrode separating from the doped semiconductor layer, and improve the structural reliability of the solar cell.

[0130] Exemplarily, the part of the doped semiconductor layer exposed to the side away from the semiconductor substrate of the opening further has a plurality of discontinuous protrusions 21. The discontinuous protrusions 21 can include at least one of a dot-shaped protrusion (such as the bright dots within the circle mark in FIG. 21), a line-shaped protrusion (such as the white curve within the square frame in FIG. 22), and the like. The line-shaped protrusion can be a straight line-shaped protrusion, a curved line-shaped protrusion, a ring-shaped protrusion that is not closed, or the like. Figure 4 Figure 4 The discontinuous protrusions 21 can be distributed at any position of the part of the doped semiconductor layer exposed to the side away from the semiconductor substrate of the opening. The discontinuous protrusions 21 are beneficial to increase the surface roughness of the doped semiconductor layer at the opening, thereby further increasing the contact area between the electrode and the doped semiconductor layer, increasing the bonding force between the electrode and the doped semiconductor layer, enhancing the connection strength between the electrode and the doped semiconductor layer, reducing the risk of the electrode being separated from the doped semiconductor layer, and improving the structural reliability of the solar cell.

[0131] Exemplarily, the doped semiconductor layer includes a doped polysilicon layer, and the doped semiconductor layer further includes amorphous silicon disposed at the part of the doped polysilicon layer exposed to the side away from the semiconductor substrate of the opening. After the opening of the dielectric layer, it is necessary to use an etching liquid to etch and remove the residues. Since the amorphous silicon has good corrosion resistance, the part of the doped semiconductor layer exposed to the side away from the semiconductor substrate of the opening is distributed with amorphous silicon, so that the amorphous silicon can protect the underlying doped polysilicon layer, prevent the underlying doped polysilicon layer from being severely corroded by the etching liquid, thereby causing severe recombination, and the amorphous silicon has good passivation effect, which is beneficial to reduce the recombination caused by the direct contact between the doped polysilicon layer and the electrode.

[0132] Optionally, when the doped semiconductor layer is a doped polysilicon layer, the part of the doped semiconductor layer exposed to the side away from the semiconductor substrate of the opening can further include at least one of microcrystalline silicon and nanocrystalline silicon. The microcrystalline silicon and / or nanocrystalline silicon have beneficial effects similar to those of the amorphous silicon described above, and can be referred to the above description, which will not be repeated here.

[0133] Optionally, when the doped semiconductor layer is a doped polysilicon layer, the part of the doped semiconductor layer exposed to the side away from the semiconductor substrate of the opening can further include at least one of microcrystalline silicon and nanocrystalline silicon. The microcrystalline silicon and / or nanocrystalline silicon have beneficial effects similar to those of the amorphous silicon described above, and can be referred to the above description, which will not be repeated here.

[0134] ​For example, the doped semiconductor layer includes a doped polysilicon layer, and the doped semiconductor layer further includes amorphous silicon located at the edge of the opening of the dielectric layer and below the dielectric layer and arranged on the side of the doped polysilicon layer away from the semiconductor substrate. After the opening of the dielectric layer, the residual needs to be removed by etching with an etching solution. When the residual is removed by etching with the etching solution, the portion of the edge of the opening of the dielectric layer and below the dielectric layer will also be side-etched. In this case, since the amorphous silicon has good corrosion resistance, the amorphous silicon is distributed at the edge of the opening of the dielectric layer and below the dielectric layer on the side of the doped polysilicon layer away from the semiconductor substrate, so that the amorphous silicon can protect the underlying doped polysilicon layer, prevent the doped polysilicon layer below the amorphous silicon layer from being severely corroded by the etching solution, and thus cause severe recombination, and the amorphous silicon has good passivation effect, which is conducive to reducing the recombination loss caused by the direct contact of the doped polysilicon layer and the electrode.

[0135] For example, the length of the amorphous silicon distributed along the direction parallel to the semiconductor substrate from the edge of the opening of the dielectric layer is greater than 0 μm and less than or equal to 6 μm. Here, the length of the amorphous silicon distributed is the length from the edge of the opening of the dielectric layer along the direction parallel to the semiconductor substrate and away from the opening edge to the farthest amorphous silicon. Here, the direction parallel to the semiconductor substrate is perpendicular to the thickness direction of the semiconductor substrate.

[0136] Based on the role of the amorphous silicon described above, if the length range of the amorphous silicon distributed is too large, since the lateral transmission resistance of the amorphous silicon relative to the polysilicon is large, it is not conducive to the lateral transmission of the carriers, which will reduce the photoelectric conversion efficiency of the solar cell. In addition, if the length range of the amorphous silicon distributed is large, a large amount of heat is required when forming the opening in the dielectric layer, and a large amount of heat will cause excessive damage to the doped semiconductor layer when forming the opening in the dielectric layer, thereby causing poor passivation effect of the doped semiconductor layer. Therefore, the length of the amorphous silicon distributed along the direction parallel to the semiconductor substrate from the edge of the opening of the dielectric layer is less than or equal to 6 μm.

[0137] Further, if the length range of the amorphous silicon distributed is too small, in the case of serious side etching, the effect of preventing corrosion and the passivation effect cannot be effectively achieved, and therefore in some examples, the length of the amorphous silicon distributed along the direction parallel to the semiconductor substrate from the edge of the opening of the dielectric layer is greater than or equal to 0.001 μm.

[0138] The length of the amorphous silicon distributed described above may be, for example, 0.001 μm, 0.007 μm, 0.01 μm, 0.07 μm, 0.09 μm, 0.1 μm, 0.3 μm, 0.5 μm, 0.7 μm, 0.9 μm, 1 μm, 2 μm, 3 μm, 5 μm, or 6 μm.

[0139] For example, the amorphous silicon has a depth range of greater than 0 nm and less than or equal to 350 nm along the thickness direction of the semiconductor substrate.

[0140] In some embodiments, the amorphous silicon at the position where the portion of the doped semiconductor layer exposed in the opening is distributed with the protrusions (e.g. annular protrusions, discontinuous protrusions) on the side away from the semiconductor substrate has a greater depth than the amorphous silicon at the position where the portion of the doped semiconductor layer exposed in the opening is not distributed with the protrusions. For example, the amorphous silicon at the position where the portion of the doped semiconductor layer exposed in the opening is distributed with the protrusions on the side away from the semiconductor substrate has a depth range of greater than 0 nm and less than or equal to 350 nm, while the amorphous silicon at the position where the portion of the doped semiconductor layer exposed in the opening is not distributed with the protrusions has a depth range of greater than 0 nm and less than or equal to 50 nm. Since the protrusions are generally formed by melting and re-solidification of the material of the doped semiconductor layer, when the doped semiconductor layer is a doped polysilicon layer, the material of the protrusions is mainly amorphous silicon, and thus the amorphous silicon of the protrusions has a greater depth than the amorphous silicon of the non-protrusion position.

[0141] With the above technical solution, considering that if the depth of the amorphous silicon is too large, the transport resistance of the carriers will be large, which will affect the electrical performance of the solar cell, thus the depth of the amorphous silicon is less than or equal to 350 nm.

[0142] Further, considering that if the depth range of the amorphous silicon is too small, it cannot protect the underlying doped semiconductor layer and prevent the underlying doped semiconductor layer from being damaged by the etching liquid, and cannot effectively passivate the surface of the doped polysilicon, thus in some examples, the depth of the amorphous silicon is greater than or equal to 0.001 nm.

[0143] The depth of the amorphous silicon along the thickness direction of the semiconductor substrate may, for example, be 0.001 nm, 0.005 nm, 0.009 nm, 0.01 nm, 0.05 nm, 0.1 nm, 0.8 nm, 1 nm, 6 nm, 10 nm, 50 nm, 100 nm, 200 nm or 350 nm.

[0144] For example, referring to Figure 5 , the edge of the opening in the dielectric layer 13, a void 22 is formed between the dielectric layer 13 and the underlying doped semiconductor layer 12. Here, the size and distribution of the void 22 are not limited. Since hydrogen will escape from the dielectric layer under the action of the laser during laser opening, the void 22 can provide space for the escape of hydrogen during laser opening, thereby facilitating the relief or avoidance of dielectric layer film rupture in the non-opening area caused by laser opening, facilitating accurate control of the size of the opening area, reducing damage to the doped semiconductor layer in the non-opening area caused by laser opening, and effectively ensuring the passivation effect of the solar cell.

[0145] For example, the amorphous silicon is distributed along a direction parallel to the semiconductor substrate layer from the edge of the opening of the dielectric layer 13, and the length of the amorphous silicon is greater than the length of the aperture 22. For example, the length of the aperture is calculated from the edge of the opening of the dielectric layer to the farthest aperture along a direction parallel to the semiconductor substrate and away from the edge of the opening. Here, the direction parallel to the semiconductor substrate is perpendicular to the thickness direction of the semiconductor substrate. After the dielectric layer is opened, the residue needs to be removed by using an etching solution. During the process of removing the residue by using the etching solution, the etching solution is more likely to remain in the aperture and is not easy to flow out. In order to prevent the etching solution from corroding the doped polysilicon in the aperture and causing damage to the doped polysilicon, some embodiments of the present application are provided. The amorphous silicon is formed on the side of the doped polysilicon layer away from the semiconductor substrate at the edge of the opening of the dielectric layer and below the dielectric layer, and the length of the amorphous silicon is greater than the length of the aperture.

[0146] In some embodiments, the aperture 22 includes at least one metal material in the electrode.

[0147] The above scheme is adopted in the present application. The aperture 22 includes at least one metal material in the electrode, which can increase the contact area between the electrode and the doped semiconductor layer. In this way, the contact resistance between the electrode and the doped semiconductor layer can be reduced, and the bonding force between the electrode and the doped semiconductor layer can be increased, thereby reducing the risk of the electrode being separated from the doped semiconductor layer and improving the structural reliability of the solar cell.

[0148] In some embodiments, the metal material includes one or more of nickel, copper, silver, or tin.

[0149] The above scheme is adopted in the present application. The metal material is filled into the aperture, thereby increasing the contact area between the electrode and the doped semiconductor layer, reducing the contact resistance between the electrode and the doped semiconductor layer, increasing the bonding force between the electrode and the doped semiconductor layer, enhancing the connection strength between the electrode and the doped semiconductor layer, reducing the risk of the electrode being separated from the doped semiconductor layer, and improving the structural reliability of the solar cell. In addition, the metal can block the diffusion of deep-level impurities or other metals into the doped semiconductor layer and the semiconductor substrate, thereby reducing the recombination of the doped semiconductor layer and the semiconductor substrate and reducing the loss of recombination.

[0150] Exemplarily, the part of the doped semiconductor layer exposed in the opening has a first surface roughness on the side away from the semiconductor substrate, and the part of the doped semiconductor layer not exposed in the opening has a second surface roughness on the side away from the semiconductor substrate, the first surface roughness is greater than the second surface roughness. Exemplarily, the first surface roughness is in the range of 0-0.5 μm, and optionally, the first surface roughness is in the range of 0.3 μm-0.5 μm; the second surface roughness is in the range of 0-100 nm. The surface roughness of the part of the doped semiconductor layer exposed in the opening is greater, which can increase the contact area between the doped semiconductor layer and the electrode, is conducive to reducing the contact resistance between the electrode and the doped semiconductor layer, and is conducive to increasing the bonding force between the electrode and the doped semiconductor layer, enhancing the connection strength between the two, reducing the risk of the electrode being separated from the doped semiconductor layer, improving the structural reliability of the solar cell, and the roughness of the second surface is smaller, which can ensure that the film forming quality of the doped semiconductor layer is better.

[0151] Exemplarily, the part of the doped semiconductor layer exposed in the opening has a first surface roughness on the side away from the semiconductor substrate, and for the unexposed part of the doped semiconductor layer not exposed in the opening: it includes a first unexposed part at the opening edge of the medium layer and a remaining unexposed part except the first unexposed part, the first unexposed part has a third surface roughness on the side away from the semiconductor substrate, and the remaining unexposed part has a fourth surface roughness on the side away from the semiconductor substrate, wherein the first surface roughness > the third surface roughness > the fourth surface roughness. The surface roughness of the part of the doped semiconductor layer exposed in the opening is greater, which can increase the contact area between the doped semiconductor layer and the electrode, is conducive to reducing the contact resistance between the electrode and the doped semiconductor layer, and is conducive to increasing the bonding force between the electrode and the doped semiconductor layer, enhancing the connection strength between the two, reducing the risk of the electrode being separated from the doped semiconductor layer, and improving the structural reliability of the solar cell. In addition, when the electrode is formed, the electrode material can be formed on the first unexposed part, so the third surface roughness of the first unexposed part is greater than the fourth surface roughness, which can further enhance the bonding force between the electrode and the doped semiconductor layer, is conducive to reducing the risk of the electrode being separated from the doped semiconductor layer, thereby improving the structural stability of the solar cell.

[0152] In this embodiment, surface roughness can refer to the arithmetic mean deviation Ra of the surface profile, specifically the arithmetic mean of the absolute values ​​of the peaks and valleys (relative to the average line) of the surface profile within a sampling length Lr. In actual measurement, the more measurement points, the more accurate Ra is. Alternatively, surface roughness can also refer to the maximum height Rz of the surface profile, specifically the distance between the peak line and the valley line of the surface profile. It is understood that when dealing with the roughness of different surface regions, such as the first, second, third, and fourth surface roughness mentioned above, the same roughness measurement standard is used.

[0153] For example, refer to Figure 6 As shown, silicon oxide is formed on the side of the doped semiconductor layer exposed at the opening that faces away from the semiconductor substrate. In one embodiment, the silicon oxide on the annular protrusion 16 is relatively thick, and the silicon oxide distribution in the peripheral region of the annular protrusion 16 (the side facing away from the hole 15) is more concentrated, and the silicon oxide in the peripheral region of the annular protrusion 16 is thicker than that in the hole 15. It is understood that after opening the dielectric layer, it is necessary to use an etchant to remove the residue. When using an etchant to remove the residue, since the silicon oxide is located above the doped semiconductor layer, the etchant preferentially reacts with the silicon oxide, which can reduce the corrosion of the next layer, i.e., the doped semiconductor layer, by the etchant, thereby reducing mold opening damage. In addition, silicon oxide has a good passivation effect. Silicon oxide can passivate the surface of the doped semiconductor layer, which is beneficial to reducing recombination losses caused by direct contact between the doped semiconductor layer and the electrode.

[0154] For example, when the dielectric layer material contains aluminum oxide, the side of the doped semiconductor layer exposed at the opening away from the semiconductor substrate contains aluminum. Since aluminum is a metallic element, the presence of residual aluminum on the side of the doped semiconductor layer exposed at the opening away from the semiconductor substrate can reduce the contact resistance between the electrode and the doped semiconductor layer, which is more conducive to carrier shunting, reduces the carrier recombination rate, and further improves the photoelectric conversion efficiency of the solar cell.

[0155] For example, such as Figure 3As shown in FIG. 1, the part of the doped semiconductor layer exposed in the opening has a first thickness d1, and the part of the doped semiconductor layer not exposed in the opening has a second thickness d2, the first thickness d1 is less than the second thickness d2. The thickness of the doped semiconductor layer at the opening is less than the thickness at the non-opening, so that the transmission distance of the carriers from the semiconductor substrate to the electrode is reduced, the longitudinal transmission resistance is reduced, and especially for the non-sintered electrode, the thickness of the doped semiconductor layer can be made smaller, thereby reducing the longitudinal transmission resistance, ensuring that the doped semiconductor layer has a higher carrier shunt capacity, reducing the carrier recombination rate, and further improving the photoelectric conversion efficiency of the solar cell.

[0156] For example, the part of the doped semiconductor layer exposed in the opening has a first thickness, and for the unexposed part of the doped semiconductor layer not exposed in the opening: it includes a first unexposed part at the opening edge of the dielectric layer and a remaining unexposed part other than the first unexposed part, the first unexposed part has a third thickness, and the remaining unexposed part has a fourth thickness, wherein the fourth thickness > the third thickness > the first thickness.

[0157] For example, the part of the doped semiconductor layer exposed in the opening has a through hole penetrating the doped semiconductor layer. Here, the size of the through hole penetrating the doped semiconductor layer can be nanoscale.

[0158] In some examples, the through hole penetrating the doped semiconductor layer is formed in the hole. In the case where the part of the doped semiconductor layer exposed in the opening includes the through hole penetrating the doped semiconductor layer, in some examples, when the electrode is formed, the material forming the electrode can directly contact the semiconductor substrate through the through hole, so that a small amount of carriers generated by the semiconductor substrate can be directly transmitted to the electrode, thereby reducing the resistance and facilitating the improvement of the shunt capacity of the carriers, further improving the photoelectric conversion rate of the solar cell.

[0159] The electrode 17 is arranged on the side of the dielectric layer 13 away from the semiconductor substrate 11, and the electrode 17 is electrically connected with the doped semiconductor layer 12 through the opening on the dielectric layer 13.

[0160] In the present embodiment, the electrode 17 can be a single-layer structure, for example Figure 1 as shown in FIG. 1, or a laminated multi-layer structure, for example Figure 2 as shown in FIG. 2. Figure 7 As shown in FIG. 2, the electrode 17 includes a laminated two-layer structure, which is a laminated conductive contact layer 17-2 and a connecting electrode 17-1. The conductive contact layer 17-2 is located on the side of the electrode 17 close to the doped semiconductor layer 12, and the connecting electrode 17-1 is electrically connected with the doped semiconductor layer 12 through the conductive contact layer 17-2.

[0161] In the case that the electrode 17 is a single layer structure, the electrode 17 can be formed by screen printing, electroplating, or the like. In the case that the electrode 17 includes a stacked multi-layer structure, each layer of the film can be formed by electroplating, electroless plating, screen printing, or the like.

[0162] The material of the electrode 17 can be a metal material, such as Ag, Cu, Al, Ni, Au, Zn, Sn, Pb, or the like; a metal oxide, including various TCOs, such as ITO, AZO, IWO, or the like; a metal nitride, such as TiN, or the like; a metal carbide, such as TiC, or the like; a metal sulfide, or the like; or other conductive connection materials, such as graphene, or the like; or various combinations of the above materials. The material of the conductive contact layer 17-2 and the connecting electrode 17-1 can also be any of the above electrode materials or suitable combinations thereof. It should be noted that, if the electrode 17 includes the conductive contact layer 17-2 and the connecting electrode 17-1, the material of the conductive contact layer 17-2 and the material of the connecting electrode 17-1 can be the same or different. The material and thickness of the conductive contact layer 17-2 can be determined according to the conductive type of the doped semiconductor layer and the actual application scenario, and are not specifically limited herein. In one possible implementation, the conductive contact layer 17-2 is formed by electroplating or electroless plating, and the material can be one or more of Ag, Ni, and Sn, for example. The connecting electrode 17-1 is formed by screen printing, and the material can be silver paste, copper paste, or silver-coated copper paste, for example.

[0163] It can be understood that, when the electrode 17 comprises a multi-layer structure, since the conductive contact layer 17-2 of the bottom layer is formed on the surface of the doped semiconductor layer 12 with uneven surface, it is beneficial to increase the bonding force between the conductive contact layer 17-2 and the doped semiconductor layer 12, reduce the risk of the conductive contact layer 17-2 being separated from the doped semiconductor layer 12, i.e. reduce the risk of the electrode 17 being separated from the doped semiconductor layer 12, and improve the structural reliability of the solar cell. Here, when the conductive contact layer 17-2 is formed on the surface of the doped semiconductor layer 12 with uneven surface, the side surface of the conductive contact layer 17-2 away from the semiconductor substrate can be flat or uneven. When the side surface of the conductive contact layer 17-2 away from the semiconductor substrate also has uneven surface characteristics, when the connecting electrode 17-1 is formed, it is beneficial to increase the contact area of the conductive contact layer 17-2 and the connecting electrode 17-1, and improve the bonding force between the conductive contact layer 17-2 and the connecting electrode 17-1, i.e. further increase the bonding force between the electrode 17 and the doped semiconductor layer 12, and further reduce the risk of the electrode 17 being separated from the doped semiconductor layer 12. When the electrode 17 is a single-layer structure, the electrode 17 is formed on the surface of the doped semiconductor layer 12 with uneven surface, which is beneficial to increase the bonding force between the electrode 17 and the doped semiconductor layer 12, reduce the risk of the electrode 17 being separated from the doped semiconductor layer 12, and improve the structural reliability of the solar cell.

[0164] The embodiment of the present application also provides a photovoltaic module, which comprises a plurality of cell strings. The plurality of cell strings can be connected together in series and / or in parallel. Each cell string comprises a plurality of solar cells and a plurality of interconnects, which are used to connect the plurality of solar cells together in series. It can be understood that the interconnects are electrically connected to the electrodes of the plurality of solar cells, thereby connecting the plurality of solar cells together in series. Here, the solar cells comprise the solar cells of any of the above embodiments.

[0165] In addition, the interconnects described above can be, for example, solder strips, metal wires, conductive adhesive tapes, etc.

[0166] In the above description, the technical details of the patterning, etching, etc. of each layer are not described in detail. However, it should be understood by those skilled in the art that the layers, regions, etc. with the desired shape can be formed by various technical means. In addition, those skilled in the art can also design methods that are not exactly the same as or different from the above-described methods in order to form the same structure. In addition, although each embodiment is described above separately, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0167] The embodiments of the application have been described above. However, these embodiments are merely meant to be illustrative of the application and are not meant to limit the scope of the application. The scope of the application is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made to the embodiments of the application without departing from the scope of the application, and it is intended that all such alternatives and modifications be included within the scope of the application.

Claims

1. A solar cell, characterized in that, include: A semiconductor substrate having opposing first and second surfaces; A doped semiconductor layer is disposed on the first surface of the semiconductor substrate; A dielectric layer is disposed on the side of the doped semiconductor layer opposite to the semiconductor substrate; The dielectric layer includes multiple openings that expose a portion of the doped semiconductor layer; the doped semiconductor layer has multiple holes formed on the side of the portion exposed by the openings that is away from the semiconductor substrate, and the edges of the holes have a ring-shaped protrusion. An electrode is disposed on the side of the dielectric layer away from the semiconductor substrate, and the electrode passes through an opening in the dielectric layer and is electrically connected to the doped semiconductor layer.

2. The solar cell according to claim 1, characterized in that, The width of the annular protrusion is greater than 0 μm and less than or equal to 0.3 μm; And / or, The height of the annular protrusion is greater than 0 μm and less than or equal to 0.5 μm; And / or, The maximum radial dimension of the hole is greater than 0 μm and less than or equal to 3 μm; And / or, The ratio of the maximum radial dimension of the hole to the width of the annular protrusion is less than or equal to 60.

3. The solar cell according to claim 1, characterized in that, The doped semiconductor layer exposed at the opening has multiple discontinuous protrusions on the side opposite to the semiconductor substrate.

4. The solar cell according to claim 1, characterized in that, At least two of the holes are in contact with each other.

5. The solar cell according to claim 1, characterized in that, The doped semiconductor layer includes a doped polycrystalline silicon layer, and the doped semiconductor layer further includes: amorphous silicon disposed on the side of the portion of the doped polycrystalline silicon layer exposed in the opening that faces away from the semiconductor substrate.

6. The solar cell according to claim 1, characterized in that, The doped semiconductor layer includes a doped polycrystalline silicon layer, and the doped semiconductor layer further includes: an amorphous silicon layer located at the edge of the opening of the dielectric layer and below the dielectric layer, and disposed on the side of the doped polycrystalline silicon layer opposite to the semiconductor substrate.

7. The solar cell according to claim 6, characterized in that, Amorphous silicon particles with a length greater than 0 μm and less than or equal to 6 μm are distributed from the edge of the opening in the dielectric layer along a direction parallel to the semiconductor substrate.

8. The solar cell according to claim 6 or 7, characterized in that, Along the thickness direction of the semiconductor substrate, the depth range of the amorphous silicon is greater than 0 nm and less than or equal to 350 nm.

9. The solar cell according to claim 1, characterized in that, A pore is formed between the dielectric layer and the underlying doped semiconductor layer at the edge of the opening in the dielectric layer.

10. The solar cell according to claim 9, characterized in that, The doped semiconductor layer includes a doped polycrystalline silicon layer, and the doped semiconductor layer further includes: an amorphous silicon layer located at the edge of the opening of the dielectric layer and below the dielectric layer, and disposed on the side of the doped polycrystalline silicon layer opposite to the semiconductor substrate; The length of the amorphous silicon distributed from the edge of the opening in the dielectric layer along a direction parallel to the semiconductor substrate layer is greater than the length of the pores distributed therein.

11. The solar cell according to claim 9, characterized in that, The pores contain at least one metallic material found in the electrodes.

12. The solar cell according to claim 1, characterized in that, The doped semiconductor layer has a first surface roughness on the side of the portion of the opening away from the semiconductor substrate, and a second surface roughness on the side of the portion of the doped semiconductor layer not exposed in the opening away from the semiconductor substrate, wherein the first surface roughness is greater than the second surface roughness.

13. The solar cell according to claim 1, characterized in that, The doped semiconductor layer is formed with silicon oxide on the side of the portion of the opening facing away from the semiconductor substrate.

14. The solar cell according to claim 1, characterized in that, The dielectric layer comprises aluminum oxide, and the doped semiconductor layer, on the side of the portion of the opening facing away from the semiconductor substrate, comprises aluminum.

15. The solar cell according to claim 1, characterized in that, The doped semiconductor layer has a first thickness at the portion exposed in the opening, and a second thickness at the portion not exposed in the opening, wherein the first thickness is less than the second thickness.

16. The solar cell according to claim 1, characterized in that, The portion of the doped semiconductor layer exposed in the opening has a through-hole extending through the doped semiconductor layer.

17. The solar cell according to claim 1, characterized in that, The edge region of the opening includes residual material from the dielectric layer.

18. The solar cell according to claim 1, characterized in that, The central region of the opening includes residual material from the dielectric layer.

19. A photovoltaic module, characterized in that, It includes multiple battery strings, each battery string comprising multiple solar cells and multiple interconnecting elements, the interconnecting elements being used to connect the multiple solar cells together in series; The solar cell is any one of claims 1-18.

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